# -*- explicit-buffer-name: "Makefile<MIPS/pipeline>" -*-

       PHYSICAL_SYNTHESIS = Coriolis
               DESIGN_KIT = sxlib

                   PLACED = Yes
            USE_CLOCKTREE = No
                USE_DEBUG = No
                 USE_KITE = No


 include ./mk/design-flow.mk


layout:  mips_r3000_1m_core_flat_r.ap
gds:     mips_r3000_1m_core_flat_r.gds

lvx:     lvx-mips_r3000_1m_core_flat_r
druc:    druc-mips_r3000_1m_core_flat_r
view:    cgt-mips_r3000_1m_core_flat_r