# -*- explicit-buffer-name: "Makefile<SpinalRTL/layout>" -*-

        LOGICAL_SYNTHESIS = Yosys
       PHYSICAL_SYNTHESIS = Coriolis
               DESIGN_KIT = sxlib

            USE_CLOCKTREE = Yes
                USE_DEBUG = No
                 USE_KITE = No

                 NETLISTS = VexRiscv

 include ./mk/design-flow.mk

blif:   VexRiscv.blif
layout: vexriscv_cts_r.ap

lvx:    lvx-vst-vexriscv_cts
druc:   druc-vexriscv_cts_r