Index of /s/sys/buster-libre-soc/home/mdasoh/src/hdl_tools/yosys/tests/asicworld
Name
Last modified
Size
Description
Parent Directory
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README
2024-09-15 02:49
59
code_hdl_models_GrayCounter.v
2024-09-15 02:49
1.1K
code_hdl_models_arbiter.v
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3.7K
code_hdl_models_arbiter_tb.v
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1.0K
code_hdl_models_cam.v
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1.7K
code_hdl_models_clk_div.v
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1.0K
code_hdl_models_clk_div_45.v
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1.4K
code_hdl_models_d_ff_gates.v
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349
code_hdl_models_d_latch_gates.v
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182
code_hdl_models_decoder_2to4_gates.v
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203
code_hdl_models_decoder_using_assign.v
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582
code_hdl_models_decoder_using_case.v
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1.2K
code_hdl_models_dff_async_reset.v
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733
code_hdl_models_dff_sync_reset.v
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711
code_hdl_models_encoder_4to2_gates.v
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130
code_hdl_models_encoder_using_case.v
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1.1K
code_hdl_models_encoder_using_if.v
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1.7K
code_hdl_models_full_adder_gates.v
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495
code_hdl_models_full_subtracter_gates.v
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575
code_hdl_models_gray_counter.v
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1.0K
code_hdl_models_half_adder_gates.v
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378
code_hdl_models_lfsr.v
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965
code_hdl_models_lfsr_updown.v
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790
code_hdl_models_mux_2to1_gates.v
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456
code_hdl_models_mux_using_assign.v
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698
code_hdl_models_mux_using_case.v
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775
code_hdl_models_mux_using_if.v
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783
code_hdl_models_one_hot_cnt.v
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813
code_hdl_models_parallel_crc.v
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1.6K
code_hdl_models_parity_using_assign.v
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644
code_hdl_models_parity_using_bitwise.v
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457
code_hdl_models_parity_using_function.v
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731
code_hdl_models_pri_encoder_using_assign.v
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1.3K
code_hdl_models_rom_using_case.v
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890
code_hdl_models_serial_crc.v
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1.3K
code_hdl_models_tff_async_reset.v
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733
code_hdl_models_tff_sync_reset.v
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712
code_hdl_models_uart.v
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3.7K
code_hdl_models_up_counter.v
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718
code_hdl_models_up_counter_load.v
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891
code_hdl_models_up_down_counter.v
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804
code_specman_switch_fabric.v
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2.2K
code_tidbits_asyn_reset.v
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285
code_tidbits_blocking.v
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158
code_tidbits_fsm_using_always.v
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2.7K
code_tidbits_fsm_using_function.v
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2.8K
code_tidbits_fsm_using_single_always.v
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2.0K
code_tidbits_nonblocking.v
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165
code_tidbits_reg_combo_example.v
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134
code_tidbits_reg_seq_example.v
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217
code_tidbits_syn_reset.v
2024-09-15 02:49
262
code_tidbits_wire_example.v
2024-09-15 02:49
106
code_verilog_tutorial_addbit.v
2024-09-15 02:49
382
code_verilog_tutorial_always_example.v
2024-09-15 02:49
175
code_verilog_tutorial_bus_con.v
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141
code_verilog_tutorial_comment.v
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364
code_verilog_tutorial_counter.v
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502
code_verilog_tutorial_counter_tb.v
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2.5K
code_verilog_tutorial_d_ff.v
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185
code_verilog_tutorial_decoder.v
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387
code_verilog_tutorial_decoder_always.v
2024-09-15 02:49
389
code_verilog_tutorial_escape_id.v
2024-09-15 02:49
259
code_verilog_tutorial_explicit.v
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472
code_verilog_tutorial_first_counter.v
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1.6K
code_verilog_tutorial_first_counter_tb.v
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814
code_verilog_tutorial_flip_flop.v
2024-09-15 02:49
205
code_verilog_tutorial_fsm_full.v
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2.9K
code_verilog_tutorial_fsm_full_tb.v
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1.2K
code_verilog_tutorial_good_code.v
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345
code_verilog_tutorial_if_else.v
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146
code_verilog_tutorial_multiply.v
2024-09-15 02:49
161
code_verilog_tutorial_mux_21.v
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150
code_verilog_tutorial_n_out_primitive.v
2024-09-15 02:49
290
code_verilog_tutorial_parallel_if.v
2024-09-15 02:49
473
code_verilog_tutorial_parity.v
2024-09-15 02:49
944
code_verilog_tutorial_simple_function.v
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132
code_verilog_tutorial_simple_if.v
2024-09-15 02:49
126
code_verilog_tutorial_task_global.v
2024-09-15 02:49
143
code_verilog_tutorial_tri_buf.v
2024-09-15 02:49
126
code_verilog_tutorial_v2k_reg.v
2024-09-15 02:49
520
code_verilog_tutorial_which_clock.v
2024-09-15 02:49
154
run-test.sh
2024-09-15 02:49
311
xfirrtl
2024-09-15 02:49
1.6K
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