# Which BEL names are global buffers for nextpnr?
global_buffer_bels:
- BUFG
- BUFGCTRL
- VCC
- GND
# Which cell names are global buffers, and which pins should use dedicated routing resources
global_buffer_cells:
  - cell: BUFG
    pins: # list of pins that use global resources
     - name: I # pin name
       guide_placement: true # attempt to place so that this pin can use dedicated resources
       max_hops: 10 # max hops of interconnect to search (10 is for test purposes and may need to be refined)
     - name: O
       force_dedicated_routing: true # the net connected to this pin _must_ use dedicated routing only
  - cell: BUFGCTRL
    pins:
      - name: I0
        guide_placement: true
        max_hops: 10
      - name: I1
        guide_placement: true
        max_hops: 10
      - name: O
        force_dedicated_routing: true
# How should nextpnr lump BELs during analytic placement?
buckets:
- bucket: FLIP_FLOPS
  cells:
   - FDRE
- bucket: LUTS
  cells:
   - LUT1
- bucket: BRAMS
  cells:
   - RAMB18E1
   - RAMB36E1
   - FIFO18E1
   - FIFO36E1
- bucket: BUFG
  cells:
   - BUFG
   - BUFGCTRL
- bucket: BUFH
  cells:
   - BUFH
   - BUFHCE
- bucket: BUFMR
  cells:
   - BUFMR
- bucket: BUFR
  cells:
   - BUFR
- bucket: IBUFs
  cells:
   - IBUF
   - IBUFDS_IBUFDISABLE_INT
- bucket: OBUFs
  cells:
   - OBUF
   - OBUFTDS
- bucket: MMCM
  cells:
   - MMCME2_ADV
- bucket: PLL
  cells:
   - PLLE2_BASE
- bucket: PULLs
  cells:
   - PULLDOWN
- bucket: CARRY
  cells:
   - MUXCY
   - XORCY
   - CARRY4
# don't route through the following cells
disabled_routethroughs:
  - BUFGCTRL
  - BUFR
  - A6LUT
  - B6LUT
  - C6LUT
  - D6LUT
# Do not allow cells to be placed at BELs
disabled_cell_bel_map:
  - cell: FDRE
    bels:
     - TFF
     - IFF
     - OUTFF
  - cell: FDCE
    bels:
     - TFF
     - IFF
     - OUTFF
  - cell: FDPE
    bels:
     - TFF
     - IFF
     - OUTFF
  - cell: FDSE
    bels:
     - TFF
     - IFF
     - OUTFF
disabled_site_pips:
  - bels:
     - A6LUT
     - B6LUT
     - C6LUT
     - D6LUT
    ipin: A6
    opin: O6
clusters:
- name: CARRY_CHAIN
  chainable_ports:
    - cell_source: CO[3]
      cell_sink: CI
      bel_source: CO3
      bel_sink: CIN
      avg_x_offset: 0
      avg_y_offset: -1
  root_cell_types:
    - CARRY4
  disallow_other_cells: true # Disable placing cells not belonging to the cluster in the same site
  cluster_cells:
    - cells:
        - LUT1
        - LUT2
        - LUT3
        - LUT4
        - LUT5
        - LUT6
      ports:
        - S[3]
        - S[2]
        - S[1]
        - S[0]
- name: IDELAY_ISERDES
  root_cell_types:
    - IDELAYE2
  out_of_site_clusters: true
  cluster_cells:
    - cells:
        - ISERDESE2
      ports:
        - DATAOUT

macro_clusters:
- name: LUT6_2
  sites:
    - site: SLICEM
      cells:
        - cell: LUT5
          bels:
            - D5LUT
            - C5LUT
            - B5LUT
            - A5LUT
        - cell: LUT6
          bels:
            - D6LUT
            - C6LUT
            - B6LUT
            - A6LUT
    - site: SLICEL
      cells:
        - cell: LUT5
          bels:
            - D5LUT
            - C5LUT
            - B5LUT
            - A5LUT
        - cell: LUT6
          bels:
            - D6LUT
            - C6LUT
            - B6LUT
            - A6LUT
- name: RAM16X2S
  sites:
    - site: SLICEM
      cells:
        - cell: RAM16X1S0/SP
          bels:
            - D6LUT
            - D5LUT
            - B6LUT
            - B5LUT
        - cell: RAM16X1S1/SP
          bels:
            - C6LUT
            - C5LUT
            - A6LUT
            - A5LUT
- name: RAM16X4S
  sites:
    - site: SLICEM
      cells:
        - cell: RAM16X2S0/RAM16X1S0/SP
          bels:
            - D6LUT
            - D5LUT
        - cell: RAM16X2S0/RAM16X1S1/SP
          bels:
            - C6LUT
            - C5LUT
        - cell: RAM16X2S1/RAM16X1S0/SP
          bels:
            - B6LUT
            - B5LUT
        - cell: RAM16X2S1/RAM16X1S1/SP
          bels:
            - A6LUT
            - A5LUT
- name: RAM16X8S
  sites:
    - site: SLICEM
      cells:
        - cell: RAM16X2S0/RAM16X1S0/SP
          bels:
            - D6LUT
        - cell: RAM16X2S0/RAM16X1S1/SP
          bels:
            - C6LUT
        - cell: RAM16X2S1/RAM16X1S0/SP
          bels:
            - B6LUT
        - cell: RAM16X2S1/RAM16X1S1/SP
          bels:
            - A6LUT
        - cell: RAM16X2S2/RAM16X1S0/SP
          bels:
            - D5LUT
        - cell: RAM16X2S2/RAM16X1S1/SP
          bels:
            - C5LUT
        - cell: RAM16X2S3/RAM16X1S0/SP
          bels:
            - B5LUT
        - cell: RAM16X2S3/RAM16X1S1/SP
          bels:
            - A5LUT
- name: RAM32X1S
  sites:
    - site: SLICEM
      cells:
        - cell: SP
          bels:
            - D6LUT
            - D5LUT
            - C6LUT
            - C5LUT
            - B6LUT
            - B5LUT
            - A6LUT
            - A5LUT
- name: RAM32X1D
  sites:
    - site: SLICEM
      cells:
        - cell: DP
          bels:
            - C6LUT
            - C5LUT
            - A6LUT
            - A5LUT
        - cell: SP
          bels:
            - D6LUT
            - D5LUT
            - B6LUT
            - B5LUT
- name: RAM32X2S
  sites:
    - site: SLICEM
      cells:
        - cell: RAM32X1S0/SP
          bels:
            - D6LUT
            - D5LUT
            - B6LUT
            - B5LUT
        - cell: RAM32X1S1/SP
          bels:
            - C6LUT
            - C5LUT
            - A6LUT
            - A5LUT
- name: RAM32X4S
  sites:
    - site: SLICEM
      cells:
        - cell: RAM32X2S0/RAM32X1S0/SP
          bels:
            - D6LUT
            - D5LUT
        - cell: RAM32X2S0/RAM32X1S1/SP
          bels:
            - C6LUT
            - C5LUT
        - cell: RAM32X2S1/RAM32X1S0/SP
          bels:
            - B6LUT
            - B5LUT
        - cell: RAM32X2S1/RAM32X1S1/SP
          bels:
            - A6LUT
            - A5LUT
- name: RAM32X8S
  sites:
    - site: SLICEM
      cells:
        - cell: RAM32X4S1/RAM32X2S0/RAM32X1S0/SP
          bels:
            - D6LUT
        - cell: RAM32X4S1/RAM32X2S1/RAM32X1S0/SP
          bels:
            - D5LUT
        - cell: RAM32X4S1/RAM32X2S0/RAM32X1S1/SP
          bels:
            - C6LUT
        - cell: RAM32X4S1/RAM32X2S1/RAM32X1S1/SP
          bels:
            - C5LUT
        - cell: RAM32X4S0/RAM32X2S0/RAM32X1S0/SP
          bels:
            - B6LUT
        - cell: RAM32X4S0/RAM32X2S1/RAM32X1S0/SP
          bels:
            - B5LUT
        - cell: RAM32X4S0/RAM32X2S0/RAM32X1S1/SP
          bels:
            - A6LUT
        - cell: RAM32X4S0/RAM32X2S1/RAM32X1S1/SP
          bels:
            - A5LUT
- name: RAM32M
  sites:
    - site: SLICEM
      cells:
        - cell: RAMA
          bels:
            - A5LUT
        - cell: RAMA_D1
          bels:
            - A6LUT
        - cell: RAMB
          bels:
            - B5LUT
        - cell: RAMB_D1
          bels:
            - B6LUT
        - cell: RAMC
          bels:
            - C5LUT
        - cell: RAMC_D1
          bels:
            - C6LUT
        - cell: RAMD
          bels:
            - D5LUT
        - cell: RAMD_D1
          bels:
            - D6LUT
- name: RAM64X1S
  sites:
    - site: SLICEM
      cells:
        - cell: SP
          bels:
            - D6LUT
            - C6LUT
            - B6LUT
            - A6LUT
- name: RAM64X1D
  sites:
    - site: SLICEM
      cells:
        - cell: DP
          bels:
            - C6LUT
            - A6LUT
        - cell: SP
          bels:
            - D6LUT
            - B6LUT
- name: RAM64X2S
  sites:
    - site: SLICEM
      cells:
        - cell: RAM64X1S0/SP
          bels:
            - D6LUT
            - B6LUT
        - cell: RAM64X1S1/SP
          bels:
            - C6LUT
            - A6LUT
- name: RAM64M
  sites:
    - site: SLICEM
      cells:
        - cell: RAMA
          bels:
            - A6LUT
        - cell: RAMB
          bels:
            - B6LUT
        - cell: RAMC
          bels:
            - C6LUT
        - cell: RAMD
          bels:
            - D6LUT
- name: RAM128X1S
  sites:
    - site: SLICEM
      cells:
        - cell: LOW
          bels:
            - D6LUT
            - B6LUT
        - cell: HIGH
          bels:
            - C6LUT
            - A6LUT
        - cell: F7
          bels:
            - F7BMUX
            - F7AMUX
- name: ROM128X1
  sites:
    - site: SLICEM
      cells:
        - cell: LOW
          bels:
            - D6LUT
            - B6LUT
        - cell: HIGH
          bels:
            - C6LUT
            - A6LUT
        - cell: F7
          bels:
            - F7BMUX
            - F7AMUX
- name: RAM128X1D
  sites:
    - site: SLICEM
      cells:
        - cell: SP.LOW
          bels:
            - D6LUT
        - cell: SP.HIGH
          bels:
            - C6LUT
        - cell: DP.LOW
          bels:
            - B6LUT
        - cell: DP.HIGH
          bels:
            - A6LUT
        - cell: F7.SP
          bels:
            - F7BMUX
        - cell: F7.DP
          bels:
            - F7AMUX
- name: RAM256X1S
  sites:
    - site: SLICEM
      cells:
        - cell: RAMS64E_D
          bels:
            - D6LUT
        - cell: RAMS64E_C
          bels:
            - C6LUT
        - cell: RAMS64E_B
          bels:
            - B6LUT
        - cell: RAMS64E_A
          bels:
            - A6LUT
        - cell: F7.A
          bels:
            - F7AMUX
        - cell: F7.B
          bels:
            - F7BMUX
        - cell: F8
          bels:
            - F8MUX
- name: R0M256X1
  sites:
    - site: SLICEM
      cells:
        - cell: D
          bels:
            - D6LUT
        - cell: C
          bels:
            - C6LUT
        - cell: B
          bels:
            - B6LUT
        - cell: A
          bels:
            - A6LUT
        - cell: F7.A
          bels:
            - F7AMUX
        - cell: F7.B
          bels:
            - F7BMUX
        - cell: F8
          bels:
            - F8MUX

