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HH=€AHH5׶HHE4/H|$8LHdgLHD$XaH|$`IHCH9thLuLH5[HIHE.H|$8LH^LHD$XTH|$`IHCH9tFhL莈H5 HHE .H|$8LHK^LHD$XHSH|$`IH9tgL@HE(HAD$E1HD$ H=7H€HELYHɇHL$H5:HHHE-H|$8LHx]LHD$XRH|$`IHCH9t%gLmH5HHE j-H|$8LH*]LHD$XHRH|$`IH9tfLHE(HH} E1H EH5IH=>DHEwH=&H€ H=HAAEEHH5HHE~,H|$8LH>\LHD$XQH|$`HSH9tHD$eHD$HHUHLuD$HD$HD$ D$/IAH5YH+H|$8LH[LHD$X1QH|$`HSH9tHD$0YeHD$0HBHUHL$ HLt$Lu zIDt$H5Hs+H|$8LHcLHD$X]H|$`IHCH9tdL(H5~HHE %+H|$8LHUcLHD$XH]H|$`IH9tdLڄHt$HHE0y@HH5&HHE*H|$8LHbLHD$X&]H|$`IHCH9t dHELuLZH5~HIX*H|$8LHbLHD$X\H|$`IHCH9tcL H5}HHE *H|$8LH:bLHD$XHy\H|$`IH9twcLA蹃Ht$HHE0XaH} bE1H k7H5׆H=0:H=ήH€HH5HHED)H|$8LHtaLHD$X[H|$`IHCH9tbHELuLH5}HI(H|$8LHaLHD$X\[H|$`IHCH9tVbL螂H5^|HHE (H|$8LH`Hƹ H=ɯHH5E|HHEK(H|$8LH{`LHD$XZH|$`IHCH9taHELuLH5hHI'H|$8LH `LHD$XcZH|$`IHCH9t]aL襁H5#HHE 'H|$8LH_D$HD$HD$ D$/l|$/LFTLHD$XXLIXHHHD$8HD$`QLHnI<$MHH14E1H ʻH56H=O7E1H H5H=C7LSH|$PHD$PSH|$HHD$H:XLISLHD$X"XLIXHHPLHI<$MMHH1tHHHHHyHqHiHaHYHQHIHAH9H1H)H!HHH HHHHHHHHHHff.AWAVAUATUSHHHcFHL$PHHHT$`H|$HDŽ$HH)HH9sHH9tHHHDŽ$HH)HH9HH?H9CH,Hm^H1HI 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Ht8H}H7HhI9uHHtH7HHt8HxHt8L@H8I9t"H}Hc7H(I9uH8HtHq7HEH9HHtH7HHt77HHt&7LHI9t%H}H6H(I9uHHtH6HHtYHEH4HLd5L9t6ff.@I(I<$H6L9uHEH4HHH},:H{ HH([]A\A]A^A_\6ff.H(I93Iff.H(I9ff.HhI9ff.L97MfH([]A\A]A^A_ÐATIUSHoHH9t!ff.fHHH9uI<$Ht []A\5[]A\DUHAWAVAUATSHH H5HH HL2H+x+HHHHnHHHHH70fo=H@ffo-Hfo5xHfo=s)@fXhH@HDžP,HHf.HHH85HHXHH=*HH`HXH=~*HHhH`H=i*HHpHhH=HCHpLHHIH@H8ff.fD3HHIHXHHL;@E4$H9PuL@L)H'.HDžPHtHHH9HFHPHP33IHPE4LHPH2I_M8L8HPI~8H8HP8)@L;@8fL@HL)HH?HxLLHDž@HLHH0HLHMH(HHHHHHHH@HHf.H@1@HȉHBȉHBȉHB ȉHBȉHBȉHBȉHBȉHB ȉHB$ȉHB(ȉHB,ȉHB0ȉH B4ȉH(B8ȉH0BH@X@`Lh@KFHC@pC|"IHfH=?H@H@1fAF IF8IF(IFIF0AF8AFhHCHAFAFHAFXEIFHCHfH==H@X@`Lh@HHCpCPEHǃ%"IH@fH=epH@1fAF IF8IF(1fAIIIFIF0AF8AFhAFpIFxIdžIdžAƆAdžHIAFAFHAFXAADHIFH5HGhG`H HG8LoG'LH=AFh\DIFpHpHǀǀLhxƀHHǃH E1IHH@8fD`fH=ioH@H@IF(IFIF0AF8AFhHAFAFHAFXCHIFH5HGXH G@LoG&H=U;dCHpǃE1IHH@8fDXfH=RH@H@IF(IFIF0AF8AFhHAFAFHAFXBIFHH5RHHH@X@`Lh@HHPL`@L;`PLPM;fHHHL LMvHI M9t6HPMfI}IEH9!I M9uHPL`HHHHHH9t!HǃpHǃE1HHIH@H@8fH=wQH@fDPHF(HFHF0F8FhHFFHFXAIFHHH5kLHH@X@`LHP@H H(@H0HL %HHLHH9t L0H HL&+LHH5LHLL$HHLHH9tS L0H LHLmLHH5LHLLO$HHLHH9tL HL0IIPALHE1H56LAAEH0HL#HHLHH9tcH HEHDPH0Hl)LHAXH5AYLrH0HDL9;HHLHH9tHtH0H HLHH5\L H0HL"HHLHH9t|L0H HDPHMHrLHH5LHLLj"HHLHH9tLLL0HL HLLM?H@HI9u#f.IL9lAtHHL!HHHH1f.HHHuHH9fHIIfHCIIFHHuM9L?LLL)LHHHH?HH)HӉHILH脆HI9taff.HHVHFHyLBPA;xPff.@LHPHPLHLBA9xP|HHI9uHHH@H(H9twM9t_HMHPff.IM9t;I$HPH@H0uHC(HPH;C0L8HHC(H8H9(uMtLHHtfDHHHuHH1HHHHHDžHDžH0H9]IL9fHHH@HH9t*HH0HsH8H9uLHH5LFH0HL0HHLHH9tHt2H L0HHDHHLHH59LH0HLHHLHH9t7H LHH5\KLxI|$ H5oFgI|$@H5 FVH@LID$`ILH H8IHH9tM9uL@LHLLXL0LHL<0LL LHI`AIMHIH AIMHIuL#H LHH5fH0LASH0HL5HHLHH9tHt&H H0HwH0HqLHH5^LH0HDL4HHIGH9tNHt*H H8HH0HVH"HHXHIIwHt H 跓LH8II9uH L MpIy(L@MSff.AoyLE111)HHu,Lff.@xvH`H@XHt"t߃DAH`H@XHuHI9uMI0MIy(rI誎HHHx11蔏@HC HH8HPH)HH L$L9wHI9IILHHH8HDL<HH9P7 H/HH8HPYHPHPI~PLc0C @ff.Lc(Lk LL)IHHHHDžHDžH0HHDžDž ?HDž(HDž0H@HDžHHDžPHDžXDž`?HDžhHDžpM9H?HLH?LHH)HIO ILIH}LM9tKff.HHVHFy ;z |H LHPHPL@9z HHI9uDž(HCHPHs HS(H8HH9OHDLHcC1IHHIHHH HI;xtgHIHi Hc@1IHH9T M3ff.@HIH1 Hc@1IHH9 LD9uMHDžMgHDžLIG(HAoo0HDž)P)IHI9ILL1HPHIG HHHxIHIHc@1HH@HHHH IIHuSIIHtEII虚I$HHc@1HHHH8uL IIHufDH8HLHHI9HID$@It$8HH)HHHH9r HPID$@It$8II)MIH9tHPLHPLHIHH9H9YHH9YH9YHHHH 0DH9Z FH9X,H9XH9XHHB H9uMHPI)IIzIgIoHPQIhL9LMIG@M'MoHPIGPHHt'IHwHP/LMvLMuIG HHt#HwILLMvLMuLMMxHH1H{H@HHDžHDžH0H9tYH8H8H9HC((9HP|HH fDH9tHH9t HH9I9ff.IcD$dH1IHHHHHLL(E;EtjMmM6IcE1HHH9!HPI0ff.MmMIcE1HHH9A9uLPHHHDžDžHDžHPHHIu HlHHH`HPHH HHJHuHH HHJHuHHHIU8HHDžHHV8HHIuPHPDžHDžH.HHHHPHHff.HH@Ht(9p }H@HuH8HPH0HHHH9(9B |HcR$ID$HHcIHDHHHHAHH(DAƉu D:x (HDHu D:p !HHLLh0Mt IwLMwL MMuLMcHPIIvHHֽMnL MMuLPL-HDžH8HHIuPDžHDžHuEH8H0ff.LL Hm1(H=7'蚄f.HHHHx0HP8HHPHHff.@HHJHuHH HHJHuHIUhHPHHH:LPH=FM ff.fHHfI9WfHHHHH@HH0Hff.H]H=F @IE1HDžPH9~PHPHB8`HPHB0PHPHB(@HP4@I M9Smff.H8LLsHAYL@HL ƄH7lIW@I9t LL)1HH@Hx8H1HLH i1H|"H=*-MHXH`HhHHLHw AHPHAH[ L4 AHH@AƅHXH QX Hƃv LLq HE1E1HH@H(H9UH HHHIHw xHPHx@L`HII9t&I>IFH9tDOI M9uHPHx@Ht1HPLh@I LhHLhP?DI M9uD1MI5H8ED(HhH="HH1EH8D(EH="HRHg3H11H@HqIH3qIH(qIHrIH6rIHqIHpIHpIHpIHqIHpIHpIHpHIkqqH9rHIqHIqHI2rHqHYrHqHpIH(rIH[qHBrIH\rf.AWIAVIAUAATL%@+UH-H+SL)HHt1LLDAHH9uH[]A\A]A^A_HHWarning %d: %luvector::_M_fill_insert%s:%d %s: Assertion '%s' failed (%s)len >= 0Warning: file: line: message: Expected '' attribute on node 'Missing required child node '' in parent node 'Multiple child '' (only one expected)Unexpected node type '' expected 'Found (expected ' child node(s) of Unexpected attribute ' found on node ' Expected (possibly) one of: basic_string::appendUnexpected child ' of node 'Unable to calloc memory.i == *num_tokensFailed to convert string '' to floatUnable to malloc memory.near '', missing '['', missing ']'', '[' after ']'basic_string::substr', expected positive integerUnknown errorFile was not foundCould not allocate memoryInternal error occurredCould not determine tag typeError parsing commentError parsing CDATA sectionError parsing PCDATA sectionError parsing end element tagStart-end tags mismatchNo document element foundrbFailed to open fileUnable to load XML file '', (line: col: basic_string::_M_construct null not validProblem decoding format string/home/mdasoh/src/symbiflow/vtr-verilog-to-routing/libs/libvtrutil/src/vtr_util.cppstatic_cast(len) == buf_size - 1Multiple matching Fc overrides found; the last will be applied ' nodes found in parent node '/home/mdasoh/src/symbiflow/vtr-verilog-to-routing/libs/libvtrutil/src/vtr_memory.cpp/home/mdasoh/src/symbiflow/vtr-verilog-to-routing/libs/libvtrutil/src/vtr_token.cpp', found ':' but not between '[' and ']'%s: __pos (which is %zu) > this->size() (which is %zu)Error reading from file/streamError parsing document declaration/processing instructionError parsing document type declarationError parsing start element tagError parsing element attributeUnable to append nodes: root is not an element or documentbA''nAVA ??>>$??>>@?113ArchFpgaErrorN3vtr8VtrErrorEN8pugiutil8XmlErrorE7 ?`@@@@@@@@@@@0GetTokensFromStringvstring_fmt/BD7q۵[V9Y?^[1$} Ut]rހܛtiGƝ̡ $o,-tJܩ\ڈvRQ>m1'Y GQcg)) '8!.m,M 8STs e jv.,r迢KfpKQl$5pjl7LwH'4 9JNOʜ[o.htocxxȄnjlPxqProcess_Fcvector::_M_insert_aux.names.latch.input.outputarch_file_name != nullptrpb_type->num_modes == 0.subckt [fixedshuffledInvalid value ' for attribute ' on <> tag, expected value or Unexpected attribute , expected Unexpected tag > in section <switchfuncsfuncformulalrlbtltbrlblbtbr pb_type->blif_modelannot->input_pinsUnrecognized delay annotation '' of model '',model_port->dir == OUT_PORT input port 'input_portsoutput_portsis_non_clock_globalclockcombinational_sink_portsModel port is missing a nametruefalseDuplicate model name: '%s'. sink_portExpected attributes on node'fromnum_connsfrom_orderto_ordernum_from_children > 0num_to_children > 0port.type == OUT_PORTpin_count == type->num_pins/home/mdasoh/src/symbiflow/vtr-verilog-to-routing/libs/libarchfpga/src/arch_util.cpppb_type->blif_model != nullptrUnrecognized switchpoint order '%s'/home/mdasoh/src/symbiflow/vtr-verilog-to-routing/libs/libarchfpga/src/parse_switchblocks.cppAnnotation_clock check encouters invalid annotation or primitive. Clock '%s' does not match any clock defined in pb_type '%s'. Unknown blif model %s in pb_type %s No matching model for pb_type %s Direction for port '%s' on model does not match port direction in pb_type '%s' Port '%s' on model does not match is_clock in pb_type '%s' No matching model port for port %s in pb_type %s Unknown permutation function specified: %s parse_comma_separated_wire_types: found empty wireconn wire type entry Failed to parse instance port specification '%s'/home/mdasoh/src/symbiflow/vtr-verilog-to-routing/libs/libarchfpga/src/arch_check.cppUnable to find model for blif_model '%s' found on pb_type '%s'Failed to find port '%s' on '%s' for sequential delay annotation timing-annotation/ mismatch on port '%s' of model '%s', model specifies no clock but timing annotation specifies '%s' timing-annotation/ mismatch on port '%s' of model '%s', model specifies clock as '%s' but timing annotation specifies '%s'Failed to find port '%s' on '%s' for combinational delay annotation timing-annotation/ mismatch on port '%s' of model '%s', timing annotation specifies combinational connection to port '%s' but the connection does not exist in the model' timing-annotation/ mismatch on port is a sequential input but has neither T_setup nor T_hold specified port is a sequential input with internal combinational connects but has neither min nor max T_clock_to_Q specified port is a sequential output but has neither min nor max T_clock_to_Q specified port is a sequential output with internal combinational connections but has neither T_setup nor T_hold specified' has combinational connections to'; specified in model, but no combinational delays found on pb_type/home/mdasoh/src/symbiflow/vtr-verilog-to-routing/libs/libarchfpga/src/read_xml_arch_file.cppport_group.name() == std::string("output_ports")Model port '%s' cannot be both a clock and a non-clock signal simultaneouslyDuplicate model port named '%s'Model output ports can not have combinational sink portsUnsupported never prune attribute value.Duplicate 'name' attribute on tag.Model '%s' output port '%s' can not have combinational sink portsModel '%s' output port '%s' can not be both: a clock source (is_clock="%d"), and combinationally connected to input port '%s' (acting as a clock buffer).Model '%s' input port '%s' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) Model '%s' output port '%s' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) Model '%s' input port '%s' can not be combinationally connected to '%s' (not an output port of the model)No matching clock port '%s' on model '%s', required for port '%s'parse_comma_separated_wire_points: found empty wireconn wire point entry Expected only 2 attributes on node '%s'Empty switchpoint specificationUnrecognized child node '%s' of parent node '%s'$I$IL$I$I$IIIProcessModelPortscheck_model_combinational_sinkswarn_model_missing_timingcheck_leaf_pb_model_timing_consistencyalloc_and_load_default_child_for_pb_typepb_type_contains_blif_modelsetup_pin_classesget_arch_file_namepower_method_inheritedparse_wireconn_multinodebuffer_sizeautoC_wireNo port name is present: %s No closing bracket: %s No closed square bracket: %s yoffsetxoffsetyincrxincrswitch_pointnum_switches != 2drivetaplocal_interconnectbufferslogical_effort_factorsramtransistors_per_bitmux_transistor_sizeFF_sizeLUT_transistor_sizefc_vallocationxlocationyclock_routingnum_instmetal_layerstartyendyrepeatxrepeatystartxendxribspineclock_networkWHWrong physical type name of the port: %s No dot is present to separate type name and port name: %s Port %s for %s could not be found: %s No open square bracket present: %s No integer to indicate least significant pin index: %s pin location should be completed, but more tokens are present: %s No integer to indicate most significant pin index: %s clock_network.type == e_clock_type::RIBFound unsupported switch type for '%s' clock network. Currently there is only support for drive and tap switch types. '%s' is not a valid switch name. Found no supported clock network type for '%s' clock network. Currently there is only support for rib and spine networks. ProcessClockSwitchPoints?directfrom_pinto_pinx_offsety_offsetz_offsetfrom_sideto_sideleftrighttopbottomInvalid side specification__vpr_delayless_switch__mux with type 'CinCoutCinternalTdelpower_buf_sizemux_trans_sizetristatebufferpass_gateshort with type Invalid switch type '%s'. num_inputsswitchblockvector::reservebidirunidirswitchblock_locationEVERYWHEREPERIMETERCORECORNERFRINGEwireconnfrom_typeto_typefrom_switchpointto_switchpointEMPTYRmetalCmetalmetal_layerssegmentvector::_M_default_appendunnamed_segment_longlinefreqaxissbcbwire_switchopin_switchvector::_M_fill_insertCB or SB depopulation is too long (%d). It should be %d symbols for CBs and %d symbols for SBs. Invalid character %c in CB or SB depopulation list. CB or SB depopulation is too short (%d). It should be %d symbols for CBs and %d symbols for SBs. '%s' is not a valid type for specifying cb and sb depopulation. Two directs with the same name '%s' were found. The source pin and sink pin are the same: %s. The x_offset, y_offset, z_offset are all zero, this is a length 0 direct chain connection. Could not find switch named '%s' in switch list. Switch name '%s' is a reserved name for VPR internal usage! Please use another name. Two switches with the same name '%s' were found. Switch delay should be specified as EITHER a Tdel property OR as a child of the switch node, not bothSwitch should contain intrinsic delay information if timing is enabledTdel node specified num_inputs (%d) that has already been specified by another Tdel nodeUnsopported switchblock type: %s unrecognized switchblock location: %s Unidirectional switch blocks are currently only allowed to drive the start points of wire segments BI_DIRECTIONAL == directionalityFailed to find segment '%s' for from type specification Invalid from_switchpoint '%d' (must be >= 0) Invalid from_switchpoints '%d' (must be < %d) Failed to find segment '%s' for to type specification Invalid to_switchpoint '%d' (must be >= 0) Invalid to_switchpoints '%d' (must be < %d) If a bidirectional switch block specifies a connection from side1->side2, no connection should be specified from side2->side1 as it is implicit. Duplicate pb_type descriptor name: '%s'. Two metal layers with the same name '%s' were found. Atleast one segment per-axis needs to get specified if no segments with non-specified (default) axis attribute exist.No name specified for the segment #%d. Unsopported parralel axis type: %s BI_DIRECTIONAL == Segs[i].directionality'%s' is not a valid opin_switch name. '%s' is not a valid mux name. '%s' is not a valid wire_switch name. ProcessSegmentscheck_switchblock?@@uniformgaussianpulsedeltawidthxpeakdcsitepin_mappingCould not find type: %s customret1.second == ret2.second_Map_base::atblock_port != nullptrsub_tile_port != nullptrtimingsizingchan_width_distrswitch_blockconnection_blockdefault_fcR_minW_nmosR_minW_pmosgrid_logic_tile_areainput_switch_namefswiltonuniversalsubsetin_typein_valout_typeout_valspreadperimeter'%s' is not a valid side. pin_low_idx >= 0pin_high_idx >= 0sub_tilecapacityequivalentnonefullInvalid pin equivalence '%s'.Unknown port type %sport_index == num_portspinlocationsequivalent_sitesheightgridlocationsswitchblock_locationsinternal_switchsb_locswitch_overridehorizontalverticalturnsstraightallexternalUnknown property %s for chan_width_distr x There are no sites corresponding to this tile: %s. There are no direct pin mappings between site %s and tile %s. The number of pins specified in the direct pin mapping is not equivalent for Physical Tile %s and Logical Block %s. /home/mdasoh/src/symbiflow/vtr-verilog-to-routing/libs/libvtrutil/src/vtr_bimap.hDuplicate logical pin (%d) to physical pin (%d) mappings found for Physical Tile %s and Logical Block %s. Pin definition differ between site %s and tile %s. User-defined pin mapping is required. Logical Block (%s) has more pins than the Sub Tile (%s). map_.size() == inverse_map_.size()Logical block (%s) and Sub tile (%s) have a different number of ports. Logical block (%s) and Physical tile (%s) do not have equivalent port specifications. Sub tile port %s, logical block port %s Unknown property %s for switch block type x . has been replaced with the tag. Please upgrade your architecture file.spread_inputs_perimeter_outputs%s is an invalid pin location pattern. Sub Tile %s has a different pin location pattern (%s) with respect to the sibling sub tiles'%d' is an invalid horizontal offset for type '%s' (must be within [0, %d]). '%d' is an invalid vertical offset for type '%s' (must be within [0, %d]). Pin location specification '%s' should not contain an instance range (should only be the block name)Mismatched sub tile name in pin location specification (expected '%s' was '%s')Failed to find port named '%s' on block '%s'Pin '%s.%s[%d]' has no pin location specificed (a location is required for pattern="custom")Duplicate pin location side/offset specification. Only a single per side/xoffset/yoffset is permitted. No sub tile found for the Physical Tile %s. At least one sub tile is needed to correctly describe the Physical Tile. Duplicate Sub Tile names in tile '%s': Sub Tile'%s' Invalid pin equivalence '%s' for %s port.Invalid number of pins %d for %s port.Port %s cannot be both a clock and a non-clock simultaneously Duplicate port names in tile '%s': port '%s' Another port found with the same name in other sub tiles that did not match the current port settings. '%s': port '%s' port.is_clock && port.type == IN_PORTexternal_full_internal_straightArea for type %s must be non-negative Duplicate tile descriptor name: '%s'. Invalid 'type' attribute '%s' Invalid 'switch_override' attribute '%s' (no matching switch named '%s' found) Invalid 'xoffset' attribute '%zu' (must be in range [%d,%d]) Invalid 'yoffset' attribute '%zu' (must be in range [%d,%d]) Duplicate specifications at xoffset=%zu yoffset=%zu Invalid 'internal_switch' attribute '%s' (no matching switch named '%s' found) Invalid 'pattern' attribute '%s' . has been replaced by the and tags in the section.insertcheck_port_direct_mappingssizeProcessPinLocationsProcessSubTilePortsmetadatametafracabsfc_overrideport_namesegment_namefc_typeUnexpected attribute '%s'!fc_override.seg_name.empty()auto_layoutaspect_ratiofixed_layoutpriorityH - 1W - 1W - 2cornersH-1W-1fillsingle + w - 1 + h - 1colincryrowincrxregionport_classlut_inDlut_outwire_capacitancewire_lengthwire_relative_lengthLUTLatchmode!is_root_pb_typeT_setupT_holdT_clock_to_Qdelay_constantdelay_matrixlutflipflopnum_pbpb_type->num_pb > 0methodauto-sizespecify-sizepin-togglec-internalabsoluteignoresum-of-childrenj == num_portsmax_internal_delayC_constantC_matrixj == num_annotationslut_childlut_pb_type->num_ports == 2complete:%s%s.%sdirect:%smemory_slicememory_slice_1bitdirect%d%s[%d:0].%sdirect%d_%d%s[%d:%d].%si == pb_type->num_modesstatic_powerpower_per_instancedynamic_powerC_internaldefaultdisable_packingcompletepack_patternmaxminvaluein_portout_port0 == strcmp(Prop, "min")Ck == num_annotationsi == num_interconnectInvalid fc_type '%s'. Must be 'abs' or 'frac'. Unexpeted node of type '%s' (expected optional 'fc_override')Missing expected attribute 'fc_type'Missing expected attribute 'fc_value'Missing expected attribute(s) 'port_name' and/or 'segment_name' is missing child , and no specified in architecture The name '%s' is reserved for auto-sized layouts; please choose another nameUnexpected tag '<%s>'. Expected '' or ''.Unrecognized grid location specification type '%s' layout_tag.name() == std::string("layout")Unexpected tag type '<%s>', expected '' or ''Expected either an or tagExpected at most one tagInputs to LUT primitives must have a port class named as "lut_in".Input to flipflop primitives must have a port class named as "D".Input port of flipflop primitives must have exactly one pin. Found %d.Output to LUT primitives must have a port class named as "lut_in".Output port of LUT primitives must have exactly one pin. Found %d.Output to flipflop primitives must have a port class named as "D".Output port of flipflop primitives must have exactly one pin. Found %d.Clock to flipflop primitives must have a port class named as "clock".Clock port of flipflop primitives must have exactly one pin. Found %d.Wire capacitance defined for port '%s'. This is an invalid option for the parent pb_type '%s' power estimation method.Wire length defined for port '%s'. This is an invalid option for the parent pb_type '%s' power estimation method.Multiple wire properties defined for port '%s', pb_type '%s'.Wire relative length defined for port '%s'. This is an invalid option for the parent pb_type '%s' power estimation method.Buffer size defined for port '%s'. This is an invalid option for the parent pb_type '%s' power estimation method.Unknown class '%s' in pb_type '%s' %s primitives must contain exactly one input port and one output port.Found '%d' input port(s) and '%d' output port(s) for '%s'Invalid power estimation method for pb_type '%s'Duplicate port names in pb_type '%s': port '%s' strcmp(lut_pb_type->ports[1].port_class, "lut_out") == 0strcmp(lut_pb_type->ports[0].port_class, "lut_out") == 0strcmp(lut_pb_type->ports[1].port_class, "lut_in") == 0memory %s has inconsistent number of data bits %d and %d count_children(Parent, "mode", loc_data, ReqOpt::OPTIONAL) == 0pb_type->class_type == UNKNOWN_CLASSDuplicate mode name: '%s' in pb_type '%s'. . has been replaced with / between sequential primitive ports.pb_type->ports[i].is_clock && pb_type->ports[i].type == IN_PORTmode '%s[%s]' is defined by user to be disabled in packing Duplicate pb_type name: '%s' in mode: '%s'. 0 == strcmp(Cur.name(), "mux")Duplicate interconnect name: '%s' in mode: '%s'. annotation->output_pins != nullptr || annotation->input_pins != nullptrFailed to find either 'max' or 'min' attribute required for <%s> in <%s>Unknown port type %s in %s in %si == annotation->num_value_prop_pairs}}_}}}kkProcessLutClassProcessPb_TypeProcessPinToPinAnnotationsProcessInterconnectProcessLayout%s scaled_by_static_prob_n: %s[%d] %s scaled_by_static_prob: %s[%d] %s scaled_by_static_prob_n: %s %s scaled_by_static_prob: %s %s power method: sum-of-children %s power method: specify-size %s port %s type %d num_pins %d %s static power_per_instance: %e %s dynamic power_per_instance: %e %s power method: error has occcured %s port %s type %d num_pins %d %s annotation %s %s %s %d: %s Could not find port '%s' needed for energy per toggle.Pin-toggle does not support pin indices (%s)Duplicate pin-toggle energy for port '%s'Pin-toggle 'scaled_by_static_prob' must be a single pin (%s)type->class_inf[iclass].type == DRIVERpin_locs->distribution == E_CUSTOM_PIN_DISTRpin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacityphysical_pin_counts[ipin] >= 1type->pin_width_offset[ipin] >= 0 && type->pin_width_offset[ipin] < type->widthtype->pin_height_offset[ipin] >= 0 && type->pin_height_offset[ipin] < type->heightArchitecture file '%s' may be in incorrect format. Expecting .xml format for architecture files. Logical Block %s does not have any equivalent tiles. Physical Tile %s has a different value for the ignored pin (physical pin: %d, logical pin: %d) different from the corresponding pins of the other equivalent site %s .Physical Tile %s has a different value for the global pin (physical pin: %d, logical pin: %d) different from the corresponding pins of the other equivalent sites .No pb_type found for model %s Port %s of model %s, has an unrecognized type %s Logical pin %d not present in pin mapping between Tile %s and Block %s. Error: Unexpected # of arguments. Expected 3 found %d arguments ---------------------------------------------------------------------------------------read_arch - Read a VPR architecture file and output internal data structuresUsage: read_arch ex: read_arch k4_n10.xml 1 arch_data.out Read timing-driven architecture k4_n10.xml and output the results to arch_data.out------------------------------------------------------------------------------- Read architecture file and print library data structures into an output file------------------------------------------------------------------------------ Inputs: architecture %s timing_driven %d output file %s Error opening file %s for %s access: %s. ************************************************* ************************************************* Layout: '%s' Type: auto Aspect_Ratio: %f /home/mdasoh/src/symbiflow/vtr-verilog-to-routing/libs/libarchfpga/src/echo_arch.cppgrid_layout.grid_type == GridDefType::FIXEDLayout: '%s' Type: fixed Width: %d Height %d Sizing: R_minW_nmos %e R_minW_pmos %e Area: grid_logic_tile_area %e x: type gaussian peak %e width %e Xpeak %e dc %e x: type pulse peak %e width %e Xpeak %e dc %e x: distr dleta peak %e Xpeak %e dc %e y: type gaussian peak %e width %e Xpeak %e dc %e y: type pulse peak %e width %e Xpeak %e dc %e y: distr dleta peak %e Xpeak %e dc %e Switch Block: type wilton fs %d Switch Block: type universal fs %d Switch Block: type subset fs %d Input Connect Block Switch Name: %s Switch[%d]: name %s type mux Switch[%d]: name %s type tristate Switch[%d]: name %s type short Switch[%d]: name %s type buffer arch->Switches[i].type() == SwitchType::PASS_GATE Switch[%d]: name %s type pass_gate #Tdel values %d buf_size %e mux_trans_size %e Segment[%d]: frequency %d length %d R_metal %e C_metal %e type bidir wire_switch %s arch_opin_switch %s Direct[%d]: name %s from_pin %s to_pin %s x_offset %d y_offset %d z_offset %d local_interconnect C_wire %e factor %f logical_effort_factor %f trans_per_sram_bit %f Clock[%d]: buffer_size auto C_wire %e Clock[%d]: buffer_size %e C_wire %e stat_prob %f switch_density %f period %e Input Ports: "%s" "%d" min_size="%d" Output Ports: "%s" "%d" min_size="%d" Failed to process architecture %s: %s %s power method: undefined %s power method: ignore %s power method: auto-size %s buffer_size %s %s buffer_size %f %s wire_cap: %e %s wire_len(abs): %e %s wire_len(rel): %f %s wire_len: %s %s power method: pin-toggle %s energy_per_toggle %e %s power method: C-internal %s dynamic c-internal: %e %s power method: absolute %spb_type name: %s %s blif_model: %s %s class_type: %d %s num_modes: %d %s num_ports: %d %s mode %s: %s interconnect %d %s %s %s annotation %s %s %d: %s %s power %e %e scaled_by_static_prob_nside_index == num_sidesipin == type->num_pinsipin == input_pins.size()ipin == output_pins.size()max(w+1,W)max(h+1,H)Storage size exceeded.Pos is out of range..xmlvector::_M_realloc_insertSHA256:modelsinpadoutpadclkdeviceswitchlistsegmentlistswitchblocklistcomplexblocklisttilesdirectlistclocknetworksclocksReading in architecturePrinting ResultsPrinting architecture... Device Info: Channel Width Distribution: x: type uniform peak %e Invalid Distribution! y: type uniform peak %e Switch List: R %e Cin %e Cout %e power_buffer_size auto power_buffer_size %e Segment List: type unidir mux_name %s cb 1 0 sb Direct List: Power: Clock: Printing user models Printing library models Model: "%s" pb_type %d: "%s" Type: "%s" capacity: %d width: %d height: %d num_drivers: %d fc_value_type: ABSOLUTEFRACTIONAL fc_value: %f segment: %s pins: %d num_receivers: %d index: %d Equivalent Site: %s Done@PrintArchInfoEchoArchg jgrn<:ORQhك[XmlReadArchLoadPinLocenergy_per_togglscaled_by_static................;4  $Lt̐֐<d^Бp4P$ ƒ ВT##%$$TX%$&&%,'ז''`((ۚd)).0*|+ʝ+,,-t-. ./8/Fl2V33,4"7Z8|9'9:d::8D;;کd<|<j<(=۫>>ϰ ??)@@i@NAAʴABh8BXBεxBܶBCp|DD,EDEHEnEGN\H^H@JԽJ0LFLMNNvNOE$P{PTQ$QXRS,TT4UU4VV?<ApCDE`F0GGHH`I JJ$LPM,OS@S<UXZP\]dd4eiLplmmmn8nLr@ssvwwx`xx py, y@ {T {h | } `~ ~!8!pL!!Ђ!! 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