Index of /s/sys/buster-libre-soc/home/mdasoh/src/symbiflow/vtr-verilog-to-routing/libs/EXTERNAL/libyosys/manual/PRESENTATION_ExSyn

	Name	Last modified	Size	Description
	Parent Directory		-
	Makefile	2024-09-14 02:34	462
	abc_01.v	2024-09-14 02:34	168
	abc_01.ys	2024-09-14 02:34	138
	abc_01_cells.lib	2024-09-14 02:34	1.3K
	abc_01_cells.v	2024-09-14 02:34	501
	memory_01.v	2024-09-14 02:34	218
	memory_01.ys	2024-09-14 02:34	71
	memory_02.v	2024-09-14 02:34	630
	memory_02.ys	2024-09-14 02:34	98
	opt_01.v	2024-09-14 02:34	78
	opt_01.ys	2024-09-14 02:34	53
	opt_02.v	2024-09-14 02:34	76
	opt_02.ys	2024-09-14 02:34	53
	opt_03.v	2024-09-14 02:34	102
	opt_03.ys	2024-09-14 02:34	53
	opt_04.v	2024-09-14 02:34	271
	opt_04.ys	2024-09-14 02:34	59
	proc_01.v	2024-09-14 02:34	134
	proc_01.ys	2024-09-14 02:34	57
	proc_02.v	2024-09-14 02:34	151
	proc_02.ys	2024-09-14 02:34	57
	proc_03.v	2024-09-14 02:34	149
	proc_03.ys	2024-09-14 02:34	57
	techmap_01.v	2024-09-14 02:34	90
	techmap_01.ys	2024-09-14 02:34	85
	techmap_01_map.v	2024-09-14 02:34	476