Index of /s/sys/buster-libre-soc/home/mdasoh/src/symbiflow/vtr-verilog-to-routing/libs/EXTERNAL/libyosys/techlibs/quicklogic

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[ ]Makefile.inc2024-09-14 02:34 866  
[ ]abc9_map.v2024-09-14 02:34 771  
[ ]abc9_model.v2024-09-14 02:34 197  
[ ]abc9_unmap.v2024-09-14 02:34 384  
[ ]cells_sim.v2024-09-14 02:34 366  
[ ]lut_sim.v2024-09-14 02:34 1.8K 
[ ]pp3_cells_map.v2024-09-14 02:34 499  
[ ]pp3_cells_sim.v2024-09-14 02:34 5.9K 
[ ]pp3_ffs_map.v2024-09-14 02:34 194  
[ ]pp3_latches_map.v2024-09-14 02:34 258  
[ ]pp3_lut_map.v2024-09-14 02:34 928  
[TXT]synth_quicklogic.cc2024-09-14 02:34 6.8K 
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