Index of /s/sys/buster-libre-soc/home/mdasoh/src/symbiflow/vtr-verilog-to-routing/libs/EXTERNAL/libyosys/techlibs/xilinx

[ICO]NameLast modifiedSizeDescription

[PARENTDIR]Parent Directory  -  
[TXT]Makefile.inc2024-09-14 02:34 3.5K 
[TXT]abc9_model.v2024-09-14 02:34 1.5K 
[TXT]arith_map.v2024-09-14 02:34 4.5K 
[TXT]brams_init.py2024-09-14 02:34 2.3K 
[TXT]cells_map.v2024-09-14 02:34 16K 
[TXT]cells_sim.v2024-09-14 02:34 157K 
[TXT]cells_xtra.py2024-09-14 02:34 32K 
[TXT]cells_xtra.v2024-09-14 02:34 1.3M 
[TXT]ff_map.v2024-09-14 02:34 4.8K 
[TXT]lut4_lutrams.txt2024-09-14 02:34 228  
[TXT]lut6_lutrams.txt2024-09-14 02:34 1.7K 
[TXT]lut_map.v2024-09-14 02:34 3.4K 
[TXT]lutrams_map.v2024-09-14 02:34 8.2K 
[TXT]mux_map.v2024-09-14 02:34 2.4K 
[TXT]synth_xilinx.cc2024-09-14 02:34 23K 
[DIR]tests/2024-09-14 02:34 -  
[TXT]xc2v_brams.txt2024-09-14 02:34 561  
[TXT]xc2v_brams_map.v2024-09-14 02:34 5.7K 
[TXT]xc3s_mult_map.v2024-09-14 02:34 266  
[TXT]xc3sa_brams.txt2024-09-14 02:34 814  
[TXT]xc3sda_brams.txt2024-09-14 02:34 621  
[TXT]xc3sda_dsp_map.v2024-09-14 02:34 560  
[TXT]xc4v_dsp_map.v2024-09-14 02:34 661  
[TXT]xc5v_dsp_map.v2024-09-14 02:34 785  
[TXT]xc6s_brams.txt2024-09-14 02:34 1.4K 
[TXT]xc6s_brams_map.v2024-09-14 02:34 5.6K 
[TXT]xc6s_dsp_map.v2024-09-14 02:34 562  
[TXT]xc7_brams_map.v2024-09-14 02:34 8.3K 
[TXT]xc7_dsp_map.v2024-09-14 02:34 884  
[TXT]xc7_xcu_brams.txt2024-09-14 02:34 2.7K 
[TXT]xcu_brams_map.v2024-09-14 02:34 8.5K 
[TXT]xcu_dsp_map.v2024-09-14 02:34 882  
[TXT]xcup_urams.txt2024-09-14 02:34 256  
[TXT]xcup_urams_map.v2024-09-14 02:34 895  
[TXT]xilinx_dffopt.cc2024-09-14 02:34 12K 

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