Index of /s/sys/buster-libre-soc/home/mdasoh/yosys/tests/asicworld

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[ ]README2024-09-14 01:26 59  
[ ]code_tidbits_wire_example.v2024-09-14 01:26 106  
[ ]code_verilog_tutorial_simple_if.v2024-09-14 01:26 126  
[ ]code_verilog_tutorial_tri_buf.v2024-09-14 01:26 126  
[ ]code_hdl_models_encoder_4to2_gates.v2024-09-14 01:26 130  
[ ]code_verilog_tutorial_simple_function.v2024-09-14 01:26 132  
[ ]code_tidbits_reg_combo_example.v2024-09-14 01:26 134  
[ ]code_verilog_tutorial_bus_con.v2024-09-14 01:26 141  
[ ]code_verilog_tutorial_task_global.v2024-09-14 01:26 143  
[ ]code_verilog_tutorial_if_else.v2024-09-14 01:26 146  
[ ]code_verilog_tutorial_mux_21.v2024-09-14 01:26 150  
[ ]code_verilog_tutorial_which_clock.v2024-09-14 01:26 154  
[ ]code_tidbits_blocking.v2024-09-14 01:26 158  
[ ]code_verilog_tutorial_multiply.v2024-09-14 01:26 161  
[ ]code_tidbits_nonblocking.v2024-09-14 01:26 165  
[ ]code_verilog_tutorial_always_example.v2024-09-14 01:26 175  
[ ]code_hdl_models_d_latch_gates.v2024-09-14 01:26 182  
[ ]code_verilog_tutorial_d_ff.v2024-09-14 01:26 185  
[ ]code_hdl_models_decoder_2to4_gates.v2024-09-14 01:26 203  
[ ]code_verilog_tutorial_flip_flop.v2024-09-14 01:26 205  
[ ]code_tidbits_reg_seq_example.v2024-09-14 01:26 217  
[ ]code_verilog_tutorial_escape_id.v2024-09-14 01:26 259  
[ ]code_tidbits_syn_reset.v2024-09-14 01:26 262  
[ ]code_tidbits_asyn_reset.v2024-09-14 01:26 285  
[ ]code_verilog_tutorial_n_out_primitive.v2024-09-14 01:26 290  
[TXT]run-test.sh2024-09-14 01:26 311  
[ ]code_verilog_tutorial_good_code.v2024-09-14 01:26 345  
[ ]code_hdl_models_d_ff_gates.v2024-09-14 01:26 349  
[ ]code_verilog_tutorial_comment.v2024-09-14 01:26 364  
[ ]code_hdl_models_half_adder_gates.v2024-09-14 01:26 378  
[ ]code_verilog_tutorial_addbit.v2024-09-14 01:26 382  
[ ]code_verilog_tutorial_decoder.v2024-09-14 01:26 387  
[ ]code_verilog_tutorial_decoder_always.v2024-09-14 01:26 389  
[ ]code_hdl_models_mux_2to1_gates.v2024-09-14 01:26 456  
[ ]code_hdl_models_parity_using_bitwise.v2024-09-14 01:26 457  
[ ]code_verilog_tutorial_explicit.v2024-09-14 01:26 472  
[ ]code_verilog_tutorial_parallel_if.v2024-09-14 01:26 473  
[ ]code_hdl_models_full_adder_gates.v2024-09-14 01:26 495  
[ ]code_verilog_tutorial_counter.v2024-09-14 01:26 502  
[ ]code_verilog_tutorial_v2k_reg.v2024-09-14 01:26 520  
[ ]code_hdl_models_full_subtracter_gates.v2024-09-14 01:26 575  
[ ]code_hdl_models_decoder_using_assign.v2024-09-14 01:26 582  
[ ]code_hdl_models_parity_using_assign.v2024-09-14 01:26 644  
[ ]code_hdl_models_mux_using_assign.v2024-09-14 01:26 698  
[ ]code_hdl_models_dff_sync_reset.v2024-09-14 01:26 711  
[ ]code_hdl_models_tff_sync_reset.v2024-09-14 01:26 712  
[ ]code_hdl_models_up_counter.v2024-09-14 01:26 718  
[ ]code_hdl_models_parity_using_function.v2024-09-14 01:26 731  
[ ]code_hdl_models_dff_async_reset.v2024-09-14 01:26 733  
[ ]code_hdl_models_tff_async_reset.v2024-09-14 01:26 733  
[ ]code_hdl_models_mux_using_case.v2024-09-14 01:26 775  
[ ]code_hdl_models_mux_using_if.v2024-09-14 01:26 783  
[ ]code_hdl_models_lfsr_updown.v2024-09-14 01:26 790  
[ ]code_hdl_models_up_down_counter.v2024-09-14 01:26 804  
[ ]code_hdl_models_one_hot_cnt.v2024-09-14 01:26 813  
[ ]code_verilog_tutorial_first_counter_tb.v2024-09-14 01:26 814  
[ ]code_hdl_models_rom_using_case.v2024-09-14 01:26 890  
[ ]code_hdl_models_up_counter_load.v2024-09-14 01:26 891  
[ ]code_verilog_tutorial_parity.v2024-09-14 01:26 944  
[ ]code_hdl_models_lfsr.v2024-09-14 01:26 965  
[ ]code_hdl_models_clk_div.v2024-09-14 01:26 1.0K 
[ ]code_hdl_models_gray_counter.v2024-09-14 01:26 1.0K 
[ ]code_hdl_models_arbiter_tb.v2024-09-14 01:26 1.0K 
[ ]code_hdl_models_encoder_using_case.v2024-09-14 01:26 1.1K 
[ ]code_hdl_models_GrayCounter.v2024-09-14 01:26 1.1K 
[ ]code_verilog_tutorial_fsm_full_tb.v2024-09-14 01:26 1.2K 
[ ]code_hdl_models_decoder_using_case.v2024-09-14 01:26 1.2K 
[ ]code_hdl_models_serial_crc.v2024-09-14 01:26 1.3K 
[ ]code_hdl_models_pri_encoder_using_assign.v2024-09-14 01:26 1.3K 
[ ]code_hdl_models_clk_div_45.v2024-09-14 01:26 1.4K 
[ ]xfirrtl2024-09-14 01:26 1.6K 
[ ]code_verilog_tutorial_first_counter.v2024-09-14 01:26 1.6K 
[ ]code_hdl_models_parallel_crc.v2024-09-14 01:26 1.6K 
[ ]code_hdl_models_cam.v2024-09-14 01:26 1.7K 
[ ]code_hdl_models_encoder_using_if.v2024-09-14 01:26 1.7K 
[ ]code_tidbits_fsm_using_single_always.v2024-09-14 01:26 2.0K 
[ ]code_specman_switch_fabric.v2024-09-14 01:26 2.2K 
[ ]code_verilog_tutorial_counter_tb.v2024-09-14 01:26 2.5K 
[ ]code_tidbits_fsm_using_always.v2024-09-14 01:26 2.7K 
[ ]code_tidbits_fsm_using_function.v2024-09-14 01:26 2.8K 
[ ]code_verilog_tutorial_fsm_full.v2024-09-14 01:26 2.9K 
[ ]code_hdl_models_arbiter.v2024-09-14 01:26 3.7K 
[ ]code_hdl_models_uart.v2024-09-14 01:26 3.7K 
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