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Changes command mode from CONFIG to EXEC. Unless 'noinit' is called, this command is called automatically at the end of startup.dir to search for config files and scriptsopenocd_mainhandle_init_commandsetup_command_handler# Defines basic Tcl procs that must exist for OpenOCD scripts to work. # # Embedded into OpenOCD executable # # We need to explicitly redirect this to the OpenOCD command # as Tcl defines the exit proc proc exit {} { ocd_throw exit } # All commands are registered with an 'ocd_' prefix, while the "real" # command is a wrapper that calls this function. Its primary purpose is # to discard 'handler' command output, proc ocd_bouncer {name args} { set cmd [format "ocd_%s" $name] set type [eval ocd_command type $cmd $args] set errcode error if {$type == "native"} { return [eval $cmd $args] } else {if {$type == "simple"} { set errcode [catch {eval $cmd $args}] if {$errcode == 0} { return "" } else { # 'classic' commands output error message as part of progress output set errmsg "" } } else {if {$type == "group"} { catch {eval ocd_usage $name $args} set errmsg [format "%s: command requires more arguments" \ [concat $name " " $args]] } else { set errmsg [format "invalid subcommand \"%s\"" $args] }}} return -code $errcode $errmsg } # Try flipping / and \ to find file if the filename does not # match the precise spelling proc find {filename} { if {[catch {ocd_find $filename} t]==0} { return $t } if {[catch {ocd_find [string map {\ /} $filename} t]==0} { return $t } if {[catch {ocd_find [string map {/ \\} $filename} t]==0} { return $t } # make sure error message matches original input string return -code error "Can't find $filename" } add_usage_text find "" add_help_text find "print full path to file according to OpenOCD search rules" # Find and run a script proc script {filename} { uplevel #0 [list source [find $filename]] } add_help_text script "filename of OpenOCD script (tcl) to run" add_usage_text script "" ######### # Defines basic Tcl procs for OpenOCD JTAG module # Executed during "init". Can be overridden # by board/target/... scripts proc jtag_init {} { if {[catch {jtag arp_init} err]!=0} { # try resetting additionally init_reset startup } } # This reset logic may be overridden by board/target/... scripts as needed # to provide a reset that, if possible, is close to a power-up reset. # # Exit requirements include: (a) JTAG must be working, (b) the scan # chain was validated with "jtag arp_init" (or equivalent), (c) nothing # stays in reset. No TAP-specific scans were performed. It's OK if # some targets haven't been reset yet; they may need TAP-specific scans. # # The "mode" values include: halt, init, run (from "reset" command); # startup (at OpenOCD server startup, when JTAG may not yet work); and # potentially more (for reset types like cold, warm, etc) proc init_reset { mode } { if {[using_jtag]} { jtag arp_init-reset } } ######### # TODO: power_restore and power_dropout are currently neither # documented nor supported except on ZY1000. proc power_restore {} { echo "Sensed power restore, running reset init and halting GDB." reset init # Halt GDB so user can deal with a detected power restore. # # After GDB is halted, then output is no longer forwarded # to the GDB console. set targets [target names] foreach t $targets { # New event script. $t invoke-event arp_halt_gdb } } add_help_text power_restore "Overridable procedure run when power restore is detected. Runs 'reset init' by default." proc power_dropout {} { echo "Sensed power dropout." } ######### # TODO: srst_deasserted and srst_asserted are currently neither # documented nor supported except on ZY1000. proc srst_deasserted {} { echo "Sensed nSRST deasserted, running reset init and halting GDB." reset init # Halt GDB so user can deal with a detected reset. # # After GDB is halted, then output is no longer forwarded # to the GDB console. set targets [target names] foreach t $targets { # New event script. $t invoke-event arp_halt_gdb } } add_help_text srst_deasserted "Overridable procedure run when srst deassert is detected. Runs 'reset init' by default." proc srst_asserted {} { echo "Sensed nSRST asserted." } # measure actual JTAG clock proc measure_clk {} { set start_time [ms]; set iterations 10000000; runtest $iterations; echo "Running at more than [expr $iterations.0 / ([ms]-$start_time)] kHz"; } add_help_text measure_clk "Runs a test to measure the JTAG clk. Useful with RCLK / RTCK." proc default_to_jtag { f args } { set current_transport [transport select] if {[using_jtag]} { eval $f $args } { error "session transport is \"$current_transport\" but your config requires JTAG" } } proc jtag args { eval default_to_jtag jtag $args } proc jtag_rclk args { eval default_to_jtag jtag_rclk $args } proc jtag_ntrst_delay args { eval default_to_jtag jtag_ntrst_delay $args } proc jtag_ntrst_assert_width args { eval default_to_jtag jtag_ntrst_assert_width $args } # BEGIN MIGRATION AIDS ... these adapter operations originally had # JTAG-specific names despite the fact that the operations were not # specific to JTAG, or otherewise had troublesome/misleading names. # # FIXME phase these aids out after about April 2011 # proc jtag_khz args { echo "DEPRECATED! use 'adapter_khz' not 'jtag_khz'" eval adapter_khz $args } proc jtag_nsrst_delay args { echo "DEPRECATED! use 'adapter_nsrst_delay' not 'jtag_nsrst_delay'" eval adapter_nsrst_delay $args } proc jtag_nsrst_assert_width args { echo "DEPRECATED! use 'adapter_nsrst_assert_width' not 'jtag_nsrst_assert_width'" eval adapter_nsrst_assert_width $args } # stlink migration helpers proc stlink_device_desc args { echo "DEPRECATED! use 'hla_device_desc' not 'stlink_device_desc'" eval hla_device_desc $args } proc stlink_serial args { echo "DEPRECATED! use 'hla_serial' not 'stlink_serial'" eval hla_serial $args } proc stlink_layout args { echo "DEPRECATED! use 'hla_layout' not 'stlink_layout'" eval hla_layout $args } proc stlink_vid_pid args { echo "DEPRECATED! use 'hla_vid_pid' not 'stlink_vid_pid'" eval hla_vid_pid $args } proc stlink args { echo "DEPRECATED! use 'hla' not 'stlink'" eval hla $args } # END MIGRATION AIDS # Defines basic Tcl procs for OpenOCD target module proc new_target_name { } { return [target number [expr [target count] - 1 ]] } global in_process_reset set in_process_reset 0 # Catch reset recursion proc ocd_process_reset { MODE } { global in_process_reset if {$in_process_reset} { set in_process_reset 0 return -code error "'reset' can not be invoked recursively" } set in_process_reset 1 set success [expr [catch {ocd_process_reset_inner $MODE} result]==0] set in_process_reset 0 if {$success} { return $result } else { return -code error $result } } proc ocd_process_reset_inner { MODE } { set targets [target names] # If this target must be halted... set halt -1 if { 0 == [string compare $MODE halt] } { set halt 1 } if { 0 == [string compare $MODE init] } { set halt 1; } if { 0 == [string compare $MODE run ] } { set halt 0; } if { $halt < 0 } { return -code error "Invalid mode: $MODE, must be one of: halt, init, or run"; } # Target event handlers *might* change which TAPs are enabled # or disabled, so we fire all of them. But don't issue any # target "arp_*" commands, which may issue JTAG transactions, # unless we know the underlying TAP is active. # # NOTE: ARP == "Advanced Reset Process" ... "advanced" is # relative to a previous restrictive scheme foreach t $targets { # New event script. $t invoke-event reset-start } # Use TRST or TMS/TCK operations to reset all the tap controllers. # TAP reset events get reported; they might enable some taps. init_reset $MODE # Examine all targets on enabled taps. foreach t $targets { if {![using_jtag] || [jtag tapisenabled [$t cget -chain-position]]} { $t invoke-event examine-start set err [catch "$t arp_examine allow-defer"] if { $err == 0 } { $t invoke-event examine-end } } } # Assert SRST, and report the pre/post events. # Note: no target sees SRST before "pre" or after "post". foreach t $targets { $t invoke-event reset-assert-pre } foreach t $targets { # C code needs to know if we expect to 'halt' if {![using_jtag] || [jtag tapisenabled [$t cget -chain-position]]} { $t arp_reset assert $halt } } foreach t $targets { $t invoke-event reset-assert-post } # Now de-assert SRST, and report the pre/post events. # Note: no target sees !SRST before "pre" or after "post". foreach t $targets { $t invoke-event reset-deassert-pre } foreach t $targets { # Again, de-assert code needs to know if we 'halt' if {![using_jtag] || [jtag tapisenabled [$t cget -chain-position]]} { $t arp_reset deassert $halt } } foreach t $targets { $t invoke-event reset-deassert-post } # Pass 1 - Now wait for any halt (requested as part of reset # assert/deassert) to happen. Ideally it takes effect without # first executing any instructions. if { $halt } { foreach t $targets { if {[using_jtag] && ![jtag tapisenabled [$t cget -chain-position]]} { continue } # don't wait for targets where examination is deferred # they can not be halted anyway at this point if { ![$t was_examined] && [$t examine_deferred] } { continue } # Wait upto 1 second for target to halt. Why 1sec? Cause # the JTAG tap reset signal might be hooked to a slow # resistor/capacitor circuit - and it might take a while # to charge # Catch, but ignore any errors. catch { $t arp_waitstate halted 1000 } # Did we succeed? set s [$t curstate] if { 0 != [string compare $s "halted" ] } { return -code error [format "TARGET: %s - Not halted" $t] } } } #Pass 2 - if needed "init" if { 0 == [string compare init $MODE] } { foreach t $targets { if {[using_jtag] && ![jtag tapisenabled [$t cget -chain-position]]} { continue } # don't wait for targets where examination is deferred # they can not be halted anyway at this point if { ![$t was_examined] && [$t examine_deferred] } { continue } set err [catch "$t arp_waitstate halted 5000"] # Did it halt? if { $err == 0 } { $t invoke-event reset-init } } } foreach t $targets { $t invoke-event reset-end } } proc using_jtag {} { set _TRANSPORT [ transport select ] expr { [ string first "jtag" $_TRANSPORT ] != -1 } } proc using_swd {} { set _TRANSPORT [ transport select ] expr { [ string first "swd" $_TRANSPORT ] != -1 } } proc using_hla {} { set _TRANSPORT [ transport select ] expr { [ string first "hla" $_TRANSPORT ] != -1 } } ######### # Temporary migration aid. May be removed starting in January 2011. proc armv4_5 params { echo "DEPRECATED! use 'arm $params' not 'armv4_5 $params'" arm $params } # Target/chain configuration scripts can either execute commands directly # or define a procedure which is executed once all configuration # scripts have completed. # # By default(classic) the config scripts will set up the target configuration proc init_targets {} { } proc set_default_target_event {t e s} { if {[$t cget -event $e] == ""} { $t configure -event $e $s } } proc init_target_events {} { set targets [target names] foreach t $targets { set_default_target_event $t gdb-flash-erase-start "reset init" set_default_target_event $t gdb-flash-write-end "reset halt" } } # Additionally board config scripts can define a procedure init_board that will be executed after init and init_targets proc init_board {} { } # deprecated target name cmds proc cortex_m3 args { echo "DEPRECATED! use 'cortex_m' not 'cortex_m3'" eval cortex_m $args } proc cortex_a8 args { echo "DEPRECATED! use 'cortex_a' not 'cortex_a8'" eval cortex_a $args } # Defines basic Tcl procs for OpenOCD server modules # Handle GDB 'R' packet. Can be overridden by configuration script, # but it's not something one would expect target scripts to do # normally proc ocd_gdb_restart {target_id} { # Fix!!! we're resetting all targets here! Really we should reset only # one target reset halt } proc prevent_cps {} { echo "Possible SECURITY ATTACK detected." echo "It looks like somebody is sending POST or Host: commands to OpenOCD." echo "This is likely due to an attacker attempting to use Cross Protocol Scripting" echo "to compromise your OpenOCD instance. Connection aborted." exit } proc POST {args} { prevent_cps } proc Host: {args} { prevent_cps } # Defines basic Tcl procs for OpenOCD flash module # # program utility proc # usage: program filename # optional args: verify, reset, exit and address # proc program_error {description exit} { if {$exit == 1} { echo $description shutdown error } error $description } proc program {filename args} { set exit 0 foreach arg $args { if {[string equal $arg "verify"]} { set verify 1 } elseif {[string equal $arg "reset"]} { set reset 1 } elseif {[string equal $arg "exit"]} { set exit 1 } else { set address $arg } } # make sure init is called if {[catch {init}] != 0} { program_error "** OpenOCD init failed **" 1 } # reset target and call any init scripts if {[catch {reset init}] != 0} { program_error "** Unable to reset target **" $exit } # start programming phase echo "** Programming Started **" if {[info exists address]} { set flash_args "$filename $address" } else { set flash_args "$filename" } if {[catch {eval flash write_image erase $flash_args}] == 0} { echo "** Programming Finished **" if {[info exists verify]} { # verify phase echo "** Verify Started **" if {[catch {eval verify_image $flash_args}] == 0} { echo "** Verified OK **" } else { program_error "** Verify Failed **" $exit } } if {[info exists reset]} { # reset target if requested # also disable target polling, we are shutting down anyway poll off echo "** Resetting Target **" reset run } } else { program_error "** Programming Failed **" $exit } if {$exit == 1} { shutdown } return } add_help_text program "write an image to flash, address is only required for binary images. verify, reset, exit are optional" add_usage_text program " \[address\] \[verify\] \[reset\] \[exit\]" # stm32f0x uses the same flash driver as the stm32f1x # this alias enables the use of either name. proc stm32f0x args { eval stm32f1x $args } # stm32f3x uses the same flash driver as the stm32f1x # this alias enables the use of either name. proc stm32f3x args { eval stm32f1x $args } # stm32f4x uses the same flash driver as the stm32f2x # this alias enables the use of either name. proc stm32f4x args { eval stm32f2x $args } # ease migration to updated flash driver proc stm32x args { echo "DEPRECATED! use 'stm32f1x $args' not 'stm32x $args'" eval stm32f1x $args } proc stm32f2xxx args { echo "DEPRECATED! use 'stm32f2x $args' not 'stm32f2xxx $args'" eval stm32f2x $args } dev_id option value ('%s') is not validfailed loading file %s to pld device %uloaded file %s to pld device %u in %jis %jiuspld device '#%s' is out of bounds'pld init' has already been calledcouldn't register '%s' commands'%s' driver rejected pld deviceprogrammable logic device commandsdriver_name [driver_args ... ]load configuration file into PLDsrc/pld/pld.cInitializing PLDs...pldno pld devices configured#%i: %spld driver '%s' not foundconfigure a PLD deviceinitialize PLD deviceslist configured pld devicespld_num filenamehandle_pld_device_commandhandle_pld_init_commandTap: %s does not existstatus: 0x%8.8xsrc/pld/virtex2.cvirtex2Virtex-II specific commandsread_statread status registerpld_numvirtex2_info->no_jstart option value ('%s') is not validvirtex2 status register: 0x%8.8xvirtex2_read_statBUG: length_size neither 2 nor 4couldn't read unknown_header from file '%s'src/pld/xilinx_bit.ccouldn't stat() %s: %s%s is a directoryEmpty file %scouldn't open %s: %sbit_file: %s %s %s,%s %iread_sectionxilinx_read_bit_fileTranslation from jtag_speed to khz not implementedTranslation from khz to jtag_speed not implementedextra reset_config %s spec (%s)unknown reset_config flag (%s)adapter_nsrst_assert_width: %udelay option value ('%s') is not validkhz option value ('%s') is not validadapter speed: RCLK - adaptiveThe following debug interfaces are available:Interface already configured, ignoringAdapter driver '%s' did not declare which transports it allows; assuming legacy JTAG-onlyThe specified debug interface was not found (%s)With an argument, change to the specified maximum jtag speed. For JTAG, 0 KHz signifies adaptive clocking. With or without argument, display current setting.Returns the name of the currently selected adapter (driver)delay after deasserting SRST in msdelay after asserting SRST in msSelect a debug adapter interface (driver)Declare transports the interface supports.List all built-in debug adapter interfaces (drivers)configure adapter reset behavior[none|trst_only|srst_only|trst_and_srst] [srst_pulls_trst|trst_pulls_srst|combined|separate] [srst_gates_jtag|srst_nogate] [trst_push_pull|trst_open_drain] [srst_push_pull|srst_open_drain] [connect_deassert_srst|connect_assert_srst]src/jtag/adapter.csrst_onlytrst_and_srsttrst_onlyseparatesrst_pulls_trstcombinedtrst_pulls_srst trst_open_drain trst_push_pull srst_nogate srst_gates_jtag srst_push_pull srst_open_drain connect_assert_srst connect_deassert_srstgatingcombinationtrst_typesrst_typeconnect_type%s %s%s%s%s%sadapter_nsrst_delay: %uundefined(no params)adapter speed: %d kHzinterface_list%u: %sadapter_khz[khz]adapter_nameadapter_nsrst_delay[milliseconds]adapter_nsrst_assert_widthdriver_nameinterface_transportstransport ... reset_configdefault_khzdefault_speed_divhandle_interface_commandhandle_reset_config_commandconvert khz to interface specific speed valueJTAG tap: %s %16.16s: 0x%08x (mfg: 0x%3.3x (%s), part: 0x%4.4x, ver: 0x%1.1x)Bad value '%s' captured during DR or IR scan:Specify TAP '%s' by name, not number %uBUG: TAP_RESET is not a valid state for pathmove sequencesBUG: TAP path doesn't finish in a stable stateBUG: %s -> %s isn't a valid TAP transitionjtag_add_clocks() called with TAP in unstable state "%s"No JTAG interface configured yet. Issue 'init' command in startup scripts before communicating with targets.JTAG reset with TLR instead of TRSTCreated Tap: %s @ abs position %d, irlen %d, capture: 0x%x mask: 0x%xDR scan interrogation for IDCODE/BYPASSJTAG scan chain interrogation failed: all %sCheck JTAG interface, timings, target power, etc.Unexpected idcode after end of chain: %d 0x%08xdouble-check your JTAG setup (interface, speed, ...)Trying to use configured scan chain anyway...AUTO %s - use "jtag newtap %s %s -irlen %d -expected-id 0x%08x"%s: IR capture error; saw 0x%0*lx not 0x%0*xIR capture error at bit %d, saw 0x%s not 0x...3Bypassing JTAG setup events due to errorsThere are no enabled taps. AUTO PROBING MIGHT NOT WORK!!Debug Adapter has to be specified, see "interface" commandAdapter driver '%s' did not declare which transports it allows; assuming JTAG-onlyThis adapter doesn't support configurable speedAn adapter speed is not selected in the init script. Insert a call to adapter_khz or jtag_rclk to proceed.adapter-specific clock speed value %dRCLK (adaptive clock speed) not supported - fallback to %d kHzInitializing with hard SRST resetInitializing with hard TRST+SRST reset'srst_nogate' reset_config option is requiredNo Valid JTAG Interface Configured.The selected interface does not support tracingsrc/jtag/core.chave interface set upjtag_trst == 0state != TAP_INVALID check_value: 0x%s check_mask: 0x%sstate != TAP_RESETtrying fallback speed...(unknown)jtag event: %sout_bits != NULLcur_state=%s goal_state=%stms_count < ARRAY_SIZE(moves)field->in_value != NULLBUG: can't assert SRSTTRST/SRST errorSRST line assertedSRST line releasedSRST timings errorBUG: can't assert only SRSTTRST line assertedTRST line releasedzeroesonesInit JTAG chainbit_count < max_taps * 32auto%u%s.%sTAP %s does not have IDCODEtap/device foundUNEXPECTEDexpected %u of %uIR capture validation scan%s: IR capture 0x%0*lxhandle jtag khzhandle jtag rclkBUG: unknown jtag clock modeclock speed %d kHzRCLK (adaptive clock speed)jtag_initreset is not supported on %stransport is not selectedTAP resetTAP setupTAP enabledTAP disabledadapter_config_traceadapter_deassert_resetadapter_assert_resetjtag_power_dropoutjtag_get_speedjtag_rclk_to_speedjtag_config_rclkadapter_khz_to_speedjtag_config_khzjtag_initjtag_init_resetswd_init_resetadapter_quitjtag_validate_ircapturejtag_examine_chain_endjtag_examine_chain_displayjtag_examine_chain_checkjtag_examine_chainjtag_examine_chainjtag_init_inneradapter_initjtag_tap_initdefault_interface_jtag_execute_queuejtag_check_value_maskjtag_add_resetswd_add_resetjtag_add_clocksjtag_add_statemovejtag_add_statemovejtag_add_pathmovejtag_add_plain_dr_scanjtag_add_dr_scanjtag_add_plain_ir_scanjtag_check_value_innerjtag_add_ir_scanjtag_checksjtag_preludejtag_call_event_callbacksjtag_tap_by_stringsrc/jtag/interface.cRUN/IDLEDRSELECTDRCAPTUREDRSHIFTDREXIT1DRPAUSEDREXIT2DRUPDATEIRSELECTIRCAPTUREIRSHIFTIREXIT1IRPAUSEIREXIT2IRUPDATEFATAL: unstable state "%s" in tap_move_ndx()fatal: invalid argument cur_state=%d66666666 066``XPHXpH  tap_state_transitiontap_move_ndx  // %+ 1/0 /10/aice_handle_aice_reset_commandsrc/jtag/aice/aice_interface.caice_handle_aice_custom_restart_script_commandaice_handle_aice_custom_trst_script_commandaice_handle_aice_custom_srst_script_commandCannot find AICE Interface! Please check connection and permissions.aice_handle_aice_count_to_check_dbger_commandcount_to_check_dbger option value ('%s') is not validexpected exactly one argument to aice count_to_check_dbger aice_handle_aice_retry_times_commandretry_times option value ('%s') is not validexpected exactly one argument to aice retry_times aice_handle_aice_adapter_commandexpected exactly one argument to aice adapter aice_handle_aice_serial_commandexpected exactly one argument to aice serial expected exactly one argument to aice desc aice_handle_aice_vid_pid_commandignoring extra IDs in aice vid_pid (maximum is 1 pair)param.vid option value ('%s') is not validparam.pid option value ('%s') is not validNeed exactly one argument to 'aice port'<-- TARGET ERROR! Failed to identify AndesCore JTAG Manufacture ID in the JTAG scan chain. Failed to access EDM registers. -->aice_init_targets: target not found: idcode: %xaice port ['aice_pipe'|'aice_usb']set the aice device descriptionset the serial number of the AICE devicethe vendor and product ID of the AICE deviceset retry times as AICE timeoutset retry times as checking $DBGER statusaice count_to_check_dbger count_of_checkingcustom_srst_script script_file_namecustom_trst_script script_file_namecustom_restart_script script_file_name* %dNo support the jtag clock: %dSupported jtag clocks are:AICE JTAG Interface readyaice_handle_aice_desc_commandaice_handle_aice_port_commandNo AICE port '%s' foundaice_handle_aice_info_commandDescription: %sSerial number: %saice_pipeAdapter: %saice_init_targetsaiceperform aice managementaice [subcommand]show aice infoset the port of the AICEaice desc [desciption string]aice serial [serial string]aice vid_pid (vid pid)*set the file name of adapteraice adapter [adapter name]retry_timesaice retry_times num_of_retrycount_to_check_dbgercustom_srst_scriptset custom srst scriptcustom_trst_scriptset custom trst scriptcustom_restart_scriptset custom restart scriptreset AICEaice resetaice_handle_aice_info_commandaice_handle_aice_port_commandaice_handle_aice_desc_commandaice_handle_aice_serial_commandaice_handle_aice_vid_pid_commandaice_handle_aice_adapter_commandaice_handle_aice_retry_times_commandaice_handle_aice_count_to_check_dbger_commandaice_handle_aice_custom_srst_script_commandaice_handle_aice_custom_trst_script_commandaice_handle_aice_custom_restart_script_commandaice_handle_aice_reset_commandaice_initaice_khzaice_init_targets0u:LS].p waice_usbaice_transport_initno transport selectedcurrent transport %saice_transport_selectToo many parameters-expected-idno memoryMissing CHIP TAP OPTIONS ....Processing option: %soption: %s bad parametererror: %#sInitializing jtag devices...aice_jtaginitialize jtag scan chainarp_initarp_init-resetnewtaptapisenabledtap_nametapenabletapdisableconfigurecgettap_name '-event' event_namenamessrc/jtag/aice/aice_transport.cNo implement: jim_aice_arp_initCreating New Tap, Chip: %s, Tap: %s, Dotted: %s, %d params'jtag init' has already been calledValidates JTAG scan chain against the list of declared TAPs.Uses TRST and SRST to try resetting everything on the JTAG scan chain, then performs 'jtag arp_init'.Create a new TAP instance named basename.tap_type, and appends it to the scan chain.basename tap_type ['-expected_id' number]Returns a Tcl boolean (0/1) indicating whether the TAP is enabled (1) or not (0).Try to enable the specified TAP using the 'tap-enable' TAP event.Try to disable the specified TAP using the 'tap-disable' TAP event.Provide a Tcl handler for the specified TAP event.tap_name '-event' event_name handlerReturn any Tcl handler for the specified TAP event.Returns list of all JTAG tap names.handle_aice_init_commandjim_aice_arp_initaice_init_resetjim_aice_newtap_cmdaice_transport_selectaice_transport_initaice_usb_memory_access, access channel: %uaice_write illegal out_length=%i (max=%i)WRITE_CTRL, address: 0x%x, data: 0x%xaice_usb_read failed (requested=%u, result=%d)aice command error (command=0x%x, response=0x%x)BATCH_BUFFER_WRITE, # of DATA %08xaice_usb_read failed (requested=%d, result=%d)aice command timeout (command=0x%x, response=0x%x)Flush usb packets (AICE_COMMAND_MODE_PACK)Flush usb packets (AICE_COMMAND_MODE_BATCH)READ_CTRL response, data: 0x%xAICE version: hw_ver = 0x%x, fw_ver = 0x%x, fpga_ver = 0x%xWRITE_DIM, COREID: %u, data: 0x%08x, 0x%08x, 0x%08x, 0x%08xUser specifies higher jtag clock than TCK_SCAN clockREAD_DTR_TO_BUFFER, COREID: %uWRITE_DTR, COREID: %u, data: 0x%xWRITE_DTR_FROM_BUFFER, COREID: %uREAD_MISC, COREID: %u, address: 0x%xREAD_MISC response, data: 0x%xWRITE_MISC, COREID: %u, address: 0x%x, data: 0x%xprogram EDM, unsupported misc register: %sprogram EDM, unsupported command: %saice_usb_memory_mode, memory select: %uREAD_EDMSR, COREID: %u, address: 0x%xREAD_EDMSR response, data: 0x%xaice_write_reg, reg_no: 0x%08x, value: 0x%08x<-- TARGET ERROR! AICE failed to write to the DTR register. --><-- TARGET WARNING! Exception is detected and suppressed. --><-- TARGET ERROR! Insufficient security privilege to execute the debug operations. -->Timeout (1000ms) waiting for $DBGER status being 0x%08x<-- TARGET ERROR! Debug operations do not finish properly: 0x%08x0x%08x0x%08x0x%08x. --><-- TARGET ERROR! Debug operations do not finish properly:0x%08x 0x%08x 0x%08x 0x%08x. -->aice_usb_write_memory_unit, addr: 0x%08x, size: %u, count: %uaice_usb_read_memory_unit, addr: 0x%08x, size: %u, count: %u<-- TARGET ERROR! The debug target failed to update the DTR register. --> icache set: %u, way: %u, line size: %u, log2(set): %u, log2(line_size): %u dcache set: %u, way: %u, line size: %u, log2(set): %u, log2(line_size): %uaice_usb_read_tlb, virtual address: 0x%08xaice_usb_write_reg_64, %s, low: 0x%08x, high: 0x%08x aice_backup_edm_registers - EDM_CTL: 0x%08x, DEX_USE_PSW: %sWRITE_EDMSR, COREID: %u, address: 0x%x, data: 0x%xaice_init_edm_registers - EDM_CTL: 0x%08x<-- TARGET ERROR! Reaching the max interrupt stack level. --><-- TARGET ERROR! Unable to stop the debug target through DBGI. --><-- AICE ERROR! AICE is unplugged. --><-- TARGET ERROR! Target is disconnected with AICE. --><-- TARGET ERROR! Insufficient security privilege. --><-- TARGET ERROR! Reaching the max interrupt stack level; CPU is stalled at 0x%08x for debugging. --><-- TARGET WARNING! The debug target exited the debug mode unexpectedly. -->restore_tmp_registers - r0: 0x%08x, r1: 0x%08xTimeout (1000ms) waiting for halt to completeSCAN_CHAIN response, # of IDs: %uWRITE_MEM_B, COREID: %u, ADDRESS %08x VALUE %08xWRITE_MEM_H, COREID: %u, ADDRESS %08x VALUE %08xWRITE_MEM, COREID: %u, ADDRESS %08x VALUE %08xFASTREAD_MEM, COREID: %u, # of DATA %08xaice_usb_bulk_read_mem, addr: 0x%08x, length: 0x%08xFASTWRITE_MEM, COREID: %u, # of DATA %08xaice_usb_bulk_write_mem, addr: 0x%08x, length: 0x%08xREAD_MEM_B response, data: 0x%02xREAD_MEM_H response, data: 0x%xBATCH_BUFFER_READ, # of DATA %08xsrc/jtag/aice/aice_usb.cWRITE_CTRL responseREAD_CTRL, address: 0x%xAICE initialization startedCannot get AICE version!Cannot initial AICE box!Flush usb packets failedAppend usb packets 0x%02xEXECUTE, COREID: %uEXECUTE responseWRITE_DIM responsecleardbgiSet jtag clock failedCannot set AICE JTAG clock!READ_DTR, COREID: %uREAD_DTR response, data: 0x%xWRITE_DTR responseWRITE_MISC responsewrite_miscgen_port0gen_port1EVA: 0x%08xITYPE: 0x%08xaice_read_reg, reg_no: 0x%08xaice_usb_cache_ctlaice_usb_init_cacheaice_usb_dcache_inval_allaice_usb_dcache_va_invalaice_usb_dcache_wb_allaice_usb_dcache_va_wbaice_usb_icache_inval_allaice_usb_icache_va_invalaice_usb_read_reg_64, %slow: 0x%08x, high: 0x%08x aice_usb_read_regaice_usb_write_regbackup_tmp_registers -Backup target DTR: 0x%08xBackup host DTR: 0x%08xr0: 0x%08x, r1: 0x%08xWRITE_EDMSR responseaice_usb_halt check haltedaice_usb_haltDBGER.CRST is on.aice_restore_edm_registers -aice_usb_runRestore target DTR: 0x%08xRestore host DTR: 0x%08xaice_usb_stepaice_issue_srstaice_issue_reset_holdSCAN_CHAIN, length: 0x0FNo target connectedThe ice chain over 16 targetsREAD_MEM_B, COREID: %uREAD_MEM_H, CORE_ID: %uREAD_MEM, COREID: %uREAD_MEM response, data: 0x%x`0`aice_get_version_infoaice_open_deviceaice_scan_chainaice_usb_set_clockaice_usb_set_jtag_clockaice_issue_reset_holdaice_issue_srstaice_restore_edm_registersaice_restore_tmp_registersaice_usb_runaice_usb_haltaice_usb_stepaice_usb_read_regaice_usb_write_regaice_usb_read_reg_64aice_usb_write_reg_64aice_usb_read_memory_unitaice_usb_write_memory_unitaice_usb_bulk_read_memaice_usb_bulk_write_memaice_backup_tmp_registersaice_init_edm_registersaice_backup_edm_registersaice_usb_stateaice_usb_memory_accessaice_usb_memory_modeaice_usb_read_tlbaice_usb_icache_va_invalaice_usb_icache_inval_allaice_usb_dcache_va_wbaice_usb_dcache_wb_allaice_usb_dcache_va_invalaice_usb_dcache_inval_allaice_usb_init_cacheaice_usb_cache_ctlaice_usb_program_edmcheck_privilegeaice_write_regaice_read_regcheck_suppressed_exceptionaice_check_dbgeraice_do_executeaice_execute_dimaice_usb_executeaice_write_dimaice_batch_buffer_readaice_read_memaice_read_mem_haice_read_mem_baice_fastwrite_memaice_fastread_memaice_write_memaice_write_mem_haice_write_mem_baice_write_edmsraice_read_edmsraice_write_miscaice_read_miscaice_write_dtr_from_bufferaice_write_dtraice_read_dtr_to_bufferaice_read_dtraice_usb_packet_appendaice_write_ctrlaice_usb_writeaice_batch_buffer_writeaice_usb_packet_flushaice_read_ctrlsrc/jtag/drivers/amt_jtagaccel.ccannot open device. check it exists and that user read and write rights are set cannot set compatible mode to deviceamt_jtagaccel timed out while waiting for end of scan, rtck was %s, last AR_STATUS: 0x%2.2xThe parport port was already configured!BUG: %i is not a valid end stateBUG: unknown JTAG command type encounteredconfigure or display the parallel port to useconfigure or display RTCK support__retval >= 0device is already opened/dev/parport%dcannot claim deviceAR_STATUS: 0x%2.2xretval == ERROR_OKamt_jtagaccel RTCK feature %sparport port = %uamt_jtagaccelparport_port[port_num]rtck[enable|disable]UAP:;@9 9UAUA8amt_jtagaccel_scanamt_jtagaccel_end_stateamt_wait_scan_busyamt_wait_scan_busyamt_jtagaccel_state_moveamt_jtagaccel_runtestamt_jtagaccel_execute_queueamt_jtagaccel_speedamt_jtagaccel_handle_parport_port_commandamt_jtagaccel_resetamt_jtagaccel_initamt_jtagaccel_init        @@ trst: %i, srst: %iOVERCURRENTarm-jtag-ewarmjtagew_infoquery armjtagew infosrc/jtag/drivers/arm-jtag-ew.cARM-JTAG-EW TRST/SRST pin set failed failed (%d)armjtagew_tap_append_step, overflowarmjtagew_write illegal out_length=%d (max=%d)usb_bulk_read failed (requested=%d, result=%d)usb_bulk_write failed (requested=%d, result=%d)ARM-JTAG-EW command CMD_GET_VERSION failed (%d)ARM-JTAG-EW firmware version %d.%d, hardware revision %c, SN=%s, Additional info: %sARM-JTAG-EW firmware version %d.%d is untested with this version of OpenOCD. You might experience unexpected behavior.armjtagew_tap_execute, emulator returned error code %d for a CMD_TAP_SHIFT commandarmjtagew_tap_execute, wrong result %d, expected %dARM-JTAG-EW setting speed failed (%d)ARM-JTAG-EW getting speed failed (%d)Requested speed %dkHz, emulator reported %dkHz.U_tg = %d mV, U_aux = %d mV, U_tgpwr = %d mV, I_tgpwr = %d mA, D1 = %d, Target power %s %sVref too low. Check Target PowerARM-JTAG-EW command CMD_GET_TAPHW_STATE failed (%d)Cannot find ARM-JTAG-EW Interface! Please check connection and permissions.ARM-JTAG-EW initial read failed, don't worryARM-JTAG-EW JTAG Interface readyGPFGEEG EDarmjtagew_tap_executearmjtagew_end_statearmjtagew_path_movearmjtagew_tap_append_steparmjtagew_execute_queuearmjtagew_speedarmjtagew_resetarmjtagew_get_statusarmjtagew_usb_writearmjtagew_usb_messagearmjtagew_get_version_infoarmjtagew_init%02x src/jtag/drivers/buspirate.cError reading dataread_count == -1Buspirate SWD mode enabledusage: buspirate_pullup <1|0>usage: buspirate_vreg <1|0>size = %d ret = %dError sending dataWrong !SWD line resetJTAG-to-SWDSWD-to-JTAGSequence %d not supportednormalFASTBuspirate switched to %s modeShutting down buspirate.BBIO1Unable to restart buspirate!error writing :(error readingbuspirate_ledbuspirate_vregbuspirate_pullupRAW1OCD1Could not open serial portBBIOUnsupported binary protocolBuspirate %s Interface ready!usage: buspirate_led <1|0>JUNK%s %s %s reg %X = %08xcmd & SWD_CMD_RnW!(cmd & SWD_CMD_RnW)buspiratebuspirate_adcreads voltages on adc pinschanges the state of pullupchanges the state of ledbuspirate_speedspeed of the interfacebuspirate_modepin mode of the interfacebuspirate_port/dev/ttyUSB0should have read = %d actual size = %dSome stale data from a previous connection was discarded.usage: buspirate_mode usage: buspirate_speed ADC: ADC_Pin = %.02f VPullup = %.02f V33 = %.02f V50 = %.02fError configuring the serial port.Buspirate did not ack speed changeBuspirate did not reply as expected to the speed change commandexecuting tap num bits = %i scans = %itap_chain overflow, bad things will happenBuspirate feature %s is not available in SWD modeBuspirate was unable to set feature %sYou need to specify the serial port!Error while attempting to discard any stale data right after establishing the connection.Entering binary mode, that is %sBuspirate error. Is binary/OpenOCD support enabled?Buspirate did not answer correctly! Do you have correct firmware?Buspirate did not answer correctlyBuspirate did not reply as expected to the configure commandBuspirate two-wire mode configured correctlyExecuting %zu queued transactionsSkipping due to previous errors: %dSWD Read data parity mismatch %x %xIncreased SWD command queue to %zu elementschanges the state of voltage regulatorsname of the serial port to opencaxaa`c``@`_buspirate_swd_initbuspirate_swd_switch_seqbuspirate_swd_read_regbuspirate_swd_queue_cmdbuspirate_swd_write_regbuspirate_swd_run_queuebuspirate_tap_executebuspirate_end_statebuspirate_path_movebuspirate_tap_appendbuspirate_execute_queuebuspirate_jtag_get_adcsbuspirate_handle_vreg_commandbuspirate_handle_pullup_commandbuspirate_handle_led_commandbuspirate_handle_speed_commandbuspirate_handle_mode_commandbuspirate_resetbuspirate_swd_set_featurebuspirate_swd_set_paramsbuspirate_bbio_enableread_and_discard_all_dataread_and_discard_all_databuspirate_initbuspirate_jtag_resetbuspirate_jtag_set_speedbuspirate_serial_readbuspirate_print_bufferbuspirate_serial_writebuspirate_jtag_commandbuspirate_quit{+dc@error writing data: %lserror reading data: %ls%s %s reg %x %xSWD ack not OK: %d %sRead result: %xunable to open HIDAPIunable to allocate memoryCMSIS-DAP: FW Version = %sSWD SupportedCMSIS-DAP: %sJTAG SupportedRTCK not supportedunable to convert serialcmsis-dap JTAG TLR_RESETempty scan, doing nothingCMSIS-DAP: SWD not supportedCMSIS-DAP: JTAG not supportedunable to reallocate memoryCMSIS-DAP: Packet Size = %dCMSIS-DAP: Packet Count = %dConnecting under resetCMSIS-DAP: Interface readycmsis-dapperform CMSIS-DAP managementcmsis_dap_vid_pid(vid pid)* cmsis_dap_serialserial_stringshow cmsis-dap infosrc/jtag/drivers/cmsis_dap_usb.cExecuting %d queued transactionsrefusing to enable sticky overrun detectionCMSIS-DAP transfer count mismatch: expected %d, got %dCannot read product string of device 0x%x:0x%xunable to find CMSIS-DAP deviceunable to open CMSIS-DAP device 0x%x:0x%xignoring extra IDs in cmsis_dap_vid_pid (maximum is %d pairs)incomplete cmsis_dap_vid_pid configuration directivecmsis_dap_vid[i >> 1] option value ('%s') is not validcmsis_dap_pid[i >> 1] option value ('%s') is not validCMSIS-DAP command CMD_DAP_JTAG_SEQ failed.CMSIS-DAP command CMD_DISCONNECT failed.CMSIS-DAP command CMD_LED failed.CMSIS-DAP command CMD_CONNECT failed.CMSIS-DAP failed to connect in mode (%d)CMSIS-DAP command CMD_INFO failed.CMSIS-DAP command CMD_DAP_SWJ_CLOCK failed.reduce speed request: %dkHz to %dkHz maximumexpected exactly one argument to cmsis_dap_serial CMSIS-DAP command CMD_DAP_SWJ_PINS failed.CMSIS-DAP: Interface reset faileddiscarding trailing empty fieldBUG: %s -> %s isn't a valid TAP transition.BUG: unknown JTAG command type 0x%X encounteredSWCLK/TCK = %d SWDIO/TMS = %d TDI = %d TDO = %d nTRST = %d nRESET = %dCMSIS-DAP: Interface Initialised (SWD)CMSIS-DAP: Interface Initialised (JTAG)Unable to allocate memory for CMSIS-DAP queueCMSIS-DAP command CMD_TFER_Configure failed.CMSIS-DAP command CMD_SWD_Configure failed.the vendor ID and product ID of the CMSIS-DAP deviceset the serial number of the adapterCMSIS-DAPtyuw wvtyuuucmsis_dap_swd_switch_seqcmsis_dap_swd_read_regcmsis_dap_swd_write_regcmsis_dap_swd_run_queuecmsis_dap_flushcmsis_dap_pathmovecmsis_dap_end_statecmsis_dap_execute_scancmsis_dap_execute_tlr_resetcmsis_dap_execute_resetcmsis_dap_execute_commandcmsis_dap_speedcmsis_dap_handle_vid_pid_commandcmsis_dap_handle_serial_commandcmsis_dap_cmd_DAP_SWJ_Pinscmsis_dap_cmd_DAP_SWD_Configurecmsis_dap_cmd_DAP_TFER_Configurecmsis_dap_cmd_DAP_SWJ_Clockcmsis_dap_get_statuscmsis_dap_cmd_DAP_Infocmsis_dap_get_version_infocmsis_dap_cmd_DAP_Connectcmsis_dap_get_caps_infocmsis_dap_usb_opencmsis_dap_swd_opencmsis_dap_initcmsis_dap_cmd_DAP_LEDcmsis_dap_usb_xfercmsis_dap_cmd_DAP_Disconnect{src/jtag/drivers/driver.cfield > start_fieldactive == tapreentry == 0field == out_fields + num_tapsfield == out_fields + scan->num_fieldsinterface_jtag_execute_queueinterface_jtag_add_dr_scaninterface_jtag_add_ir_scanreset to: %ssrc/jtag/drivers/dummy.cdummy_tap: %d stable clocksdummy_tap: %sdummy_writedummy_resetdummy interface driver commandsinterface doesn't provide signal '%s'interface can't drive '%s' highinterface can't tri-state '%s'0 && "invalid signal level specifier"ftdi interface using 7 step jtag state transitionsftdi interface using shortest path jtag state transitionsSWD mode is active but SWD_EN signal is not definedinterface configuration doesn't define signal '%s'unknown signal level '%s', use 0, 1 or zftdi samples TDO on %s edge of TCKignoring extra IDs in ftdi_vid_pid (maximum is %d pairs)incomplete ftdi_vid_pid configuration directiveftdi_vid[i >> 1] option value ('%s') is not validftdi_pid[i >> 1] option value ('%s') is not validdata_mask option value ('%s') is not validinput_mask option value ('%s') is not validoe_mask option value ('%s') is not validftdi_channel option value ('%s') is not validftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"jtag_output_init option value ('%s') is not validjtag_direction_init option value ('%s') is not validexpected exactly one argument to ftdi_device_desc BUG: %s is not a stable end stateCan't assert TRST: nTRST signal is not definedCan't assert SRST: nSRST signal is not definedBUG: %s -> %s isn't a valid TAP state transitionBUG: unknown JTAG command type encountered: %derror while flushing MPSSE queue: %dset the USB device description of the FTDI deviceset the serial number of the FTDI deviceset the USB bus location of the FTDI deviceset the channel of the FTDI device that is used as JTAGinitialize the FTDI GPIO signals used to control output-enables and reset signalsdefine a signal controlled by one or more FTDI GPIO as data and/or output enablename [-data mask|-ndata mask] [-oe mask|-noe mask] [-alias|-nalias name]control a layout-specific signalread the value of a layout-specific signalthe vendor ID and product ID of the FTDI deviceset which TCK clock edge is used for sampling TDO - default is rising-edge (Setting to falling-edge may allow signalling speed increase)src/jtag/drivers/ftdi.cSWD_ENSWDIO_OESignal %s = %#06x-data-ndata-input-ninput-oe-noe-alias-naliassignal %s is not definedunknown option '%s'failed to create signal %stms_count <= 8RCLK not supportedcouldn't set FTDI TCK speedFTDI SWD mode enabledTCKTDITMSLEDMPSSE failedSWD Read data parity mismatchnTRSTnSRSTrisingfallingftdiftdi_device_descdescription_stringftdi_serialftdi_location:port[,port]...ftdi_channel(0-3)ftdi_layout_initdata directionftdi_layout_signalftdi_set_signalname (1|0|z)ftdi_get_signalftdi_vid_pidftdi_tdo_sample_edge(rising|falling)`@Pؕcreate_default_signalftdi_swd_initftdi_swd_switch_seqftdi_swd_read_regftdi_swd_queue_cmdftdi_swd_write_regftdi_swd_run_queueftdi_execute_scanftdi_execute_pathmovemove_to_stateftdi_end_stateftdi_execute_resetftdi_execute_commandftdi_execute_queueftdi_speedftdi_handle_device_desc_commandftdi_handle_layout_signal_commandftdi_handle_set_signal_commandftdi_get_signalftdi_handle_get_signal_commandftdi_handle_vid_pid_commandftdi_set_signalftdi_set_signalftdi_initializeftdi_khz{src/jtag/drivers/gw16012.cparport/dev/%s%dopening %s......opengw16012[port_number]gw16012_port option value ('%s') is not validDisplay the address of the I/O port (e.g. 0x378) or the number of the '/dev/parport' device used. If a parameter is provided, first change that port.`` gw16012_end_stategw16012_path_movegw16012_datagw16012_execute_queuegw16012_handle_parport_port_commandgw16012_controlgw16012_resetgw16012_inputgw16012_init_devicejaylink_swo_read() failed: %s.jaylink_swo_stop() failed: %s.jaylink_unregister() failed: %s.jaylink_get_hardware_status() failed: %s.TCK = %u TDI = %u TDO = %u TMS = %u SRST = %u TRST = %uTarget voltage too low. Check target power.Device does not support EMUCOM.channel option value ('%s') is not validlength option value ('%s') is not validChannel is not supported by the device.Channel is not available for the requested amount of data. %u bytes are avilable.Failed to read from channel: %s.Failed to convert data into hexadecimal string.Data must be encoded as hexadecimal pairs.Channel not supported by the device.Failed to write to channel: %s.Only %u bytes written to the channel.IP address: %d.%d.%d.%d [%d.%d.%d.%d]Subnet mask: %d.%d.%d.%d [%d.%d.%d.%d]Need exactly one argument for jlink targetpower.Target power supply is not supported by the device.jaylink_set_target_power() failed: %s.jaylink_get_speeds() failed: %s.Adaptive clocking is not supported by the device.Reduced speed from %d kHz to %d kHz (maximum).jaylink_set_speed() failed: %s.jaylink_get_free_memory() failed: %s.Not enough free device internal memory: %u bytes.Adjusted SWD transaction buffer size to %u bytes.Trace capturing is not supported by the device.Selected pin protocol is not supported.Not enough free device memory to start trace capturing.jaylink_swo_get_speeds() failed: %s.Found suitable frequency divider %u with deviation of %.02f %%.Selected trace frequency is not supported by the device. Please choose a different trace frequency.Maximum permitted deviation is 3.00 %%, but only %.02f %% could be achieved.Using %u bytes device memory for trace capturing.jaylink_start_swo() failed: %s.Retrieval of free memory is not supported by the device.Device has %u bytes of free memory.MAC address: %.02x:%.02x:%.02x:%.02x:%.02x:%.02xMAC address: %.02x:%.02x:%.02x:%.02x:%.02x:%.02x [%.02x:%.02x:%.02x:%.02x:%.02x:%.02x]Device doesn't support reading configuration.Reading configuration is not supported by the device.Ethernet connectivity is not supported by the device.subnet_bits option value ('%s') is not validInvalid MAC address: zero address.Invalid MAC address: multicast address.Need exactly one argument for jlink config mac.Need exactly one argument for jlink config targetpower.Need exactly one argument for jlink config usb.Need exactly one argument for jlink usb.Need exactly one argument for jlink jtag.Need exactly one argument for jlink serial.jaylink_parse_serial_number() failed: %s.BUG: Unknown JTAG command type encountered.jaylink_read_raw_config() failed: %s.Using libjaylink %s (compiled with %s).jaylink_log_set_callback() failed: %s.jaylink_discovery_scan() failed: %s.jaylink_get_devices() failed: %s.No device selected, using first device.jaylink_device_get_serial_number() failed: %s.jaylink_device_get_usb_address() failed: %s.jaylink_get_firmware_version() failed: %s.Device responds empty firmware version string.jaylink_get_caps() failed: %s.jaylink_get_extended_caps() failed: %s.Failed to retrieve hardware version: %s.Failed to read device configuration data.jaylink_register() failed: %s.Device supports JTAG transport only.jaylink_get_available_interfaces() failed: %s.Selected transport is not supported by the device.jaylink_select_interface() failed: %s.Registration failed: maximum number of connections on the device reached.Writing configuration is not supported by the device.Operation not performed due to no changes in the configuration.jaylink_write_raw_config() failed: %s.Failed to read device configuration for verification.Verification of device configuration failed. Please check your device.The new device configuration applies after power cycling the J-Link device.Executing %d queued transactions.Skipping due to previous errors: %d.SWD: Read data parity mismatch.select the JTAG command versionset the USB address of the device that should be usedset the serial number of the device that should be usedaccess the device configuration. If no argument is given this will show the device configurationset the IP address, where A.B.C.D is the IP address, E the bit of the subnet mask, F.G.H.I the subnet maskwrite configuration to the devicesrc/jtag/drivers/jlink.cTarget power supply: %s [%s]Target power supply: %sUSB address: %u [%u]USB address: %uVTarget = %u.%03u VFailed to allocate buffer.IP address: %d.%d.%d.%dSubnet mask: %d.%d.%d.%dInvalid argument: %s.TRST: %i, SRST: %i.jaylink_jtag_io() failed: %s.J-Link device configuration:Invalid MAC address format.%hhdInvalid USB address: %s.Invalid USB address: %u.JTAG command version: %iInvalid serial number: %s.0.1.0jaylink_init() failed: %s.Failed to open device: %s.Hardware version: %u.%02uNo J-Link device found.Sequence %d not supported.jaylink_swd_io() failed: %s.jlinkperform jlink management[2|3]targetpowerset the target power supplyfreememshow free device memoryhwstatusshow the hardware status<0-3>emucomaccess EMUCOM channelwrite to a channel read from a channel set the USB address[0-3][on|off]macset the MAC Address[ff:ff:ff:ff:ff:ff][A.B.C.D[/E] [F.G.H.I]]undo configuration changesFPjlink_swd_switch_seqjlink_swd_read_regjlink_swd_write_regjlink_swd_run_queuejlink_execute_scanjlink_path_movejlink_end_statejlink_execute_commandjlink_speedjlink_handle_config_write_commandjlink_handle_emucom_write_commandjlink_handle_emucom_read_commandjlink_flushjlink_resetselect_interfacejlink_registerread_device_configjaylink_log_handlerjlink_initjlink_quitadjust_swd_buffer_sizecheck_trace_freqcalculate_trace_buffer_sizeconfig_tracepoll_trace{?Q?Y@libusb_open() failed with %susb ep %s %02xClaiming interface %dsrc/jtag/drivers/libusb1_common.clibusb_get_string_descriptor_ascii() failed with %dDevice serial number '%s' doesn't match requested serial '%s'jtag_libusb_choose_interfacestring_descriptor_equaljtag_libusb_openlibusb_get_string_descriptor_ascii() failed with %sctx->write_count < ctx->write_sizectx->write_count + DIV_ROUND_UP(bit_count, 8) <= ctx->write_sizectx->read_count + DIV_ROUND_UP(bit_count, 8) <= ctx->read_sizeunable to purge ftdi rx buffers: %sunable to purge ftdi tx buffers: %slibusb_get_device_list() failed with %slibusb_get_device_descriptor() failed with %scannot determine path to usb device! (more than 7 ports in path)no more tokens in path at step %ilibusb_get_config_descriptor() failed with %slibusb_get_configuration() failed with %slibusb_set_configuration() failed with %slibusb_detach_kernel_driver() failed with %s, trying to continue anywaylibusb_claim_interface() failed with %sfailed to reset FTDI device: %sunsupported FTDI chip type: 0x%04xunrecognized USB device descriptorunable to open ftdi device with vid %s, pid %s, description '%s', serial '%s' at bus location '%s'unable to set latency timer: %sunable to set MPSSE bitmode: %sctx->write_count == 0 && ctx->read_count == 0ctx->write_count > 0 || ctx->read_count == 0libusb_handle_events() failed with %sftdi device did not accept all data: %d, tried %dftdi device did not return all data: %d, expected %dsrc/jtag/drivers/mpsse.clibusb_init() failed with %sdevice path has %i stepsno ':' in pathbus mismatchpath mismatch at step %ino device foundtarget %d Hzfrequency >= 0divisor >= 0actually %d Hzmpsse_flushmpsse_flushmpsse_set_frequencympsse_set_frequencympsse_rtck_configmpsse_divide_by_5_configmpsse_set_divisormpsse_loopback_configmpsse_clock_tms_csbuffer_write_bytebuffer_add_readbuffer_writempsse_purgestring_descriptor_equaldevice_location_equalopen_matching_devicempsse_openopendous_jtag_write illegal out_length=%d (max=%d)opendous_tap_execute, wrong result %d, expected %dopendous_tap_append_step, overflowopendous command 0x%02x failed (%d)No opendous_type specified, using default 'opendous'No matching cable found for %sCannot find opendous Interface! Please check connection and permissions.access opendous HW JTAG command version[usbvlab|usbprog-jtag|opendous]src/jtag/drivers/opendous.copendous hw jtag %iusbprog-jtagopendousopendous JTAG Interface readyopendous_infoshow opendous infoopendous_hw_jtagopendous_typeset opendous typeusbvlabj `jopendous_tap_executeopendous_end_stateopendous_path_moveopendous_tap_append_stepopendous_execute_queueopendous_usb_writeopendous_usb_messageopendous_simple_commandopendous_resetopendous_initvendor command failed, error %dadapter speed not recognized, reverting to 375 kHzunable to open cy7c65215 deviceunable to claim JTAG interfaceno openjtag device description specified, using default 'Open JTAG Project'unable to open ftdi device: %sCan't set baud rate to max: %srequire exactly one argument to openjtag_variant require exactly one argument to openjtag_device_desc BUG: unknown Open JTAG command type encounteredset the USB device description of the OpenJTAGsrc/jtag/drivers/openjtag.cbulk write failed, error %dftdi_write_data: %scould not disable JTAG modulecould not enable JTAG moduleOpen JTAG Projectunable to reset ftdi deviceunable to set latency timerunable to get latency timercurrent latency timer: %uftdi_purge_buffers: %sstandardunknown openjtag variant '%s'bulk read failed, error %dnum_cycles > 16 on run testopenjtagopenjtag_device_descdescription-stringopenjtag_variantset the OpenJTAG variantvariant-stringcy7c65215   openjtag_buf_read_cy7c65215openjtag_execute_runtestopenjtag_execute_commandopenjtag_speedopenjtag_handle_device_desc_commandopenjtag_handle_variant_commandopenjtag_buf_write_standardopenjtag_buf_write_cy7c65215openjtag_init_standardopenjtag_init_cy7c65215openjtag_quit_cy7c65215BUG: sequences with zero length are not allowedBUG: current state (%s) is not stableBUG: can't allocate bit sequenceOSBDM communication error: can't writeOSBDM communication error: can't readOSBDM communication error: reply too smallOSBDM communication error: reply size mismatchOSBDM communication error: reply command mismatchBUG: bit sequence equal or less than 0osbdm->count <= OSBDM_USB_BUFSIZEOSBDM communication error: invalid swap command replyBUG: nTRST signal is not supportedFATAL: can't execute jtag commandsrc/jtag/drivers/osbdm.cNot enough memoryCan't open OSBDM deviceOSBDM initBUG: bit sequence too longBUG: can't allocate bit queuenum_states <= 32Can't allocate bit sequenceosbdmKK`osbdm_swaposbdm_swaposbdm_add_scanosbdm_add_tmsosbdm_add_stableclocksosbdm_add_statemovequeue_add_tailosbdm_add_pathmoveosbdm_add_pathmoveosbdm_execute_commandqueue_allocosbdm_execute_queueosbdm_send_and_recvosbdm_initBX^0 ns is not a valid parport toggling timeno parport speed set - defaulting to zero wait statesparport_exit option value ('%s') is not validparport_port option value ('%s') is not validNo parport cable specified, using default 'wiggler'cannot open device. check it exists and that user read and write rights are set. errno=%dcannot set compatible 1284 mode to deviceSet the layout of the parallel port cable used to connect to the target.Configure the parallel driver to write a known value to the parallel interface on exit.Displays or assigns how many nanoseconds it takes for the hardware to toggle TCK.src/jtag/drivers/parport.cparport toggling time = %u ns choices are '%s' or '%s'parport port = 0x%xopening /dev/parport%d...parport_cable[layout]parport_write_on_exitparport_toggling_time[nanoseconds]wiggler2wiggler_ntrst_invertedold_amt_wigglerarm-jtagchameleondlc5tritonlatticeflashlinkaltiumaspoparport_handle_parport_port_commandparport_handle_parport_toggling_time_commandparport_resetparport_initparport_khzsetting speed to %d, max. TCK freq. is %d MHzsetting speed to %d, max. TCK freq. is %d kHzcouldn't write the requested number of bytes to PRESTO (%u < %u)couldn't read the requested number of bytes from PRESTO (%u < %u)error in previous communication, canceling I/O operationBUG: unexpected TAP condition, TCK lowsearching for PRESTO using libftdiunable to purge PRESTO buffersno response from PRESTO, retryingno response from PRESTO, giving uperror writing PRESTO init sequencePRESTO open, serial number '%s'Cannot open PRESTO, serial number '%s'Configure USB serial number of Presto device.src/jtag/drivers/presto.cPRESTO closedftdi_read_data: %sunable to init libftdi: %sunable to open PRESTO: %sunable to reset PRESTO deviceerror writing to PRESTOCannot open PRESTOprestopresto_serialpresto_jtag_speedpresto_open_libftdipresto_readpresto_writepresto_flushpresto_tdi_flushpresto_jtag_initpresto_jtag_quitfputs: %sfflush: %sfclose: %sremote_bitbang interface quitremote_bitbang_putc: %sTerminating openocd.localhosthost/socket not specifiedConnecting to unix socket %sConnecting to %s:%sgetaddrinfo: %s Failed to connect: %sremote_bitbangremote_bitbang_portport_numberremote_bitbang_hosthost_namesrc/jtag/drivers/remote_bitbang.cremote_bitbang: invalid read response: %c(%i)Initializing remote_bitbang driverfdopen: failed to open read streamfdopen: failed to open write streamremote_bitbang driver initializedSet the port to use to connect to the remote jtag. if 0 or unset, use unix sockets to connect to the remote jtag.Set the host to use to connect to the remote jtag. if port is 0 or unset, this is the name of the unix socket to use.remote_bitbang_init_tcpremote_bitbang_init_unixremote_bitbang_rreadremote_bitbang_putcremote_bitbang_initremote_bitbang_quitsrc/jtag/drivers/rlink.cOpened device, pHDev = %pusb_claim_interface: %sdetach kernel driver: %sinterface claimed!Initialisation failed.Failed to set interface.USB write error: %sUSB read error: %starget detection problemtarget not plugged inMalformed DTC imagedownloadstarting DTC: %s%d is not a supported speed%d/%ddtc_run_download: %senqueuing DTC reply entry: %srlinkWhoops! NumConfigurations is not 1, don't know what to do...Whoops! NumInterfaces is not 1, don't know what to do...RLink firmware version: %d.%d.%dThe rlink device is not of the version that the developers have played with. It may or may not work.Invalid DTC image record type: 0x%02xAn error occurred while trying to load DTC code for speed "%d".The lowest supported JTAG speed is %d KHz(dtc_queue.rq_head != 0) == (dtc_queue.reply_index > 0)dtc_queue.cmd_index < USB_EP2BANK_SIZEdtc_queue.reply_index <= USB_EP2IN_SIZEtoo many retries waiting for DTC statusRead of endpoint 2 returned %d, expected %dscan_size cannot be less than 1 bit$$%%%(%!70110x0!7//dtc_run_downloaddtc_queue_rundtc_queue_runrlink_scanrlink_end_staterlink_path_moverlink_execute_queuedtc_load_from_bufferrlink_speedrlink_resetrlink_initrlink_khzrlink_speed_divDTCDTC***IXj download'3`ـ9ED3< b`ɠ39DC'(E'3+cfailed to enable tap %sfailed to disable tap %scommand '%s' unknown ...-event ...-event unknown event: %sdrscandrscan: jtag execute failedjtag_flush_queue_sleep[sleep in ms]jtag_rclk[fallback_speed_khz]jtag_ntrst_delayjtag_ntrst_assert_widthscan_chainjtag_resettrst_active srst_activeruntestnum_cyclesirscanverify_ircaptureverify_jtagtms_sequence['short'|'long']wait_srst_deassertperform jtag tap actionspost-resettap-enabletap-disableJTAG tap: %s event: %d (%s) action: %stimeout_ms option value ('%s') is not validTimeout must be an integer between 0 and 100000Waiting for srst assert + deassert for at most %dmsenable option value ('%s') is not validnum_clocks option value ('%s') is not validRCLK not supported - fallback to %d kHzsleep_ms option value ('%s') is not validSpecify a single value for tap TapName Enabled IdCode Expected IrLen IrCap IrMask-- ------------------- -------- ---------- ---------- ----- ----- ------%2d %-18s %c 0x%08x %s %5d 0x%02x 0x%02x %s-event drscan with unsafe endstate "%s"drscan: no scan fields suppliedFor debug purposes(simulate long delays of interface) to test performance or change in behavior. Default 0ms.With an argument, change to to use adaptive clocking if possible; else to use the fallback speed. With or without argument, display current setting.delay after deasserting trst in msdelay after asserting trst in msprint current scan chain configurationSet reset line values. Value '1' is active, value '0' is inactive.Move to Run-Test/Idle, and issue TCK for num_cycles.Execute Instruction Register (DR) scan. The specified opcodes are put into each TAP's IR, and other TAPs are put in BYPASS.[tap_name instruction]* ['-endstate' state_name]Display or assign flag controlling whether to verify values captured during Capture-IR.Display or assign flag controlling whether to verify values captured during IR and DR scans.Display or change what style TMS sequences to use for JTAG state transitions: short (default) or long. Only for working around JTAG bugs.Wait for an SRST deassert. Useful for cases where you need something to happen within ms of an srst deassert. Timeout in ms Validates JTAG scan chain against the list of declared TAPs using just the four standard JTAG signals.basename tap_type '-irlen' count ['-enable'|'-disable'] ['-expected_id' number] ['-ignore-version'] ['-ircapture' number] ['-mask' number] Execute Data Register (DR) scan for one TAP. Other TAPs must be in BYPASS mode.tap_name [num_bits value]* ['-endstate' state_name]Returns the number of times the JTAG queue has been flushed.Move JTAG state machine from current state (start_state) to state1, then state2, state3, etc.start_state state1 [state2 [state3 ...]]handle_irscan_commandhandle_wait_srst_deasserthandle_jtag_init_commandJim_Command_drscanjtag_tap_handle_eventjim_jtag_tap_enablerjim_newtap_ir_paramjim_newtap_cmdThe following transports are available:session transport was not selected. Use 'transport select 'Error selecting '%s' as transportNo transport named '%s' is available.Debug adapter does not support any transports? Check config file order.auto-selecting first available session transport "%s". To override use 'transport select '.Transport "%s" was already selectedCan't change session's transport after the initial selection was madeDebug adapter doesn't support any transports?Debug adapter doesn't support '%s' transportCan't modify the set of allowed transports.only one transport option; autoselect '%s'Initialize this session's transportSelect this session's transportsrc/transport/transport.cTransports available:[too many parameters]transport name already usedinvalid transport %sregister '%s'no such transport '%s'transportTransport command grouplist all built-in transports[transport_name]handle_transport_initjim_transport_selecttransport_list_parsetransport_registertransport_selectallow_transports#%s: not probedraw access is %serror while reading filenot erasederase state unknown (marked bad) (block condition unknown) #%i: 0x%8.8x (%dkB) %s%ssrc/flash/nand/tcl.cinvalid target %sEnd of memoryInitializing NAND devices...nand#%i: not probedNAND flash command groupdefines a new NAND banklists available NAND driversinitialize NAND devicesidentify NAND flash devicebank_idcheck_bad_blocksbank_id [offset length]dumpdump from NAND flash deviceverifyverify NAND flash devicewrite to NAND flash deviceraw_accessbank_id ['enable'|'disable']p->use_raw option value ('%s') is not validfailed writing file %s to NAND flash %s at offset 0x%8.8xwrote file %s to NAND flash %s up to offset 0x%8.8x in %fs (%0.3f KiB/s)reading NAND flash page failedNAND flash contents differ at 0x%8.8xverified file %s in NAND flash %s up to offset 0x%8.8x in %fs (%0.3f KiB/s)dumped %zu bytes in %fs (%0.3f KiB/s)offset option value ('%s') is not validerased blocks %lu to %lu on NAND flash device #%s '%s'checked NAND flash device for bad blocks, use "nand info" command to list blocksNAND flash device '%s (%s)' foundi option value ('%s') is not validfirst option value ('%s') is not validlast option value ('%s') is not valid#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %iAvailable NAND flash controller drivers:No valid NAND flash driver found (%s)'%s' driver rejected nand flash. Usage: %s'%s' driver usage field missing'nand init' has already been calledno NAND flash devices configured#%i: %s (%s) pagesize: %i, buswidth: %i, blocksize: %i, blocks: %ibank_id driver target [driver_options ...]list configured NAND flash devicesprint info about one or more NAND flash devices[banknum | first_bank_num last_bank_num]check all or part of NAND flash device for bad blockserase all or subset of blocks on NAND flash devicebank_id filename offset length ['oob_raw'|'oob_only']bank_id filename offset ['oob_raw'|'oob_only'|'oob_softecc'|'oob_softecc_kw']raw access to NAND flash devicecreate_nand_devicehandle_nand_device_commandhandle_nand_init_commandmflash: io error 0x%02xsrc/flash/mflash.cmflash: timeout occuredmflash: wrote %u'th sectorsmflash: read %u'th sectorsmflash: copies %u byte%s is unsupported socmflash: invalid port %d%smflash: verify interface failmflash: verify interface okmflash: reset okmflash: read drive infomflash: set pll okmflash: storage config okmflash: boot config okstoragemflash: erase nand okmflashmflash command groupinitialize mflash devicesbank_num filename addressConfigure MFLASH options.s3c2440pxa270mflash: duration measurement failed: %dmflash: %u (0x%8.8x) sector writemflash: sect num : %ubuff : %pmflash: sect num : %u buff : %pmflash: %u (0x%8.8x) sector readmflash: sect num : %x buff : %pmflash: copies %u byte from sector offset 0x%8.8xmflash: copies %u byte to sector offset 0x%8.8xsize option value ('%s') is not validdump image (address 0x%8.8x size %u) to file %s in %fs (%0.3f kB/s)wrote %zu bytes from file %s in %fs (%0.3f kB/s)mflash_bank->base option value ('%s') is not valid'mflash init' has already been calledInitializing mflash devices...mflash (total %u sectors) found at 0x%8.8xmflash: input freq. is too largemflash: cannot generate valid pllmflash: Fout=%u Hz, feedback=%u,indiv=%u, outdiv=%u, lock=%uconfigure a mflash device banksoc_type base_addr pin_id targetDetect bank configuration informationWrite binary file at the specified address.Write specified number of bytes from a binary file to the specified, address.bank_num filename address size('boot'|'storage'|'pll' frequency)s3c2440_set_gpio_to_outputs3c2440_set_gpio_output_valmg_bank_cmdmg_dsk_drv_infomg_mflash_write_sectsmg_mflash_writemg_mflash_do_read_sectsmg_mflash_read_sectsmg_mflash_readmg_set_pllmg_erase_nandmg_storage_configmg_mflash_do_write_sectsmg_boot_configmg_dsk_waitmg_mflash_rstmg_verify_interfacemg_config_cmdhandle_mflash_init_commandFXALHS2 00s7 FXLT2v0.Gmni-eeSgael A.A8lAחAeͽA@`fA@@xA@@#%d : %s (%s) at 0x%8.8x, size 0x%8.8x, buswidth %u, chipwidth %uimage.base_address option value ('%s') is not validwrote %u bytes from file %s in %fs (%0.3f KiB/s)pattern option value ('%s') is not validcount option value ('%s') is not validVerification error address 0x%08x, read back 0x%02x, expected 0x%02xwrote %u bytes to 0x%8.8x in %fs (%0.3f KiB/s)usage: flash bank flash bank name '%s' already existsc->base option value ('%s') is not validc->size option value ('%s') is not validc->chip_width option value ('%s') is not validc->bus_width option value ('%s') is not valid'%s' driver rejected flash bank at 0x%8.8x; usage: %sno arguments to 'flash list' command'flash init' has already been calledbank_num option value ('%s') is not validflash bank '#%s' is out of boundsp->default_padded_value option value ('%s') is not validDefault padded value set to 0x%x for flash bank %uset option value ('%s') is not validERROR: first sector must be <= last sectorERROR: last sector must be <= %d%s protection for sectors %i through %i on flash bank %dread %ld bytes from file %s and flash bank %u at offset 0x%8.8x in %fs (%0.3f KiB/s)diff %d address 0x%08x. Was 0x%02x instead of 0x%02xMore than 128 errors, the rest are not printed.wrote %ld bytes to file %s from flash bank %u at offset 0x%8.8x in %fs (%0.3f KiB/s)wrote %zu bytes from file %s to flash bank %u at offset 0x%8.8x in %fs (%0.3f KiB/s)erased sectors %u through %u on flash bank %d in %fssuccessfully checked erase stateunknown error when checking erase state of flash bank #%s at 0x%8.8x#%d : %s at 0x%8.8x, size 0x%8.8x, buswidth %i, chipwidth %ierased address 0x%8.8x (length %i) in %fs (%0.3f KiB/s)Define a new bank with the given name, using the specified NOR flash driver.bank_id driver_name base_address size_bytes chip_width_bytes bus_width_bytes target [driver_options ...]Display table with information about flash banks.Returns a list of details about the flash banks.Print information about a flash bank.Check erase state of all blocks in a flash bank.Erase a range of sectors in a flash bank.bank_id first_sector_num last_sector_numErase flash sectors starting at address and continuing for length bytes. If 'pad' is specified, data outside that range may also be erased: the start address may be decreased, and length increased, so that all of the first and last sectors are erased. If 'unlock' is specified, then the flash is unprotected before erasing.['pad'] ['unlock'] address lengthFill n words with 32-bit value, starting at word address. (No autoerase.)Fill n halfwords with 16-bit value, starting at word address. (No autoerase.)Fill n bytes with 8-bit value, starting at word address. (No autoerase.)Write binary data from file to flash bank, starting at specified byte offset from the beginning of the bank.Write an image to flash. Optionally first unprotect and/or erase the region to be used. Allow optional offset from beginning of bank (defaults to zero)[erase] [unlock] filename [offset [file_type]]Read binary data from flash bank to file, starting at specified byte offset from the beginning of the bank.bank_id filename offset lengthRead binary data from flash bank and file, starting at specified byte offset from the beginning of the bank. Compare the contents.Turn protection on or off for a range of protection blocks or sectors in a given flash bank. See 'flash info' output for a list of blocks.bank_id first_block [last_block|'last'] ('on'|'off')Set default flash padded valuesrc/flash/nor/tcl.cauto erase enabledunlockauto unlock enabledno target selectedflash driver '%s' not foundbus_widthchip_widthInitializing flash devices...flash '%s' found at 0x%8.8xclearedlastCould not open fileOut of memoryFile read failureShort readFlash read errorcontents %sdifferRead errorCould not write file Bank is erased #%3i: 0x%8.8x (0x%x %ikB) %snot protectedprotection state unknownerror retrieving flash infopadLength must be >0NOR flash command groupInitialize flash devices.banksIdentify a flash bank.bank_id ['sectors']erase_checkerase_sectorerase_addressfillwaddress value nfillhfillbwrite_bankbank_id filename offsetwrite_imageread_bankverify_bankpadded_valuebank_id valuehandle_flash_bank_commandhandle_flash_info_commandhandle_flash_fill_commandhandle_flash_write_bank_commandhandle_flash_write_image_commandhandle_flash_read_bank_commandhandle_flash_verify_bank_commandhandle_flash_init_commandhandle_flash_banks_commandsrc/target/adi_v5_swd.cSWD DPIDR %#8.8xSWD mode is not availableEnter SWD modeno SWD driver?can't init SWD driverSWD command groupnewdapdeclare a new SWD DAPswd_selecttarget_to_armdap_to_swdswd_queue_dp_readswd_queue_dp_writeswd_queue_ap_readswd_clear_sticky_errorsswd_connectswd_queue_ap_writeswd_queue_ap_abortbuildELFELF image detected.src/target/image.cIHEX image detected.S19 image detected.:%2x%4x%2x%4hx%8ximage->num_sections > 0S%1x%2x%4x%6xunhandled S19 record type: %iCalculating checksumCalculating checksum doneToo many sections found in IHEX fileunhandled IHEX record type: %iincorrect record checksum found in IHEX filepremature end of IHEX file, no end-of-file record foundfailed buffering IHEX image, check server output for additional informationinsufficient memory to perform operation cannot read ELF file header, read failedcannot read ELF file header, only partially readinvalid ELF file, bad magic numberinvalid ELF file, only 32bits files are supportedinvalid ELF file, unknown endianness settinginvalid ELF file, no program headerscannot seek to ELF program header table, read failedcannot read ELF segment headers, read failedcannot read ELF segment headers, only partially readincorrect record checksum found in S19 filepremature end of S19 file, no end-of-file record foundfailed buffering S19 image, check server output for additional informationread past end of section: 0x%8.8x + 0x%8.8x > 0x%8.8xload segment %d at 0x%x (sz = 0x%x)read elf: size = 0x%zu at 0x%xcannot find ELF segment content, seek failedcannot read ELF segment content, read failedimage_calculate_checksumimage_elf_read_sectionimage_read_sectionimage_mot_buffer_complete_innerimage_mot_buffer_completeimage_elf_read_headersimage_elf_read_headersimage_ihex_buffer_complete_innerimage_ihex_buffer_completeautodetect_image_typeimage_opengpd0lod0hid1lod1hiitbifc_lpCPU_VERICM_CFGDCM_CFGMMU_CFGMSC_CFGCORE_IDFUCOP_EXISTir0ir1ir2ir3IVBir4ir5ir6ir7ir8MERRir9ir10ir11OIPCir12ir13ir14INT_MASKir15INT_PENDir16ir17ir18ir19ir20ir21ir22ir23ir24ir25ir26ir27ir28ir29ir30MMU_CTLL1_PPTBTLB_VPNTLB_DATATLB_MISCVLPT_IDXILMBDLMBmr8CACHE_CTLmr9HSMP_SADDRmr10HSMP_EADDRmr11BPC0BPA0dr2BPAM0dr3BPV0dr4BPCID0dr5BPC1dr6BPA1dr7BPAM1dr8BPV1dr9BPCID1dr10BPC2dr11BPA2dr12BPAM2dr13BPV2dr14BPCID2dr15BPC3dr16BPA3dr17BPAM3dr18BPV3dr19BPCID3dr20BPC4dr21BPA4dr22BPAM4dr23BPV4dr24BPCID4dr25BPC5dr26BPA5dr27BPAM5dr28BPV5dr29BPCID5dr30BPC6dr31BPA6dr32BPAM6dr33BPV6dr34BPCID6dr35BPC7dr36BPA7dr37BPAM7dr38BPV7dr39BPCID7dr40EDM_CFGdr41EDMSWdr42EDM_CTLdr43EDM_DTRdr44BPMTCdr45DIMBRdr46TECR0dr47TECR1dr48pfr0PFMC0pfr1PFMC1pfr2PFMC2pfr3PFM_CTLdmar0DMA_CFGdmar1DMA_GCSWdmar2DMA_CHNSELdmar3DMA_ACTdmar4DMA_SETUPdmar5DMA_ISADDRdmar6DMA_ESADDRdmar7DMA_TCNTdmar8DMA_STATUSdmar9DMA_2DSETdmar10DMA_2DSCTLracrPRUSR_ACC_CTLfucprFUCOP_CTLidr0SDZ_CTLidr1MISC_CTLsecur0D0L24D1L24I0I1I2I3I4I5I6I7MODLBEADM_VBASESHFT_CTL0SHFT_CTL1CB_CTLCBB0CBB1CBB2CBB3CBE0CBE1CBE2CBE3fpcsrFPCSRfpcfgFPCFGfs0FS0fs1FS1fs2FS2fs3FS3fs4FS4fs5FS5fs6FS6fs7FS7fs8FS8fs9FS9fs10FS10fs11FS11fs12FS12fs13FS13fs14FS14fs15FS15fs16FS16fs17FS17fs18FS18fs19FS19fs20FS20fs21FS21fs22FS22fs23FS23fs24FS24fs25FS25fs26FS26fs27FS27fs28FS28fs29FS29fs30FS30fs31FS31fd0FD0fd1FD1fd2FD2fd3FD3fd4FD4fd5FD5fd6FD6fd7FD7fd8FD8fd9FD9fd10FD10fd11FD11fd12FD12fd13FD13fd14FD14fd15FD15fd16FD16fd17FD17fd18FD18fd19FD19fd20FD20fd21FD21fd22FD22fd23FD23fd24FD24fd25FD25fd26FD26fd27FD27fd28FD28fd29FD29fd30FD30fd31FD31src/target/nds32_reg.cIt will generate exceptions as setting %d to %snds32_reg_exception..//00PPPPsrc/target/target.ccmd_ctx != NULLEvent%-25s | Body%-25s | %s***END***usage: %s ['allow-defer'][TAP is disabled]allow-deferDeferring arp_examine of %sTarget not examined yet%c%c 0x%08x-0x%08x (%u bytes)freeing all working areasnot settable: %sNO PARAMS-event ?event-name? ...-event ?event-name??name? ?type? ..options...Command/target: %s Exists or target command groupmissing: -option ...[no parameters]failed to write %zu bytes: %smwwmwhmwbcommand '%s' unknown: array2mem: zero width read?%s(%d)array2mem: cannot read memory(*BUG*unknown*BUG*)Invalid debug reason: %dexamine deferredInvalid target state: %dInvalid target event: %dInvalid target reset mode: %dmem2array: zero width read?mem2array: cannot read memorymdwmdhmdb0x%08x %04x %s tap-disabledtarget not halted !!context != NULLarray2mem: no current targetmem2array: no current targetFailure setting watchpointsbreakpoint set at 0x%8.8xhwhw_ctx%2.2x %4.4x invalid memory read size: %u0x%8.8x: (dirty)===== %s(%i) %s (/%u): 0x%s%s(%i) %s (/%u)force%s (/%i): 0x%sPhysical address 0x%08xtarget %s is not haltedinit_target_eventsinit_boardInitializing targets...type->init_target != NULLtarget '%s' init failedtype '%s' has bad MMU hookstarget reset %i (%s)invalid reset modeocd_process_reset %sNot enough working areaTest pattern write failedUnsupported alignmentMemory read failedPass in %fs (%0.3f KiB/s)Compare failedref:buf:Memory write failedNo target has been configuredNo image in memoryLoaded image %f kBytes/schecksum mismatchaddress 0x%08x length 0x%08zxNo more differences found.address: 0x%lx failedaddress: 0x%8.8x failedfailed: %ifailed to get read pointertarget event %i (%s)Halt timed out, wake up GDB.waiting for target %s...background polling: %sTAP: %s (%s)No memory to store samples.gmonaddressSpace >= 2Wrote %sTarget not halted or runningsrst_assertedsrst_deassertedpower_dropoutpower_restore%s fast_load_imagefast_loadprofiling samples the CPU PCseconds filename [start end]virt2physvirtual_address['on'|'off']wait_halt[address][run|halt|init]soft_reset_haltdisplay memory words['phys'] address [count]display memory half-wordsdisplay memory byteswrite memory wordwrite memory half-wordwrite memory byterbpremove breakpointrwpremove watchpointdump_imagefilename address sizeverify_image_checksumfilename [offset [type]]verify_imagetest_imagemem2arrayarray2memreset_naglist all tasks test_mem_access[target]configure targetinitialize targetscreatecurrenttypessmptargetname1 targetname2 ...[target_attribute ...]target_attributeaddress data [count]eventlistcurstatearp_examinearp_examine ['allow-defer']was_examinedexamine_deferredarp_halt_gdbarp_pollarp_resetarp_haltarp_waitstateinvoke-event-type-work-area-virt-work-area-phys-work-area-size-work-area-backup-endian-coreid-chain-position-dbgbase-rtos-defer-examinelittledebug-requestwatchpoint-and-breakpointtarget-not-haltedprogram-exitdebug-runninggdb-haltresume-startresume-endgdb-startgdb-endreset-startreset-assert-prereset-assertreset-assert-postreset-deassert-prereset-deassert-postreset-halt-prereset-halt-postreset-wait-prereset-wait-postreset-initreset-endexamine-startexamine-enddebug-halteddebug-resumedgdb-attachgdb-detachgdb-flash-write-startgdb-flash-write-endgdb-flash-erase-startgdb-flash-erase-endtrace-configerr-invaliderr-init-failederr-timeouterr-not-haltederr-failureerr-unaligned-accesserr-data-aborterr-resource-not-availableerr-translation-faulterr-not-runningerr-not-examinedEvent actions for target (%d) %s ------------------------- | ----------------------------------------Use arp_examine command to examine it manually!Nag after each reset about options to improve performanceTarget %s doesn't support read_memoryTarget %s doesn't support read_phys_memoryTarget %s doesn't support write_memoryTarget %s doesn't support write_phys_memoryfailed to restore %u bytes of working area at address 0x%08xc->next->address == c->address + c->size([tT]|[fF]|assert|deassert) BOOLNo target-specific reset for %s-event ?event-name? ?EVENT-BODY?The selected transport doesn't support this targetThe selected transport took over low-level target control. The results might differ compared to plain JTAG/SWDtarget name is deprecated use: '%s'-chain-position required when creating targetunable to register '%s' commandsUnknown target type %s, try one of [ ...]usage: %s [phys]
[]Invalid width param, must be 8/16/32array2mem: addr + len - wraps to zero?array2mem: absurd > 64K item requestarray2mem address: 0x%08x is not aligned for %d byte readsarray2mem: Write @ 0x%08x, w=%d, cnt=%d, failednot enough working area available(requested %u)addr option value ('%s') is not valid*min_address option value ('%s') is not valid*max_address option value ('%s') is not validerror allocating buffer for section (%d bytes)error allocating buffer for section (%u bytes)%u bytes written at address 0x%8.8xLoaded %u bytes in %fs (%0.3f KiB/s)WARNING: image has not been loaded to target!You can issue a 'fast_load' to finish loading.freed %u bytes of working area at address 0x%08xvarname width addr nelems [phys]mem2array: addr + len - wraps to zero?mem2array: absurd > 64K item requestmem2array address: 0x%08x is not aligned for %d byte readsmem2array: Read @ 0x%08x, w=%d, cnt=%d, failedusage: %s [phys]
[]error reading target @ 0x%08lxuse '%s' as target identifier, not '%u'Target: %s is unknown, try one of: Target: TAP %s is disabled, can't be the current target TargetName Type Endian TapName State -- ------------------ ---------- ------ ------------------ ------------%2d%c %-18s %-10s %-6s %-18s %sBUG: current_target out of boundsaddress: 0x%8.8x, len: 0x%8.8x, r/w/a: %i, value: 0x%8.8x, mask: 0x%8.8xdata_value option value ('%s') is not validinvalid watchpoint mode ('%c')Failure setting breakpoint, the same address(IVA) is already usedContext breakpoint not availableContext breakpoint set at 0x%8.8xFailure setting breakpoint, the same address(CONTEXTID) is already usedHybrid breakpoint not availableHybrid breakpoint set at 0x%8.8xFailure setting breakpoint, the same address is already usedIVA breakpoint: 0x%8.8x, 0x%x, %i, 0x%sContext breakpoint: 0x%8.8x, 0x%x, %iHybrid breakpoint(IVA): 0x%8.8x, 0x%x, %i |--->linked with ContextID: 0x%8.8xBreakpoint(IVA): 0x%8.8x, 0x%x, %iasid option value ('%s') is not validvalue option value ('%s') is not validrequesting target halt and executing a soft resetTarget %s does not support soft_reset_haltnum option value ('%s') is not validregister %s not found in current target%i is out of bounds, the current target has only %i registers (0 - %i)va option value ('%s') is not validTarget type '%s' does not support %sTarget is already running an algorithmTarget is not running an algorithmerror allocating buffer for reset callback entryerror allocating buffer for trace callback entry'target init' has already been calledtype '%s' is missing virt2physMMU disabled, using physical address for working memory 0x%08xNo working memory available. Specify -work-area-phys to target.MMU enabled, using virtual address for working memory 0x%08xNo working memory available. Specify -work-area-virt to target.allocated new working area of %u bytes at address 0x%08xtest_size option value ('%s') is not validTest read %u x %d @ %d to %saligned buffer: Test write %u x %d @ %d from %saligned buffer: writing buffer of %i byte at 0x%8.8xaddress + size wrapped (0x%08x, 0x%08x)downloaded %u bytes in %fs (%0.3f KiB/s)Write to 0x%08x, length 0x%08xreading buffer of %i byte at 0x%8.8xchecksum mismatch - attempting binary compareverified %u bytes in %fs (%0.3f KiB/s)address: 0x%lx, value: 0x%16.16lxaddress: 0x%8.8x, value: 0x%8.8xaddress: 0x%8.8x, value: 0x%4.4xaddress: 0x%8.8x, value: 0x%2.2x!block_size || !(block_size & (block_size - 1))error starting target flash write algorithmoffs 0x%zx count 0x%x wp 0x%x rp 0x%xflash write algorithm aborted by targetcorrupted fifo read pointer 0x%xtimeout waiting for algorithm, a target reset is recommendederror waiting for target flash write algorithmtarget: (%d) %s (%s) event: %d (%s) action: %stimed out while waiting for target %s%s target: %s wait %s fails (%#s) %snum_of_samples <= MAX_PROFILE_SAMPLE_NUMstart_address option value ('%s') is not validend_address option value ('%s') is not validStarting profiling. Halting and resuming the target as often as we can...Profiling completed. %u samples.srst asserted detected, running srst_asserted proc.Power dropout detected, running power_dropout proc.Polling target %s failed, trying to reexamineExamination failed, GDB will be halted. Polling again in %dmsLoad image into server memory for later use by fast_load; primarily for profilingfilename address ['bin'|'ihex'|'elf'|'s19'] [min_address [max_length]]loads active fast load image to current target - mainly for profiling purposestranslate a virtual address into a physical addressdisplay (reread from target with "force") or set a register; with no arguments, displays all registers and their values[(register_number|register_name) [(value|'force')]]poll target state; or reconfigure background pollingwait up to the specified number of milliseconds (default 5000) for a previously requested haltrequest target to halt, then wait up to the specifiednumber of milliseconds (default 5000) for it to completeresume target execution from current PC or addressReset all targets into the specified mode.Default reset mode is run, if not given.halt the target and do a soft resetstep one instruction from current PC or address['phys'] address value [count]list or set hardware or software breakpoint
[] ['hw'|'hw_ctx']list (no params) or create watchpoints[address length [('r'|'w'|'a') value [mask]]]filename address ['bin'|'ihex'|'elf'|'s19'] [min_address] [max_length]read 8/16/32 bit memory and return as a TCL array for script processingarrayname bitwidth address countconvert a TCL array to memory locations and write the 8/16/32 bit valuesNag after each reset about options that could have been enabled to improve performance. Test the target's memory access functionschange current default target (one parameter) or prints table of all targets (no parameters)Creates and selects a new targetname type '-chain-position' name [options ...]Returns the currently selected targetReturns the available target types as a list of stringsReturns the names of all targets as a list of stringsgather several target in a smp listconfigure a new target for usereturns the specified target attributeWrite 32-bit word(s) to target memoryWrite 16-bit half-word(s) to target memoryWrite byte(s) to target memoryDisplay target memory as 32-bit wordsDisplay target memory as 16-bit half-wordsDisplay target memory as 8-bit bytesWrites Tcl array of 8/16/32 bit numbers to target memoryLoads Tcl array of 8/16/32 bit numbers from target memorydisplays a table of events defined for this targetdisplays the current state of this targetused internally for reset processingused internally for reset processing to halt GDBinvoke handler for specified eventP0pHfind_targethandle_fast_load_commandwriteDatawrite_gmonhandle_profile_commandhandle_profile_commandhandle_reg_commandhandle_halt_commandtarget_process_resettarget_soft_reset_halthandle_soft_reset_halt_commandhandle_step_commandhandle_md_outputhandle_bp_command_sethandle_wp_commandhandle_verify_image_command_internaljim_mem2arrayjim_mem2arrayjim_array2memjim_array2memhandle_ps_commandhandle_test_mem_access_commandtarget_profiling_defaulttarget_init_onetarget_init_onehandle_targethandle_target_init_commandtarget_fill_memjim_target_mwjim_target_mdtarget_array2memtarget_mem2arrayjim_target_event_listjim_target_examinetarget_createtarget_createjim_target_currentjim_target_smptarget_handle_eventtarget_wait_statetarget_write_u8target_write_u16target_write_u32target_write_u64target_read_u8target_read_u16target_read_u32target_read_u64target_blank_check_memorytarget_checksum_memorytarget_read_buffertarget_write_buffertarget_arch_statetarget_free_all_working_areas_restoretarget_merge_working_areastarget_restore_working_areatarget_free_working_area_restoretarget_alloc_working_areaprint_wa_layouttarget_alloc_working_area_trytarget_call_reset_callbackstarget_call_event_callbackstarget_register_trace_callbacktarget_register_reset_callbacktarget_profilingtarget_gdb_fileio_endtarget_get_gdb_fileio_infotarget_hit_watchpointtarget_add_watchpointtarget_add_hybrid_breakpointtarget_add_context_breakpointtarget_add_breakpointtarget_write_phys_memorytarget_write_memorytarget_read_phys_memorytarget_read_memorytarget_run_flash_async_algorithmtarget_run_flash_async_algorithmtarget_wait_algorithmtarget_start_algorithmtarget_run_algorithmtarget_resumetarget_halttarget_pollget_current_targetget_targettarget_reset_mode_nametarget_event_nametarget_state_namedebug_reason_nameP?src/target/target_request.csize: %i, length: %iunknown target request: %2.2xcharmsgtarget_requesttarget request command groupdebugmsgstarget->type->target_request_dataTarget %s does not support target requestsreceiving debug messages from current target %sdisplay and/or modify reception of debug messages from target['enable'|'charmsg'|'disable']handle_target_request_debugmsgs_commandtarget_charmsgtarget_hexmsgtarget_asciimsgtarget_requesttarget_requesttesteetestee target commandstrace point 0x%8.8x (%lld times hit)trace->trace_history_size option value ('%s') is not validtrace history buffer is not allocateddisplay trace history, clear history or set sizedisplay trace points, clear list of trace points, or add new tracepoint at addressnew trace history size: %itrace point %i: 0x%8.8xtrace point %i: -not defined-tracepoint: %isrc/target/trace.ctrace command group['clear'|size]['clear'|address]trace_pointsrc/target/xscale.cXSCALE_MAINIDXScale registersno trace data collectedlow %d: 0x%xhigh %d: 0x%xTarget not halted0x%8.8x --- exception %i ---address unknownJTAG error while writing DCSRJTAG error while reading DCSRtarget->state: %starget was already haltedtarget->state == TARGET_RESETloading miniIC at 0x%8.8xpolling RXJTAG error while writing RXtime out writing RX registerwaiting 100mswrapfillfill buffer count must be > 0fill %dtrace buffer enabled (%s)trace buffer disabledXSCALE_DCSRXSCALE_RXXSCALE_TXXSCALE_TXRXCTRLbreakpoint already setbreakpoint not setJTAG error while reading TXtime out reading TX registericachemmu %sinvalid register number%s (/%i): 0x%xignore%15s: %sNo vector '%s'BUG: size neither 4, 2 nor 1data abort writing memoryunset breakpoint at 0x%8.8xenable single-stepwriting PC with value 0x%8.8xdisable single-stepwrote PC with value 0x%8.8xtarget resumedr0: 0x%8.8xpc: 0x%8.8xr%i: 0x%8.8xcpsr: 0x%8.8xMethod of Entry is 'Reserved'current pc %xtarget stepped (processor reset) (trace buffer full)xscalexscale command groupdebug_handler
cache_clean_addresscache_infoenable or disable the MMUdcachevector_catchvector_table[('high'|'low') index code]trace_bufferdump_traceanalyze_tracetrace_imagefilename [offset [filetype]]cp15register [value]XSCALE_CACHETYPEXSCALE_CTRLXSCALE_AUXCTRLXSCALE_TTBXSCALE_DACXSCALE_FSRXSCALE_FARXSCALE_PIDXSCALE_CPACCESSXSCALE_IBCR0XSCALE_IBCR1XSCALE_DBR0XSCALE_DBR1XSCALE_DBCONXSCALE_TBREGXSCALE_CHKPT0XSCALE_CHKPT1no more watchpoint registers availablexscale does not support value, mask arguments; ignoringxscale requires that watchpoint length is a power of twoinsufficient watchpoint registers availablexscale does not support watchpoints with length greater than addresspreviously loaded image found and closedxscale->trace.image->base_address option value ('%s') is not validerror while reading instructionBUG: unknown core state encounteredtarget must be stopped for "%s" commandactive user-set static vectors:idx option value ('%s') is not validvec option value ('%s') is not validcache_clean_address option value ('%s') is not validxscale cache_clean_address
must be 64kb alignedhandler_address option value ('%s') is not validxscale debug_handler
must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800%s: hardware has 2 breakpoints and 2 watchpointsBUG: called for a non-ARMv4/5 targetMMU: %s, D-Cache: %s, I-Cache: %s%sNo trace image loaded; use 'xscale trace_image'trace is suspect: invalid trace message bytetrace is suspect: checkpoint register inconsistent with adddress from imagetrace is suspect: checkpoint register inconsistent with address from trace buffertrace is suspect: excessive gap at end of tracetarget was in unknown state when halt was requestedbuffcount option value ('%s') is not validBUG: no hardware comparator availableno breakpoint unit available for hardware breakpointonly breakpoints of two (Thumb) or four (ARM) bytes length supportedBUG: xscale->ibcr0_used is set, but no breakpoint with that address foundReset is not asserted because the target is not examined.Use a reset button or power cycle the target.JTAG error while receiving data from debug handlerFailed to receiving data from debug handler after 1000 attemptstarget must be stopped to read trace datareg_no option value ('%s') is not validaddress: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8xJTAG error while sending data to debug handler%s: %s is not implemented. Disable MMU?BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8xwriting cpsr with value 0x%8.8xwriting r%i with value 0x%8.8xBUG: watchpoint->rw neither read, write nor accessBUG: sufficient hardware comparators unavailablecpsr contains invalid mode value - communication failuretarget entered debug state in %s modeerror while polling TX register, reset CPUChange address used for debug handler.Change address used for cleaning data cache.display information about CPU cachesdisplay ICache state, optionally enabling or disabling itdisplay DCache state, optionally enabling or disabling itset or display mask of vectors that should trigger debug entry['all'|'none'|'fiq'|'irq'|'dabt'|'pabt'|'swi'|'undef'|'reset']set vector table entry in mini-ICache, or display current tablesdisplay trace buffer status, enable or disable tracing, and optionally reconfigure trace mode['enable'|'disable' ['fill' [number]|'wrap']]dump content of trace buffer to fileanalyze content of trace bufferload image from file to address (default 0)Read or write coprocessor 15 register.hhhhhhhhX88`8X`X@(pppppppp0xscale_pollxscale_arch_statexscale_haltxscale_set_watchpointxscale_resumexscale_restore_bankedxscale_enable_single_stepxscale_step_innerxscale_stepxscale_assert_resetxscale_read_tracexscale_debug_entryxscale_load_icxscale_deassert_resetxscale_read_memoryxscale_sendxscale_write_memoryxscale_set_breakpointxscale_add_breakpointxscale_unset_breakpointxscale_remove_breakpointxscale_add_watchpointxscale_remove_watchpointxscale_handle_debug_handler_commandxscale_handle_cache_clean_address_commandxscale_handle_vector_catch_commandxscale_read_instructionxscale_analyze_tracexscale_read_core_regxscale_write_core_regxscale_receivetarget_to_armxscale_full_contextxscale_init_arch_infoxscale_read_txxscale_read_dcsrxscale_write_rxxscale_jtag_set_instrxscale_write_dcsrxscale_virt2physxscale_read_phys_memoryxscale_write_phys_memoryxscale_mmufiqirq@dabtpabtswiundefresettarget is not an XScale Ѡ jjpnljhfdObO Q=\P9 PZ P{ P P !P "P $P 0P 1P+ @P AP PP QP RP SP `P aP  bP 4i2p0`.P,@*0( &$Z^p!jjjjjjjQ Oj!p!ZZZZZZZQ Zi!| 䚏Qr Qh 䚏Q^ 䚏QT QJ 䚏Q@  < Q531O-#0!0   SUS 00     $Q Qip`P@0  ZЍ ^jZhardforce %s breakpointssrc/server/gdb_server.cBUG: connection->priv == NULLieee_doubleieee_singlefloatdata_ptrcode_ptruint128uint64uint32uint16uint8get register list failed qXfer:features:read:Unable to allocate memoryqXfer:threads:read: QStartNoAckModereg_packet_size > 0addr: 0x%8.8x, len: 0x%8.8xW00S%2.2xMemory write failure!continuevFlashErase:flash_erase returned %ivFlashWrite:vFlashDoneE.memtypeocd_gdb_restart %signoring 0x%2.2x packetT%2.2xgdb server disabledgdb port disabled3333gdb_syncgdb_portgdb_memory_mapenable or disable memory map('enable'|'disable')gdb_flash_programgdb_report_data_abortgdb_breakpoint_override('hard'|'soft'|'disable')gdb_target_descriptiongdb_save_tdescbreakpoint type is not overriddenGDB Close, Target: %s, state: %s, gdb_actual_connections=%dgdb_use_target_description option value ('%s') is not validgdb_report_data_abort option value ('%s') is not validgdb_flash_program option value ('%s') is not validgdb_use_memory_map option value ('%s') is not validBUG: couldn't put character backCan't get the registers feature list Unable to Generate Target DescriptionError while writing the tdesc fileBUG: gdb value with uneven number of characters encounteredBUG: unable to convert register valuegdb_sync command can only be run from within gdb using "monitor gdb_sync"GDB missing ack(1) - assumed goodunknown character(1) 0x%2.2x in reply, dropping connectionGDB missing ack(2) - assumed goodunknown character(2) 0x%2.2x in reply, dropping connectionConnect failed. Consider setting up a gdb-attach event for the target to prepare target for GDB connect, or use 'gdb_memory_map disable'.New GDB Connection: %d, Target %s, state: %sundefined debug reason %d - target needs resetReporting %i to GDB as generic erroracknowledgment received, but no packet pendingReceived first acknowledgment after entering noack mode. Ignoring it.negative acknowledgment, but no packet pendingreceived packet: '%s:'incomplete read memory packet received, dropping connectionTarget Descriptions Supported, but disabledPacketSize=%x;qXfer:memory-map:read%c;qXfer:features:read%c;qXfer:threads:read+;QStartNoAckMode+ 0x%x Unable to Generate Thread ListGDB set_registers packet with uneven characters received, dropping connectionBUG: register packet is too small for registersgdb requested a non-existing registerGDB 'set register packet', but no '=' following the register numbergdb sent a packet with wrong register sizeinvalid read memory packet received (len == 0)incomplete write memory packet received, dropping connectionunable to decode memory packetinvalid gdb watch/breakpoint type(%d), dropping connectionincomplete breakpoint/watchpoint packet received, dropping connectionWARNING! The target is already running. All changes GDB did to registers will be discarded! Waiting for target to halt.The target is not in the halted nor running stated, stepi/continue ignored.stepi ignored. GDB will now fetch the register state from the target.incomplete vFlashErase packet received, dropping connectionwrote %u bytes from vFlash image to flashincomplete write memory binary packet received, dropping connectionFile-I/O response, retcode: 0x%x, errno: 0x%x, ctrl-c: %sThe target is not running when halt was requested, stopping GDB.Failed detecting Target Description Support, disablinggdb services need one or more targets definednext stepi will return immediately allowing GDB to fetch register state without affecting target stateNormally gdb listens to a TCP/IP port. Each subsequent GDB server listens for the next port number after the base port number specified. No arguments reports GDB port. "pipe" means listen to stdin output to stdout, an integer is base port number, "disabled" disables port. Any other string is are interpreted as named pipe to listen to. Output pipe is the same name as input pipe, but with 'o' appended.enable or disable flash programenable or disable reporting data abortsDisplay or specify type of breakpoint to be used by gdb 'break' commands.enable or disable target descriptionSave the target description file8p`0 P@ HHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHH0 H H@HH8HH0 H HHH`HHHHHHHHH0HHHHHH HH H0HH(HHHhandle_gdb_breakpoint_override_commandhandle_gdb_save_tdesc_commandgdb_outputgdb_new_connectiongdb_fileio_response_packetgdb_write_memory_binary_packetgdb_v_packetgdb_step_continue_packetgdb_breakpoint_watchpoint_packetgdb_write_memory_packetgdb_read_memory_packetgdb_set_register_packetgdb_get_register_packetgdb_target_to_reggdb_set_registers_packetgdb_get_registers_packetgdb_errorgdb_get_thread_list_chunkgdb_generate_target_descriptiongdb_get_target_description_chunkgdb_target_description_supportedgdb_query_packetfetch_packetgdb_get_packet_innergdb_input_innergdb_last_signalgdb_fileio_replygdb_connection_closedgdb_target_add_onegdb_target_add_allgdb_putback_chargdb_get_char_innergdb_put_packet_innerYou need to set a period valuepolling_period option value ('%s') is not validset servers polling period to %umscouldn't resolve bindto address: %scouldn't bind %s to socket: %scouldn't set SIGPIPE to SIG_IGNaccepting '%s' connection on tcp/%sattempted '%s' connection rejectedaccepting '%s' connection from pipeaccepting '%s' connection from pipe %srejected '%s' connection, no more connections allowedunable to change server port after initset the servers polling periodSpecify address by name on which to listen for incoming TCP/IP connectionssrc/server/server.cshutdown command invokedbindto name: %serror creating socket: %scouldn't listen on socket: %scould not open %serror during select: %s%sodropped '%s' connectionOpen On-Chip Debuggershutdownshut the server downpoll_periodbindto[name]server_pipe_commandhandle_shutdown_commandhandle_poll_period_commandadd_connectionserver_loopadd_serviceerror during write: %d != %dsrc/server/tcl_server.ctype target_trace data type target_event event %s type target_state state %s error during read: %sline too long type target_reset mode %s Target trace output Target Notification output tcl server disabled6666tcl_porttcl_notificationsTarget Notification outputtcl_traceTarget trace output%s: can only be called from the tcl serverSpecify port on which to listen for incoming Tcl syntax. Read help on 'gdb_port'.handle_tcl_notifications_commandhandle_tcl_trace_commandtcl_inputtcl_outputtcl_init   .openocd_historysrc/server/telnet_server.c unhandled nonprintable: %2.2xunknown telnet state> telnet server disabledtelnet4444exit telnet sessiontelnet_portunable to get user home directory, telnet history will be disabledBUG: unexpected value in t_con->last_escapeFailed to allocate telnet connection.Failed to allocate telnet service.Specify port on which to listen for incoming telnet connections. Read help on 'gdb_port'. GFGG|G|G|G|G,Htelnet_load_historytelnet_new_connectiontelnet_inputtelnet_save_historytelnet_connection_closedtelnet_init or autosrc/rtos/rtos.cqSymbol::qSymbol:%lx:Auto-detected RTOS: %sqThreadExtraInfo,qThreadExtraInfo,%lxE01qSymbolqfThreadInfo%c%016lxqsThreadInfoqAttachedqOffsetsqCQC%016lxQC0T%lxHg%16lxUnknown RTOS type %s, try one of: RTOS: getting register list for thread 0x%lx, target->rtos->current_thread=0x%lx RTOS: failed to get register listError: null stack pointer in threadError reading stack frame from threadRTOS: Read stack frame at 0x%xRTOS %s not detected. (GDB could not find symbol '%s')No RTOS could be auto-detected!ERROR: RTOS symbol '%s' name is too long for GDB!strlen(tmp_str) == (size_t) (tmp_str_ptr - tmp_str)RTOS: GDB requested to set current thread to 0x%lxrtos_generic_stack_readrtos_get_gdb_reg_listrtos_thread_packetrtos_thread_packetrtos_qsymbolText=0;Data=0;BsOSRunninguCOS-III: out of memorysrc/rtos/uCOS-III.ccortex_mUnknownState: %s, Priority: %duCOS-IIIDelayPendPend TimeoutDelay SuspendedPend SuspendedPend Timeout SuspendedOSTCBCurPtrOSTaskDbgListPtrOSTaskQtyopenocd_OS_TCB_StkPtr_offsetopenocd_OS_TCB_NamePtr_offsetopenocd_OS_TCB_Prio_offsetuCOS-III: failed to find thread addressuCOS-III: failed to read stack addressuCOS-III: target not supported: %suCOS-III: failed to read RTOS runninguCOS-III: failed to read thread offsetuCOS-III: failed to update thread offsetsuCOS-III: failed to read current thread addressuCOS-III: failed to read thread countuCOS-III: failed to read thread list addressuCOS-III: failed to read next thread addressuCOS-III: too many threads; increase UCOS_III_MAX_THREADSuCOS-III: failed to find or create threaduCOS-III: failed to name addressuCOS-III: failed to read thread nameuCOS-III: failed to read thread stateuCOS-III: failed to read thread priorityuCOS-III: failed to read previous thread addressuCOS-III: failed to find last thread addressopenocd_OS_TCB_TaskState_offsetopenocd_OS_TCB_DbgPrevPtr_offsetopenocd_OS_TCB_DbgNextPtr_offsetuCOS_III_createuCOS_III_find_or_create_threaduCOS_III_find_last_thread_addressuCOS_III_update_thread_offsetsuCOS_III_update_threadsuCOS_III_find_thread_addressuCOS_III_get_thread_reg_listuCOS_III_get_symbol_list_to_lookup0123456789ABCDEF0123456789abcdef@ `P0pH(hX8xD$dT4t L,l\<|B"bR2r J*jZ:zF&fV6vN.n^>~A!aQ1q I)iY9yE%eU5u M-m]=}C#cS3s K+k[;{G'gW7wO/o_?*@@ @>?V>%.*ssrc/helper/command.c (?mode error?) (configuration command) (command valid any time)command recursion exceededunable to build search string-ncommand - %socd_nativesimpleanyexecocd_%sregistering '%s'...retvalif Cthulhu is summoned bybeforeafterusage %sUnknown command: %sfailed to add '%s' help textadded '%s' help textreplaced existing '%s' helpreplaced existing '%s' usageadded '%s' usage text%s: insufficient argumentsadd_help_textadd_usage_textcommand name '%s' is unknownlinuxocd_HOSTOSocd_findembedded:startup.tclInvalid command argumentArgument overflowArgument underflownoyes%s is %secho[-n] stringcommand_name helptext_stringcommand_name usage_stringmilliseconds ['busy'][command_name][command_name ...]command_name [...]command '%s' is already registered in '%s' contextBUG: command '%s%s%s' does not have the '.usage' field filled outproc %s {args} {eval ocd_bouncer %s $args}The '%s' command must be used %s 'init'.Command failed with error code %dunknown command, but usage is missing tooFailed to run startup.tcl (embedded into OpenOCD)%s: argument '%s' is not validLogs a message at "user" priority. Output message to stdout. Option "-n" suppresses trailing newlineAdd new command help text; Command can be multiple tokens.Add new command usage text; command can be multiple tokens.Sleep for specified number of milliseconds. "busy" will busy wait instead (avoid this).Show full command help; command can be multiple tokens.Show basic command usage; command can be multiple tokens.core command group (introspection)Returns the command modes allowed by a command:'any', 'config', or 'exec'. If no command isspecified, returns the current command mode. Returns 'unknown' if an unknown command is given. Command can be multiple tokens.Returns the type of built-in command:'native', 'simple', 'group', or 'unknown'. Command can be multiple tokens.handle_command_parse_boolparse_llongparse_longparse_ullongparse_ulongjim_echohandle_help_add_commandcommand_help_show_wrapcommand_help_show_indentcommand_help_showhandle_help_commandcommand_inithelp_add_commandcommand_run_linecommand_printcommand_print_samelinescript_commandrun_commandscript_command_runcommand_unknownregister_command_handlercommand_newregister_commandscript_debugadding %ssrc/helper/configuration.cfound %sscript openocd.cfgHOMEfind_fileadd_script_search_dirBUG: access neither read, write nor readwriteBUG: fileio->file not a valid file descriptorsrc/helper/fileio.ccouldn't open %scouldn't close %s: %scouldn't seek file %s: %s@XpHfileio_seekfileio_close_localfileio_open_locallibocdhelper was built without I/O utility supportsrc/helper/ioutil_stubs.cioutil_initsrc/helper/jep106.cAMDAMIFairchildFujitsuGTEHarrisHitachiInmosIntelI.T.T.IntersilMonolithic MemoriesMostekFreescale (Motorola)NationalNECRCARaytheonConexant (Rockwell)SeeqNXP (Philips)SynertekTexas InstrumentsToshibaXicorZilogEurotechniqueMitsubishiLucent (AT&T)ExelAtmelSTMicroelectronicsLattice Semi.NCRWafer Scale IntegrationIBMTristarVisicIntl. CMOS TechnologySSSIMicrochipTechnologyRicoh Ltd.VLSISK HynixOKI SemiconductorACTELSharpCatalystPanasonicIDTCypressDECLSI LogicZarlink (Plessey)UTMCThinking MachineThomson CSFIntegrated CMOS (Vertex)HoneywellTektronixOracle CorporationSilicon Storage TechnologyProMos/Mosel VitelicInfineon (Siemens)MacronixXeroxPlus LogicSanDisk CorporationElan Circuit Tech.European Silicon Str.Apple ComputerXilinxCompaqProtocol EnginesSCISeiko InstrumentsSamsungI3 Design SystemKlicCrosspoint SolutionsAlliance SemiconductorTandemHewlett-PackardIntegrated Silicon SolutionsBrooktreeNew MediaMHS ElectronicPerformance Semi.Winbond ElectronicKawasaki SteelBright MicroTECMARExarPCMCIALG Semi (Goldstar)Northern TelecomSanyoArray MicrosystemsCrystal SemiconductorAnalog DevicesPMC-SierraAsparixConvex ComputerQuality SemiconductorNimbus TechnologyTranswitchMicronas (ITT Intermetall)CannonAlteraNEXCOMQualcommSonyCray ResearchAMS(Austria Micro)VitesseAster ElectronicsBay Networks (Synoptic)Zentrum/ZMDTRWThesysSolbourne ComputerAllied-SignalDialog SemiconductorMedia VisionNumonyx CorporationCirrus LogicNational InstrumentsILC Data DeviceAlcatel MietecMicro LinearUniv. of NCJTAG TechnologiesBAE Systems (Loral)NchipGalileo TechBestlink SystemsGraychipGENNUMVideoLogicRobert BoschChip ExpressDATARAMUnited Microelectronics Corp.TCSISmart ModularHughes AircraftLanstar SemiconductorQlogicKingstonMusic SemiEricsson ComponentsSpaSEEon Silicon DevicesDoDInteg. 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Ltd.Seagate Technology PLCGigacom Semiconductor LLCV2 TechnologiesTLiNeotionLenovoCompound Photonicsin2H2 incVasekeyEyenix Co., Ltd.HeoriadyINVECAS, Inc.AP MemoryDouqi TechnologyEtron Technology, Inc.Indie SemiconductorSocionext Inc.HGSTEVGAAudience Inc.EpicGearVitesse Enterprise Co.Bretelon Inc.GraphcoreEoplex IncMaxLinear, Inc.ETA DevicesLOKIIMS Electronics Co., Ltd.Dosilicon Co., Ltd.Dolphin IntegrationBoya Microelectronics Inc.Geniachip (Roche)AxignCrocus Technology Inc.Creative Chips GmbHGE Aviation Systems LLC.AsgardGood Wealth Technology Ltd.TriCor TechnologiesNova-Systems GmbHJUHORDSL MemoryAnvo-Systems Dresden GmbHRealtekAltoBeamWave ComputingInnovium, Inc.Starsway Technology LimitedWeltronics Co. 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Ltd.Xi’an SinoChip SemiconductorShenzhen City Gcai ElectronicsDasima International DevelopmentHIMA Paul Hildebrandt GmbH Co KGTechcomp International (Fastable)Korea Uhbele International Group Ltd.Silicon Integrated Systems CorporationHong Kong Zetta Device TechnologyUnimemory Technology(s) Pte Ltd.Hong Kong Gaia Group Co. LimitedShenzhen Zhongteng Electronic Corp. Ltd.Shenzhen Pango Microsystems Co. LtdCal-Comp Industria de SemicondutoresAccelerated Memory Production Inc.Foxtronn International CorporationShenzhen Mic Electronics TechnologyKingred Electronic Technology Ltd.Chao Yue Zhuo Computer Business Dept.Guangzhou Si Nuo Electronic Technology.Zhuhai Douke Commerce Co. Ltd.Beijing TrustNet Technology Co. Ltd.Paragon Technology (Shenzhen) Ltd.Shenzhen Yong Sheng TechnologySNOAMOO (Shenzhen Kai Zhuo Yue)Shenzhen XinRuiYan ElectronicsShenzhen Chixingzhe Tech Co. Ltd.jep106_manufacturer---args--- %2d) %s ------- not a number: %#soption%#s: Unknown: %#s, try one of: Unknown param: %#s, try one of: %s%d %ld %s:%d %s(): %sOPENOCD_DEBUG_LEVELsrc/helper/log.cdebug_level: %ilog_outputfile_namedebug_levelUser : Error: Warn : Info : Debug: new_level option value ('%s') is not validlevel must be between %d and %dkeep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not sent! (%ld). Workaround: increase "set remotetimeout" in GDBkeep_alive() was not invoked in the 1000ms timelimit (%ld). This may cause trouble with GDB connections.redirect logging to a file (default: stderr)Sets the verbosity level of debugging output. 0 shows errors only; 1 adds warnings; 2 (default) adds other info; 3 adds debugging.keep_alivehandle_debug_level_commandsrc/helper/options.chvd::l:f:s:c:pscript {%s}debug_level %slog_output %s/proc/self/exe/proc/self/path/a.out/proc/curproc/file/usr/binBINDIR = %s/usr/share/openocdbindir=%spkgdatadir=%sexepath=%sbin2data=%s%s/.openocdOPENOCD_SCRIPTSsite%s/%s/%sscriptsgdb_port pipe; log_output openocd.logdeprecated option: -p/--pipe. Use '-c "gdb_port pipe; log_output openocd.log"' instead.Open On-Chip Debugger Licensed under GNU GPL v2 --help | -h display this help --version | -v display OpenOCD version --file | -f use configuration file --search | -s dir to search for config files and scripts --debug | -d set debug level <0-3> --log_output | -l redirect log output to file --command | -c run Could not determine executable path, using configured BINDIR.^x^x]@^x]0^x]x]x]^x]x]x]]x]x]]x]x]^find_exe_pathadd_default_dirsparse_cmdline_argsconfiguration_output_handler@ls ?dir?Returns ever increasing milliseconds. Used to calculuate differences in time.foo flagGreetings%s%s!src/hello.chelloprints a warm welcomefooan example commandaddress ['enable'|'disable']baza sample commandset a flag%s: address=0x%8.8x enabled=%sexample command handler skeletonhandle_foo_commandUNKNOWN XSVF STATE 0x%02Xsrc/xsvf/xsvf.cXSDRXSDRTDOplainfile "%s" not foundvirt2xsvf processing file: "%s"XSVF: path too longXSTATE 0x%02X %sXSVF: dodgey RESETXSVF: pathmove error %dXCOMPLETEXTDOMASKXRUNTEST %d 0x%08XXREPEAT %dXSDRSIZE %d%s %d%s mismatchunsupported XSETSDRMASKSunsupported XSDRINCunsupported XSDRBunsupported XSDRCunsupported XSDREunsupported XSDRTDOBunsupported XSDRTDOCunsupported XSDRTDOEXSVF: bad XSTATE %02xXENDIR 0x%02X %sXENDDR %02X %sXSIR %dXSIR2 %d# %sXWAIT %s %s usecs:%dLCOUNT %dLDELAY %s clocks:%d usecs:%dLSDRLSDR retry %dLSDR mismatchunknown xsvf command (0x%02X)xsvfXSVF support in OpenOCD is limited. Consider using SVF instead%s mismatch, xsdrsize=%d retry=%dillegial XENDIR argument: 0x%02Xillegial XENDDR argument: 0x%02XXWAITSTATE %s %s clocks:%i usecs:%iillegal XWAITSTATE wait_state: "%s"XTRST mode argument (0x%02X) out of rangexsvf failed, setting taps to reasonable stateTDO mismatch, somewhere near offset %lu in xsvf file, abortingunsupported xsvf command (0x%02X) at offset %jd, abortingpremature end of xsvf file detected, abortingXSVF file programmed successfullyRuns a XSVF file. If 'virt2' is given, xruntest counts are interpreted as TCK cycles rather than as microseconds. Without the 'quiet' option, all comments, retries, and mismatches will be reported.(tapname|'plain') filename ['virt2'] ['quiet']`pnmn mppllnkkk`kkPjjjji@imq`h gfedd   xsvf_to_taphandle_xsvf_commandtoooooo many operation undonesrc/svf/svf.cnot enough memory0x%01x%8s = %stdo check error at line %dREADWANTSVF: can not move to %sfail to parse svf commandinvalid parameter of %s IR end_state = %s DR end_state = %sHZadapter_khz %d frequency = %f length = %ddata section errorSMASKunknow parameter: %sinvalid hex stringvalue execeeds lengthfail to parse hex value run_state = %sSEC run_count@TCK = %d%s not supported for clock min_time = %fsMAXIMUM max_time = %fsENDSTATE end_state = %s%s: %s is not a valid state move to %s by path_moveunknown TRST mode: %s trst_mode = %sinvalid svf command: %sTDO read%s: %s is not a stable stateunsuccessfully-tap-quiet-nil-progress-ignore_erroropen("%s"): %sfailed to set data headerfailed to set data trailer %d%% %3d%% %s Time used: %dm%ds%ldms svf file programmed failedRuns a SVF file.OFFABSENTENDDRENDIRFREQUENCYHDRHIRPIOPIOMAPRUNTESTSIRTDRTIRHZ not found in FREQUENCY commandfail to adjust length of arrayPIO and PIOMAP are not supportedfail to parse parameter of RUNTEST, %d out of %d is parsed move to %s by svf_add_statemovecan not accpet TRST command if trst_mode is ABSENT(Above Padding command skipped, as per -tap argument)failed to set instruction headerfailed to set instruction trailerfail to run command at line %dsvf file programmed %s for %d commands with %d errorssvf [-tap device.tap] [quiet] [nil] [progress] [ignore_error]PPăw}b/AЄJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJJ(svf_check_tdosvf_read_command_from_filesvf_add_check_parasvf_copy_hexstring_to_binarysvf_parse_cmd_stringsvf_run_commandsvf_adjust_array_lengthhandle_svf_commandsvf_add_statemove                        $tIsrc/jtag/commands.cNULL != last_cmdNULL == *last_cmdjtag_queue_commandhl_interface_quitsrc/jtag/hla/hla_interface.chl_interface_initNo adapter layout '%s' foundhl_interface_init_targetexpected %u of %u: 0x%08xUNEXPECTED idcode: 0x%08xhl_interface_openhla_targethlahla_device_deschla_serialhla_layoutset the layout of the adapterlayout_namehla_vid_pidhla_commandhla_command hl_interface_handle_layout_commandNeed exactly one argument to stlink_layoutalready specified hl_layout %sThe selected adapter doesn't support custom commandshl_interface_execute_queue: ignoredhl_interface_handle_vid_pid_commandignoring extra IDs in hl_vid_pid (maximum is 1 pair)hl_if.param.vid option value ('%s') is not validhl_if.param.pid option value ('%s') is not validhl_interface_handle_serial_commandexpected exactly one argument to hl_serial hl_interface_handle_device_desc_commandexpected exactly one argument to hl_device_desc set the a device description of the adapterthe vendor and product ID of the adapterexecute a custom adapter-specific commandhl_interface_execute_queuehl_interface_handle_device_desc_commandhl_interface_handle_serial_commandhl_interface_handle_layout_commandhl_interface_handle_vid_pid_commandinterface_handle_hla_commandhl_interface_inithl_interface_quithl_interface_config_tracehl_interface_init_targethl_interface_openhl_layout_opensrc/jtag/hla/hla_layout.chl_layout_initno layout specifiedti-icdihl_layout_inithl_layout_openhl_transport_initsrc/jtag/hla/hla_transport.chla_swdhla_jtagstlink_swimhl_transport_selecthl_transport_jtag_commandperform hl adapter actionshl_transport_jtag_commandhl_transport_selecthl_transport_initbasename tap_type '-irlen' count ['-expected_id' number] read from pipe failedsrc/jtag/aice/aice_pipe.cwrite to pipe failedwrite failed read failed Create pipes failedFork new process failedMap aice_pipe to STDIN failedExecute aice_pipe failedRegister SIGPIPE handler failedMap aice_pipe to STDOUT failedAICE_PIPE child process initial errorAICE_PIPE parent process initial erroraice_pipe_parent_initaice_pipe_child_initaice_pipe_openaice_pipe_readaice_pipe_writebitbang_exchangesrc/jtag/drivers/bitbang.cbitbang_swd_run_queueSWD queue return value: %02xbitbang_swd_initbitbang_swd_switch_seqbitbang_swd_write_regSWD_ACK_WAITSWD_ACK_FAULTNo valid acknowledge: ack=%dbitbang_swd_read_regWrong parity detectedbitbang_switch_to_swdSkip bitbang_swd_write_reg because queued_retval=%dSkip bitbang_swd_read_reg because queued_retval=%dBUG: Bitbang interface called, but not yet initializedbitbang_switch_to_swdbitbang_swd_switch_seqbitbang_end_statebitbang_path_movebitbang_execute_queuebitbang_swd_initbitbang_swd_read_regbitbang_swd_read_regbitbang_swd_write_regbitbang_swd_write_regbitbang_exchangebitbang_swd_run_queue{TAP move from or to unstable statemissing data from bitq interfaceextra data from bitq interfacesrc/jtag/drivers/bitq.cp@@bitq_state_movebitq_end_statebitq_path_movebitq_execute_queuesrc/jtag/drivers/stlink_usb.chandle != NULLSWD fault response (0x%x)Write errorVerify errorSTLINK_SWD_AP_FAULTSTLINK_SWD_AP_ERRORSTLINK_SWD_AP_PARITY_ERRORSTLINK_SWD_DP_FAULTSTLINK_SWD_DP_ERRORSTLINK_SWD_DP_PARITY_ERRORSTLINK_SWD_AP_WDATA_ERRORSTLINK_SWD_AP_STICKY_ERRORbulk write failedbulk read failedget senseTracing: disableTracing: recording at %uHzIDCODE: 0x%08Xmax buffer length exceededInvalid data alignmenth->version.stlink >= 2bulk trace read failedUnable to set adapter speedstlink_usb_openmalloc failedopen failedclaim interface failedread version failedrelease interface failedreset device failedusing stlink api v%dMODE: 0x%02XTarget voltage: %fvoltage check failedSupported clock speeds are:Using TAR autoincrement: %uwait status SWD_AP_WAIT (0x%x)wait status SWD_DP_WAIT (0x%x)STLINK_SWD_AP_STICKYORUN_ERRORunknown/unexpected STLINK status code 0x%xh->version.jtag >= STLINK_TRACE_MIN_VERSIONTracing is not supported by this version.The attached ST-LINK version doesn't support this trace modeST-LINK doesn't support SWO frequency higher than %uUnable to match requested speed %d kHz, using %d kHzPrevious state query failed, trying to reconnecttransport: %d vid: 0x%04x pid: 0x%04x serial: %sSTLINK v%d JTAG v%d API v%d SWIM v%d VID 0x%04X PID 0x%04Xvid/pid are not identical: 0x%04X/0x%04X 0x%04X/0x%04Xmode (transport) not supported by devicetarget voltage may be too low for reliable debuggingselected mode (transport) not supportedinit mode failed (unable to connect to the target)p8x@@0stlink_usb_current_modestlink_usb_check_voltagestlink_usb_init_modestlink_usb_versionstlink_usb_openstlink_usb_resetstlink_usb_assert_srststlink_usb_runstlink_usb_haltstlink_usb_stepstlink_usb_read_regsstlink_usb_read_regstlink_usb_write_regstlink_usb_read_mem8stlink_usb_read_mem8stlink_usb_read_mem32stlink_usb_read_mem32stlink_usb_write_mem8stlink_usb_write_mem8stlink_usb_get_rw_statusstlink_usb_write_mem32stlink_usb_write_debug_regstlink_usb_idcodestlink_usb_idcodestlink_speedstlink_usb_read_tracestlink_usb_read_tracestlink_usb_trace_readstlink_usb_error_checkstlink_usb_error_checkstlink_usb_mode_enterstlink_usb_statestlink_usb_statestlink_usb_trace_enablestlink_usb_trace_enablestlink_usb_xfer_v1_get_statusstlink_usb_xfer_rwstlink_usb_xfer_rwstlink_usb_xferstlink_usb_xferstlink_usb_trace_disablestlink_usb_trace_disablestlink_config_trace}d(2O 333333??src/jtag/drivers/ti_icdi_usb.cUnexpected Reply from ICDI: %cmaximum nack retries attemptedmaximum data retries attemptedmemory buffer too small: requires 0x%x actual 0x%xReceived too much data from the target.Unmatched escape character in target response.read more bytes than expected: actual 0x%x expected 0x%xtransport: %d vid: 0x%04x pid: 0x%04xinvalid max packet, using defaultsmax packet supported : %i bytesunable to enable extended mode: 0x%xError TX Data %dError RX Data %dResending packet %dError RX timeout %d$%s$X%x,%x:memory write failed: 0x%xx%x,%xmemory read failed: 0x%xicdi_usb_openlibusb init failedInvalid Reply Receivedunable to get ICDI versionICDI Firmware version: %squery supported failed: 0x%xPacketSizeP%x=register write failed: 0x%xstep failed: 0x%xhalt failed: 0x%xcontinue failed: 0x%xp%xregister read failed: 0x%xfailed to convert resulticdi_usb_queryicdi_usb_versionicdi_usb_openicdi_usb_runicdi_usb_halticdi_usb_stepicdi_usb_read_regicdi_usb_write_regremote_unescape_inputicdi_usb_read_mem_inticdi_get_cmd_resulticdi_usb_write_mem_inticdi_send_packeticdi_send_packetLack of memory.Index %d is invalid for %s.versaloon pending dataversaloon_bufBuffer %s is not valid.Invalid parameter of %s.send usb dataFail to %s.receive usb datacommunicate with versalooninitialize usbtoxxxsrc/jtag/drivers/versaloon/versaloon.cversaloon_get_target_voltageversaloon_initversaloon_send_commandversaloon_add_pendingversaloon_add_want_possrc/jtag/drivers/usb_blaster/ublast2_access_libusb.cAltera USB-Blaster II (uninitialized) foundError while downloading the firmwareAltera USB-Blaster II not foundAltera USB-Blaster II found (Firm. rev. = %s)Loading firmware...No firmware path specifiedWaiting for renumerate...ublast2_write_firmware_sectionload_usb_blaster_firmwareublast2_libusb_initusb blaster interface using libftdisrc/jtag/drivers/usb_blaster/ublast_access_ftdi.cublast_ftdi_writeublast_ftdi_readublast_ftdi_initfailed erasing sectors %d to %dillegal protection block rangefailed setting protection for blocks %d to %derror writing to flash at address 0x%08x at offset 0x%8.8xerror reading to flash at address 0x%08x at offset 0x%8.8xiterating over more than one flash bank.Whole bank access must start at beginning of bank.Flash access does not fit into bank.Adding extra %s range, %#8.8x to %#8.8xaddress range 0x%8.8x .. 0x%8.8x is not sector-alignedRunning slow fallback erase check - add working memoryno flash bank found for address %xsections[section_last + 1]->base_address >= c->basePadding image section %d with %d bytesTruncate flash run size to the current flash chip.Out of memory for flash bank bufferimage_read_section: section = %d, t_section_num = %d, section_offset = %d, buffer_size = %d, size_read = %dsrc/flash/nor/core.ccall flash_driver_read()flash bank %d does not existauto_probe failedNo flash at address 0x%08xBank is invalidempty section %drun_size > 0flash_write_unlockflash_write_unlockflash_iterate_address_range_innerflash_iterate_address_rangedefault_flash_mem_blank_checkdefault_flash_blank_checkget_flash_bank_by_addrget_flash_bank_by_numget_flash_bank_by_nameget_flash_bank_by_num_noprobeflash_driver_readflash_driver_writeflash_driver_protectflash_driver_erase%s: Flash bank cannot fit data.src/flash/nor/dsp5680xx_flash.c%s: Writing to odd addresses not supported for this target%s not implemented%s not tested yet.dsp5680xx_flashdsp5680xx_build_sector_listdsp5680xx_flash_writedsp5680xx_probesrc/flash/nor/efm32.cbank->num_sectors > 0Failed to read PLW %dFailed to read ULWFailed to read DLWFailed to read MLWFailed to read LB dataNULL != bank->sectorsEZR32 EFM32 Giant GeckoTiny GeckoLeopard GeckoWonder GeckoZero GeckoHappy Gecko - Rev: %dInvalid page size %uUnknown MCU family %dFailed to read EFM32 infodetected part: %sflash size = %dkbytesflash page size = %dbytes0 != efm32_mcu_info.page_sizenum_pages > 0page erase was abortederasing flash page at 0x%08xstatus 0x%xPage is lockedInvalid address 0x%xFailed to enable MSC writeFailed to erase page %dflash memory write protectedWait for WDATAREADY failedWDATA write failedWRITECMD write failedWait for BUSY failedFailed to erase LB pageFailed to write LB pageefm32efm32 flash command groupdebuglock(888888888888888888888888888888888888888888efm32x_handle_debuglock_commandefm32x_eraseefm32x_erase_pageefm32x_write_lock_dataefm32x_protectefm32x_wait_statusefm32x_write_wordNc&`h."UhBa&`i'>Bi'>B.ha&`54i'>BѝBF5U`9) P`0Fqefm32x_write_blockefm32x_writeefm32x_probeefm32x_probeefm32x_read_lock_dataefm32x_read_lock_dataefm32x_protect_checkefm32x_protect_checkefm32x_read_infoget_efm32x_infoTarget is not Cortex-Mx Devicetimed out waiting for MSC statusno working area available, can't do block memory writesno large enough working area available, can't do block memory writesflash write failed at address 0x%xinvalid flash memory write addressoffset 0x%x breaks required 4-byte alignmentodd number of bytes to write and no memory for padding bufferodd number of bytes to write (%u), extending to %u and padding with 0xffcouldn't use block writes, falling back to single memory accessesErase device data to reset page locksefm32x debug interface locked, reset the device to applyLock the debug interface of the device.No size specified for em357 flash driver, assuming 192k!em357 device programming failedaligned start protect sector to a %d sector boundaryaligned end protect sector to a %d sector boundaryem357 unlocked. INFO: a reset or power cycle is required for the new settings to take effect.error executing em357 flash write algorithmflash memory not erased before writingoffset 0x%x breaks required 2-byte alignmentUnlock entire protected flash device.src/flash/nor/em357.ctimed out waiting for flashem357 device protectedem357 mass erase completeem357 mass erase failedDevice Security Bit Setreg, bit: %d, %dem357 failed to unlock deviceem357 failed to lock deviceem357 failed to erase optionsem357 lockedem357em357 flash command groupLock entire flash device.mass_eraseErase entire flash device.em357_handle_lock_commandem357_handle_unlock_commandem357_mass_eraseem357_eraseem357_read_optionsem357_protectem357_wait_status_busyLD##a0;!;h:@em357_write_blockem357_writeem357_probeem357_protect_checkfaux flash driversrc/flash/nor/faux.cno memory for flash bank infofauxfaux flash command groupset protection sector %d to %d to %sfaux_flash_bank_commandfaux_protectoob_rawoob_onlyoob_softeccoob_softecc_kwunknown option: %sonly page-aligned addresses are supportedfailed to open '%s' for %s accessstate->address option value ('%s') is not validstate->size option value ('%s') is not validonly page-aligned sizes are supportedsrc/flash/nor/fm3.cFlash/Device type unknown!mb9bfxx1.cpumb9bfxx2.cpumb9bfxx3.cpumb9bfxx4.cpumb9bfxx5.cpumb9bfxx6.cpumb9bfxx7.cpumb9bfxx8.cpumb9afxx1.cpumb9afxx2.cpumb9afxx3.cpumb9afxx4.cpumb9afxx5.cpumb9afxx6.cpumb9afxx7.cpumb9afxx8.cpuunknown fm3 variant: %s*** Erasing mb9bfxxx type*** Erasing mb9afxxx typefm3 chip erase completefm3 chip erase failedfm3fm3 Flash command groupchip_eraseErase entire Flash device.Polling data reading timed out!fm3_busy_wait(%x) needs about %d msFujitsu MB9[A/B]FXXX: Sector Erase ... (%d to %d)Error executing flash erase programming algorithmFujitsu MB9[A/B]xxx: Chip Erase ... (may take several seconds)Fujitsu MB9[A/B]FXXX: FLASH Write ...No large enough working area available, can't do block memory writesError executing fm3 Flash programming algorithmFujitsu MB9[A/B]FXXX: Flash programming ERROR (Timeout) -> Reg R3: %x"U# $ !fm3_chip_erasefm3_flash_bank_commandfm3_busy_wait$U# % 0 fm3_erase_E-hOv5@_F5`_E-hU_F5`(M_F6h.`&M&.`*,$M-h-(Ѫ%`U%%`%` M-h- M&.` BM&.`M-h-M&.`R_E-hOv5@_F5`_E-hU_F5`M_F6h.`P-h  fm3_write_blockfm3_probeMB9BFx65S6E2CxAS6E2Cx8S6E2Cx9MB9BFx64S6E2DxMB9BFx68MB9BFx67MB9BFx66src/flash/nor/fm4.c%s MainFlash%s MainFlash Macro #%iMB9BFS6E2CxFamily %s not recognized.Error writing data bufferwriting 0x%08x-0x%08x (%dx)No working area available.fm4fm4 flash command groupCannot communicate... target not halted.Dual Flash mode is not implemented.MB9BF variant %s not recognized.S6E2CC variant %s not recognized.Spansion FM4 write at 0x%08x (%d bytes)length %d is not 2-byte aligned, rounding upNo working area available for write code.No working area available for write data.copying %d bytes to SRAM 0x%08xError executing flash sector erase programming algorithmTimeout error from flash write programming algorithmUnexpected error %d from flash write programming algorithmSpansion FM4 erase sectors %d to %dTimeout error from flash sector erase programming algorithmUnexpected error %d from flash sector erase programming algorithm N0N@NMMMNxMNOOOOOTOTOTOPs6e2cc_bank_setupmb9bf_bank_setupfm4_flash_bank_commandfm4_flash_erasefm4_flash_writes6e2cc_probemb9bf_probefm4_probefm4_get_info_commandsrc/flash/nor/jtagspi.cFlash sector invalidno memory for spi bufferloading jtagspi irTarget has no JTAG tapFlash bank not yet probed.waited %ld mstimeout, device still busypage write errorwrote page at 0x%08xFlash bank not probedFlash sector %d protectedTrying bulk erase.sector %d took %ld msSector erase failed.jtagspiinfo->ir option value ('%s') is not validinfo->dr_len option value ('%s') is not valid JTAGSPI flash bank not probed yet SPIFI flash information: Device '%s' (ID 0x%08x) Unknown flash device (ID 0x%08x)Found flash device '%s' (ID 0x%08x)Cannot enable write to flash. Status=0x%08xerase from sector %d to sector %dBulk flash erase failed. Falling back to sector erase.jtagspi_flash_bank_commandjtagspi_sector_erasejtagspi_bulk_erasejtagspi_erasejtagspi_protectjtagspi_waitjtagspi_write_enablejtagspi_writejtagspi_readjtagspi_set_irjtagspi_cmdjtagspi_probe(ANY)PFlashFlexNVMFlexRAMsrc/flash/nor/kinetis.cIssue a 'reset init' command.Unsupported K-family FAMIDUnsupported Kinetis K22 DIEIDUnsupported K-seriesadd flash_bank kinetis %sFlash operation timed outFlash controller is busyFCF_FOPT 0x%02xprotection./src/target/arm_adi_v5.hWDOG_STCTRLH = 0x%xFailed to read SIMSDIDMDM_REG[0x%02x] <- %08Xap->dap->ops != NULLMDM: dap_run failedError writing flash at %08xdataflasheebkpEEPROM backup %d KBdata flash %d KBUnsupported EEPROM sizetarget_write_memory failedError writing section at %08xFlash write error at %08xwrite longword @ %08xflash write @08%xerase sector %d failedMDM_REG[0x%02x]: %08XMDM: halt timed outMDM: polling timed outMDM: failed to assert resetMDM: mass erase is disabledMDM: mass erase timeoutMDM: unknown ID %08XkinetismdmMDM-AP command groupdisable_wdogDisable the watchdog timernvm_partitionfcf_source['protection'|'write']fopt[num]check_securityIssue a halt via the MDM-APIssue a reset via the MDM-AP%s driver for %s flash bank %s at 0x%8.8xProtection checks for FlexRAM not supportedProtection setting is possible with 'kinetis fcf_source protection' only!No protection possible for current bank!Protection bits will be written at the next FCF sector erase or write.Do not issue 'flash info' command until protection is written,doing so would re-read protection status from MCU.Switching from VLPR to RUN mode.Flash operation not possible in current run mode: SMC_PMSTAT: 0x%xUnsupported Kinetis FAMILYID SUBFAMIDUnsupported KV FAMILYID SUBFAMIDMCU is unsupported, SDID 0x%08xSDID: 0x%08X FCFG1: 0x%08X FCFG2: 0x%08XMAXADDR1 is zero, number of flash banks adjusted to 1MAXADDR1 is non zero, number of flash banks adjusted to 2SIM_FCFG1 PFSIZE = 0xf: please check if pflash is %u KBFlexNVM: %u PFlash: %u FlexRAM: %u PFLSH: %d%d blocks total: %d PFlash, %d FlexNVMProbing flash info for bank %dFlexNVM bank %d limited to 0x%08x due to active EEPROM backupFlexRAM support not yet implementedCannot determine parameters for bank %d, only %d banks on deviceMAXADDR0 0x%02x check failed, please report to OpenOCD mailing listFlexNVM MAXADDR1 0x%02x check failed, please report to OpenOCD mailing listUnknown sector size for bank %dFlash operation failed, illegal commandFlash operation failed, protection violatedFlash operation failed, read collisionArbitrary Flash Configuration Field writes enabled.Protection info writes to FCF disabled.BEWARE: incorrect flash configuration may permanently lock the device.Protection info writes to Flash Configuration Field enabled.Arbitrary FCF writes disabled. Mode safe from unwanted locking of the device.Disabling Kinetis watchdog (initial WDOG_STCTRLH = 0x%x)error executing kinetis wdog unlock algorithmMDM: failed to queue a write requestError executing kinetis Flash programming algorithmftfx command failed FSTAT: %02X FCCOB: %02X%02X%02X%02X %02X%02X%02X%02X %02X%02X%02X%02XNo EEPROM backup, data flash onlyNo data flash, EEPROM backup onlyNo EEPROM backup, data flash only (DEPART not set)Unsupported EEPROM backup size code 0x%02xUnsupported EEPROM sizes ratioDEPART 0x%x, EEPROM size code 0x%xFlexNVM partition set. Please reset MCU.FlexNVM banks will be re-probed to set new data flash size.This device supports Program Longword execution only.FlexRAM not ready, fallback to slow longword write.section @ %08x aligned begin %u, end %uwrite section @ %08x with length %u bytesoffset 0x%x breaks the required alignmentError writing longword at %08xFlash write strategy not implementedFlash Configuration Field written.Reset or power off the device to make settings effective.Flash Configuration Field erased, DO NOT reset or power off the deviceuntil correct FCF is programmed or MCU gets security lock.Flash Configuration Field write failedIgnoring errored PFlash sector blank-checkkinetis_blank_check not supported yet for FlexRAMMDM: failed to queue a read requestCannot perform halt with a high-level adapterMDM: failed to read MDM_REG_STATMDM: halt succeded after %d attempts.MDM: failed to clear MDM_REG_CTRLCannot perform mass erase with a high-level adapterMDM: Press RESET button now if possible.MDM: waiting for mass erase conditions timed out.Mass erase of a secured MCU is not possible without hardware reset.Connect SRST, use 'reset_config srst_only' and retry.MDM: failed to start mass eraseCannot perform reset with a high-level adapterMDM: failed to write MDM_REG_CTRLCannot check flash security status with a high-level adapterMDM: failed to read ID registerMDM: dap_run failed when validating secured state*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! ************** ******** Your Kinetis MCU is in secured state, which means that, ******** with exception for very basic communication, JTAG/SWD ******** interface will NOT work. In order to restore its ******** functionality please issue 'kinetis mdm mass_erase' ******** command, power cycle the MCU and restart OpenOCD. ******** Your Kinetis MCU is probably locked-up in RESET/WDOG loop. ******** Common reason is a blank flash (at least a reset vector). ******** Issue 'kinetis mdm halt' command or if SRST is connected ******** and configured, use 'reset halt' ******** If MCU cannot be halted, it is likely secured and running ******** in RESET/WDOG loop. Issue 'kinetis mdm mass_erase' ****MDM: Chip is unsecured. Continuing.Kinetis flash controller commandsShow/set data flash or EEPROM backup size in kilobytes, set two EEPROM sizes in bytes and FlexRAM loading during reset('info'|'dataflash' size|'eebkp' size) [eesize1 eesize2] ['on'|'off']Use protection as a source for Flash Configuration Field or allow writing arbitrary values to the FCF Mode 'protection' is safe from unwanted locking of the device.FCF_FOPT value source in 'kinetis fcf_source protection' modeCheck status of device security lockIssue a complete flash erase via the MDM-AP@feeeeee@feeeeeeyyyyyyy+zy z z z z z zyKJځJځ$C @ (kinetis_disable_wdogkinetis_check_flash_security_statuskinetis_mdm_haltkinetis_mdm_mass_erasedap_queue_ap_writekinetis_mdm_write_registerdap_rundap_queue_ap_readkinetis_mdm_read_registerkinetis_mdm_poll_registerkinetis_mdm_resetkinetis_disable_wdog_handlerkinetis_nvm_partitionkinetis_fcf_source_handlerkinetis_flash_bank_commandkinetis_erasekinetis_protectkinetis_write_blockkinetis_write_sectionskinetis_write_innerkinetis_writekinetis_probekinetis_ftfx_decode_errorkinetis_ftfx_commandkinetis_ftfx_preparekinetis_check_run_modekinetis_blank_checkkinetis_protect_checkh.UhB``'q/h`''p5B5U`h. &x>Bp'>B09)%U`src/flash/nor/kinetis_ke.cNo flash protection found.Unsupported KE familyKE02 sub-familyKE04 sub-familyKE06 sub-familyUnsupported KE sub-familyadd flash_bank kinetis_ke %sKE04 - Unknown pin countPlease reset the target.Flash clock readyMDM: flash ready timeoutWatchdog stoppedMDM : flash ready timeoutbank != NULLKinetis KE: FLASH Write ...flash access errorflash protection violationkinetis_ketest_securingFlash protected. FPOPEN=%i FPLDIS=%i FPHDIS=%i FPLS=%i FPHS=%i%s driver for flash bank %s at 0x%8.8xkinetis_ke_protect not supported yetFlash clock was already set and contains an invalid value.Flash clock register is locked and contains an invalid value.**** functionality please issue 'kinetis_ke mdm mass_erase' ****MDM: Failed to check security status of the MCU. Cannot proceed furtherNo working area available for watchdog algorithmError executing Kinetis KE watchdog algorithmflash configuration field erased, please reset the deviceKinetis KE NAND flash controller commandsLTXkinetis_ke_check_flash_security_statusdap_queue_ap_readkinetis_ke_mdm_read_registerkinetis_ke_mdm_poll_registerdap_rundap_queue_ap_writekinetis_ke_mdm_write_registerkinetis_ke_mdm_mass_erasekinetis_ke_securing_testkinetis_ke_securing_testkinetis_ke_flash_bank_commandkinetis_ke_erasekinetis_ke_protectkinetis_ke_write_wordskinetis_ke_writekinetis_ke_probekinetis_ke_probekinetis_ke_prepare_flashkinetis_ke_blank_checkkinetis_ke_protect_checkK"x\x*@Mو]M]\pـp @ (kinetis_ke_stop_watchdoglpc2000 flash driver variant: %i, clk: %ikHzlpc2000_info->cclk option value ('%s') is not validtemp_base option value ('%s') is not validno working area specified, can't write LPC2000 internal flashBUG: unknown lpc2000_info->variant encounteredWrite memory at address 0x%8.8x failed (check work_area definition)BUG: unknown lpc2000->variant encounteredIAP command = %i (0x%8.8x, 0x%8.8x, 0x%8.8x, 0x%8.8x, 0x%8.8x) completed with result = %8.8xlpc2000 prepare sectors returned %ilpc2000 erase sectors returned %iBUG: unknown Part ID encountered: 0x%xIf auto-detection fails for this part, please email openocd-devel@lists.sourceforge.net, citing part id 0x%x. BUG: unknown bank->size encounteredBUG: unknown bank->size encountered, LPC1100 flash size must be a multiple of 4096no sufficient working area specified, can't access LPC2000 IAP interfacelpc2000 IAP returned status code %iBUG: unknown LPC2000 status code %ioffset 0x%x breaks required alignment 0x%xfirst_sector: %i, last_sector: %ilpc2000_info->checksum_vector < 8Verification will fail since checksum in image (0x%8.8x) to be written to flash is different from calculated vector checksum (0x%8.8x).To remove this warning modify build tools on developer PC to inject correct LPC vector checksum.writing 0x%x bytes to address 0x%xprint part id of lpc2000 flash bank lpc2000_v1lpc2000_v2lpc1700lpc4000lpc1800lpc4300lpc800lpc1100lpc1500lpc54100unknown LPC2000 variant: %ssrc/flash/nor/lpc2000.ccalc_checksumsp_svclr_svcCould not get part IDlpc2000 part id: 0x%8.8xVector 0x%2.2x: 0x%8.8xchecksum: 0x%8.8xlpc2000 returned %ilpc2000lpc2000 flash command grouppart_id((lpc2000_handle_part_id_commandlpc2000_flash_bank_commandlpc2000_eraselpc2000_writelpc2000_writelpc2000_build_sector_listget_lpc2000_part_idlpc2000_auto_probe_flashlpc2000_probelpc2000_iap_calllpc2000_iap_working_area_initlpc2000_iap_blank_checklpc2000_erase_checklpc288x_info->cclk option value ('%s') is not validProcessor not halted/not probedCannot identify target as an LPC288X (%08x)src/flash/nor/lpc288x.cLPC288xTimedout!Bad sector rangeRange check failed %x %xWrite to flash buffer failedlpc288xlpc288x_eraselpc288x_wait_status_busylpc288x_writelpc288x_read_part_infolpc288x_probelpc288x_system_readylpc288x_erase_checkclk_sys_fmc option value ('%s') is not validflash clock must be at least %u kHzflash clock must be a maximum of %u kHzWrite operation to file %s failedUnknown LPC29xx derivative (FEATx=%08x:%08x:%08x:%08x)Flash bank %d: Device %s, %u KiB in %d sectorsFlashless device cannot be handledCannot determine sector security statussignature: 0x%8.8x:0x%8.8x:0x%8.8x:0x%8.8xIndex sector write failed @ page %dno (large enough) working area, falling back to host modeUnable to write block write code to targetUnable to write data to targetExecution of flash algorithm failed.Command execution not allowed! (use 'password' command first)failed to update index sector page 5failed to update index sector page 6failed to update index sector page 7Sectors security will become effective after next power cycleCommand execution not allowed!Only one section allowed in image file.Incorrect image file size. Expected %d, got %uPotentially dangerous operation allowed in next command!Calculate and display signature of flash bank.Copies 912 bytes of customer information from index sector into file.Enter fixed password to enable 'dangerous' options.Copies 912 bytes of customer info from file to index sector.bank_id filename ('bin'|'ihex'|'elf'|'s19')Activate sector security for a range of sectors. It will be effective after a power cycle.bank_id first_sector last_sectorDisable the JTAG port. It will be effective after a power cycle.src/flash/nor/lpc2900.cCould not open file %sLPC2917LPC2919LPC2939LPC2930LPC2923LPC2927LPC2919/01LPC2929LPC2926LPC2925LPC2921LPC2917/01Device is not an LPC29xxNever heard about sector %dTimeout!Skip secured sector %dWrite failed @ 0x%8.8xJTAG security set. Good bye!Illegal sector rangecouldn't read from file '%s'I_know_what_I_am_doingWrong password (use '%s')lpc2900LPC2900 flash command groupsignatureread_custombank_id filenamebank_id passwordwrite_customsecure_sectorsecure_jtaglpc2900_handle_signature_commandlpc2900_handle_read_custom_commandlpc2900_handle_write_custom_commandlpc2900_handle_secure_sector_commandlpc2900_write_index_pagelpc2900_handle_secure_jtag_commandlpc2900_flash_bank_commandlpc2900_erase ``V诃@僠௓  Rlpc2900_writelpc2900_probelpc2900_wait_statuslpc2900_erase_checklpc2900_is_ready?@`?MbP?target must be halted to use LPC3180 NAND flash controllerlpc3180_nand_ready count start=%dlpc3180_nand_ready count end=%dBUG: no LPC3180 NAND flash controller selectedBUG: bus_width neither 8 nor 16 bitosc_freq option value ('%s') is not validLPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i%s controller selected bulk mode is not available%s controller selected bulk mode is availablenand device '#%s' is out of boundsLPC3180 HCLK currently clocked at %i kHzlpc3180_controller_ready count start=%dlpc3180_controller_ready count=%dLPC3180 NAND controller timed out after resetLPC3180 only supports 8 or 16 bit bus width, not %iLPC3180 only supports 8 bit bus widthLPC3180 only supports 3 or 4 address cycles, not %iLPC3180 only supports 512 or 2048 byte pages, not %ino LPC3180 NAND flash controller selected, using default 'mlc'lpc3180_tc_ready count start=%dLPC3180 MLC controller can't write OOB data onlyLPC3180 MLC controller can't write more than 6 bytes for each quarter's OOB datatimeout while waiting for completion of auto encode cyclewrite operation didn't pass, status: 0x%2.2xReserve at least 0x%x physical target working areaReserve the physical target working area at word boundaryno working area specified, can't read LPC internal flashtimeout while waiting for completion of DMAtimeout while waiting for completion of auto decode cycleuncorrectable error detected: 0x%2.2x%i symbol error detected and correctedECC mismatch at 256 bytes size block= %d at page= 0x%xLPC3180 NAND flash controller commandsselect MLC or SLC controller (default is MLC), SLC can be set to bulk modebank_id ['mlc'|'slc' ['bulk'] ]src/flash/nand/lpc3180.cslcmlcbulk%s controller selectedPLL is not lockedlpc3180_tc_ready count=%ddata size exceeds page sizecouldn't read statusPage = 0x%x was written.Page = 0x%x was read.lpc3180lpc3180_nand_device_commandlpc3180_plllpc3180_cycle_timelpc3180_initlpc3180_resetlpc3180_commandlpc3180_addresslpc3180_write_datalpc3180_read_datalpc3180_write_pagelpc3180_tc_readylpc3180_controller_readylpc3180_read_pagelpc3180_nand_readyAA BpAB4B A%02x: %02x %02x %02x %02x %02x %02x %02x %02xtarget must be halted to use LPC32xx NAND flash controllerBUG: no LPC32xx NAND flash controller selectedlpc32xx_nand_ready count start=%dlpc32xx_nand_ready count end=%dLPC32xx oscillator frequency should be between 1000 and 20000 kHz, was %iLPC32xx HCLK currently clocked at %i kHzlpc32xx_controller_ready count start=%dlpc32xx_controller_ready count=%dLPC32xx MLC NAND controller timed out after resetLPC32xx SLC NAND controller timed out after resetLPC32xx driver doesn't support %i address cyclesLPC32xx doesn't support page size %ino LPC32xx NAND flash controller selected, using default 'slc'lpc32xx_tc_ready count start=%dlpc32xx_start_slc_dma: Could not set SLC_TCcould not set MLC_ECC_AUTO_DEC_REGCan't allocate working area in LPC internal RAMSLC read page %x data=%u, oob=%uCould not write DMA descriptors to IRAMlpc32xx_read_page_slc: NAND_CMD_READ0 failedlpc32xx_read_page_slc: Could not set SLC_CFGCould not write DMA descriptor to DMAClpc32xx_read_page_slc: DMA read failedCould not read hw generated ECC from IRAMerror detected and corrected: %u/%duncorrectable error detected: %u/%dLPC32xx MLC controller can't write OOB data onlyLPC32xx MLC controller can't write more than 6 bytes for each quarter's OOB datacould not set MLC_ECC_AUTO_ENC_REGSLC write page %x data=%d, oob=%d, data_size=%u, oob_size=%ulpc32xx_dma_ready count start=%dCould not read DMACRawIntTCStatCould not read DMACRawIntErrStatlpc32xx_dma_ready DMA error, abortedReading hw generated ECC from IRAM failedCould not write OOB DMA descriptor to DMACLPC32xx NAND flash controller commandsselect MLC or SLC controller (default is MLC)src/flash/nand/lpc32xx.ccould not read MLC_DATAcould not read SLC_DATAcould not read MLC_ISRcould not read SLC_STATcould not set MLC_DATAcould not set SLC_DATAcould not set MLC_ADDRcould not set SLC_ADDRcould not set MLC_CMDcould not set SLC_CMDcould not read SYSCLK_CTRLcould not read HCLK_CTRLcould not read HCLKPLL_CTRLcould not read CLKDIV_CTRLcould not set MLC_STATcould not set SLC_STATcould not set SLC_CTRLLPC32xx doesn't support %icould not set FLASHCLK_CTRLcould not set MLC_CEHcould not set MLC_LOCKcould not set MLC_ICRcould not set MLC_TIME_REGcould not set SLC_CFGcould not set SLC_IENcould not set DMACLK_CTRLcould not set DMACConfigcould not set SLC_TACCould not read SLC_INT_STATlpc32xx_tc_ready count=%dCould not set DMACIntTCClearCould not set DMACIntErrClearCould not set DMACC0ConfigCould not set SLC_CTRLCould not set SLC_ICRcould not read MLC_BUF (data)could not read MLC_BUF (oob)Could not read data from IRAMCould not read OOB from IRAMcould not set MLC_ECC_ENC_REGcould not set MLC_BUF (data)could not set MLC_BUF (oob)NAND_CMD_SEQIN failedCould not set SLC_CFGCould not write data to IRAMDMA failedlpc32xx_dma_ready count=%dData DMA failed during writeWriting OOB to IRAM failedDMA OOB failednand_write_finish failedlpc32xxbank_id ['mlc'|'slc' ]lpc32xx_nand_device_commandlpc32xx_plllpc32xx_cycle_timelpc32xx_initlpc32xx_resetlpc32xx_commandlpc32xx_addresslpc32xx_write_datalpc32xx_read_datalpc32xx_dma_readylpc32xx_write_page_slclpc32xx_write_page_mlclpc32xx_write_pagelpc32xx_dump_ooblpc32xx_tc_readylpc32xx_start_slc_dmalpc32xx_read_page_slclpc32xx_controller_readylpc32xx_read_page_mlclpc32xx_read_pagelpc32xx_nand_ready()*+,-./0123456789:;<=>?  SPIFI flash bank not probed yet Allocating working area for SPIFI init algorithmInsufficient working area to initialize SPIFI module. You must allocate at least %zdB of working area in order to use this driver.Writing algorithm to working area at 0x%08xError executing SPIFI init algorithmWrites past end of flash. Extra data discarded.Insufficient working area. You must configure a working area > %zdB in order to write to SPIFI flash.Insufficient working area. Please allocate at least %zdB of working area to enable flash writes.Working area size is limited; flash writes may be slow. Increase working area size to at least %zdB to reduce write times.Error executing flash write algorithmtimeout waiting for flash to finish write/erase operationChip supports the bulk erase command. Will use bulk erase instead of sector-by-sector erase.Bulk flash erase failed. Falling back to sector-by-sector erase.Insufficient working area. You must configure a working area of at least %zdB in order to erase SPIFI flash.Error executing flash erase algorithmsrc/flash/nor/lpcspifi.cUninitializing LPC43xx SSPRunning SPIFI init algorithmoffset=0x%08x count=0x%08xTimeout while polling BSYGetting IDlpcspifilpcspifi_flash_bank_commandlpcspifi_write_enableOJ OO@O@OOODOJ OhOJ OO  OOZ OO@Z OORO ;HJO 3O /<E:O #OIO)O $&O O 9DO@Z  pGOOOJ pG lpcspifi_eraseOJ OO@O@OOODOJ OhOJ OO  OOZ OO@Z OOO DEjO S`bO KO GT]RO ;OI7O)3O /GGhGE?!B(G`;E"D#O O O@Z  pGOOOJ pG P`0Flpcspifi_writeOOCO!OCOBOAO@OA FFOCO!@@hh@0OOOGlpcspifi_set_hw_modepoll_ssp_busywait_till_readylpcspifi_read_flash_idlpcspifi_probeNAND flash device '%s' not foundcontroller initialization failedBUG: controller reported that it doesn't support default parametersBUG: unknown controller initialization failureunknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2xNAND flashes with 256 byte pagesize are not supportedBUG: small page NAND device with more than 8 GiB encounteredBUG: large page NAND device with more than 32 GiB encounteredcontroller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)timeout waiting for NAND flash block erase to completedidn't erase %sblock %d; status: 0x%2.2xUnable to write data to NAND deviceUnable to write OOB data to NAND deviceK9GAG08 2GB NAND 3.3V x8 MLC 2b/cellK9LBG08 4GB NAND 3.3V x8 MLC 2b/cellsrc/flash/nand/core.cfound %s (%s)bad block: %ibad RenesasST MicroNAND 1MiB 5V 8-bitNAND 2MiB 5V 8-bitNAND 4MiB 5V 8-bitNAND 1MiB 3.3V 8-bitNAND 2MiB 3.3V 8-bitNAND 4MiB 3.3V 8-bitNAND 8MiB 3.3V 8-bitNAND 8MiB 1.8V 8-bitNAND 8MiB 1.8V 16-bitNAND 8MiB 3.3V 16-bitNAND 16MiB 1.8V 8-bitNAND 16MiB 3.3V 8-bitNAND 16MiB 1.8V 16-bitNAND 16MiB 3.3V 16-bitNAND 32MiB 1.8V 8-bitNAND 32MiB 3.3V 8-bitNAND 32MiB 1.8V 16-bitNAND 32MiB 3.3V 16-bitNAND 64MiB 1.8V 8-bitNAND 64MiB 3.3V 8-bitNAND 64MiB 1.8V 16-bitNAND 64MiB 3.3V 16-bitNAND 128MiB 1.8V 8-bitNAND 128MiB 3.3V 8-bitNAND 128MiB 1.8V 16-bitNAND 128MiB 3.3V 16-bitNAND 256MiB 3.3V 8-bitNAND 256MiB 1.8V 8-bitNAND 256MiB 1.8V 16-bitNAND 256MiB 3.3V 16-bitNAND 512MiB 1.8V 8-bitNAND 512MiB 3.3V 8-bitNAND 512MiB 1.8V 16-bitNAND 512MiB 3.3V 16-bitNAND 1GiB 1.8V 8-bitNAND 1GiB 3.3V 8-bitNAND 1GiB 1.8V 16-bitNAND 1GiB 3.3V 16-bitNAND 2GiB 1.8V 8-bitNAND 2GiB 3.3V 8-bitNAND 2GiB 1.8V 16-bitNAND 2GiB 3.3V 16-bitnand_write_page_rawnand_write_finishnand_erasenand_probenand_build_bbtinfo memorymain memoryMDR32Fx - %ssrc/flash/nor/mdr.cmdrmdr_info->mem_type option value ('%s') is not validmdr_info->page_count option value ('%s') is not validmdr_info->sec_count option value ('%s') is not validTarget needs reset before flash operationsodd number of bytes to write, padding with 0xffCan't use block writes, falling back to single memory accessescount 0x%x breaks required 4-byte alignmentflash bank mdr 0 0 : 0 for main memory, 1 for info memorymdr_erasehh..UhB.hD``N7C`&%N7C` &&7C`=&&C`NC`& NC`54BF5U`9)0F>.pG@ @ mdr_write_blockmdr_writemdr_readstatus: 0x%08xsrc/flash/nor/mrvlqspi.cstatus: 0x%08XID is 0x%02x 0x%02x 0x%02xmrvlqspi QSPI flash bank not probed yet QSPI flash information: Device '%s' ID 0x%08x mrvlqspi_info->reg_base option value ('%s') is not validUnknown flash device ID 0x%08xFound flash device '%s' ID 0x%08xmrvlqspi_flash_bank_commandmrvlqspi_flash_busy_statusmrvlqspi_stop_transfermrvlqspi_flash_eraseO DEk___ k}_1F__ ZGhGE?0B(G`;+EPD-__ __ )  4+S_hpG_h pGHx_XpGH_xiM8HHpG_x_HhHH_H(_xpG P`0Fmrvlqspi_flash_writemrvlqspi_read_idmrvlqspi_probemrvlqspi_set_ss_statemrvlqspi_read_bytemrvlqspi_fifo_flushmrvlqspi_flash_readwrite_data() not implementedsrc/flash/nand/mx3.c%s sending timeoutdata outputnothing to programdata inputIOMUX for {%s} is badclock gating to EMI disabledpins mode overrided by GPRd0,d1,d2d3,d4,d5,d6d8,d9,d10d11,d12,d13,d14nfwp,nfce,nfrbnfwe,nfre,nfale,nfcleNAND read-onlyno memory for nand controllerhweccimx31NAND flash is tight-locked, reset neededmain area readed with 1 (correctable) errormain area readed with more than 1 (incorrectable) errorspare area readed with 1 (correctable) errorpart of spare block will be overrided by hardware ECC generatorNAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with itnand device imx31 target noecc|hweccimx31_nand_device_commandtest_iomux_settingsimx31_initinitialize_nf_controllerimx31_write_dataget_next_byte_from_sram_bufferget_next_halfword_from_sram_bufferimx31_write_pagepoll_for_complete_opdo_data_outputimx31_read_pagevalidate_target_statecan't get NAND statustrying to access out of SRAM buffer bound (addr=0x%x)minimal granularity is one half-word, %d is incorrecttarget must be halted to use mx3 NAND flash controllersrc/flash/nand/mxc.cMXC_NF : work with ECC modemx25mx27mx35biswapBI-swap enabledBI-swapping enabled on %sBI-swapping disabled on %sUnCorrectable RS-ECC ErrorMXC_NF : bus is 16-bit widthMXC_NF : bus is 8-bit widthmxcMXC_NF : work in Big Endian modeMXC_NF : work in Little Endian modeMXC_NF : work without ECC modeuse "nand device mxc target mx25|mx27|mx31|mx35 noecc|hwecc [biswap]"invalid nand device number or name: %smain area read with 1 (correctable) errormain area read with more than 1 (incorrectable) errorspare area read with 1 (correctable) error%d Symbol Correctable RS-ECC ErrorMXC_NF : Error reading page %dDue to NFC Bug, oob is not correctly implemented in mxc drivermxc_read_data : read data failed : '%x'MXC_NF : NAND controller can handle pagesize of 2048MXC driver does not have support for 4k pagesize.MXC NAND flash controller commandsTurns on/off bad block information swaping from main area, without parameter query status.mxc_nand_device_commandmxc_initinitialize_nf_controllermxc_write_dataget_next_byte_from_sram_bufferget_next_halfword_from_sram_buffermxc_read_datamxc_write_pagepoll_for_complete_opmxc_read_pagevalidate_target_stateecc_status_v2ecc_status_v1can't get NAND statustrying to access out of SRAM buffer bound (addr=0x%x)minimal granularity is one half-word, %d is incorrecttarget must be halted to use mxc NAND flash controller NIIET Cortex-M4F %s %ssrc/flash/nor/niietcm4.cService mode erase timeoutdone! All data erased.Userflash operation timeoutUserflash operation errorUserflash full erase done!mainK1921VK01TGPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOH0x%08x base adressPlese wait ...gpioagpiobgpiocgpiodgpioegpiofgpioggpiohfunc1func3Bootflash operation timeoutBootflash operation error%d byte of %dniietcm4niietcm4 flash command groupuflash_read_byteuflash_write_byteuflash_full_eraseuflash_eraseuflash_protect_checkCheck sectors protect.bank_id ('main'|'info')uflash_protectbflash_info_remapbank_id ('on'|'off')extmem_cfgextmem_bootservice_mode_erasedriver_infoTry to perform service mode erase. Please wait ...All sectors of info userflash are not protected!All sectors of info userflash are protected!Userflash sector #%03d: 0x%04x (0x100) is not protected!Userflash sector #%03d: 0x%04x (0x100) is protected!uflash_addr option value ('%s') is not validRead userflash %s region: address = 0x%04x, value = 0x%02x. this flash will be used for debugging, writing and etc unknown chipid, assuming K1921VK01T MEMORY CONFIGURATION Bootflash : %d kB total %d pages %d kB each 0x%08x base adress %sInfo bootflash : %d kB total %d pages %d kB each %s %sUserflash : %d kB total %d pages %d B each %d bit cells not maped to global adress space Info userflash : %d B total %d pages of %d B each %d bit cells not maped to global adress space RAM : 192 kB total 0x20000000 base adress External memory : 8/16 bit address space 0x%08x base adress INFOWORD STATUS Bootflash info region remap : %s External memory boot port : %s External memory boot pin : %d External memory interface alternative function : %d Option boot from external memory : %s H[2] was HIGH while startup. Device entered service mode. All flashes were locked. If you want to perform emergency erase (erase all flashes), please use "service_mode_erase" command and reset device. Do not forget to pull H[2] down while reset for returning to normal operation mode. Try to enable %s userflash sectors %d through %d protection. Please wait ... Try to disable %s userflash sectors %d through %d protection. Please wait ... Try to enable boot from external memory. Please wait ...Try to disable boot from external memory. Please wait ...Try to enable bootflash info region remap. Please wait ...Try to disable bootflash info region remap. Please wait ...pin option value ('%s') is not validTry to configure external memory boot interface: port = %s pin = %s func = %s Please wait ...Erase %s userflash pages %d through %d done!uflash_data option value ('%s') is not validWrite userflash %s region: address = 0x%04x, value = 0x%02x. Please wait ... niietcm4 flash driver version: %d.%d author: Bogdan Kolbov mail: kolbov@niiet.ruoffset 0x%x breaks required 4-word alignmentOdd number of words to write and no memory for padding bufferOdd number of words to write, padding with 0xFFFFFFFFflash bank niietcm4 0 0 Read byte from main or info userflash regionbank_id ('main'|'info') addressWrite byte to main or info userflash regionbank_id ('main'|'info') address valueErase all userflash including info regionErase sectors of main or info userflash region, starting at sector first up to and including last.bank_id ('main'|'info') first_sector_num last_sector_numProtect sectors of main or info userflash region, starting at sector first up to and including last.bank_id ('main'|'info') first_sector_num last_sector_num ('on'|'off')Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).Configure external memory interface for boot.bank_id ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')Enable boot from external memory.Perform emergency erase of all flash (bootflash and userflash).Show information about flash driver.niietcm4_handle_uflash_write_byte_commandniietcm4_handle_uflash_full_erase_commandniietcm4_handle_uflash_erase_commandniietcm4_handle_uflash_protect_check_commandniietcm4_handle_uflash_protect_commandniietcm4_handle_bflash_info_remap_commandniietcm4_handle_extmem_cfg_commandniietcm4_handle_extmem_boot_commandniietcm4_handle_service_mode_erase_commandniietcm4_eraseniietcm4_protectniietcm4_opstatus_checkOh.#UhB.h~`5.h>e5.h~e5.he5<`4`h.. &~aBF5U`9) P`0Fniietcm4_write_blockniietcm4_writeniietcm4_probeniietcm4_uopstatus_checkget_niietcm4_infonot maped to global adress spacenoncesrc/flash/nor/nrf51.cchip != NULLUnknown device (HWID 0x%08x)Couldn't read code page sizeInvalid bank address 0x%08xCouldn't read %xCouldn't read PPFC registerbytes % 4 == 0Erase enable did not completeErasing page at 0x%xFailed to erase the chipWrite enable did not completeInvalid sector @ 0x%08xnrf51nrf51 flash command group51822QFAACA/C0QFABCEAABAFA0GC0G0G2G3CA0DA0D00H0QFACCDABCFAC51422A0ADAAA00Couldn't read code region 0 size[FICR]Couldn't read code region 0 size[UICR]Couldn't read CONFIGID registernRF%s-%s(build code: %s) %ukB FlashCouldn't read code memory sizeChip's reported Flash capacity does not match expected one [factory information control block] code page size: %uB code memory size: %ukB code region 0 size: %ukB pre-programmed code: %s number of ram blocks: %u ram block 0 size: %uB ram block 1 size: %uB ram block 2 size: %uB ram block 3 size: %uB config id: %x device id: 0x%x%08x encryption root: 0x%08x%08x%08x%08x identity root: 0x%08x%08x%08x%08x device address type: 0x%x device address: 0x%x%08x override enable: %x NRF_1MBIT values: %x %x %x %x %x BLE_1MBIT values: %x %x %x %x %x [user information control block] code region 0 size: %ukB read back protection configuration: %x reset value for XTALFREQ: %x firmware id: 0x%04xCode region 0 must start at the begining of the bankCode region 0 size was pre-programmed at the factory, can't change flash protection settingsCouldn't write code region 0 size[UICR]You need to perform chip erase before changing the protection settingsCouldn't read NVMC_READY registerTimed out waiting for NVMC_READYWriting buffer to flash offset=0x%x bytes=0x%xno working area available, falling back to slow memory writesusing fast async flash loader. This is currently supportedonly with ST-Link and CMSIS-DAP. If you have issues, add"set WORKAREASIZE 0" before sourcing nrf51.cfg to disable itFailed to enable read-only operationRead only enable did not completeFailed to enable erase operationFailed to erase reg: 0x%08x val: 0x%08xCannot erase protected sector at 0x%xThe chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this regionCode region 0 size was pre-programmed at the factory, mass erase command won't work.Erasing all non-volatile memoryFailed to check chip's write protectionFailed to enable write operationPadding write from 0x%08x-0x%08x as 0x%08x-0x%08xstart % chip->code_page_size == 0end % chip->code_page_size == 0Can't erase protected sector @ 0x%08xFailed to erase sector @ 0x%08xFailed to write to nrf51 flashErase all flash contents of the chip.nrf51_erase_allnrf51_handle_mass_erase_commandnrf51_handle_mass_erase_commandnrf51_write_pagesnrf51_write_pagesnrf51_code_flash_writenrf51_ll_flash_writenrf51_ll_flash_writenrf51_nvmc_write_enablenrf51_flash_bank_commandnrf51_nvmc_read_onlynrf51_wait_for_nvmcnrf51_nvmc_erase_enablenrf51_nvmc_generic_erasenrf51_erase_pagenrf51_protectnrf51_probenrf51_protect_checknrf51_protect_checknrf51_get_probed_chip_if_haltednrf51_infonrf51_bank_is_probed h- LhB ÔB F4L`8src/flash/nand/nuc910.cnuc910nuc910 only supports 8 bit bus width, not %inuc910_nand_device_commandnuc910_nand_initvalidate_target_stateadd flash_bank numicro %ssrc/flash/nor/numicro.cDevice ID: 0x%08xDevice Name: %sNuvoton NuMicro: Probed ...protected = 0x%08xprotection removedstill protected!!failure: 0x%xErase done.CONFIG0: 0x%x,CONFIG1: 0x%xCBS=0: Boot From LPROMCBS=1: Boot From APROMFlash is secure locked!Flash is not locked!0x%08x: 0x%08xunable to get armv7m targetwrite longword @ %08XWrite OKWrite done.numicro chip_erase failednumicro chip_erase completenumicronumicro flash command groupread_ispread flash through ISP.write_ispwrite flash through ISP.address valuechip erase through ISP.NUC100LD2BNNUC100LD1BNNUC100LD0BNNUC100LC2BNNUC100LC1BNNUC100LC0BNNUC100LB2BNNUC100LB1BNNUC100LB0BNNUC100LA2BNNUC100LA1BNNUC100LA0BNNUC100RD2BNNUC100RD1BNNUC100RD0BNNUC100RC2BNNUC100RC1BNNUC100RC0BNNUC100RB2BNNUC100RB1BNNUC100RB0BNNUC100RA2BNNUC100RA1BNNUC100RA0BNNUC100LE3CNNUC100LE2CNNUC100LE1CNNUC100LD3CNNUC100LD2CNNUC100LD1CNNUC100LC3CNNUC100LC2CNNUC100LC1CNNUC100RE3CNNUC100RE2CNNUC100RE1CNNUC100RD3CNNUC100RD2CNNUC100RD1CNNUC100RC3CNNUC100RC2CNNUC100RC1CNNUC100VE3CNNUC100VE2CNNUC100VE1CNNUC100VD3CNNUC100VD2CNNUC100VD1CNNUC100VC3CNNUC100VC2CNNUC100VC1CNNUC101YD2BNNUC101YD1BNNUC101YD0BNNUC101YC2BNNUC101YC1BNNUC101YC0BNNUC101YB2BNNUC101YB1BNNUC101YB0BNNUC101YA2BNNUC101YA1BNNUC101YA0BNNUC101LD2BNNUC101LD1BNNUC101LD0BNNUC101LC2BNNUC101LC1BNNUC101LC0BNNUC101LB2BNNUC101LB1BNNUC101LB0BNNUC101LA2BNNUC101LA1BNNUC101LA0BNNUC101RD2BNNUC101RD1BNNUC101RD0BNNUC101RC2BNNUC101RC1BNNUC101RC0BNNUC101RB2BNNUC101RB1BNNUC101RB0BNNUC101RA2BNNUC101RA1BNNUC101RA0BNNUC101LE3CNNUC101LE2CNNUC101LE1CNNUC101LD3CNNUC101LD2CNNUC101LD1CNNUC101LC3CNNUC101LC2CNNUC101LC1CNNUC101RE3CNNUC101RE2CNNUC101RE1CNNUC101RD3CNNUC101RD2CNNUC101RD1CNNUC101RC3CNNUC101RC2CNNUC101RC1CNNUC101VE3CNNUC101VE2CNNUC101VE1CNNUC101VD3CNNUC101VD2CNNUC101VD1CNNUC101VC3CNNUC101VC2CNNUC101VC1CNNUC102ZD2ANNUC102ZC1ANNUC102LD2ANNUC102LC1ANNUC102RB3ANNUC102RB2ANNUC102RB1ANNUC102RA3ANNUC102RA2ANNUC102RA1ANNUC102VB3ANNUC102VB2ANNUC102VB1ANNUC102VA3ANNUC102VA2ANNUC102VA1ANNUC102LA0ANNUC102LB0ANNUC102LC0ANNUC102LD0ANNUC102RA0ANNUC102RB0ANNUC102RC0ANNUC102RD0ANNUC102VA0ANNUC102VB0ANNUC102VC0ANNUC102VD0ANNUC102ZA0ANNUC102ZB0ANNUC102ZC0ANNUC102ZD0ANNUC122LD2ANNUC122LD1ANNUC122LC2ANNUC122LC1ANNUC122RD2ANNUC122RD1ANNUC122RC2ANNUC122RC1ANNUC122SD2ANNUC122SD1ANNUC122SC2ANNUC122SC1ANNUC122ZD2ANNUC122ZD1ANNUC122ZC2ANNUC122ZC1ANNUC122ZB2ANNUC122ZB1ANNUC122ZA2ANNUC122ZA1ANNUC122LB2ANNUC122LB1ANNUC122LA2ANNUC122LA1ANNUC122RB2ANNUC122RB1ANNUC122RA2ANNUC122RA1ANNUC122SB2ANNUC122SB1ANNUC122SA2ANNUC122SA1ANNUC122LA0ANNUC122LB0ANNUC122LC0ANNUC122LD0ANNUC122RA0ANNUC122RB0ANNUC122RC0ANNUC122RD0ANNUC122SA0ANNUC122SB0ANNUC122SC0ANNUC122SD0ANNUC122ZA0ANNUC122ZB0ANNUC122ZC0ANNUC122ZD0ANNUC122YD2ANNUC122YD1ANNUC122YD0ANNUC122YC2ANNUC122YC1ANNUC122YC0ANNUC122YB2ANNUC122YB1ANNUC122YB0ANNUC122YA2ANNUC122YA1ANNUC122YA0ANNUC120LD2BNNUC120LD1BNNUC120LD0BNNUC120LC2BNNUC120LC1BNNUC120LC0BNNUC120LB2BNNUC120LB1BNNUC120LB0BNNUC120LA2BNNUC120LA1BNNUC120LA0BNNUC120RD2BNNUC120RD1BNNUC120RD0BNNUC120RC2BNNUC120RC1BNNUC120RC0BNNUC120RB2BNNUC120RB1BNNUC120RB0BNNUC120RA2BNNUC120RA1BNNUC120RA0BNNUC120LE3CNNUC120LE2CNNUC120LE1CNNUC120LD3CNNUC120LD2CNNUC120LD1CNNUC120LC3CNNUC120LC2CNNUC120LC1CNNUC120RE3CNNUC120RE2CNNUC120RE1CNNUC120RD3CNNUC120RD2CNNUC120RD1CNNUC120RC3CNNUC120RC2CNNUC120RC1CNNUC120VE3CNNUC120VE2CNNUC120VE1CNNUC120VD3CNNUC120VD2CNNUC120VD1CNNUC120VC3CNNUC120VC2CNNUC120VC1CNNUC130LD2BNNUC130LD1BNNUC130LD0BNNUC130LC2BNNUC130LC1BNNUC130LC0BNNUC130LB2BNNUC130LB1BNNUC130LB0BNNUC130LA2BNNUC130LA1BNNUC130LA0BNNUC130RD2BNNUC130RD1BNNUC130RD0BNNUC130RC2BNNUC130RC1BNNUC130RC0BNNUC130RB2BNNUC130RB1BNNUC130RB0BNNUC130RA2BNNUC130RA1BNNUC130RA0BNNUC130LE3CNNUC130LE2CNNUC130LE1CNNUC130LD3CNNUC130LD2CNNUC130LD1CNNUC130LC3CNNUC130LC2CNNUC130LC1CNNUC130RE3CNNUC130RE2CNNUC130RE1CNNUC130RD3CNNUC130RD2CNNUC130RD1CNNUC130RC3CNNUC130RC2CNNUC130RC1CNNUC130VE3CNNUC130VE2CNNUC130VE1CNNUC130VD3CNNUC130VD2CNNUC130VD1CNNUC130VC3CNNUC130VC2CNNUC130VC1CNNUC140LD2BNNUC140LD1BNNUC140LD0BNNUC140LC2BNNUC140LC1BNNUC140LC0BNNUC140LB2BNNUC140LB1BNNUC140LB0BNNUC140LA2BNNUC140LA1BNNUC140LA0BNNUC140RD2BNNUC140RD1BNNUC140RD0BNNUC140RC2BNNUC140RC1BNNUC140RC0BNNUC140RB2BNNUC140RB1BNNUC140RB0BNNUC140RA2BNNUC140RA1BNNUC140RA0BNNUC140LE3CNNUC140LE2CNNUC140LE1CNNUC140LD3CNNUC140LD2CNNUC140LD1CNNUC140LC3CNNUC140LC2CNNUC140LC1CNNUC140RE3CNNUC140RE2CNNUC140RE1CNNUC140RD3CNNUC140RD2CNNUC140RD1CNNUC140RC3CNNUC140RC2CNNUC140RC1CNNUC140VE3CNNUC140VE2CNNUC140VE1CNNUC140VD3CNNUC140VD2CNNUC140VD1CNNUC140VC3CNNUC140VC2CNNUC140VC1CNNUC100LE3ANNUC100LE2ANNUC100LE1ANNUC100LD3ANNUC100LD2ANNUC100LD1ANNUC100LC3ANNUC100LC2ANNUC100LC1ANNUC100RE3ANNUC100RE2ANNUC100RE1ANNUC100RD3ANNUC100RD2ANNUC100RD1ANNUC100RC3ANNUC100RC2ANNUC100RC1ANNUC100VE3ANNUC100VE2ANNUC100VE1ANNUC100VD3ANNUC100VD2ANNUC100VD1ANNUC100VC3ANNUC100VC2ANNUC100VC1ANNUC101LE3ANNUC101LE2ANNUC101LE1ANNUC101LD3ANNUC101LD2ANNUC101LD1ANNUC101LC3ANNUC101LC2ANNUC101LC1ANNUC101RE3ANNUC101RE2ANNUC101RE1ANNUC101RD3ANNUC101RD2ANNUC101RD1ANNUC101RC3ANNUC101RC2ANNUC101RC1ANNUC101VE3ANNUC101VE2ANNUC101VE1ANNUC101VD3ANNUC101VD2ANNUC101VD1ANNUC101VC3ANNUC101VC2ANNUC101VC1ANNUC120LE3ANNUC120LE2ANNUC120LE1ANNUC120LD3ANNUC120LD2ANNUC120LD1ANNUC120LC3ANNUC120LC2ANNUC120LC1ANNUC120RE3ANNUC120RE2ANNUC120RE1ANNUC120RD3ANNUC120RD2ANNUC120RD1ANNUC120RC3ANNUC120RC2ANNUC120RC1ANNUC120VE3ANNUC120VE2ANNUC120VE1ANNUC120VD3ANNUC120VD2ANNUC120VD1ANNUC120VC3ANNUC120VC2ANNUC120VC1ANNUC130LE3ANNUC130LE2ANNUC130LE1ANNUC130LD3ANNUC130LD2ANNUC130LD1ANNUC130LC3ANNUC130LC2ANNUC130LC1ANNUC130RE3ANNUC130RE2ANNUC130RE1ANNUC130RD3ANNUC130RD2ANNUC130RD1ANNUC130RC3ANNUC130RC2ANNUC130RC1ANNUC130VE3ANNUC130VE2ANNUC130VE1ANNUC130VD3ANNUC130VD2ANNUC130VD1ANNUC130VC3ANNUC130VC2ANNUC130VC1ANNUC140LE3ANNUC140LE2ANNUC140LE1ANNUC140LD3ANNUC140LD2ANNUC140LD1ANNUC140LC3ANNUC140LC2ANNUC140LC1ANNUC140RE3ANNUC140RE2ANNUC140RE1ANNUC140RD3ANNUC140RD2ANNUC140RD1ANNUC140RC3ANNUC140RC2ANNUC140RC1ANNUC140VE3ANNUC140VE2ANNUC140VE1ANNUC140VD3ANNUC140VD2ANNUC140VD1ANNUC140VC3ANNUC140VC2ANNUC140VC1ANM052LANM052PANM052YANM052ZANM054LANM054PANM054YANM054ZANM058LANM058PANM058YANM058ZANM0516LANM0516PANM0516YANM0516ZANM051LBNM051PBNM051YBNM051ZBNM052LBNM052PBNM052YBNM052ZBNM054LBNM054PBNM054YBNM054ZBNM058LBNM058PBNM058YBNM058ZBNM0516LBNM0516PBNM0516YBNM0516ZBNM052LDNM054LDNM058LDNM0516LDNM052ZDNM054ZDNM058ZDNM0516ZDNM052TDNM054TDNM058TDNM0516TDNM052XDNM054XDNM058XDNM0516XDNM052LDEM054LDEM058LDEM0516LDEM052ZDEM054ZDEM058ZDEM0516ZDEM052TDEM054TDEM058TDEM0516TDEM052XDEM054XDEM058XDEM0516XDEMINI51LANMINI51QANMINI51 MINI51ZANMINI51TANMINI52LANMINI52QANMINI52 MINI52ZANMINI52TANMINI54LANMINI54QANMINI54 MINI54ZANMINI54TANMINI51LBNMINI51QBNMINI51ZBNMINI51TBNMINI52LBNMINI52QBNMINI52ZBNMINI52TBNMINI54LBNMINI54QBNMINI54ZBNMINI54TBNMINI51LDEMINI51QDEMINI51ZDEMINI51TDEMINI51FDEMINI52LDEMINI52QDEMINI52ZDEMINI52TDEMINI52FDEMINI54LDEMINI54QDEMINI54ZDEMINI54TDEMINI54FDEMINI55LDENANO100VF3ANNANO100VF2ANNANO100RF3ANNANO100RF2ANNANO100LF3ANNANO100LF2ANNANO100VE3ANNANO100VE2ANNANO100RE3ANNANO100RE2ANNANO100LE3ANNANO100LE2ANNANO100VD3ANNANO100VD2ANNANO100VD1ANNANO100RD3ANNANO100RD2ANNANO100RD1ANNANO100LD3ANNANO100LD2ANNANO100LD1ANNANO100VC2ANNANO100VC1ANNANO100RC2ANNANO100RC1ANNANO100LC2ANNANO100LC1ANNANO100VB1ANNANO100VB0ANNANO100RB1ANNANO110VF3ANNANO110VF2ANNANO110RF3ANNANO110RF2ANNANO110VE3ANNANO110VE2ANNANO110RE3ANNANO110RE2ANNANO110VD3ANNANO110VD2ANNANO110VD1ANNANO110RD3ANNANO110RD2ANNANO110RD1ANNANO110VC2ANNANO110VC1ANNANO110SC2ANNANO110SC1ANNANO120VF3ANNANO120VF2ANNANO120RF3ANNANO120RF2ANNANO120LF3ANNANO120LF2ANNANO120VE3ANNANO120VE2ANNANO120RE3ANNANO120RE2ANNANO120LE3ANNANO120LE2ANNANO120VD3ANNANO120VD2ANNANO120VD1ANNANO120SD3ANNANO120SD2ANNANO120SD1ANNANO120LD3ANNANO120LD2ANNANO120LD1ANNANO120VC2ANNANO120VC1ANNANO120SC2ANNANO120SC1ANNANO120LC2ANNANO120LC1ANNANO130VF3ANNANO130VF2ANNANO130SF3ANNANO130SF2ANNANO130VE3ANNANO130VE2ANNANO130SE3ANNANO130SE2ANNANO130VD3ANNANO130VD2ANNANO130VD1ANNANO130SD3ANNANO130SD2ANNANO130SD1ANNANO130VC2ANNANO130VC1ANNANO130SC2ANNANO130SC1ANNANO100KE3BNNANO100KE2BNNANO100VE3BNNANO100VE2BNNANO100SE3BNNANO100SE2BNNANO100LE3BNNANO100LE2BNNANO100KD3BNNANO100KD2BNNANO100VD3BNNANO100VD2BNNANO100SD3BNNANO100SD2BNNANO100LD3BNNANO100LD2BNNANO100KC2BNNANO100VC2BNNANO100SC2BNNANO100LC2BNNANO110KE3BNNANO110KE2BNNANO110VE3BNNANO110VE2BNNANO110SE3BNNANO110SE2BNNANO110KD3BNNANO110KD2BNNANO110VD3BNNANO110VD2BNNANO110SD3BNNANO110SD2BNNANO110KC2BNNANO110VC2BNNANO110SC2BNNANO120KE3BNNANO120KE2BNNANO120VE3BNNANO120VE2BNNANO120SE3BNNANO120SE2BNNANO120LE3BNNANO120LE2BNNANO120KD3BNNANO120KD2BNNANO120VD3BNNANO120VD2BNNANO120SD3BNNANO120SD2BNNANO120LD3BNNANO120LD2BNNANO120KC2BNNANO120VC2BNNANO120SC2BNNANO120LC2BNNANO130KE3BNNANO130KE2BNNANO130VE3BNNANO130VE2BNNANO130SE3BNNANO130SE2BNNANO130KD3BNNANO130KD2BNNANO130VD3BNNANO130VD2BNNANO130SD3BNNANO130SD2BNNANO130KC2BNNANO130VC2BNNANO130SC2BNN512DC4N512LC4N512MC4N512SC4N512VD4N512MD4N512SD4NANO110RC2BNNANO110RD3BNTX110VE3BNNANO112LB0ANNANO112LB1ANNANO112LC1ANNANO112LC2ANNANO112SB0ANNANO112SB1ANNANO112SC1ANNANO112SC2ANNANO112RB0ANNANO112RB1ANNANO112RC1ANNANO112RC2ANNANO112VB0ANNANO112VB1ANNANO112VC1ANNANO112VC2ANNANO102ZB0ANNANO102ZB1ANNANO102ZC1ANNANO102ZC2ANNANO102LB0ANNANO102LB1ANNANO102LC1ANNANO102LC2ANNANO102SB0ANNANO102SB1ANNANO102SC1ANNANO102SC2ANNUC123SC2ANNUC123SD4ANNUC123LC2ANNUC103LC2ANNUC105LC2ANNUC123LD4ANNUC103LD4ANNUC105LD4ANNUC123ZC2ANNUC103ZC2ANNUC105ZC2ANNUC123ZD4ANNUC103ZD4ANNUC105ZD4ANNUC200LC2ANNUC200LD2ANNUC200LE3ANNUC200SC1ANNUC200SD2ANNUC200SE3ANNUC200VE3ANNUC220LC2ANNUC220LD2ANNUC220LE3ANNUC220SC1ANNUC220SD2ANNUC220SE3ANNUC220VE3ANNUC230LC2ANNUC230LD2ANNUC230LE3ANNUC230SC1ANNUC230SD2ANNUC230SE3ANNUC230VE3ANNUC240LC2ANNUC240LD2ANNUC240LE3ANNUC240SC1ANNUC240SD2ANNUC240SE3ANNUC240VE3ANNUC230RC1AENUC200LC2AENUC200LD2AENUC200LE3AENUC200SC2AENUC200SD2AENUC200SE3AENUC200VE3AENUC230LC2AENUC230LD2AENUC230LE3AENUC230SC2AENUC230SD2AENUC230SE3AENUC230VE3AENUC240LC2AENUC240LD2AENUC240LE3AENUC240SC2AENUC240SD2AENUC240SE3AENUC240VE3AENUC100LC1DNNUC100LD1DNNUC100LD2DNNUC100RC1DNNUC100RD1DNNUC100RD2DNNUC100LD3DNNUC100LE3DNNUC100RD3DNNUC100RE3DNNUC100VD2DNNUC100VD3DNNUC100VE3DNNUC120LC1DNNUC120LD1DNNUC120LD2DNNUC120RC1DNNUC120RD1DNNUC120RD2DNNUC120LD3DNNUC120LE3DNNUC120RD3DNNUC120RE3DNNUC120VD2DNNUC120VD3DNNUC120VE3DNNUC130RC1DNUNKNOWNNuMicro flash driver: Failed to Get PartID NuMicro flash driver: Failed to detect a known part bank base = 0x%08x, size = 0x%08xNuMicro flash driver: Failed to detect flash size Nuvoton NuMicro: Sector Erase ... (%d to %d)erasing sector %d at address 0x%xNuvoton NuMicro: Flash Lock Check...TO UNLOCK FLASH,EXECUTE chip_erase COMMAND!!ispdat option value ('%s') is not validError executing NuMicro Flash programming algorithmNuvoton NuMicro: Flash Write ...odd number of bytes to write (%d), extending to %d and padding with 0xffnumicro_handle_read_isp_commandnumicro_handle_write_isp_commandnumicro_flash_bank_commandnumicro_erasenumicro_writeblocknumicro_writenumicro_get_flash_sizenumicro_get_cpu_typenumicro_probenumicro_fmc_cmdnumicro_reg_unlocknumicro_init_ispnumicro_protect_check# gB N7`M/`M&.`/h3Kh@!@PPPPtarget has to be running to communicate with the loaderloader response to OCL_ERASE_ALL 0x%08xloader response to OCL_ERASE_BLOCK 0x%08xloader response to OCL_PROBE 0x%08xnumber of sectors shall be non zero valuebank size not divisible by number of sectorsbuflen shall be non zero valuebuflen is not multiple of bufalignbuflen shall be divisible by 4loader response to OCL_FLASH_BLOCK 0x%08xsrc/flash/nor/ocl.coclocl_eraseocl_writeocl_probeNAND flash access requires halted targetbase option value ('%s') is not validsrc/flash/nand/orion.corion orion_nand_device_commandorion_nand_commandorion_nand_addressorion_nand_writeorion_nand_read110F016C110F016BPIC32MX%s Ver: 0x%02xsrc/flash/nor/pic32mx.ctimeout: status: 0x%xErasing entire program flashpic32mx unlock pic32mx pgm word completeflash writing failedpic32mxpic32mx flash command grouppgm_wordprogram a word Unlock/Erase entire device.[bank_id]110F016D120F032B120F032C120F032D130F064B130F064C130F064D150F128B150F128C150F128D170F256B170F256D210F016B210F016C210F016D220F032B220F032C220F032D230F064B230F064C230F064D250F128B250F128C250F128D270F256B270F256D330F064H330F064L430F064H430F064L350F128H350F128L450F128H450F128L350F256H350F256L450F256H450F256L370F512H370F512L470F512H470F512L360F512L360F256L340F128L320F128L340F512H340F256H340F128H320F128H320F064H320F032H460F512L460F256L440F128L440F256H440F512H440F128H420F032H795F512L795F512H775F512L775F512H775F256L775F256H764F128L764F128H695F512L695F512H675F512L675F512H675F256L675F256H664F128L664F128H664F064L664F064H575F512L575F512H575F256L575F256H564F128L564F128H564F064L564F064H534F064H534F064LCannot identify target as a PIC32MX family (manufacturer 0x%03d != 0x%03d) device id = 0x%08x (manuf 0x%03x dev 0x%04x, ver 0x%02x)Cannot identify target as a PIC32MX family.PIC32MX flash size failed, probe inaccurate - assuming 32k flashPIC32MX flash size failed, probe inaccurate - assuming 512k flashpic32mx is already unlocked, erasing anywaytimeout waiting for unlock: 0x%xpic32mx unlocked. INFO: a reset or power cycle is required for the new settings to take effect.flash address '%s' is out of boundspic32mx pgm word failed (status = 0x%x)error executing pic32mx flash write algorithmFlash write error NVMERR (status = 0x%08x)Flash write error LVDERR (status = 0x%08x)writing to flash at address 0x%08x at offset 0x%8.8x count: 0x%8.8xoffset 0x%xbreaks required 4-byte alignmentpic32mx_handle_unlock_commandpic32mx_erasepic32mx_protectpic32mx_wait_status_busypic32mx_write_blockpic32mx_writepic32mx_probepic32mx_protect_checkFlash auto-erase enabled, non mass erase commands will be ignored.Flash auto-erase disabled. Use psoc mass_erase before flash programming.Unknown PSoC 4 device silicon id 0x%08x.PSoC 4 %s rev 0x%04x package %sUnknown protection state 0x%02xno working area for sysreq codeno working area for sysreq parameterssysreq wait code execution failedsysreq silicon id request not servedCannot identify target as a PSoC 4 family.SPCIF geometry: %u kb flash, row %u bytes.PSoC 4 flash size failed, probe inaccurate - assuming %u k flashignoring flash probed value, using configured bank sizeAutoerase enabled, erase command ignoredoffset 0x%08x breaks required 2-byte alignmentoffset / row: 0x%08x / %u, size %uSet autoerase mode for flash bank.src/flash/nor/psoc4.cprotection VIRGINPROTECTEDprotection KILLprotection openPSoC 4 silicon id 0x%08x flash %u kb %ssilicon id: 0x%08xprotection: 0x%02xcpu id = 0x%08x%s device detected.Flash size mismatchflash size = %u kbytesflash_size_in_kb != 0xffffnum_rows > 0flash bank set %u rowsOnly mass erase availablepsoc mass erase completepsoc mass erase failedno memory for row bufferpsoc4PSoC 4 flash command groupflash_autoerasebank_id on|offCY8C4245PVI-482SSOP-28CY8C4245LQI-483QFN-40CY8C4245AXI-483TQFP-44CY8C4245AXI-473CY8C4244PVI-432CY8C4244PVI-442CY8C4244LQI-443CY8C4244AXI-443CY8C4124PVI-432CY8C4124PVI-442CY8C4124LQI-443CY8C4124AXI-443CY8C4125AXI-473CY8C4125PVI-482CY8C4125LQI-483CY8C4125AXI-483CYPD1103-35FNXICSP-35CYPD1121-40LQXICYPD1122-40LQXICYPD1131-35FNXICYPD1132-16SXISOIC-16CYPD1134-28PVXICYPD1134-40LQXIpsoc4_handle_flash_autoerase_commandpsoc4_mass_erasepsoc4_erasepsoc4_protectpsoc4_writepsoc4_probepsoc4_probepsoc4_sysreqpsoc4_get_silicon_idpsoc4_decode_chip_protectionpsoc4_details_by_idtarget must be halted to use S3C24XX NAND flash controllersrc/flash/nand/s3c2410.cs3c2410s3c2410_write_datas3c2410_read_datas3c2410_nand_readys3c2412%s: reading data: %p, %p, %dsrc/flash/nand/s3c2440.cs3c2440_write_block_datas3c2440_read_block_datas3c2440_nand_readys3c2443src/flash/nand/s3c24xx.cs3c24xx_read_datas3c24xx_write_datas3c24xx_addresss3c24xx_commands3c24xx_resets3c24xx_nand_device_commands3c6400Can not read Lock Wordsrc/flash/nor/sim3x.cFailed to read CPU IDTarget is not Cortex-M3Unknown Part number %dSiM3C%d detectedSiM3U%d detectedSiM3L%d detectedUnsupported MCU family %cFailed to parse info from MCUFlash size = %dKBSiM3%c%d-%c-G%s flash_size = %dKBFailed to init MCUDAP: dap_run failedDAP_REG[0x%02x]: %08XDAP_REG[0x%02x] <- %08XWrong SIM3X_AP_IDDAP: polling timed outMass erase successFalsh is lockedFlash is already lockedFlash lockedFlash lock errorFlash unlock errorFlash unlockedTarget is already lockedTarget is successfully lockedUnexpected lock word valueMaybe this isn't a SiM3x MCUsim3xsim3x flash command groupErase the complete flashFailed to read info from MCU, using info from flash bank parametersFlash size not set in the flash bank commandtimed out waiting for FLASHCTRL0_CONFIG_BUSYFDAP: failed to queue a read requestDAP: failed to queue a write requestmass_erase can't be used by this debug interfaceFlash does not support finer granularityTarget can't by unlocked by this debug interfaceTarget is not ARM Cortex-M3 or is already lockedTarget doesn't seem to be locked but memory was not read correctTarget is unlocked by firmware and can't by locked again without the lock page erase or mass eraseLocks the flash. Unlock by mass eraseHHHdap_queue_ap_writeap_write_registerap_poll_registersim3x_mass_erasedap_rundap_queue_ap_readap_read_registersim3x_locksim3x_erase_pagesim3x_flash_erasesim3x_flash_protect&`&`h.UhBh@.`54BF5U`I)Z&`hsim3x_write_blocksim3x_flash_writesim3x_flash_lock_checksim3x_flash_protect_checksim3x_parse_part_infosim3x_read_infost m25p05st m25p10st m25p20st m25p40st m25p80st m25p16st m25p32st m25p64st m25p128st m45pe10st m45pe20st m45pe40st m45pe80sp s25fl004sp s25fl008sp s25fl016sp s25fl116ksp s25fl032sp s25fl132ksp s25fl064sp s25fl164ksp s25fl128sp s25fl256atmel 25f512atmel 25f1024atmel 25f2048atmel 25f4096atmel 25fs040mac 25l512mac 25l1005mac 25l2005mac 25l4005mac 25l8005mac 25l1605mac 25l3205mac 25l6405micron n25q064micron n25q128win w25q80bvwin w25q32fvwin w25q32dwwin w25q64cvwin w25q128fvgd gd25q20gd gd25q16cgd gd25q32cgd gd25q128cUnknown targetsrc/flash/nor/stellaris.cStellaris RCC %xStellaris RCC2 %xStellaris PLLCFG %x (±30%)ARMv7MUnknown did1 version/family. (±50%) (±1%)Unknown did0 classusecrl = %iCan't protect unaligned pageswriting flash word-at-a-timeflash_cris 0x%xstellaris mass erase completestellaris mass erase failedstellarisStellaris flash command grouperase entire devicerecoverSandstormFuryDustDevilTempestBlizzard/TM4C123xFirestormSnowflakeLM3S101LM3S102LM3S1110LM3S1133LM3S1138LM3S1150LM3S1162LM3S1165LM3S1166LM3S1332LM3S1435LM3S1439LM3S1512LM3S1538LM3S1601LM3S1607LM3S1608LM3S1620LM3S1621LM3S1625LM3S1626LM3S1627LM3S1635LM3S1636LM3S1637LM3S1651LM3S1751LM3S1776LM3S1811LM3S1816LM3S1850LM3S1911LM3S1918LM3S1937LM3S1958LM3S1960LM3S1968LM3S1969LM3S1B21LM3S1C21LM3S1C26LM3S1C58LM3S1D21LM3S1D26LM3S1F11LM3S1F16LM3S1G21LM3S1G58LM3S1H11LM3S1H16LM3S1J11LM3S1J16LM3S1N11LM3S1N16LM3S1P51LM3S1R21LM3S1R26LM3S1W16LM3S1Z16LM3S2110LM3S2139LM3S2276LM3S2410LM3S2412LM3S2432LM3S2533LM3S2601LM3S2608LM3S2616LM3S2620LM3S2637LM3S2651LM3S2671LM3S2678LM3S2730LM3S2739LM3S2776LM3S2793LM3S2911LM3S2918LM3S2919LM3S2939LM3S2948LM3S2950LM3S2965LM3S2B93LM3S2D93LM3S2U93LM3S300LM3S301LM3S308LM3S310LM3S315LM3S316LM3S317LM3S328LM3S3634LM3S3651LM3S3654LM3S3739LM3S3748LM3S3749LM3S3826LM3S3J26LM3S3N26LM3S3W26LM3S3Z26LM3S5632LM3S5651LM3S5652LM3S5656LM3S5662LM3S5732LM3S5737LM3S5739LM3S5747LM3S5749LM3S5752LM3S5762LM3S5791LM3S5951LM3S5956LM3S5B91LM3S5C31LM3S5C36LM3S5C51LM3S5C56LM3S5D51LM3S5D56LM3S5D91LM3S5G31LM3S5G36LM3S5G51LM3S5G56LM3S5K31LM3S5K36LM3S5P31LM3S5P36LM3S5P3BLM3S5P51LM3S5P56LM3S5R31LM3S5R36LM3S5T36LM3S5U91LM3S5Y36LM3S600LM3S601LM3S608LM3S610LM3S6100LM3S611LM3S6110LM3S612LM3S613LM3S615LM3S617LM3S618LM3S628LM3S6420LM3S6422LM3S6432LM3S6537LM3S6610LM3S6611LM3S6618LM3S6633LM3S6637LM3S6730LM3S6753LM3S6911LM3S6918LM3S6938LM3S6950LM3S6952LM3S6965LM3S6C11LM3S6C65LM3S6G11LM3S6G65LM3S800LM3S801LM3S808LM3S811LM3S812LM3S815LM3S817LM3S818LM3S828LM3S8530LM3S8538LM3S8630LM3S8730LM3S8733LM3S8738LM3S8930LM3S8933LM3S8938LM3S8962LM3S8970LM3S8971LM3S8C62LM3S8G62LM3S9781LM3S9790LM3S9792LM3S9971LM3S9997LM3S9B81LM3S9B90LM3S9B92LM3S9B95LM3S9B96LM3S9BN2LM3S9BN5LM3S9BN6LM3S9C97LM3S9D81LM3S9D90LM3S9D92LM3S9D96LM3S9DN5LM3S9DN6LM3S9G97LM3S9GN5LM3S9L71LM3S9L97LM3S9U81LM3S9U90LM3S9U92LM3S9U96LM4F120B2QR/TM4C1233C3PMLM4F120C4QR/TM4C1233D5PMLM4F120E5QR/TM4C1233E6PMLM4F120H5QR/TM4C1233H6PMLM4F121B2QR/TM4C1232C3PMLM4F121C4QR/TM4C1232D5PMLM4F121E5QR/TM4C1232E6PMLM4F121H5QR/TM4C1232H6PMLM4F110E5QR/TM4C1231E6PMLM4F110H5QR/TM4C1231H6PMLM4F110B2QR/TM4C1231C3PMLM4F110C4QR/TM4C1231D5PMLM4F111E5QR/TM4C1230E6PMLM4F111H5QR/TM4C1230H6PMLM4F111B2QR/TM4C1230C3PMLM4F111C4QR/TM4C1230D5PMLM4F112E5QC/TM4C1231E6PZLM4F112H5QC/TM4C1231H6PZLM4F112H5QD/TM4C1231H6PGELM4F112C4QC/TM4C1231D5PZLM4F130E5QR/TM4C1237E6PMLM4F130H5QR/TM4C1237H6PMLM4F130C4QR/TM4C1237D5PMLM4F131E5QR/TM4C1236E6PMLM4F131H5QR/TM4C1236H6PMLM4F131C4QR/TM4C1236D5PMLM4F132E5QC/TM4C1237E6PZLM4F132H5QC/TM4C1237H6PZLM4F132H5QD/TM4C1237H6PGELM4F132C4QC/TM4C1237D5PZLM4F210E5QR/TM4C123BE6PMLM4F210H5QR/TM4C123BH6PMLM4F211E5QR/TM4C123AE6PMLM4F211H5QR/TM4C123AH6PMLM4F230E5QR/TM4C123GE6PMLM4F230H5QR/TM4C123GH6PMLM4F231E5QR/TM4C123FE6PMLM4F231H5QR/TM4C123FH6PMLM4F232E5QC/TM4C123GE6PZLM4F232H5QC/TM4C123GH6PZLM4F212E5QC/TM4C123BE6PZLM4F212H5QC/TM4C123BH6PZLM4F232H5QD/TM4C123GH6PGELM4F212H5QD/TM4C123BH6PGELM4F122C4QC/TM4C1233D5PZLM4F122E5QC/TM4C1233E6PZLM4F122H5QC/TM4C1233H6PZLM4F122H5QD/TM4C1233H6PGELM4FSXLH5BBLM4F232H5BB/TM4C123GH6ZRBLM4FS99H5BBLM4FS1AH5BBLM4F212H5BB/TM4C123BH6ZRBLM4FS1GH5BBTM4C123GH6ZXRTM4C1290NCPDTTM4C1290NCZADTM4C1292NCPDTTM4C1292NCZADTM4C1294NCPDTTM4C1294NCZADTM4C1297NCZADTM4C1299NCZADTM4C129CNCPDTTM4C129CNCZADTM4C129DNCPDTTM4C129DNCZADTM4C129ENCPDTTM4C129ENCZADTM4C129LNCZADTM4C129XNCZADTM4C1294KCPDTTM4C129EKCPDTTM4C1299KCZADTM4C129XKCZADUnknown Part(bank=%p buffer=%p offset=%08x wcount=%08xno working area for block memory writesretry target_alloc_working_area(%s, size=%u)error %d executing stellaris flash write algorithmcatch { hla_command "debug unlock" }Can't recover Stellaris flash without SRSTUSER ACTION: power cycle Stellaris chip, then restart OpenOCD. TI/LMI Stellaris information: Chip is class %i (%s) %s rev %c%i did1: 0x%8.8x, arch: 0x%4.4x, eproc: %s, ramsize: %uk, flashsize: %uk master clock: %ikHz%s, rcc is 0x%x, rcc2 is 0x%x, pagesize: %u, pages: %udid0 0x%x, did1 0x%x, dc0 0x%x, dc1 0x%xUnknown did0 version, cannot identify targetCannot identify target as a StellarisHardware doesn't support page-level unprotect. Try the 'recover' command.DustDevil A0 parts can't be unprotected, see errata; refusing to proceedError setting flash page protection, flash_cris 0x%xError erasing flash page %i, flash_cris 0x%x(bank=%p buffer=%p offset=%08x count=%08xoffset size must be word alignedflash writing failed with CRIS: 0x%xrecover (and erase) locked device*@r````stellaris_handle_recover_commandstellaris_mass_erasestellaris_erasestellaris_protectstellaris_write_blockstellaris_set_flash_timingstellaris_writestellaris_read_part_infostellaris_read_clock_info@@@PGhGE"`W`яB(G`;@B@B %6@8 =>K@KL N[]pz}dz$src/flash/nor/stm32f1x.cstm32x device protectedstm32x mass erase completestm32x mass erase failedSTM32F302x6/8STM32F03xSTM32F302xB/CSTM32F10x (Connectivity)STM32F10x (High Density)STM32F10x (Low Density)STM32F10x (Medium Density)STM32F04xSTM32F07xSTM32F303xD/ESTM32F33xSTM32F37xSTM32F05xSTM32F100 (High Density)STM32F10x (XL Density)STM32F09x2.0%s - Rev: unknown (0x%04x)%s - Rev: %sOption Byte: 0x%xOption Byte Complement ErrorReadout Protection OnReadout Protection OffSoftware WatchdogHardware WatchdogStop: No reset generatedStop: Reset generatedStandby: No reset generatedStandby: Reset generatedBoot: Bank 0Boot: Bank 1User Option0: 0x%02xUser Option1: 0x%02xdevice id = 0x%08xSWWDGHWWDGNORSTSTOPNORSTSTNDBYBOOT0BOOT1stm32x failed to lock devicestm32x lockedstm32f1xstm32f1x flash command groupoptions_readoptions_writestm32x device programming failedCannot identify target as a stm32xSTM32F100 (Low/Medium Density)Cannot identify target as a STM32F0/1/3 Option Byte Operation's must use bank0Cannot identify target as a STM32 family.STM32 flash size failed, probe inaccurate - assuming %dk flashworking area required to erase options bytesstm32x failed to erase optionsstm32x failed to write optionsstm32x write options complete. INFO: a reset or power cycle is required for the new settings to take effect.stm32x failed to unlock devicestm32x unlocked. INFO: a reset or power cycle is required for the new settings to take effect.Read and display device option byte.Replace bits in device option byte.bank_id ('SWWDG'|'HWWDG') ('RSTSTNDBY'|'NORSTSTNDBY') ('RSTSTOP'|'NORSTSTOP') @Pp8@~~~~~5~~~~~~~~<~~~~~L~~~~~~~c~<~~~~~{{~~~~~~~o~~ostm32x_handle_lock_commandstm32x_handle_unlock_commandstm32x_handle_options_read_commandstm32x_handle_options_write_commandstm32x_mass_erasestm32x_erasestm32x_write_optionsstm32x_read_optionsstm32x_protectstm32x_wait_status_busyh.UhB.&54h'>B'>BѝBF5U`9) P`0Fstm32x_write_blockstm32x_writestm32x_get_flash_sizestm32x_probestm32x_probestm32x_check_operation_supportedstm32x_get_device_idflash not unlocked STM32_FLASH_CR: %xoptions not unlocked STM32_FLASH_OPTCR: %x(0 <= first) && (first <= last) && (last < bank->num_sectors)stm32f4x errata detected - fixing incorrect MCU_IDCODECannot identify target as a STM32F2/4/7 sector protection must be double sector alignedstm32f2x user_options 0x%03X, boot_add0 0x%04X, boot_add1 0x%04X%s unlocked. INFO: a reset or power cycle is required for the new settings to take effect.stm32f2x options_write ...stm32f2x options_write boot_addr0 option value ('%s') is not validboot_addr1 option value ('%s') is not validstm32f2x options_write user_options option value ('%s') is not validstm32f2x failed to write optionsstm32f2x write options complete. INFO: a reset or power cycle is required for the new settings to take effect.Dual Bank %d kiB STM32F42x/43x/469/479 foundSingle Bank %d kiB STM32F42x/43x/469/479 foundSingle Bank %d kiB STM32F76x/77x foundDual Bank %d kiB STM32F76x/77x found(bank->size >> 10) == flash_size_in_kberror executing stm32x flash write algorithmRead and display device option bytes.bank_id user_options [ boot_add0 boot_add1]src/flash/nor/stm32f2x.cSTM32F7[4|5]xSTM32F2xxSTM32F4xxSTM32F4xx (Low Power)STM32F446STM32F7[6|7]xunable to read option bytesstm32f2x options_read stm32f2x user_options 0x%03X,stm32f2x user_options 0x%02X%s failed to read options%s failed to unlock device%s failed to lock device%s lockedstm32f2x invalid user_optionsi < bank->num_sectorssector %d: %dkBytesallocated %d sectorsstm32x mass_erase flash write failed = %08xstm32f2xstm32f2x flash command groupWrite option bytes0XXXX(X  0000`@stm32x_handle_lock_commandstm32x_handle_unlock_commandstm32x_mass_erasestm32x_erasestm32x_erasestm32x_unlock_option_regstm32x_protectstm32x_wait_status_busyGhGE4`&a7k"kOh?яB(G`;!A`0Fstm32x_write_blockstm32x_unlock_regstm32x_writesetup_sectorsetup_sectorstm32x_probestm32x_probestm32x_read_optionsstm32x_protect_checkstm32x_get_device_idsrc/flash/nor/stm32l4x.cSTM32L4xxSTM32L43x%s - Rev: %1d.%02dfirst < bank->num_sectorslast < bank->num_sectorsblock write failedblock write succeededstm32l4xstm32l4x flash command groupCannot identify target as a STM32L4 family.(flash_size_in_kb != 0xffff) && flash_size_in_kboptions not unlocked STM32_FLASH_CR: %xCannot identify target as a STM32L4 stm32x mass_erase error executing stm32l4 flash write algorithmoffset 0x%x breaks required 8-byte alignmentPadding %d bytes to keep 8-byte write sizestm32l4_handle_lock_commandstm32l4_handle_unlock_commandstm32l4_mass_erasestm32l4_wait_status_busystm32l4_erasestm32l4_erasestm32l4_unlock_option_regstm32l4_protect!EhDv6.6`faggO&i?эB(E`;!A`0Fstm32l4_write_blockstm32l4_unlock_regstm32l4_writestm32l4_probestm32l4_probestm32l4_read_optionsstm32l4_protect_checkprotection of the STM32L flash is not implementedCannot identify target as a STM32L family.STM32L flash size failed, probe inaccurate - assuming %dk flashSTM32L probed flash size assumed incorrect since FLASH_SIZE=%dk > %dk, - assuming %dk flashSTM32L flash bank base address config is incorrect. 0x%x but should rather be 0x%x or 0x%xSTM32L flash has dual banks. Bank (%d) size is %dkb, base address is 0x%xSTM32L flash size is %dkb, base address is 0x%xignoring flash probed value, using configured bank size: %dkbytesfailed to allocate bank sectorsUnable to find bank information.Cannot identify target as a STM32Lxaccess denied / write protectedThe byte count must be %uB-aligned but count is %iB)couldn't use loader, falling back to page memory writesSTM32Lx locked, takes effect after power cycle.STM32Lx unlocked, takes effect after power cycle.failed to allocate bank structureErase entire flash device. including available EEPROMIncrease the readout protection to Level 1.Lower the readout protection from Level 1 to 0.STM32L1xx (Cat.1 - Low/Medium Density)STM32L1xx (Cat.3 - Medium+ Density)STM32L1xx (Cat.4/Cat.3 - Medium+/High Density)src/flash/nor/stm32lx.cDevice: %sinvalid program addressPELOCK is not cleared :(PRGLOCK is not cleared :((offset % hp_nb) == 0STM32Lx lock failedSTM32Lx unlock failedstm32lx mass erase completestm32lx mass erase failedstm32lxstm32lx flash command groupSTM32L0xx (Cat. 3)STM32L0xx (Cat. 2)STM32L1xx (Cat.2)STM32L1xx (Cat.5/Cat.6)STM32L0xx (Cat.5)STM32L0xx (Cat.1)stm32lx_mass_erasestm32lx_lockstm32lx_unlockstm32lx_flash_bank_commandstm32lx_erasestm32lx_protectstm32lx_wait_until_bsy_clear_timeoutstm32lx_unlock_program_memory#Q@3Bstm32lx_write_half_pagesstm32lx_writestm32lx_writestm32lx_probe SMI flash bank not probed yet SMI flash information: Device '%s' (ID 0x%08x) %s: offset=0x%08x count=0x%08xWrite pasts end of flash. Extra data discarded.Valid SMI on device %s at address 0x%xDevice ID 0x%x is not known as SMI capable%s: from sector %d to sector %dsrc/flash/nor/stmsmi.cTimeout while polling TFF%s: address=0x%08x len=0x%08xSTR75xSPEAr3xx/6xxInvalid SMI base address 0x%xstmsmistmsmi_flash_bank_commandstmsmi_erasesmi_write_enablesmi_write_bufferstmsmi_writepoll_tffwait_till_readyread_flash_idstmsmi_probeSTR7x flash protection info is only valid after a power cycle, clearing the protection is only temporary and may not be reflected in the current info returned.str7x suspended program erase not resumedstr7x trying to set bit to 1 when it is already 0str7x write operation failed / bad setupTimed out waiting for str7x flashstr7x hw write protection setsrc/flash/nor/str7x.cstr7x program errorstr7x erase errorSTR71xSTR73xunknown STR7x variant: '%s'sectors: 0x%xstr7xstr7x flash command groupdisable_jtagdisable jtag accessstr7x_handle_disable_jtag_commandstr7x_build_block_liststr7x_flash_bank_commandstr7x_erasestr7x_protectstr7x_resultstr7x_waitbusystr7x_write_blockB@@@@ @ B@@@ 0Sstr7x_writestr7x_protect_check  @ `  @src/flash/nor/str9x.ctotal_timeout > 0erase timed outwrite timed outstr9xstr9x flash command groupflash_configerror erasing flash bank, status: 0x%xbbsr option value ('%s') is not validnbbsr option value ('%s') is not validbbadr option value ('%s') is not validnbbadr option value ('%s') is not validerror executing str9x flash write algorithmConfigure str9x flash controller, prior to programming the flash.bank_id BBSR NBBSR BBADR NBBADRstr9x_handle_flash_config_commandstr9x_build_block_liststr9x_erasestr9x_erasestr9x_protect@@0000p000 PPPPP Rp str9x_write_blockstr9x_writestr9x_protect_checkLVD Reset Warning: VDD or VDDQ InputsLVD Reset Warning: VDD Input OnlyLVD Reset Selection: VDD or VDDQ InputsLVD Reset Selection: VDD Input Onlyerase: first_bank: %i, last_bank: %istr9xpec unlocked. INFO: a reset or power cycle is required for the new settings to take effect.protect: first_bank: %i, last_bank: %istr9xpec write options complete. INFO: a reset or power cycle is required for the new settings to take effect.**STR9FLASH** (tap0) invalid chain?**STR9FLASH** (tap1) invalid chain?**STR9FLASH** (tap2) invalid chain?blank check: first_bank: %i, last_bank: %iconfigure str9xpec boot sectorconfigure str9xpec lvd thresholdconfigure str9xpec lvd selectionconfigure str9xpec lvd warningprint part id of str9xpec flash bank src/flash/nor/str9xpec.cvdd_vddqstatus: 0x%2.2xISC_CONFIGURATIONCS Map: bank0CS Map: bank1OTP Lock: OTP LockedOTP Lock: OTP UnlockedLVD Threshold: 2.7vLVD Threshold: 2.4vISC_MODE EnabledISC_MODE DisabledISC_PROGRAMISC_ERASEstr9xpec part id: 0x%8.8xstr9xpecstr9xpec flash command groupenable_turboenable str9xpec turbo modedisable_turbodisable str9xpec turbo modeoptions_cmap options_lvdthd <2.4v | 2.7v>options_lvdsel options_lvdwarnread str9xpec optionswrite str9xpec optionsunlock str9xpec devicestr9xpec_build_block_liststr9xpec_erase_areastr9xpec_protectstr9xpec_writestr9xpec_isc_disablestr9xpec_isc_enablestr9xpec_blank_checkstr9xpec_isc_statusstr9xpec_read_configtms470 fmbbusy = 0x%08x -> %ssrc/flash/nor/tms470.cTMS470R1A256TMS470R1A288TMS470R1A3841.8v3.3vdevice_ident_reg = 0x%08xbank %d sector %d is %ssector erasedplldis=%d0xflash keys not setset fmmac2 = 0x%04xset fmmac1 = 0x%04xset fmtcreg = 0x2fc0set fmmaxpp = 50set fmmaxcp = 0x%04xset fmptr3 = 0x9964set fmptr3 = 0x9b64set fmmaxep = 0x%04xset fmptr4 = 0xa000set fmpsetup = 0x%04xset fmpvevaccess = 0x%04xset fmpchold = 0x%04xset fmpvevhold = 0x%04xset fmpvevsetup = 0x%04xset fmcvaccess = 0x%04xset fmcsetup = 0x%04xset fmehold = 0x%04xset fmpwidth = 0x%04xset fmcwidth = 0x%04xset fmewidth = 0x%04xwriting 0x%04x at 0x%08xfmstat = 0x%04xskipping 0xffff at 0x%08xset glbctrl = 0x%08xset fmregopt = 0x%08xset fmbsea = 0x%04xset fmbseb = 0x%04xset fmmstat = 0x%04xsector erased successfully.tms470 flash is unlockedosc_megahertz=%dtms470TI tms470 flash command groupflash_keyset osc_megahertztms470 osc_megahertz plldistms470 plldis <0/1><0 | 1>Cannot identify target as a TMS470 family.No %s flash bank contains base address 0x%08x.Could not identify part 0x%02x as a member of the TMS470 family.Identified %s, ver=%d, core=%s, nvmem=%s.Sector range %d to %d invalid.checking flash bank %d sector %dtms470 bank %d, sector %d, not erased.at location 0x%08x: flash data is 0x%02x.could not process flash key %stms470 flash_keyset using flash keys 0x%08x, 0x%08x, 0x%08x, 0x%08xCannot identify target as a TMS470 tms470 information: Chip is %s Flash protection level 2 is %s Writing %d bytes starting at 0x%08xCould not program word 0x%04x at address 0x%08x.tms470 writing fmpkey = 0x%08xtms470 could not unlock flash memory protection level 2Erasing tms470 bank %d sector %d...write *(uint16_t *)0x%08x=0x0040write *(uint16_t *)0x%08x=0x0020write *(uint16_t *)0x%08x=0xfffftms470 flash command: erase still active after busy clear.tms470 flash command: program still active after busy clear.tms470 flash command: invalid data command.tms470 flash command: program, erase or validate sector failed.tms470 flash command: voltage instability detected.tms470 flash command: command suspend detected.tms470 flash command: sector was locked.tms470 could not erase flash sector.osc_megahertz must be positive and non-zero!tms470_handle_flash_keyset_commandtms470_handle_osc_megahertz_commandtms470_flash_statustms470_erase_sectortms470_try_flash_keystms470_unlock_flashtms470_erasetms470_protecttms470_flash_initialize_internal_state_machinetms470_writetms470_probetms470_erase_checktms470_protect_checktms470_check_flash_unlockedtms470_read_part_info @@@@@@@    @ ` @ `     master flash bank '%s' does not existsrc/flash/nor/virtual.cvirtualvirtual_flash_bank_commandvirtual_get_master_bankIDCHIP register does not match XMC1xxx.Cannot read DBGROMID register.XMC%x00 %X flash %uKB ROM %uKB SRAM %uKBError executing flash sector erase check programming algorithmCouldn't restore NVMPROG.ACTIONInfineon XMC1000 erase sectors %d to %dInfineon XMC1000 write at 0x%08x (%d bytes)offset 0x%x breaks required block alignmentlength %d is not block aligned, rounding upError executing flash write programming algorithmsrc/flash/nor/xmc1xxx.cCannot read NVMCONF register.NVMCONF = %08xCannot read IDCHIP register.IDCHIP = %08xCannot read FLSIZE register.Cannot read CS0 register %i.ID[%d] = %08XID[7] = %08XNVMPROG.ACTIONErase-checking 0x%08xCouldn't read NVMSTATUSError writing data paddingxmc1xxxxmc1xxx flash command groupxmc1xxx_erasexmc1xxx_writexmc1xxx_probexmc1xxx_nvm_check_idlexmc1xxx_erase_checkxmc1xxx_protect_checkxmc1xxx_get_info_commandUnable to read flash User0 protection registerUnable to read flash User1 protection registerUnable to read flash User2 protection registerCannot read device identification register.Platform ID doesn't match XMC4xxx: 0x%08xFound XMC4xxx with devid: 0x%08xCannot read Flash bank configuration.XMC4xxx: XMC4100/4200 detected.XMC4xxx: XMC4700/4800 detected.XMC4xxx: Unexpected flash ID. got %02xUnexpected number of sectors, %d Unable to load bank information.XMC4xxx flash passwords set to: Cannot identify target as an XMC4xxx. SCU_ID: %x OTP Protection is enabled for sectors: Cannot read flash status register.Unable to write erase command sequenceError with flash erase sequencelevel option value ('%s') is not validInvalid user level. Must be 0-1Error erasing user configuration blockUnable to erase, target is not haltedUnable to write enter page mode commandSequence error while entering page modeUnable to enter write command sequenceError with flash write sequenceAttempting to write past the end of flashWrite does not start on a 256 byte boundary. Padding by %d bytesPadding end of page @%08x by %d bytesFlash passwords not set, use xmc4xxx flash_password to set themFlash protection will be temporarily disabled for all pages (User 0 only)!Unable to write temp unprotect sequenceFlash is temporarily unprotectedUnable to disable flash protectionFlash protection is installed for user %d and must be removed before continuingSetting flash protection with procon:Error writing user configuration block 0Set the flash passwords used for protect operations. Passwords should be in standard hex form (0x00000000). (You must call this before any other protect commands) NOTE: The xmc4xxx's UCB area only allows for FOUR cycles. Please use protection carefully!Permanently Removes flash protection (read and write) for the specified user levelsrc/flash/nor/xmc4xxx.cXMC4xxx: XMC4400 detected.XMC4xxx: XMC4500 detected. %d: %uk-0x%08x XMC4500XMC4800AA13XMC4500 EESXMC4100XMC4200XMC4300XMC4400XMC4700EES-AA- %d %s - Rev: %s%s%s - Rev: unknown (0x%01x)%sClearing flash statusTimed out waiting for flashXMC4xxx flash protectedFlash failed to eraseInvalid sector %dErasing sector %d @ 0x%08xUnable to enter page modeWLO: %08xWHI: %08xError loading page bufferFailed to write flash pageUnable to write flash pagePROCON: %xxmc4xxxxmc4xxx flash command groupflash_passwordbank_id password1 password2flash_unprotectbank_id user_level[0-1]xmc4xxx_flash_unprotectxmc4xxx_erase_sectorxmc4xxx_erasexmc4xxx_flash_protectxmc4xxx_temp_unprotectxmc4xxx_protectxmc4xxx_clear_flash_statusxmc4xxx_wait_status_busyxmc4xxx_get_flash_statusxmc4xxx_enter_page_modexmc4xxx_write_pagexmc4xxx_writexmc4xxx_load_bank_layoutxmc4xxx_probexmc4xxx_protect_checkxmc4xxx_get_info_command Flash is read pInvalid ACK (%1x) in DAP responseDAP transaction stalled (WAIT) - slowing downDebug regions are unpowered, an unexpected reset might have happenedsrc/target/adi_v5_jtag.cTimeout during WAIT recoveryjtag-dp: CTRL/STAT 0x%xJTAG-DP STICKY ERRORJTAG-DP STICKY OVERRUNEnter JTAG modedap_to_jtagjtagdp_transaction_endcheckjtagdp_overrun_checkvcr option value ('%s') is not validfatal error mode for memory writesADDR %08x SIZE %08x COUNT %08xData transfer failed. Expected end address 0x%08x, got 0x%08xuse 'arm11 memwrite burst disable' to disable fast burst modearm11_sc7_set_vcr(arm11, arm11->vcr | 1)arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr)Timeout (1000ms) waiting for instructions to completetarget_call_event_callbacks(target, old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED)Watchpoint triggered at PC %#08xonly breakpoints of four bytes length supportedBringing target into debug modearm11_write_DSCR(arm11, arm11->dscr)Only ARM v6 and v6.1 debug supported.IDCODE %08x IMPLEMENTOR %02x DIDR %08x%s: ran after reset and before halt ...arm11_sc7_set_vcr(arm11, arm11->vcr)'target arm11' expects IR LENGTH = 5wDTR/rDTR inconsistent (DSCR %08x)arm_dpm_write_dirty_registers(&arm11->dpm, bpwp)arm11_run_instr_no_data1(arm11, !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000)arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1)arm11_run_instr_no_data1(arm11, !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0)arm11_run_instr_data_from_core(arm11, instr, words, count)arm11_read_memory_word(arm11, address, &next_instruction)arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp))arm11_leave_debug_state(arm11, handle_breakpoints)target_call_event_callbacks(target, TARGET_EVENT_HALTED)arm11_leave_debug_state(arm11, true)target_call_event_callbacks(target, TARGET_EVENT_RESUMED)DEBUG ONLY - Hardware single stepping (default: disabled)Display or modify flag controlling interrupt enable while stepping (default: disabled)Display or modify Vector Catch RegisterDisplay or modify flag controlling potentially risky fast burst mode (default: enabled)Display or modify flag controlling transfer termination on transfer errors (default: enabled)VCR 0x%08xsrc/target/arm11.cIRQs while steppingmemory write burst modehardware single steptarget was not haltederror while calling "%s"%s: how to reset?DPM REG READ -- failReset c1 Control Registerjtag_execute_queue()arm11_read_DSCR(arm11)arm11_debug_entry(arm11)DSCR %08xarm11_sc7_clear_vbw(arm11)ARM1176ARM1136ARM1156ARM11 MPCoreunexpected ARM11 ID codearm11_dpm_init(arm11, didr)etm_setup(target)arm11_check_init(arm11)enter TARGET_HALTEDenter TARGET_RUNNINGarm11_poll(target)arm11_bpwp_flush(arm11)STEP PC %08x%sSkipping BKPT %08xSkipping WFI %08xNot stepping jump to selfDSCR %08x eRESUME PC %08x%smust step over %08xAdd BP %d at %08xarm11ARM11 command grouphardware_stepmemwritememwrite command groupstep_irq_enablevcrerror_fatalarm11_pollarm11_arch_statearm11_haltarm11_resumearm11_debug_entryarm11_leave_debug_statearm11_steparm11_assert_resetarm11_deassert_resetarm11_read_memory_innerarm11_write_memory_innerarm11_add_breakpointarm11_handle_vcrarm11_target_createarm11_check_initarm11_examinesrc/target/arm11_dbgtap.clast word not transferred'arm11 target' JTAG error SCREG OUT 0x%02xOut of memory allocating %u bytes%u words out of %u not transferredScan chain 7 shifted out unexpected addressScan chain 7 shifted out unexpected dataarm11_run_instr_data_to_core1(arm11, 0xee100e15, address)arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1)arm11_read_memory_wordarm11_sc7_runarm11_run_instr_data_from_corearm11_run_instr_data_to_core_noackarm11_run_instr_data_to_core_noack_inner_defaultarm11_run_instr_data_to_corearm11_run_instr_no_dataarm11_write_DSCRarm11_read_DSCRarm11_in_handler_SCAN_N   MMU: %s, Cache: %ssrc/target/arm720t.c%s: target not haltedcp15_control_reg: %8.8xOnly cp15 is supportedtarget is not an ARM7200x%8.8x: 0x%8.8xarm720tarm720t command groupinstruction [value]out: %8.8x, instruction: %i, clock: %iFailed to halt CPU after 1 secopcode option value ('%s') is not validcouldn't access cp15 with opcode 0x%8.8xdisplay/modify cp15 register using ARM opcode (DEPRECATED)arm720t_arch_statearm720t_soft_reset_haltarm720t_mrcarm720t_mcrarm720t_post_debug_entryarm720t_scan_cp15arm720_mmusrc/target/arm7_9_common.cBPID: %d, Address: 0x%08xBPID: %d Releasing hw wp: %ddcc downloads are %sfast memory access is %sSW BP using hw wp: %dthumb state, applying fixupsexamining %s modeexamining dirty reg: %srequire mode changeunhandled core statenew PC after step: 0x%8.8xJTAG error while reading cpsrarm7_9arm7/9 specific commandsdbgrqfast_memory_accessdcc_downloadscurrent target isn't an ARM7/ARM9 targetarm7_9->dcc_downloads option value ('%s') is not validarm7_9->fast_memory_access option value ('%s') is not validarm7_9->use_dbgrq option value ('%s') is not validuse of EmbeddedICE dbgrq instead of breakpoint for target halt %sBPID: %d (0x%08x) using hw wp: %dBPID: %d, Address: 0x%08x, Type: %dUnable to set 32 bit software breakpoint at address %08x - check that memory is read/writableUnable to set thumb software breakpoint at address %08x - check that memory is read/writablecan't enable sw breakpoints with no watchpoint unit availableBUG: both watchpoints used, but wp_available >= 1target entered debug from Thumb stater0_thumb: 0x%8.8x, pc_thumb: 0x%8.8xtarget entered debug from Jazelle stateJazelle debug entry -- BROKEN!target entered debug from ARM stateentered debug state at PC 0x%xnot a valid arm core mode - communication failure?BUG: dirty register '%s', but no valid datawriting register %i mode %s with value 0x%8.8xwriting SPSR of mode %i with value 0x%8.8xwriting lower 8 bit of cpsr with value 0x%2.2xno watchpoint unit available for hardware breakpointtimeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %xDBGACK already set during server startup.DBGACK set, but the target did not end up in the halted state %dsrst pulls trst - can not reset into halted mode. Issuing halt after reset.target entered debug from Thumb state, changing to ARMBUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()unset breakpoint at 0x%8.8x (id: %dCouldn't calculate PC of next instruction, current opcode was 0x%8.8xmemory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)no working area available, falling back to memory writesDCC write failed, expected end address 0x%08x got 0x%0xNOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.NOTE! Severe performance degradation without working memory enabled.NOTE! Severe performance degradation without fast memory access enabled. Type 'help fast'.use EmbeddedICE dbgrq instead of breakpoint for target halt requestsuse fast memory accesses instead of slower but potentially safer accessesuse DCC downloads for larger memory writesarm7_9_full_contextarm7_9_setup_semihostingarm7_9_check_resetarm7_9_bulk_write_memoryarm7_9_write_memoryarm7_9_read_memoryarm7_9_steparm7_9_restore_contextarm7_9_set_watchpointarm7_9_resumearm7_9_haltarm7_9_soft_reset_haltarm7_9_deassert_resetarm7_9_assert_resetarm7_9_debug_entryarm7_9_pollarm7_9_execute_sys_speedarm7_9_unset_watchpointarm7_9_unset_breakpointarm7_9_set_software_breakpointsarm7_9_set_breakpointarm7_9_assign_wparm7_9_clear_watchpointsarm7_9_add_breakpoint src/target/arm7tdmi.cxpsr: %8.8x, spsr: %iarm7tdmixpsr_im: %2.2x, rot: %i, spsr: %iarm7tdmi_write_xpsrarm7tdmi_write_xpsr_im8arm7tdmi_branch_resume_thumbtarget_to_armsrc/target/arm920t.cBUG: %sfailed executing JTAG queue(valid)(invalid)D TLB content: I TLB content: DCache: segment: %i ----------%i: 0x%8.8x ICache: couldn't access reg %icouldn't execute %8.8x%8.8x: %8.8x%8.8x: %8.8x %8.8xarm920tarm920t command groupdisplay/modify cp15 registerregnum [value]cp15iinstruction [value [address]]read_cacheread_mmudump I/D mmu content to fileMMU: %s, D-Cache: %s, I-Cache: %sD-Cache buffered, drain write bufferD-Cache in 'write back' mode, flush cache lineD-Cache enabled, invalidate cache lineI-Cache enabled, invalidating affected I-Cache lineerror opening mmu content file%i: 0x%8.8x 0x%8.8x 0x%8.8x %s mmu content successfully output to %serror opening cache content file segment: %i, index: %i, CAM: 0x%8.8x, content (%s): cache content successfully output to %sD FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8xdisplay information about target cachesdump I/D cache content to filearm920t_mrcarm920t_mcrarm920_mmuarm920t_handle_read_cache_commandarm920t_handle_read_mmu_commandarm920t_soft_reset_haltarm920t_write_memoryarm920t_arch_statearm920t_write_cp15_interpretedarm920t_post_debug_entryarm920t_execute_cp15target_to_armarm920t_read_cp15_interpretedtarget is not an ARM920src/target/arm926ejs.cbreakpoint from EICE unit 0breakpoint from EICE unit 1vector catch breakpointexternal breakpointwatchpoint from EICE unit 0watchpoint from EICE unit 1external watchpointinternal debug requestexternal debug requestunexpected -- debug re-entrycp15 read operation timed outarm926ejsarm926ejs command groupD FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8xno *NEW* debug entry (?missed one?)soft breakpoint (BKPT instruction)debug re-entry from system speed accessWARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt.WARNING: unknown debug reason: 0x%xcp15 write operation timed outPP0harm926ejs_mmuarm926ejs_mrcarm926ejs_mcrarm926ejs_post_debug_entryarm926ejs_cp15_readarm926ejs_cp15_writearm926ejs_examine_debug_reasonarm926ejs_soft_reset_haltarm926ejs_arch_statetarget is not an ARM926src/target/arm946e.cERROR enabling cacheaddr [value]arm946e: no current targettarget is not an ARM946%s cp15 reg %i access failedERROR writing indexERROR cleaning cache lineERROR flushing cache lineFLUSHING I$ERROR flushing I$ERROR disabling cache%s-cache absent%s-cache size: %uK, %sflusharm946earm946e command groupread/modify cp15 registerI-cache info and operations['enable'|'disable'|'flush']D-cache info and operationstarget %s must be stopped for "cp15" command%s-cache absent, '%s' operation undefinedarm946e: MPU must be enabled for cache to operatejim_arm946e_cp15jim_arm946e_cp15arm946e_handle_idcachearm946e_read_memoryarm946e_write_memoryarm946e_invalidate_icachearm946e_invalidate_dcachearm946e_pre_restore_contextarm946e_post_debug_entryarm946e_invalidate_whole_icachearm946e_invalidate_whole_dcachetarget is not an ARM966arm966earm966e command groupundefdon't catchsrc/target/arm9tdmi.carm9tdmiarm9arm9 command groupswipabtdabttarget doesn't have EmbeddedICE with vector_catchvector '%s' not found, leaving current setting unchangedDisplay, after optionally updating, configuration of vector catch unit.[all|none|(reset|undef|swi|pabt|dabt|irq|fiq)*]handle_arm9tdmi_catch_vectors_commandarm9tdmi_write_xpsrarm9tdmi_write_xpsr_im8arm9tdmi_branch_resume_thumbtarget_to_arm(RESERVED)iapsreapsrxpsripsriepsrmsppspprimaskbasepribasepri_maxfaultmaskCDPSPSRCPSR0x%8.8x 0x%8.8x MRS%s r%i, %sMVNANDEORADCSBCRSCTEQCMPCMNORRMOVBICr%i, LSL r%ir%i, LSR r%ir%i, ASR r%ir%i, ROR r%i0x%8.8x 0x%8.8x NOP0x%8.8x 0x%8.8x %s%s r%i, %sLDMPOPPUSHr%i%s, r%i, 0x%8.8x 0x%4.4x %s %s{%s}MCRRMRRCSTCLDC[r%i, #%s%d][r%i, #%s%d]![r%i], #%s%d[r%i], {%d}LDRSTRBT, #%s0x%x, %sr%i, %sr%i, LSL #0x%x, %sr%i, LSR #0x%x, %sr%i, ASR #0x%x, %sr%i, ROR #0x%x, %sr%i, RRXSMLALUMULLUMLALSMULLSWPSWPBQDSUBQADDQSUBQDADDSMCBRKTHVCUHUQSUB8ADD16SUBADDXSUB16ADD8ADDSUBXLSLASR, ROR #24, ROR #16, ROR #8REVSHREVREV16^0x%8.8x 0x%8.8x RFE%s r%d%s0x%8.8x 0x%8.8x BLX 0x%8.8x0x%8.8x 0x%8.8x BX%s r%i0x%8.8x 0x%8.8x BXJ%s r%i0x%8.8x 0x%8.8x BLX%s r%i0x%8.8x 0x%8.8x ERET0x%8.8x 0x%8.8x %s 0x%4.4x0x%8.8x 0x%8.8x UNDEF0x%8.8x 0x%8.8x %s%s%s r%d, r%d, r%dPKH%s%s r%d, r%d, r%d, %s #%d%cSAT%s r%d, #%d, r%d, %s #%d%cXT%s%s r%d, r%d%s%cXTA%s%s r%d, r%d, r%d%sSML%cD%s%s r%d, r%d, r%d, r%dSMU%cD%s%s r%d, r%d, r%dSMML%c%s%s r%d, r%d, r%d, r%dSMMUL%s%s r%d, r%d, r%d%cSAT16%s r%d, #%d, r%dSEL%s r%d, r%d, r%dUSAD8%s r%d, r%d, r%dUSADA8%s r%d, r%d, r%d, r%d%s%s r%d, r%d, r%i0x%8.8x 0x%8.8x B%s%s 0x%8.8x0x%8.8x 0x%8.8x SVC %#6.6xsrc/target/arm_disassembler.cSUBSADDSASRSLSRSLSLSMOVSMVNSBICSMULSORRSRSBSRORSSBCSADCSEORSANDSLDRSHSTRHSTRBLDRSBLDRHLDRBHINT (UNRECOGNIZED)WFEWFISEVYIELDBLBLXprefix0x%8.8x 0x%4.4x BLX r%i0x%8.8x 0x%4.4x BX r%i0x%8.8x 0x%4.4x %sORNADDWSUBWHINT.W (UNRECOGNIZED)YIELD.WWFE.WWFI.WSEV.WNOP.WLEAVEXCLREXDMBENTERXSTREXBSTREXHSTREXLDREXLDREXBLDREXHSTRDLDRDLDRB.WLSRCLZREV.WRBITREVSH.WREV16.WMULMLA0x%8.8x 0x%8.8x %s%s r%d, #%d ; %#8.8x%s%s%s r%d, r%d, #%d ; %#8.8xMOVW r%d, #%d ; %#3.3xMOVT r%d, #%d ; %#4.4x%sSAT r%d, #%d, r%d, %s #%d %sBFX r%d, r%d, #%d, #%d BFC r%d, #%d, #%d BFI r%d, r%d, #%d, #%d %s r%d, r%d, #%d ; %#3.3xADR.W r%d, %#8.8x%s %#8.8xB%s.W %#8.8xMSR %s, r%dDBG #%dBXJ r%dMRS r%d, %sSRS%s sp%s, #%dSTM.W r%d%s, POP.W LDM.W r%d%s, STMDB r%d%s, LDMDB.W r%d%s, TBB [r%u, r%u]TBH [r%u, r%u, LSL #1]%s r%u, r%u, [r%u]%s r%u, [r%u, #%u] ; %#2.2x%s r%u, [r%u]%s r%u, r%u, %#8.8xLDR r%d, %#8.8xLDRT r%d, [r%d, #%d] ; %#2.2xHINT (UNALLOCATED)LDR%sH r%d, %#8.8xPLD r%d, %#8.8xLDRB r%d, %#8.8xPLD%s [r%d, #%d] ; %#6.6xLDRB.W r%d, [r%d, r%d, LSL #%d]PLI %#8.8xLDRSB %#8.8xPLI [r%d, #%d] ; -%#2.2xLDRSB.W r%d, PLI [r%d, #%d] ; %#3.3xMOV%s.W r%d, r%dRRX%s r%d, r%d%s%s.W r%d, r%d, r%d%s%s.W r%d, r%d%s%s.W r%d, r%d, #%d%cXT%c.W r%d, r%d%sMUL r%d, r%d, r%dMLA r%d, r%d, r%d, r%dMLS r%d, r%d, r%d, r%d%c%sL r%d, r%d, r%d, r%d%cDIV r%d, r%d, r%dPLHIGT-,--- -0-@-P-`-------p----,32<2\2|222223<3\3|3301RQQQRQQQQSRtRbRDRRR;R:edddbb1deedcdbbcb1g gff}fkfYf)ffeeeeeeg|hXhFh4h"hhgjh`jjjjyjpxpUpooXnXnXnoXnooXngoornnnrnnnnn]rn>rnnn-rn-rnqnqnqnqnrsss_s2smrrttsmsssts"ttt3v'vvuuurttwwvwwvvwwwwwwwwwwzzWzzzyllzzzzvyvyrrrwrJrlrr|}|&}|lll|lz||l]|{ arm_access_sizethumb2_opcodethumb_evaluate_opcodearm_evaluate_opcode0x%8.8x 0x%8.8x %s%s p%i, 0x%2.2x, r%i, c%i, c%i, 0x%2.2x0x%8.8x 0x%8.8x %s%s p%i, 0x%2.2x, c%i, c%i, c%i, 0x%2.2x0x%8.8x 0x%8.8x MSR%s %s_%s%s%s%s, 0x%8.8x0x%8.8x 0x%8.8x MSR%s %s_%s%s%s%s, r%i0x%8.8x 0x%8.8x %s%s%s r%i, r%i, %s0x%8.8x 0x%8.8x %s%s%s r%i, %s0x%8.8x 0x%8.8x %s%s%s p%i, %x, r%i, r%i, c%i0x%8.8x 0x%8.8x %s%s%s p%i, c%i, %s0x%8.8x 0x%8.8x %s%s%s r%i, [r%i%s]0x%8.8x 0x%8.8x %s%s%s r%i, [r%i%s]!0x%8.8x 0x%8.8x %s%s%s r%i, [r%i]%s0x%8.8x 0x%8.8x PLD ...TODO...0x%8.8x 0x%8.8x UNDEFINED INSTRUCTION0x%8.8x 0x%8.8x SRS%s SP%s, #%d0x%8.8x 0x%8.8x MLA%s%s r%i, r%i, r%i, r%i0x%8.8x 0x%8.8x MUL%s%s r%i, r%i, r%i0x%8.8x 0x%8.8x %s%s%s r%i, r%i, r%i, r%i0x%8.8x 0x%8.8x %s%s r%i, r%i, [r%i]0x%8.8x 0x%8.8x %s%s%s r%i, [r%i, %s]0x%8.8x 0x%8.8x %s%s%s r%i, [r%i, %s]!0x%8.8x 0x%8.8x %s%s%s r%i, [r%i], %s0x%8.8x 0x%8.8x CLZ%s r%i, r%i0x%8.8x 0x%8.8x %s%s r%i, r%i, r%i0x%8.8x 0x%8.8x SMLA%s%s%s r%i, r%i, r%i, r%iSML%cLD%s%s r%d, r%d, r%d, r%d0x%8.8x 0x%8.8x %s%s%s r%i%s, {%s}%sARM: should never reach this point (opcode=%08x)0x%8.8x 0x%4.4x %s r%i, r%i, #%d0x%8.8x 0x%4.4x %s r%i, r%i, r%i0x%8.8x 0x%4.4x %s r%i, r%i, #%#2.2x0x%8.8x 0x%4.4x %s r%i, #%#2.2x0x%8.8x 0x%4.4x UNDEFINED INSTRUCTION0x%8.8x 0x%4.4x NOP ; (%s r%i, r%i)0x%8.8x 0x%4.4x %s r%i, r%i0x%8.8x 0x%4.4x LDR r%i, [pc, #%#x] ; %#8.8x0x%8.8x 0x%4.4x %s r%i, [r%i, r%i]0x%8.8x 0x%4.4x %s%c r%i, [r%i, #%#x]0x%8.8x 0x%4.4x %s r%i, [SP, #%#x]0x%8.8x 0x%4.4x ADD r%i, %s, #%#x0x%8.8x 0x%4.4x %s SP, #%#x0x%8.8x 0x%4.4x CB%sZ r%d, %#8.8x0x%8.8x 0x%4.4x %cXT%c r%d, r%d0x%8.8x 0x%4.4x SETEND %s0x%8.8x 0x%4.4x CPSI%c %s%s%s0x%8.8x 0x%4.4x REV%s r%d, r%d0x%8.8x 0x%4.4x BKPT %#2.2x0x%8.8x 0x%4.4x IT%s%s%s %s0x%8.8x 0x%4.4x SVC %#2.2x0x%8.8x 0x%4.4x B%s %#8.8x0x%8.8x 0x%8.8x UNDEFINED INSTRUCTION0x%8.8x 0x%4.4x %s %#8.8xThumb: should never reach this point (opcode=%04x)%s r%u, r%u, [r%u, #%u] ; %#2.2x%s r%u, r%u, [r%u%s, #%s%u%s ; %#2.2xLDR.W r%d, [r%d, #%d] ; %#3.3xLDR.W r%d, [r%d, r%d, LSL #%d]LDR r%d, [r%d%s, #%s%u%s ; %#2.2xLDR%sH.W r%d, [r%d, r%d, LSL #%d]LDR%sHT r%d, [r%d, #%d] ; %#2.2xLDR%sH r%d, [r%d%s, #%d%s ; %#8.8xLDR%sH%s r%d, [r%d, #%d] ; %#6.6xLDRBT r%d, [r%d, #%d] ; %#2.2x%s r%d, [r%d%s, #%d%s ; %#8.8xLDRSBT r%d, [r%d, #%d] ; %#2.2xSTR%s.W r%d, [r%d, r%d, LSL #%d]STR%s.W r%d, [r%d, #%u] ; %#3.3xSTR%s%s r%d, [r%d%s, #%s%u%s ; %#2.2xCan't decode 32-bit Thumb2 yet (opcode=%08x)BUG: instruction type %i isn't a load/store instructionUNDEFINED OPCODE(32-bit Thumb2 .watch%s: can't %s HW %spoint %dsrc/target/arm_dpm.cinvalid register #%uusing HW bkpt, not SW...MCR p%d, %d, r0, c%d, c%d, %dMRC p%d, %d, r0, c%d, c%d, %dJazelle PC adjustment unknownREAD: %s, %8.8xWRITE: %s, %8.8xunsupported {break,watch}point length/alignmentBPWP: addr %8.8x, control %x, number %dwatchpoint values and masking not supported%s: hardware has %d breakpoints, %d watchpoints%s: can't disable breakpoints and watchpointsarm_dpm_initializedpm_mapmodedpm_mrcdpm_mcrdpm_watchpoint_setuparm_dpm_setupdpm_write_regdpm_maybe_update_bpwpdpm_bpwp_setuptarget_to_armdpm_add_breakpointdpm_read_reg:ttsrc/target/arm_semihosting.cfoobarsemihosting: exception %#x SPSR not valid!Failed semihosting operationFailed to resume targetSYS_READC not supported by semihosting fileioSYS_FLEN not supported by semihosting fileiosemihosting: *** application exited *** semihosting: unsupported call %#x Unsupported semi-hosting TargetFailed to post semihosting result Pȗp`8 P p  do_semihostingarm_semihostingtarget_to_armarm_semihosting_initAABBAABBHX 0hݤФarm_shifter_operandarm_simulate_step_coretarget_to_armsrc/target/arm_simulator.cunhandled instruction typeno updating of flags yetBUG: shifter_operand.variant not 0, 1 or 2BUG: offset_mode neither 0 (offset) nor 1 (scaled register)Unimplemented instruction, could not simulate it.%s doesn't implement MCRsrc/target/armv4_5.c%s doesn't implement MRCarm != NULLNo target selectedcurrent target isn't an ARMsemihosting is not enabledsemihosting fileio is %ssemihosting is %s%s: no current target%s: not yet examined%s: not an ARM%s: wrong number of arguments%s: %s %d out of rangecoprocessorop1CRnCRmUnsupported Commandarmthumbcore state: %sDisassemble as Thumbunrecognized psr mode: %#02xUNRECOGNIZEDshadow System and User%s%s mode %sregisters%8s: %8.8x mode index out of bounds %dThumbEE -- incomplete supportInvalid CPSR modeARM registersorg.gnu.gdb.arm.coregeneralbanked fileio, semihostingRunning algorithmBUG: register '%s' not foundsetting core_mode: 0x%2.2xARM command groupdisplay ARM core registerscore_statedisplay/change ARM core state['arm'|'thumb']disassembledisassemble instructions address [count ['thumb']]write coprocessor registercpnum op1 CRn CRm op2 valuemrcread coprocessor registercpnum op1 CRn CRm op2semihosting_fileioGDB dummy FPA status registerfake_fpaGDB dummy FPA registersp_usrlr_usrr8_fiqr9_fiqr10_fiqr11_fiqr12_fiqsp_fiqlr_fiqsp_irqlr_irqsp_abtlr_abtsp_undlr_undspsr_fiqspsr_irqspsr_svcspsr_abtspsr_undsp_monlr_monspsr_monJazelleThumbEEFIQSupervisorAbortIRQUndefined instructionSecure MonitorSecure Monitor ARM1176JZF-SThreadThread (User)Handlerarm->is_semihosting_fileio option value ('%s') is not validsemihosting not supported for current targetsemihosting option value ('%s') is not validFailed to Configure semihostingerror: target must be halted for register accessesMicrocontroller Profile not supported - use standard reg cmderror: target doesn't support %starget reentered debug state, but not at the desired exit point: 0x%4.4xinvalid mode value encountered %dJazelle state handling is BROKEN!set CPSR %#8.8x: %s mode, %s statechanging ARM core mode to '%s'Register map is not available yet, the target is not fully initialisednet.sourceforge.openocd.bankedBUG: called for a non-ARM targettarget halted in %s state due to %s, current mode: %s cpsr: 0x%8.8x pc: 0x%8.8x%s%snot a valid register class type in query.current target isn't an ARMV4/5 targetARMv4 target needs HW breakpoint locationBUG: register '%s' size doesn't match reg_params[i].sizeBUG: can't execute algorithms when not in ARM or Thumb statecan't add HW breakpoint to terminate algorithmrestoring register %s with value 0x%8.8xerror executing ARM crc algorithmErase value 0x%02x not yet supported for ARMv4/v5 targetsactivate support for semihosting operationsactivate support for semihosting fileio operationsnet.sourceforge.openocd.fake_fpa`йййййййййййййййй`hpйййййййarm_default_mrcarm_default_mcr0 Qp arm_blank_check_memoryarm_checksum_memory 0@ 0p PP`P&U@Tp armv4_5_run_algorithm_completionarmv4_5_run_algorithm_innerarm_get_gdb_reg_listhandle_armv4_5_reg_commandhandle_arm_disassemble_commandjim_mcrmrcjim_mcrmrchandle_arm_semihosting_commandis_armhandle_arm_semihosting_fileio_commandarm_arch_statearmv4_5_get_core_regtarget_to_armarmv4_5_set_core_regarm_reg_currentarm_set_cpsrarmv4_5_number_to_modearm_mode_to_numberarm_mode_name   ! " # $  %&''()$#"!  separate cachesunified cachecache not yet identifiedcache type: 0x%1.1x, %sD-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%xI-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x1st lvl desc: %8.8xsrc/target/armv4_5_mmu.cAddress translation failure2nd lvl desc: %8.8xarmv4_5_mmu_translate_va%s: implement mesrc/target/avr32_ap7k.cavr32 registersdevice id: %08xtarget is haltedwrite core reg %i value 0x%xtarget resumed at 0x%xtarget debug resumed at 0x%xavr32_ap7ktarget halted due to %s, pc: 0x%8.8xcan't request a halt while in reset if nSRST pulls nTRSTavr32_ap7k_haltavr32_ap7k_resumeavr32_ap7k_stepavr32_ap7k_assert_resetavr32_ap7k_deassert_resetavr32_ap7k_read_memoryavr32_ap7k_write_memoryavr32_ap7k_add_breakpointavr32_ap7k_remove_breakpointavr32_ap7k_add_watchpointavr32_ap7k_remove_watchpointavr32_ap7k_examineavr32_ap7k_get_gdb_reg_listavr32_ap7k_arch_stateavr32_write_core_reg %s: setting address failedsrc/target/avr32_jtag.c%s: reading data failedavr32_jtag_mwa_write_dataavr32_jtag_mwa_read_dataavr32_jtag_mwa_set_addressavr32_jtag_set_instravr32_jtag_nexus_write_dataavr32_jtag_nexus_read_dataavr32_jtag_nexus_set_addresssrc/target/avrt.cdr_len overflow, maxium is 32invalid tapinvalid ir_lenmcu_write_irmcu_write_drmcu_write_dr_u32avr_pollavr_arch_stateavr_haltavr_resumeavr_stepavr_assert_resetavr_deassert_resetavr_init_targetfree BPID: %u --> %dsrc/target/breakpoints.cfree WPID: %d --> %dunknown reasontarget runningresource not availablecan't add breakpoint: %scould not add breakpointunrecognized errorhardwaresoftwareDuplicate Breakpoint address: 0x%08x (BP %u)added %s breakpoint at 0x%8.8x of length 0x%8.8x, (BPID: %u)Duplicate Breakpoint asid: 0x%08x (BP %u)added %s Context breakpoint at 0x%8.8x of length 0x%8.8x, (BPID: %u)Duplicate Hybrid Breakpoint asid: 0x%08x (BP %u)Duplicate Breakpoint IVA: 0x%08x (BP %u)added %s Hybrid breakpoint at address 0x%8.8x of length 0x%8.8x, (BPID: %u)no breakpoint at address 0x%8.8x foundDelete all breakpoints for target: %saddress 0x%8.8x already has watchpoint %dcan't add %s watchpoint at 0x%8.8x, %sadded %s watchpoint at 0x%8.8x of length 0x%8.8x (WPID: %d)no watchpoint at address 0x%8.8x foundDelete all watchpoints for target: %sFound hit watchpoint at 0x%8.8x (WPID: %d)watchpoint_hitwatchpoint_clear_targetwatchpoint_freewatchpoint_removewatchpoint_addbreakpoint_clear_target_internalbreakpoint_removebreakpoint_freebreakpoint_remove_internalhybrid_breakpoint_add_internalcontext_breakpoint_add_internalbreakpoint_add_internalenable mmudisable mmusrc/target/cortex_a.c%s, writing cp15 ctrl: %xA: bpwp disable, cr %08xCould not read DSCR registerTimeout waiting for haltexec opcode 0x%08xDSCR_DTR_RX_FULL, dscr 0x%08xread DCC 0x%08xcp15_dacr_reg: %8.8xgdb coreid %d -> %dTimeout waiting for resumebrp(CTX) found num: %d brp(IVA) found num: %d Timeout waiting for read dccwrite DCC 0x%08xcortex_a interrupt mask %sdscr = 0x%08xregister %i, value 0x%08xcpsr: %8.8xTarget haltedDIDRExamine %s failedCPUIDdidr = 0x%08xcpuid = 0x%08xtarget->coreid %d was reset!Configured %i hw breakpointstarget not examined yetresume pc = 0x%08xcortex_r4Cortex-R4 command groupdbginitInitialize core debugmaskisrmask cortex_r4 interruptscortex_acortex_a8Cortex-A command groupsmp_offStop smp handlingsmp_onRestart smp handlingsmp_gdbmask cortex_a interruptsdacrfixuptrying to enable mmu on target stopped with mmu disableA: bpwp enable, vr %08x cr %08xTimeout waiting for InstrCompl=1Timeout waiting for cortex_a_exec_opcodeTimeout waiting for dpm prepareTimeout waiting for dtr tx fullcortex_a domain access control fixup %scoreid option value ('%s') is not validInvalid BRP number in breakpointrbp %i control 0x%0x value 0x%0xERROR Can not find free Breakpoint Register Pairbrp %i control 0x%0x value 0x%0xDSCR InstrCompl must be set before leaving debug!no hardware breakpoint availabletimeout waiting for DSCR bit changeWriting CPU memory address 0x%x size %u count %udata abort at 0x%08x, dfsr = 0x%08xerror restoring dfar/dfsr - dscr = 0x%08xWriting memory to real address 0x%x; size %d; count %dWriting memory at address 0x%x; size %d; count %dReading CPU memory address 0x%x size %u count %uReading memory at real address 0x%x; size %d; count %dReading memory at address 0x%x; size %d; count %dWriting to virtual address. Translating v:0x%x to r:0x%xReading at virtual address. Translating v:0x%x to r:0x%xUnknown parameter: %s - should be off or onUnknown target state dscr = 0x%08xCould not initialize the debug portCould not find APB-AP for debug accessCould not initialize the APB-APNo AHB-AP available for memory access%s's dbgbase is not set, trying to detect using the ROM tableCan't detect %s's dbgbase from the ROM table; you need to specify it explicitly.Detected core %d dbgbase: %08xtarget->coreid %d DBGPRSR 0x%xtarget->coreid %d powered down!target->coreid %d DBGOSLSR 0x%xtarget->coreid %d OSLock set! Trying to unlocktarget->coreid %d OSLock sticky, core not powered?How do I resume into Jazelle state??timeout waiting for target haltdisplay/fix current core played to gdbset domain access control (DACR) to all-manager on memory accesscortex_a_dap_read_coreregister_u32cortex_a_dap_write_coreregister_u32cortex_a_debug_entrycortex_a_pollcortex_a_haltcortex_a_internal_restartcortex_a_restore_contextcortex_a_internal_restorecortex_a_resumecortex_a_stepcortex_a_assert_resetcortex_a_deassert_resetcortex_a_read_memorycortex_a_write_memorycortex_a_read_memory_ahbcortex_a_write_memory_ahbcortex_a_set_breakpointcortex_a_add_breakpointcortex_a_set_context_breakpointcortex_a_add_context_breakpointcortex_a_set_hybrid_breakpointcortex_a_add_hybrid_breakpointcortex_a_unset_breakpointcortex_a_handle_dbginit_commandhandle_cortex_a_mask_interrupts_commandcortex_a_post_debug_entrycortex_a_handle_target_requestcortex_a_dpm_preparecortex_a_write_dcccortex_a_read_dcccortex_a_bpwp_enablecortex_a_bpwp_disablecortex_a_examine_firstcortex_a_read_cpu_memorycortex_a_read_phys_memorycortex_a_exec_opcodecortex_a_wait_dscr_bitscortex_a_wait_instrcmplcortex_a_write_cpu_memorycortex_a_mmu_modifycortex_a_write_phys_memorycortex_a_mmuno comparators?src/target/cortex_m.cunsupported watchpoint lengthdwt_comp_available: %ddata 0x%x ctrl 0x%x NVIC_DFSR 0x%xsysresetreqvectresettarget is not a Cortex-Mcortex_m reset_config %s%9s: %sNo CM3 vector '%s'cortex_m interrupt mask %sDP initialisation failedSYSRESETREQVECTRESETUsing Cortex-M %sJTAG failurewrite FPSCR value 0x%xwrite FPU reg S%d value 0x%xDCB_DEMCR = 0x%8.8xFailed to enable the FPBJTAG failure %iload from FPSCR value 0x%xfpc_num %i fpcr_value 0x%xFPB wasn't enabled, do it nowwatchpoint (wpid: %d) not set/triggerno DWTout of memCortex-M DWT registerscpuid: 0x%8.8xcortex_m3Cortex-M command groupmask cortex_m interrupts['auto'|'on'|'off']dwt_0_compdwt_0_maskdwt_0_functiondwt_1_compdwt_1_maskdwt_1_functiondwt_2_compdwt_2_maskdwt_2_functiondwt_3_compdwt_3_maskdwt_3_functiondwt_ctrldwt_cyccntwatchpoint value masks not supportedwatchpoint address is unaligneddata value watchpoint not YET supportedTarget not examined, will not halt after reset!Target not examined, reset NOT asserted!AP write error, reset will not haltOnly resetting the Cortex-M core, use a reset-init event handler to reset any peripherals or configure hardware srst support.Ignoring AP write error right after resetwrite special reg %i value 0x%x %s SHCSR 0x%x, SR 0x%x, CFSR 0x%x, AR 0x%xentered debug state in core mode: %s at PC 0x%x, target->state: %s%s -- clearing lockup after double faultExit from reset with dcb_dhcsr 0x%xsoft_reset_halt is deprecated, please use 'reset halt' instead.system reset-halted, DHCSR 0x%08x, DFSR 0x%08xwaiting for system reset-halt, DHCSR 0x%08x, %d msload from core reg %i value 0x%xload from FPU reg S%d value 0x%xload from special reg %i value 0x%xbreakpoint (BPID: %u) already setCan not find free FPB Comparator!Unhandled Cortex-M Flash Patch Breakpoint architecture revisionBPID: %u, Type: %d, Address: 0x%08x Length: %d (set=%d)flash patch comparator requested outside code memory regionsoft breakpoint requested in code (flash) memory regionno flash patch comparator unit available for hardware breakpointUsing a two byte breakpoint for 32bit Thumb-2 requestonly breakpoints of two bytes length supportedInvalid FP Comparator number in breakpointStepping over next instruction with interrupts disabledStarting core to serve pending interruptsInterrupt handlers didn't complete within time, leaving target runningtarget stepped dcb_dhcsr = 0x%x nvic_icsr = 0x%xCan not find free DWT ComparatorWatchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05xWatchpoint (ID %d) DWT%d address: 0x%08x clearInvalid DWT Comparator number in watchpointunset breakpoint at 0x%8.8x (ID: %u)DWT dwtcr 0x%x, comp %d, watch%sCould not find MEM-AP to control the coreCortex-M%d r%dp%d processor detectedSilicon bug: single stepping will enter pending exception handler!Cortex-M%d floating point feature FPv4_SP foundCortex-M%d floating point feature FPv5_SP foundCortex-M%d floating point feature FPv5_DP foundFPB fpcr 0x%x, numcode %i, numlit %iconfigure hardware vectors to trigger debug entry['all'|'none'|('bus_err'|'chk_err'|...)*]configure software reset handling['srst'|'sysresetreq'|'vectreset']OOO^QQPPOOOOOPOOOcortex_m_endreset_eventcortex_m_pollcortex_m_haltcortex_m_single_step_corecortex_m_resumedap_runcortex_m_examine_exception_reasoncortex_m_debug_entrycortex_m_stepcortex_m_clear_haltcortex_m_assert_resetcortex_m_deassert_resetcortex_m_soft_reset_halthandle_cortex_m_vector_catch_commandcortex_m_load_core_reg_u32cortex_m_store_core_reg_u32cortex_m_dcc_readcortex_m_examinecortex_m_dwt_setupcortex_m_remove_watchpointcortex_m_add_watchpointcortex_m_unset_watchpointcortex_m_set_watchpointcortex_m_remove_breakpointcortex_m_add_breakpointcortex_m_unset_breakpointcortex_m_set_breakpointhard_errint_errbus_errstate_errchk_err@nocp_err mm_errresetsrc/target/dsp563xx.cdsp563xx registersmemspaceno IDCODE present on deviceDSP56%03d device foundtarget->state: %s (%x)halted: PC: 0x%x%s %08X %08Xfetch: %08Xdecode: %08Xexecute: %08Xsize is not aligned to 4 bytedsp563xxmwwxwrite x memory wordsaddress value [count]mwwywrite y memory wordsmwwpwrite p memory wordsmdwxdisplay x memory wordsmdwydisplay y memory wordsmdwpdisplay p memory wordswppCreate p memspace watchpoint(>|<|=|!) (r|w|a) addresswpxCreate x memspace watchpointwpyCreate y memspace watchpointrwpcremove watchpoint customn0n1n2n3n4n5n7m0m1m2m5m6x0x1y0y1a0a1a2b0b1b2sshsslszomrvbaiprciprpbcrdcraar0aar1aar2aar3OSCROMBCOBCROMLR0OMLR1OGDBROPDBROPILRPDBOTCOPABFROPABDROPABEXOPABF0OPABF1OPABF2OPABF3OPABF4OPABF5OPABF6OPABF7OPABF8OPABF9OPABF10OPABF11Cannot remove watchpoint, as no watchpoint is currently configured!%s conditional branch not supported yet (0x%x 0x%x 0x%x)jtag status contains invalid mode value - communication failurememtype: %d address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8xCannot add watchpoint. Hardware resource already used.pwwXxXxXxXxvXxXxXxXxXxHvHvHvHvHvHvHvHvaidsp563xx_polldsp563xx_arch_statedsp563xx_haltdsp563xx_resumedsp563xx_stepdsp563xx_assert_resetdsp563xx_reg_pc_readdsp563xx_step_exdsp563xx_deassert_resetdsp563xx_run_algorithmdsp563xx_write_memory_coredsp563xx_write_memorydsp563xx_read_memory_coredsp563xx_read_memorydsp563xx_add_custom_watchpointdsp563xx_remove_custom_watchpointdsp563xx_examinedsp563xx_get_core_regdsp563xx_set_core_regdsp563xx_init_target! ()*+,"#$%&'-./012345 debug request: %02Xsrc/target/dsp563xx_once.cenable once: %02Xdsp563xx_once_request_debugDSP5680XX_ERROR:%d At:%s:%d:%sMaster:%d Core:%d Only 1 should be enabled. Failed to reset JTAG state machineEOnCE successfully entered debug mode.Failed to set EOnCE module to debug mode%s:Data read from 0x%06X: 0x%02X%02XTarget already halted and in debug mode.Target already halted, re attempting to enter debug mode.%s: Failed to put EOnCE in debug mode.Flash locked?...%s: JTAG running, but EOnCE run failed.Try resetting..Inconsistent target status. Restart!%s: Cannot communicate with JTAG. Check connection...%s: Target status invalid - communication failureDebug mode be enabled to read mem.HFM CLK divisor contained incorrect value (0x%02X).HFM CLK divisor was already set to correct value (0x%02X).Unable to set HFM CLK divisor.HFM CLK divisor set to 0x%02x.Timed out waiting for FM to finish old command.pviol and/or accer bits set. HFM command execution error%s: Could not write to p:0x%04XCannot handle odd number of words.Flashed data failed CRC check, flash again!src/target/dsp5680xx.cNot implemented yet.%s not implemented yet.Invalid tapInvalid irlendsp568013.chpirscan failed!target initiated!drscan failed!Data read (%d bits): 0x%04XData read was discarded.Failed to get master tap.dsp568013.cpuFailed to get core tap.Target already running.Target must be halted.EOnCE status: 0x%02X.Failed to exit debug mode...Reg. data: 0x%02X.Failed to halt target.PC value: 0x%X%X %s: Invalid read size.FM execution did not finish.Invalid data size.dsp568013NULL pointer not valid.Memory was not locked.dsp5680xxdsp5680xx_polldsp5680xx_arch_statedsp5680xx_stepdsp5680xx_read_bufferdsp5680xx_write_bufferdsp5680xx_init_targetdsp5680xx_f_lockdsp5680xx_f_unlockdsp5680xx_f_signaturecore_move_value_to_pcdsp5680xx_resumedsp5680xx_f_wrdsp5680xx_f_exset_fm_ck_diveonce_pc_storedsp5680xx_read_core_regdsp5680xx_irscanswitch_tapeonce_enter_debug_mode_without_reseteonce_enter_debug_modedsp5680xx_haltdsp5680xx_f_protect_checkdsp5680xx_write_32dsp5680xx_write_16jtag_data_readdsp5680xx_drscandsp5680xx_read_16_singledsp5680xx_readdsp5680xx_write_8dsp5680xx_writeF}D{cF FB@ F g@eFadebug_ctrlEmbeddedICE registersEmbedded ICE version %dsrc/target/embeddedice.cferoceondragoniteInvalid argumentsembeddedice handshake timeoutdebug_statuscomms_ctrlcomms_datawatch_0_addr_valuewatch_0_addr_maskwatch_0_data_valuewatch_0_data_maskwatch_0_control_valuewatch_0_control_maskwatch_1_addr_valuewatch_1_addr_maskwatch_1_data_valuewatch_1_data_maskwatch_1_control_valuewatch_1_control_maskEmbeddedICE v%d handling might be brokenunknown EmbeddedICE version (comms ctrl: 0x%8.8x)%s: hardware has %d breakpoint/watchpoint unit%serror queueing EmbeddedICE register readEmbeddedICE register read failed~BZ,Uembeddedice_handshakeembeddedice_write_regembeddedice_get_regembeddedice_set_reg_w_execembeddedice_build_reg_cacheetm_reg_add is requested to add non-existing registers, ETM config might be bogusETM: register 0x%02x not availabletarget '%s' is '%s'; not an ARMport_width option value ('%s') is not validunsupported ETM port width '%s'unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'unsupported ETM port clocking '%s', must be 'full' or 'half'trace capture driver '%s' not foundETM: current target isn't an ARMcurrent target doesn't have an ETM configuredtrace capture running, stop firstsize isn't a multiple of 4, no valid trace datanot enough memory to perform operationtrace capture wasn't enabled, no trace data capturedetm_ctx->image->base_address option value ('%s') is not validdbgrq option value ('%s') is not validabandoned branch encountered, correctness of analysis uncertain--- tracing enabled at 0x%8.8x ------ trace restarted after FIFO overflow at 0x%8.8x ------ exit from debug state at 0x%8.8x ------ periodic synchronization point at 0x%8.8x ---BUG: branch reason code 0x%x is reservedBUG: tracing of jazelle code not supportedTODO: add support for 64-bit valuesfurther analysis failed (corrupted trace data or just end of datano instruction for current address available, analysis abortedno image available for trace analysisBUG: can't write read--only register %sBUG: error scheduling etm register writecontext_id option value ('%s') is not validetmv1_cycle_accurate option value ('%s') is not validetmv1_branch_output option value ('%s') is not validcurrent tracemode configuration:data tracing: address and datacycle-accurate tracing enabledcycle-accurate tracing disabledfull branch address output enabledfull branch address output disabledBUG: can't read write-only register %sBUG: error scheduling etm register readpairs of address comparators: %icoprocessor and memory access %ssupportednumber of context comparators: %ihalf-rate clocking %ssupportedfull-rate clocking %ssupportednormal trace format %ssupportedmultiplex trace format %ssupporteddemultiplex trace format %ssupportedcurrent trace format %ssupportedetb selected as etm capture driver, but no ETB configuredETM capture driver initialization failed('none'|'data'|'address'|'all') context_id_bits ['enable'|'disable'] ['enable'|'disable']display info about the current target's ETMdisplay current target's ETM statusenable/disable debug entry on triggerload image from file with optional offsetdump captured trace data to fileload trace data for analysis Embedded Trace Macrocell command grouptarget port_width port_mode clocking capture_driversrc/target/etm.cdemultiplexedhalffulletmtrace capture not completedtriggersdoes not triggerETM: %s isn't an ARMETM: no ETM configured for %sETM: %s debug haltcycle (not executed)Trace is empty.--- trigger ---unknown errordata abortexception vector 0x%2.2xaddress: 0x%8.8xdata: 0x%8.8x (%i %s)%s (%u): 0x%8.8xinvalid option '%s'data tracing: nonedata tracing: data onlydata tracing: address onlycontextid tracing: nonecontextid tracing: 8 bitcontextid tracing: 16 bitcontextid tracing: 32 bit%s (%u) untraced-overflow start/stop, triggered, overflowed is runningetm: %s%s%s%s%s: idle%s: trace collection%s%s%s%i frames of trace data readnot ETM v%d.%ddata comparators: %imemory map decoders: %inumber of counters: %isequencer %spresentnumber of ext. inputs: %inumber of ext. outputs: %iFIFO full %spresentprotocol version: %itrace start/stop %spresentETM SYS CONFIG %08xIllegal max_port_sizemax. port size: %icurrent port size %ssupportedfetch comparisons %ssupportedFIFO full %ssupportedetm registersETMv2+ support is incompleteETM ID: %08xBad ETMv1 protocol %detbtracemodeconfigure/display trace modestart ETM trace collectionstop ETM trace collectiontrigger_debuganalyzeanalyze collected ETM trace [base address] [type]Set up ETM output port.ETM_external_output1ETM_external_output2ETM_external_output3ETM_external_output4ETM_sequencer_event0ETM_sequencer_event1ETM_sequencer_event2ETM_sequencer_event3ETM_sequencer_event4ETM_sequencer_event5ETM_sequencer_stateETM_counter_1_reload_valueETM_counter_1_enableETM_counter_1_reload_eventETM_counter_1_valueETM_counter_2_reload_valueETM_counter_2_enableETM_counter_2_reload_eventETM_counter_2_valueETM_counter_3_reload_valueETM_counter_3_enableETM_counter_3_reload_eventETM_counter_3_valueETM_counter_4_reload_valueETM_counter_4_enableETM_counter_4_reload_eventETM_counter_4_valueETM_data_1_comparator_valueETM_data_1_comparator_maskETM_data_2_comparator_valueETM_data_2_comparator_maskETM_data_3_comparator_valueETM_data_3_comparator_maskETM_data_4_comparator_valueETM_data_4_comparator_maskETM_data_5_comparator_valueETM_data_5_comparator_maskETM_data_6_comparator_valueETM_data_6_comparator_maskETM_data_7_comparator_valueETM_data_7_comparator_maskETM_data_8_comparator_valueETM_data_8_comparator_maskETM_addr_1_comparator_valueETM_addr_1_access_typeETM_addr_2_comparator_valueETM_addr_2_access_typeETM_addr_3_comparator_valueETM_addr_3_access_typeETM_addr_4_comparator_valueETM_addr_4_access_typeETM_addr_5_comparator_valueETM_addr_5_access_typeETM_addr_6_comparator_valueETM_addr_6_access_typeETM_addr_7_comparator_valueETM_addr_7_access_typeETM_addr_8_comparator_valueETM_addr_8_access_typeETM_addr_9_comparator_valueETM_addr_9_access_typeETM_addr_10_comparator_valueETM_addr_10_access_typeETM_addr_11_comparator_valueETM_addr_11_access_typeETM_addr_12_comparator_valueETM_addr_12_access_typeETM_addr_13_comparator_valueETM_addr_13_access_typeETM_addr_14_comparator_valueETM_addr_14_access_typeETM_addr_15_comparator_valueETM_addr_15_access_typeETM_addr_16_comparator_valueETM_addr_16_access_typeETM_fifofull_regionETM_fifofull_levelETM_ctrlETM_trig_eventETM_asic_ctrlETM_statusETM_sys_configETM_trace_resource_ctrlETM_trace_en_ctrl2ETM_trace_en_eventETM_trace_en_ctrl1ETM_viewdata_eventETM_viewdata_ctrl1ETM_viewdata_ctrl2ETM_viewdata_ctrl3ETM_sync_freqETM_config_code_extETM_ext_input_selectETM_trace_start_stopETM_behavior_controlETM_configETM_idxx(xxx8xxxxxxxxxxxxxxxxxxxxxhxxxxxxxxxxxxxxxHxxxxxxxxxxxxxxxXTDd(8X8HH(((handle_etm_info_commandetmv1_dataetm_read_instructionetmv1_analyze_traceis_armhandle_etm_config_commandetm_reg_lookuptarget_to_armetm_setupetm_write_regetm_set_regetm_set_reg_w_execetm_reg_addetm_read_reg_w_checketm_get_regetm_build_reg_cachesrc/target/etm_dummy.ctarget '%s' isn't an ARMetm_dummytarget has no ETM defined, ETM dummy left unconfiguredDummy ETM capture driver command groupis_armhandle_etm_dummy_config_command%s: there is no Thumb state on FA526src/target/fa526.cfa526fa526_change_to_armfa526_write_xpsrfa526_write_xpsr_im8fa526_branch_resume_thumbunexpected Feroceon EICE version signaturesrc/target/feroceon.cferoceon_assert_resetferoceon_write_xpsrferoceon_write_xpsr_im8feroceon_branch_resume_thumbferoceon_bulk_write_memoryferoceon_examine%s 0x%08x %u %usrc/target/hla_target.c%s %d 0x%08x %d %dhalted: PC: 0x%08xstm32_stlinkHardware srst not supported, falling back to software resetentered debug state in core mode: %s at PC 0x%08x, target->state: %sadapter_polladapter_haltadapter_resumeadapter_debug_entryadapter_stepadapter_assert_resetadapter_deassert_resetadapter_read_memoryadapter_write_memoryadapter_load_core_reg_u32adapter_store_core_reg_u32hl_dcc_readadapter_init_arch_infoadapter_target_createadapter_init_targetjsp7777jsp_portsrc/target/openrisc/jsp_server.cSpecify port on which to listen for incoming JSP telnet connections.-,,,8-8-8-8-jsp_inputjsp_connection_closedsrc/target/ls1_sap.cls1_sapWriting memory at physical address 0x%x; size %d; count %dReading memory at physical address 0x%x; size %d; count %dls1_sap_arch_statels1_sap_haltls1_sap_resumels1_sap_stepls1_sap_assert_resetls1_sap_deassert_resetls1_sap_read_memoryls1_sap_write_memoryls1_sap_init_targetsrc/target/mips_ejtag.cejtag_info->tap != NULLFailed to remove DCR MPbit!ejtag_ctrl: 0x%8.8xFailed to enter Debug Mode! MIPS64 noDMA DMA MIPS16 ASID_6 ASID_8 noIB IB noDB DB noPB PB ICACHE_COH ICACHE_NOT_COH DCACHE_COH DCACHE_NOT_COH COMPLEX_BREAK EADDR>32bit EADDR=32bit SDBBP_SPECIAL2 SDBBP DINT R3k R4kimpcode: 0x%8.8xEJTAG: Version 2.5 DetectedEJTAG: Version 2.6 DetectedEJTAG: Version 3.1 DetectedEJTAG: Version 4.1 DetectedEJTAG: Version 5.1 DetectedEJTAG v2.6: features:%s%sEJTAG: Version 1 or 2.0 DetectedEJTAG: Unknown Version DetectedEJTAG main: features:%s%s%s%s%sEJTAG v2.0: features:%s%s%s%s%s%s%s%sEJTAG v2.0: Break Channels: %uEJTAG: DMA Access Mode detected. Disabling to workaround current broken code.x@AB@B0?@@mips_ejtag_fastdata_scanejtag_v26_print_impejtag_v20_print_impejtag_main_print_impmips_ejtag_get_impcodemips_ejtag_initdisable_dcr_mpmips_ejtag_enter_debugmips_ejtag_drscan_8_outmips_ejtag_drscan_8mips_ejtag_drscan_8mips_ejtag_drscan_32_outmips_ejtag_drscan_32mips_ejtag_drscan_32mips_ejtag_add_scan_96mips_ejtag_get_idcodemips_ejtag_set_instrscan delay: %d nsecrunning in legacy moderunning in fast queued modetarget is not an MIPS_M4Kcp0 reg %i, select %i: %8.8xsrc/target/mips_m4k.cwp_num %i bp_value 0x%xbpid: %u - releasing hw: %dbpid: %uNo working area availableFastdata access Failedtarget stepped Reset Detectedmips_m4kmips_m4k command groupdisplay/modify cp0 registerscan_delayejtag_info->scan_delay option value ('%s') is not validcp0_reg option value ('%s') is not validcp0_sel option value ('%s') is not validcouldn't access cp0 reg %i, select %iCan not find free FP ComparatorOnly watchpoints of length 4 are supportedWatchpoints address should be word alignedInvalid FP Comparator number in breakpoint (bpid: %u)Can not find free FP Comparator(bpid: %u)bpid: %u, bp_num %i bp_value 0x%xUnable to set 32bit breakpoint at address %08x - check that memory is read/writableUnable to set 16bit breakpoint at address %08x - check that memory is read/writableaddress: 0x%8.8x, count: 0x%8.8xfast_data (0x%8.8x) is within write area (0x%8.8x-0x%8.8x).Change work-area-phys or load_image address!Falling back to non-bulk writeUsing MTAP reset to reset processor...Using EJTAG reset (PRRST) to reset processor...halt failed target->coreid: %dPIC32MX Detected - using EJTAG InterfaceInvalid FP Comparator number in watchpointno hardware watchpoints availableentered debug state at PC 0x%x, target->state: %sEJTAG_CTRL_BRKST already set during server startup.target->coreid :%d failed to resume at address :0x%xdisplay/set scan delay in nano seconds/mips_m4k_halt_smpmips_m4k_pollmips_m4k_haltmips_m4k_restore_smpmips_m4k_internal_restoremips_m4k_debug_entrymips_m4k_stepmips_m4k_assert_resetmips_m4k_deassert_resetmips_m4k_read_memorymips_m4k_bulk_write_memorymips_m4k_write_memorymips_m4k_set_breakpointmips_m4k_add_breakpointmips_m4k_unset_breakpointmips_m4k_remove_breakpointmips_m4k_set_watchpointmips_m4k_add_watchpointmips_m4k_unset_watchpointmips_m4k_remove_watchpointmips_m4k_examineAdd hardware BP %d at %08xsrc/target/nds32_v2.cMap PSW to IPSWMap PC to IPCMapping P0 to P_P0Mapping P1 to P_P1Mapping IPSW to P_IPSWMapping EVA to P_EVAMapping ITYPE to P_ITYPEMapping IPC to P_IPCMapping PC to O_IPCNot implemented: %snds32_edm_config(nds32)nds32_reset_halt(nds32)nds32_v2_leave_debug_statends32_restore_context(target)nds32_v2_debug_entrynds32_config(nds32)Remove hardware BP %d at %08xnds32 != NULLnds32_poll(target)nds32_v2<-- TARGET WARNING! Insert too many hardware breakpoints/watchpoints! The limit of combined hardware breakpoints/watchpoints is %d. -->%s: total hardware breakpoint %dAdd hardware watchpoint %d at %08x mask %08xnds32_v2_activate_hardware_breakpoint(nds32->target)nds32_v2_activate_hardware_watchpoint(nds32->target)<-- TARGET WARNING! Virtual hosting is not supported under V1/V2 architecture. -->nds32_v2_deactivate_hardware_breakpoint(nds32->target)Remove hardware watchpoint %d at %08x mask %08x<-- TARGET ERROR! Reaching the max interrupt stack level %u. -->nds32_v2_target_request_datands32_v2_deassert_resetnds32_v2_read_memorynds32_v2_write_memorynds32_v2_read_buffernds32_v2_write_buffernds32_v2_checksum_memorynds32_v2_add_breakpointnds32_v2_add_watchpointnds32_v2_run_algorithmnds32_v2_register_mappingnds32_reach_max_interrupt_levelnds32_v2_check_interrupt_stacknds32_v2_deactivate_hardware_watchpointnds32_v2_deactivate_hardware_breakpointnds32_v2_debug_entrynds32_v2_activate_hardware_watchpointnds32_v2_activate_hardware_breakpointnds32_v2_leave_debug_statetarget_to_aicends32_v2_examinetarget_to_nds32src/target/nds32_v3.cnds32_v3<-- TARGET WARNING! Insert too many hardware breakpoints/watchpoints! The limit of combined hardware breakpoints/watchpoints is %d. --><-- TARGET STATUS: Inserted number of hardware breakpoint: %d, hardware watchpoints: %d. --><-- TARGET WARNING! The number of watchpoints exceeds the hardware resources. Stop at every load/store instruction to check for watchpoint matches. -->nds32_v3_deassert_resetnds32_v3_add_breakpointnds32_v3_add_watchpointnds32_v3_examinends32_v3_check_interrupt_stacknds32_v3_activate_hardware_breakpointnds32_v3_activate_hardware_watchpointnds32_v3_deactivate_hardware_breakpointtarget_to_aicends32_v3_deactivate_hardware_watchpointnds32_v3_debug_entrysrc/target/nds32_v3_common.c./src/target/nds32.hnds32_v3_leave_debug_statev3_common_callback->deactivate_hardware_breakpoint(nds32->target)v3_common_callback->deactivate_hardware_watchpoint(nds32->target)v3_common_callback->activate_hardware_breakpoint(nds32->target)v3_common_callback->activate_hardware_watchpoint(nds32->target)nds32_v3_get_exception_addressPC: 0x%08x, access start: 0x%08x, end: 0x%08xv3_common_callback->activate_hardware_breakpoint(target)v3_common_callback->activate_hardware_watchpoint(target)nds32_v3_write_memorynds32_v3_read_memorynds32_v3_write_buffernds32_v3_read_buffernds32_v3_run_algorithmnds32_v3_debug_entrynds32_v3_leave_debug_statetarget_to_aicends32_v3_get_exception_addresstarget_to_nds32nds32_v3_checksum_memorynds32_v3_target_request_data<-- TARGET WARNING! Insert too many hardware watchpoints! The limit of hardware watchpoints is %d. --><-- TARGET STATUS: Inserted number of hardware watchpoint: %d. -->%s: total hardware breakpoint %d (simple breakpoint %d)%s: total hardware watchpoint %dsrc/target/nds32_v3m.cRemove hardware BP %u at %08xAdd hardware BP %u at %08xnds32_v3mnds32_v3m_deassert_resetnds32_v3m_add_breakpointnds32_v3m_add_watchpointnds32_v3m_examinends32_v3m_check_interrupt_stacknds32_v3m_activate_hardware_breakpointnds32_v3m_activate_hardware_watchpointnds32_v3m_deactivate_hardware_breakpointtarget_to_aicends32_v3m_deactivate_hardware_watchpointsrc/target/openrisc/or1k.cRead core reg %i value 0x%08xRead spr reg %i value 0x%08xCouldn't read the CPU stateTarget is haltedBad argumentsError while asserting RESETError while resuming targetError while reading NPCorg.gnu.gdb.or1k.group0dtlbw%dmr%dorg.gnu.gdb.or1k.group1dmmudtlbw%dtr%ditlbw%dmr%dorg.gnu.gdb.or1k.group2immuitlbw%dtr%d%s debug unit selectedTarget was already haltedImpossible to stall the CPUError while stalling the CPUNo debug unit selectedNo tap selectedOpenRISC 1000 registers%s tap selected%s unknown, no tap selectedError while restoring contextUnset breakpoint at 0x%08xTarget resumed at 0x%08x...attempt %d of %dError while calling or1k_haltor1kaddregtap_selectSelect the TAP core to usetap_select nametap_listDisplay available TAP coredu_selectdu_select namedu_listselect_tap nameppcnpccpucfgrdmmucfgrimmucfgrdccfgriccfgrdcfgrpccfgrepcr0epcr1epcr2epcr3epcr4epcr5epcr6epcr7epcr8epcr9epcr10epcr11epcr12epcr13epcr14epcr15eear0eear1eear2eear3eear4eear5eear6eear7eear8eear9eear10eear11eear12eear13eear14eear15esr0esr1esr2esr3esr4esr5esr6esr7esr8esr9esr10esr11esr12esr13esr14esr15dmmuucrdmmuuprdtlbeirdatbmr0datbmr1datbmr2datbmr3datbtr0datbtr1datbtr2datbtr3immucrimmupritlbeiriatbmr0iatbmr1iatbmr2iatbmr3iatbtr0iatbtr1iatbtr2iatbtr3dccrorg.gnu.gdb.or1k.group3dcbprdcbfrdcbirdcbwrdcblriccrorg.gnu.gdb.or1k.group4icbpricbiricblrmacloorg.gnu.gdb.or1k.group5machidvr0org.gnu.gdb.or1k.group6dvr1dvr2dvr3dvr4dvr5dvr6dvr7dcr0dcr1dcr2dcr3dcr4dcr5dcr6dcr7dmr1dmr2dcwr0dcwr1dsrdrrpccr0org.gnu.gdb.or1k.group7perfpccr1pccr2pccr3pccr4pccr5pccr6pccr7pcmr0pcmr1pcmr2pcmr3pcmr4pcmr5pcmr6pcmr7pmrorg.gnu.gdb.or1k.group8picmrorg.gnu.gdb.or1k.group9picpicsrttmrorg.gnu.gdb.or1k.group10ttcrError while reading spr 0x%08xRemoving breakpoint: addr 0x%08x, len %d, type %d, set: %d, id: %dHW breakpoints not supported for now. Doing SW breakpoint.Error while writing back the instruction at 0x%08xError while invalidating the ICACHEWrite memory at 0x%08x, size: %u, count: 0x%08xCan't handle unaligned memory accessRead memory at 0x%08x, size: %u, count: 0x%08xError while desasserting RESETStarting or1k profiling. Sampling npc as fast as we can...Error while calling or1k_save_contextoptions option value ('%s') is not validOption %x is passed to %s debug unit%s unknown, no debug unit selectedAdd reg "%s" @ 0x%08x, group "%s", feature "%s"Adding breakpoint: addr 0x%08x, len %d, type %d, set: %d, id: %dError while reading the instruction at 0x%08xError while writing OR1K_TRAP_INSTR at 0x%08xTarget was in unknown state when halt was requestedCan't request a halt while in reset if nSRST pulls nTRSTAddr: 0x%x, stepping: %s, handle breakpoints %s Write core reg %i value 0x%08xError while reading debug registersError while writing back debug registersError while unstalling the CPUTarget debug resumed at 0x%08xError while calling or1k_restore_contextError while writing spr 0x%08xDebug IF CPU control reg read failure.Resetting JTAG TAP state and reconnectiong to debug IF.Could not re-establish communication with targetError while calling or1k_is_cpu_runningError while calling or1k_debug_entryAdd a register to the register listaddreg name addr feature groupSelect the Debug Unit core to useDisplay available Debug Unit coreor1k_debug_entryor1k_is_cpu_runningor1k_pollor1k_haltis_any_soft_breakpointor1k_jtag_write_regsor1k_write_core_regor1k_restore_contextor1k_resume_or_stepor1k_assert_resetor1k_deassert_resetor1k_soft_reset_haltor1k_jtag_read_regsor1k_save_contextor1k_get_gdb_reg_listor1k_read_memoryor1k_write_memoryor1k_add_breakpointor1k_remove_breakpointor1k_add_watchpointor1k_remove_watchpointor1k_addreg_command_handleror1k_tap_select_command_handleror1k_du_select_command_handleror1k_create_reg_listor1k_examineor1k_read_core_regor1k_get_core_regor1k_set_core_regor1k_build_reg_cacheor1k_init_targetor1k_profilingIllegal debug chain selected (%i) while selecting control registersrc/target/openrisc/or1k_du_adv.cdst == src || dst + len <= src || src + len <= dstadv debug unit is configured with option ADBG_USE_HISPEEDadv debug unit is configured with option ENABLE_JSP_MULTIadv debug unit is configured with option ENABLE_JSP_SERVER ****************************** ** JTAG Serial Port ** ****************************** Error while calling adbg_select_ctrl_regIllegal debug chain selected (%i) while doing control readWrite control register %d: 0x%08xIllegal debug chain selected (%i) while doing control writeDoing burst read, word size %d, word count %d, start address 0x%08xTried burst read with invalid word size (%d),defaulting to 4-byte wordsIllegal debug chain selected (%i) while doing burst readCRC ERROR! Computed 0x%08x, read CRC 0x%08xWB bus error during burst read, address 0x%08x, retrying!Doing burst write, word size %d, word count %d,start address 0x%08lxTried WB burst write with invalid word size (%d),defaulting to 4-byte wordsTried CPU0 burst write with invalid word size (%d),defaulting to 4-byte wordsTried CPU1 burst write with invalid word size (%d),defaulting to 4-byte wordsIllegal debug chain selected (%i) while doing burst writeCRC ERROR! match bit after write is %i (computed CRC 0x%08x)WB bus error during burst write, address 0x%08x, retrying!Select module: %s./src/helper/types.hTAP initialization failedCouldn't start the JSP serverInit doneBurst read timed outBurst read failedCRC OK!Reading WB%d at 0x%08xCRC OK! Writing WB%d at 0x%08xlen % 4 == 0len % 2 == 0JSP transfertWISHBONECPU0CPU1JSPadvadbg_select_moduleor1k_adv_jtag_initadbg_wb_burst_reador1k_adv_jtag_read_memoryadbg_ctrl_writeadbg_select_ctrl_regadbg_ctrl_readadbg_wb_burst_writebuf_bswap16buf_bswap32or1k_adv_jtag_write_memoryor1k_adv_jtag_jsp_xferInitialising OpenCores JTAG TAPsrc/target/openrisc/or1k_tap_mohor.cor1k_tap_mohor_initmohorVirtual JTAGSignal TAPSerial Flash LoaderJTAG to avalon bridgem_width = %dmanufacturer_id = 0x%02xnb_of_node = %dversion = %dVIR length = %dNo VJTAG TAP instance found !Node info register--------------------instance_id = %dnode_id = %d (%s)vjtagInitialising Altera Virtual JTAG TAPsrc/target/openrisc/or1k_tap_vjtag.cSLD HUB Configuration register------------------------------or1k_tap_vjtag_initInitialising Xilinx Internal JTAG TAPsrc/target/openrisc/or1k_tap_xilinx_bscan.cor1k_tap_xilinx_bscan_initxilinx_bscan%s out of memorysrc/target/quark_d20xx.c%s core state update fail%s could not resume targetquark_d20xxquark_d20xx_reset_deassertquark_d20xx_target_createsrc/target/quark_x10xx.cquark_x10xxquark_x10xx_target_createjcJc%s fail for %ssrc/target/x86_32_common.creg %s value 0x%08xbp_num=%u%s error write EAX%s error write EDX%s invalid write mem size%s error on mem write%s could not disable paging%s could not enable paging%s invalid read mem size%s error read EDX%s error on mem read%s invalid read sizenum_regs=%d, reg_class=%dvalue %s = %08xaddr=0x%08x, size=%u, buf=%p%s error EDX write%s invalid read io size%s error on read EAX%s error on io read%s error on EDX write%s error on EAX write%s invalid write io size%s error on io writetype=%d, addr=0x%08x%s watchpoint already set%s no debug registers leftwatchpoint not setid %x%s current=0x%02x orig=0x%02xx86_32x86_32 target commandsiwwwrite I/O port wordport data[word]iwhwrite I/O port halfwordport data[halfword]iwbwrite I/O port byteport data[byte]idwdisplay I/O port wordidhdisplay I/O port halfwordidbdisplay I/O port byte%s dr7 error, not enabled, val=0x%08xaddr=0x%08x, size=%u, count=0x%x, buf=%p%s invalid params count=0x%x, buf=%p, addr=0x%08xaddr=0x%08x, bp_num=%u, bp_type=%u, pb_length=%u%s dr7 error, already enabled, val=%08x%s unsupported feature bp_type=%d%s couldn't read page directory pointer table entry at 0x%08x%s page directory pointer table entry at 0x%08x is not present%s couldn't read page directory entry at 0x%08x%s page directory entry at 0x%08x is not present%s couldn't read page table entry at 0x%08x%s page table entry at 0x%08x is not present%s failed to calculate physical address from 0x%08x%s failed to read memory from physical address 0x%08x%s failed to read memory from address 0%08x%s failed to write memory to physical address 0x%08x%s failed to write memory to address 0x%08x%s invalid params buf=%p, addr=%08x%s IA-32 I/O space is 2^16, 0x%08x exceeds max%s invalid params buf=%p, addr=0x%08xaddress=0x%08x, data_size=%u, b=0x%08x%s no support for 'read' watchpoints, use 'access' or 'write'%s only watchpoints of length 1, 2 or 4 are supported%s only 'access' or 'write' watchpoints are supported'%s' watchpoint %d set at 0x%08x with length %u (hwreg=%d)'%s' watchpoint %d removed from 0x%08x with length %u (hwreg=%d)%s no free hw breakpoint bpid=0x%x%s hardware breakpoint %u set at 0x%08x (hwreg=%u)%s error setting hardware breakpoint at 0x%08xset software breakpoint - orig byte=0x%02x%s software breakpoint error at 0x%08x, check memory%s readback=0x%02x orig=0x%02x%s software breakpoint %u set at 0x%08x%s error setting software breakpoint at 0x%08x%s core doesn't support SW breakpoints%s invalid breakpoint number=%d, bpid=%u%s hardware breakpoint %u removed from 0x%08x (hwreg=%d)%s error removing hardware breakpoint at 0x%08x%s software breakpoint remove error at 0x%08x, check memory%s software breakpoint %u removed from 0x%08x%s error removing software breakpoint at 0x%08xtarget_fill_iohandle_iod_commandunset_swbpunset_hwbpunset_breakpointx86_32_common_remove_breakpointset_swbpset_hwbpset_breakpointx86_32_common_add_breakpointunset_debug_regsunset_watchpointset_debug_regsset_watchpointx86_32_common_write_iox86_32_common_read_iox86_32_common_write_memoryx86_32_common_read_memorywrite_memwrite_phys_memx86_32_common_write_phys_memread_memread_phys_memcalcaddr_physfromlinx86_32_common_virt2physread_hw_reg_to_cachewrite_hw_reg_from_cachex86_32_common_init_arch_infox86_32_get_gdb_reg_listIt looks like the target may be running ChibiOS without ch_debug.Could not read CPACR register to check FPU stateFailed to determine exact stacking for the target type %sError reading stack frame from ChibiOS threadCould not allocate space for ChibiOS/RT memory signatureCould not read ChibiOS/RT memory signature from targetMemory signature identifier does not contain magic bytes.ChibiOS/RT memory signature claims to be smaller than expectedChibiOS/RT memory signature claims to be bigger than expected. Assuming compatibility...Successfully loaded memory map of ChibiOS/RT target running version %i.%i.%iChibiOS/RT target memory signature claims an addresswidth unequal to 32 bits!Reading the memory signature of ChibiOS/RT failedCould not read next ChibiOS threadChibiOS registry integrity check failed, NULL pointerChibiOS registry integrity check failed, double linked list violationOnly showing current execution because of a broken ChibiOS thread registry.Could not allocate space for thread detailsCould not read ChibiOS thread name pointer from targetError reading thread name from ChibiOS targetError reading thread state from ChibiOS targetCould not read current Thread from ChibiOS targetCould not find target "%s" in ChibiOS compatibility listsrc/rtos/ChibiOS.cEnabled FPU detected.No symbols for ChibiOSState: %srlistch_debugREADYSUSPENDEDWTSEMWTMTXWTCONDSLEEPINGWTEXITWTOREVTWTANDEVTSNDMSGQSNDMSGWTMSGWTQUEUEFINALChibiOS_detect_rtosChibiOS_createChibiOS_update_memory_signatureChibiOS_update_threadsChibiOS_update_stackingChibiOS_get_thread_reg_listCurrent ExecutiopxCurrentTCBsrc/rtos/FreeRTOS.cNo symbols for FreeRTOSpxReadyTasksListsxDelayedTaskList1xDelayedTaskList2pxDelayedTaskListpxOverflowDelayedTaskListxPendingReadyListxTasksWaitingTerminationxSuspendedTaskListuxCurrentNumberOfTasksuxTopUsedPriorityError reading stack frame from FreeRTOS threadFreeRTOS: Read stack pointer at 0x%lx, value 0x%lx Error reading stack frame from FreeRTOS thread Don't have the number of threads in FreeRTOSFreeRTOS: Read uxCurrentNumberOfTasks at 0x%lx, value %d Could not read FreeRTOS thread count from targetError reading current thread in FreeRTOS thread listFreeRTOS: Read pxCurrentTCB at 0x%lx, value 0x%lx Error allocating memory for %d threadsFreeRTOS: uxTopUsedPriority is not defined, consult the OpenOCD manual for a work-aroundFreeRTOS: Read uxTopUsedPriority at 0x%lx, value %ld FreeRTOS maximum used priority is unreasonably big, not proceeding: %ldError allocating memory for %ld prioritiesError reading number of threads in FreeRTOS thread listFreeRTOS: Read thread count for list %d at 0x%lx, value %ld Error reading first thread item location in FreeRTOS thread listFreeRTOS: Read first item for list %d at 0x%lx, value 0x%lx Error reading thread list item object in FreeRTOS thread listFreeRTOS: Read Thread ID at 0x%lx, value 0x%lx FreeRTOS: Read Thread Name at 0x%lx, value "%s" Error reading next thread item location in FreeRTOS thread listFreeRTOS: Read next thread location at 0x%lx, value 0x%lx Could not find target in FreeRTOS compatibility listFreeRTOS_createFreeRTOS_update_threadsFreeRTOS_get_thread_reg_list_tx_thread_current_ptr_tx_thread_created_ptr_tx_thread_created_countsrc/rtos/ThreadX.cnull stack pointer in thread solicited stack interrupt stack: %uUnknown stateNo symbols for ThreadXCompletedTerminatedSleepingWaiting - QueueWaiting - SemaphoreWaiting - Event flagWaiting - MemoryWaiting - I/OWaiting - FilesystemWaiting - NetworkWaiting - MutexError reading stack frame from ThreadX threadthread: 0x%lx, stack_ptr=0x%lxUnknown stacking info for thread id=0x%lxError reading stack data from ThreadX thread: stack_ptr=0x%lxDon't have the number of threads in ThreadXCould not read ThreadX thread count from targetCould not read ThreadX current thread from targetCould not read ThreadX thread location from targetCould not read ThreadX thread name pointer from targetError reading thread name from ThreadX targetError reading thread state from ThreadX targetError reading next thread pointer in ThreadX thread listCould not find target in ThreadX compatibility listget_stacking_info_arm926ejsThreadX_createThreadX_update_threadsThreadX_get_thread_reg_list     $ ( , 0 4 8 < @       $ (  Cyg_Thread::thread_listsrc/rtos/eCos.cNo symbols for eCosCountsleepCreatingExitedCyg_Scheduler_Base::current_threadError reading unique id from eCos threadError reading stack frame from eCos threadDon't have the thread list headCould not read eCos current thread from targetCould not read eCos thread id from targetCould not read eCos thread name pointer from targetError reading thread name from eCos targetError reading thread state from eCos targetError reading next thread pointer in eCos thread listCould not find target in eCos compatibility listeCos_createeCos_update_threadseCos_get_thread_reg_listRtos::sCurrentTaskRtos::sListReadyRtos::sListSleepRtos::sListSuspendedRtos::sMaxPrioritiesRtos::sCurrentTaskCountsrc/rtos/embKernel.cNoName:[0x%08X]State: Running, Priority: %uState: %s, Priority: %uNo symbols for embKernelFound %u tasks Error reading stack frame from embKernel threadGetting task details: iterable=0x%08X, task=0x%08X, name=%s Error reading current thread in embKernel thread listCould not read embKernel thread count from targetCould not find target "%s" in embKernel compatibility listembKernel_createembKernel_get_tasks_detailsembKernel_update_threadsembKernel_get_thread_reg_listshould no be calledsrc/rtos/linux.cinit_tasklinux os creation unaligned address %x!!no init symbol unable to read piddel task %ldmore than %d threads !!threadid count %d%d %d %x %s thread not foundHc%16lxno current thread identifiedthreads_needs_update = 1linux awareness : address in user spacefill_task: unable to read memoryfill task: unable to read memoryfill task: unable to read memory -- ASIDget_name: unable to read memory error in linux current thread updatecpu_context: unable to read memorycpu_context: cannot read at thread_info_addrcpu_context : thread_info_addr in userspace!!!cpu_context: unable to read memory current thread %lx: no target to perform access of core id %xnext task: unable to read memoryupdate thread done %ld, mean%ld complete time %ld, thread mean %ld allocation for %d threads linereceived thread request without init task addressgdb requested status on non existing threadname of unidentified thread %sCannot compute linux virt2phys translationWARNING! current GDB thread do not matchcurrent thread running.Switch thread in GDB to threadid %d311111111211211111111111111(2111111111111121(2linux_gdb_h_packetlinux_gdb_T_packetlinux_thread_extra_infolinux_gdb_thread_packetlinux_get_tasksliste_del_tasknext_taskcpu_context_readget_currentget_namefill_tasklinux_os_detectlinux_compute_virt2physlinux_thread_packetlinux_os_createlinux_os_thread_reg_listlinux_os_thread_reg_listlinux_identify_current_threadslinux_task_updatelinux_ps_commandlinux_read_memoryfill_bufferPID CPU ASID --- --- ---- linux_ps_command_mqx_kernel_dataMQX_init_structsrc/rtos/mqx.ckernel_data->ACTIVE_PTRkernel_data->TD_LIST.SIZEtd_struct_ptr->NEXTtd_struct_ptr->TASK_IDtask->STACK_PTRtd_struct_ptr->STATEmqxRCV_SPECIFIC_BLOCKEDRCV_ANY_BLOCKEDDYINGUNHANDLED_INT_BLOCKEDSEND_BLOCKEDBREAKPOINT_BLOCKEDIO_BLOCKEDMUTEX_BLOCKEDTASK_QUEUE_BLOCKEDLWSEM_BLOCKEDLWEVENT_BLOCKEDMQX RTOS - unknown architecture %sMQX RTOS - target address 0x%x is not allowed to readMQX RTOS - reading target address 0x%x failedMQX RTOS - cannot read "%s" at address 0x%xkernel_data->ADDRESSING_CAPABILITYMQX RTOS - value of '_mqx_kernel_data->ADDRESSING_CAPABILITY' contains invalid valueMQX RTOS - scheduler does not runMQX RTOS - invalid threadid: 0x%XMQX_RTOS - threadid %ld does not match any tasktd_struct_ptr->TEMPLATE_LIST_PTRtd_struct_ptr->TEMPLATE_LIST_PTR->NAME*td_struct_ptr->TEMPLATE_LIST_PTR->NAMEtd_struct_ptr->TASK_ERROR_CODEState: %s, Address: 0x%x, Error Code: %uMQX RTOS - could not find target "%s" in MQX compatibility listmqx_createmqx_valid_address_checkmqx_target_read_buffermqx_get_membermqx_is_scheduler_runningmqx_get_thread_reg_list @ D H L P T X \ `           $ ( , 0 4 8 < @ $ ( , 0       4 8 < @ , 0 4 8      $ < ( D H XPSR(0x%08x) indicated stack alignment was necessary src/rtos/rtos_standard_stackings.crtos_Cortex_M_stack_align    $ ( , 0 4 8 < @ D H L P T X \ ` d h l p t x |         $ ( , 0 4 8 < @ ````````  d h l p       t x | $ ( , 0       4 8 < @ $ ( ,       0 4 8 < $ ( ,       0 4 8 < src/jtag/hla/hla_tcl.cjim_hl_newtap_cmdinvalid inteface %dsrc/jtag/drivers/versaloon/usbtoxxx/usbtogpio.cusbtogpio_outusbtogpio_inusbtogpio_configsrc/jtag/drivers/versaloon/usbtoxxx/usbtojtagraw.cusbtojtagraw_executeusbtojtagraw_configsrc/jtag/drivers/versaloon/usbtoxxx/usbtopwr.cusbtopwr_outputusbtopwr_configsrc/jtag/drivers/versaloon/usbtoxxx/usbtoswd.cusbtoswd_transactusbtoswd_seqinusbtoswd_seqoutusbtoswd_configusbtoxxx_bufferUSB_TO_POLLInvalid usage of %svalidate previous commands%s is not supported by %s.current donglelength of return dataInvalid %sUSB_TO_POLL toooooo longcheck poll nestingusbtousartusbtospiusbtoi2cusbtogpiousbtocanusbtopwmusbtoadcusbtodacusbtomicrowireusbtoswimusbtodusin/ausbtopowerusbtodelayusbtojtagllusbtojtaghlusbtoisspusbtoc2usbtosbwusbtolpcicpusbtoswdusbtojtagrawusbtobdmusbtomsp430jtagusbtopollusbtoallsrc/jtag/drivers/versaloon/usbtoxxx/usbtoxxx.c%s command 0x%02x failed with 0x%02x%s command 0x%02x process errorUSB_TO_XXX abilities: 0x%08X:0x%08X:0x%08Xusbtodelay_delayusbtopoll_verifybuffusbtopoll_checkfailusbtopoll_checkokusbtopoll_endusbtopoll_startusbtoinfo_get_abilitiesusbtoxxx_add_commandusbtoxxx_ensure_buffer_sizeusbtoxxx_initusbtoxxx_execute_commandusbtoxxx_validate_current_command_typeaduc702x_protect_check not implemented yet.aduc702x_protect not implemented yet.failed to erase sector at address 0x%08lXerased sector at address 0x%08lXwrite block must be multiple of two bytes in offset & lengtherror executing aduc702x flash write algorithmaduc702x detected error writing flashsingle write failed for address 0x%08lXwrote %d bytes at address 0x%08lXperforming mass erase.src/flash/nor/aduc702x.cmass erase successful.slow write failedaduc702xaduc702x_eraseaduc702x_write_singlePP`!PP`0 Q aduc702x_write_blockaduc702x_writeaducm360_protect_check not implemented.aducm360_protect not implemented.'aducm360_write_block_sync' requested, dst:0x%08x, count:0x%08xbytes.write block must be multiple of four bytes in offset & lengthcouldn't allocate a buffer space of 0x%08xbytes in the target's SRAM.error executing aducm360 flash write algorithmaducm360 fast sync algorithm reports an error (%02X)performing slow write (offset=0x%08x, count=0x%08x)...src/flash/nor/aducm360.cmass erase failed.page erase failed at 0x%08xaducm360aducm360_page_eraseaducm360_mass_eraseaducm360_protectaducm360_write_modifiedMG/hh`/?Q{B@ :oh'OO(@P 0aducm360_write_block_syncaducm360_writeaducm360_protect_checkstatus(%d):%s src/flash/nor/ambiqmicro.cstate = %d%s:%d:%s(): status(0x%x) Flash not happy: status(0x%x)Target not probedMass erase on bank %d.error setting bootloader bit.%d pages erased!ambiqmicro page erase failedNot yet implementedTarget already probedPart number: 0x%xFlashing main arrayaddress = 0x%08xMain array flashederror clearing bootloader bitoffset=0x%08x count=%dCount must be < 256Programming OTP finished.error check logProgramming OTP offset 0x%08xambiqmicro mass erase failedambiqmicroErase entire devicepage_eraseErase device pages program_otp ApolloApollo2error executing ambiqmicro commandTarget not halted or running %derror clearing bootloader bit.error writing target SRAM parameters.error executing ambiqmicro flash mass erase.error executing flash page eraseErasing pages %d to %d on bank %dambiqmicro page erase complete Ambiq Micro information: Chip is class %d (%s) %s status(0x%x):Could not read PartNum. Unknown Class. Using Apollo-64 as default.num_pages: %d, pagesize: %d, flash: %d, sram: %dwrite block must be multiple of 4 bytes in offset & lengtherror executing ambiqmicro flash write algorithmerror setting target SRAM parameters.error executing ambiqmicro otp program algorithmambiqmicro mass erase completeambiqmicro flash command groupSupport for Ambiq Micro parts.Program OTP (assumes you have already written array starting at 0x10000010)ambiqmicro_otp_programambiqmicro_handle_program_otp_commandambiqmicro_mass_eraseambiqmicro_eraseambiqmicro_protectcheck_flash_statusambiqmicro_exec_commandambiqmicro_write_blockambiqmicro_writeambiqmicro_read_part_infoambiqmicro_probeambiqmicro_protect_checkget_ambiqmicro_info %s: no %d byte buffersrc/flash/nand/arm_io.cerror executing hosted NAND writeerror executing hosted NAND readarm_nandread00 Rp x;:arm_code_to_working_areaarm_nandwrite00 Rp ;p:CKGR_MORStart: %ssrc/flash/nor/at91sam3.c%*s: [0x%08x] -> 0x%08xEnd: %s rc-osc: %3.03f MHz mainosc: %3.03f MHz plla: %3.03f MHz cpu-freq: %3.03f MHzmclk-freq: %3.03f MHzNO RAM!No current target?No SAM3 chips exist?Cannot find SAM3 chip?Slowclk freq: %d.%03dkhzHere %*s: %*u [0x%0*x] YESNOMAINFRDY(main ready: %s)MAINFexternal xtalinternal RCMOSCXTEN(main xtal enabled: %s)MOSCXTBY(main osc bypass: %s)MOSCRCENMOSCXTSTMOSCSEL(mainosc source: %s)CFDEN(clock failure enabled: %s)(onchip RC-OSC enabled: %s)MOSCRCF(onchip RC-OSC freq: %s)AT91SAM9XExx SeriesAT91SAM9xx SeriesVersionEPROCNVPSIZENVPSIZE2SRAMSIZEARCHNVPTYPEXTID(exists: %s)DIVAMULA PLLA Freq: %3.03f MHzslowclkmainoscpllaupllclock/6selected clockclock/4clock/8clock/16clock/32clock/64clock/2CSS%s (%3.03f Mhz)PRES Result CPU Freq: %3.03fResult: 0x%08xUnknown command %dCommand: 0x%08xError Write failedCommand timeoutBeginno private for this bank?Failed: %dCKGR_MCFRat91sam3u2eBegin: Bank: %d, Noise: %dInvalid/unknown bank numberINVALID SAM3 REGISTEREndNo memory!Bank = %d, nbanks = %dSam3Info, Failed %dEnd: r=%dHere,r=%dGPNVM only works with Bank0sam3 - target not haltedshowsam3-gpnvm%u: %usam3-gpnvm invalid GPNVM: %uMissing GPNVM numberclrUnknown command: %sFlash Mode: 0x%08xOffset: 0x%08x, Count: 0x%08xPage start: %d, Page End: %dSpecial case, all in one pageNot-Aligned startDone!at91sam3at91sam3 flash command groupgpnvm[('clr'|'set'|'show') bitnum][clock_hz]CKGR_PLLARCKGR_UCKRPMC_FSMRPMC_FSPRPMC_IMRPMC_MCKRPMC_PCK0PMC_PCK1PMC_PCK2PMC_PCSRPMC_SCSRPMC_SRCHIPID_CIDRCHIPID_CIDR2CHIPID_EXIDCHIPID_EXID24 MHz8 MHz12 MHzreservedromless or onchip flashembedded flash memorysram emulating flashAT91x34 SeriesCAP7 SeriesCAP9 SeriesCAP11 SeriesAT91x40 SeriesAT91x42 SeriesAT91x55 SeriesAT91SAM7Axx SeriesAT91SAM7AQxx SeriesAT91x63 SeriesAT91SAM7Sxx SeriesAT91SAM7XCxx SeriesAT91SAM7SExx SeriesAT91SAM7Lxx SeriesAT91SAM7Xxx SeriesAT91SAM7SLxx SeriesAT91x92 SeriesATSAM5AAT75Cxx Series48K Bytes1K Bytes112K Bytes80K Bytes160K Bytes16K Bytes32K Bytes64K Bytes128K Bytes256K Bytes96K Bytes512K Bytes16K bytes32K bytes64K bytes128K bytes256K bytes512K bytes1024K bytes2048K bytesarm946esat91sam3u4eat91sam3u1eat91sam3u4cat91sam3u2cat91sam3u1cat91sam3s4cat91sam3s4bat91sam3s4aat91sam3s2cat91sam3s2bat91sam3sd8aat91sam3sd8bat91sam3sd8cat91sam3s2aat91sam3s1cat91sam3s1bat91sam3s1aat91sam3s8aat91sam3s8bat91sam3s8cat91sam3n4cat91sam3n4bat91sam3n4aat91sam3n2cat91sam3n2bat91sam3n2aat91sam3n1cat91sam3n1bat91sam3n1aat91sam3n0bat91sam3n0aat91sam3n00bat91sam3n00aat91sam3a8cat91sam3a4cat91sam3x8h - ESat91sam3x8hat91sam3x8eat91sam3x8cat91sam3x4eat91sam3x4c UniqueId: 0x%08x 0x%08x 0x%08x 0x%08xAddress 0x%08x invalid bank address (try 0x%08x or 0x%08x [at91sam3u series] or 0x%08x [at91sam3s series] or 0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )SAM3: Flash program failed to read page phys address: 0x%08xv option value ('%s') is not validAbsurd/illegal slow clock freq: %d Target: not supported/not probedsam3 - supports auto-erase, erase_check ignored(%3.03f Mhz (%u.%03ukhz slowclk)(startup clks, time= %f uSecs) PLLA Freq: (Disabled,mula = 0) PLLA Freq: (Disabled,diva = 0)upll (*ERROR* UPLL is disabled)Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)*BUG*: Embedded flash has only %u pages*BUG*: Embedded flash has only %d GPNVMsArgument is meaningless for cmd: %dflash controller(%d) is not ready! ErrorFlash controller(%d) is not ready, attempting resetCannot read SAM3 register: %s @ 0x%08x, Err: %dEnd: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08xSAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)SAM3 CHIPID_CIDR: 0x%08x decodes as followsCannot read SAM3 register: %s @ 0x%08x, Error: %dPlease define bank %d via command: flash bank %s ... sam3 auto-erases while programming (request ignored)Invalid GPNVM %d, max: %d, ignoredBank0 must be defined first via: flash bank %s ...v32 option value ('%s') is not validError Read failed: read flash mode registerError Write failed: set flash mode registerWr Page %u @ phys address: 0x%08xSAM3: Failed to write (buffer) page at phys address 0x%08xSAM3: Error performing Erase & Write page @ phys address 0x%08xSAM3: Page @ Phys address 0x%08x is lockedSAM3: Flash Command error @phys address 0x%08xFlash write error - past end of bank offset: 0x%08x, count 0x%08x, BankEnd: 0x%08xNo memory for %d Byte page bufferoffset % pPrivate->page_size == 0Full Page Loop: cur=%d, end=%d, count = 0x%08xTerminal partial page, count = 0x%08xWithout arguments, shows all bits in the gpnvm register. Otherwise, clears, sets, or shows one General Purpose Non-Volatile Memory (gpnvm) bit.Print information about the current at91sam3 chipand its flash configuration.Display or set the slowclock frequency (default 32768 Hz).rom(nvpsiz) + embedded flash (nvpsiz2)ATSAM3UxC Series (100-pin version)ATSAM3UxE Series (144-pin version)ATSAM3AxC Series (100-pin version)ATSAM3XxC Series (100-pin version)ATSAM3XxE Series (144-pin version)ATSAM3XxG Series (208/217-pin version)ATSAM3SxA Series (48-pin version)ATSAM3SxB Series (64-pin version)ATSAM3SxC Series (100-pin version)ATSAM3NxA Series (48-pin version)ATSAM3NxB Series (64-pin version)ATSAM3NxC Series (100-pin version)ATSAM3SDxA Series (48-pin version)ATSAM3SDxB Series (64-pin version)ATSAM3SDxC Series (100-pin version)lll0lHl`lPkkFLASHD_ClrGPNVMFLASHD_SetGPNVMFLASHD_GetGPNVMsam3_handle_gpnvm_commandsam3_handle_info_commandsam3_flash_bank_commandFLASHD_EraseEntireBanksam3_erasesam3_protectsam3_page_writesam3_page_readsam3_writesam3_writesam3_erase_checkEFC_GetResultFLASHD_GetLockBitssam3_protect_checkEFC_PerformCommandEFC_GetStatusEFC_StartCommandFLASHD_ReadUniqueIDsam3_GetDetailssam3_GetInfosam3_GetRegsam3_ReadThisRegsam3_explain_ckgr_morsam3_explain_ckgr_mcfrsam3_explain_ckgr_pllasam3_explain_mckrsam3_reg_fieldnamesam3_explain_chipid_cidrsam3_ReadAllRegs_sam3_probeunknown~@src/flash/nor/at91sam4.cNo SAM4 chips exist?Cannot find SAM4 chip? %*s: %*d [0x%0*x] at91sam4c32cINVALID SAM4 REGISTERSam4Info, Failed %dsam4 - target not haltedsam4-gpnvm%u: %usam4-gpnvm invalid GPNVM: %uErasing sector: 0x%08xat91sam4at91sam4 flash command groupATSAM4ESAMG51 SeriesSAMG53 SeriesSAM4CxxC (100-pin version)SAM4CxxE (144-pin version)160K bytesCortex-M7Cortex-A5Cortex-M4at91sam4c32eat91sam4c16cat91sam4c8cat91sam4c4cat91sam4e16eat91sam4n8aat91sam4n8bat91sam4n8cat91sam4n16bat91sam4n16cat91sam4s16cat91sam4s16bat91sam4sa16bat91sam4s16aat91sam4s8cat91sam4s8bat91sam4s8aat91sam4s4cat91sam4s4bat91sam4s4aat91sam4s2cat91sam4s2bat91sam4s2aat91sam4sd32cat91sam4sd32bat91sam4sd16cat91sam4sd16bat91sam4sa16cat91samg53n19Address 0x%08x invalid bank address (try 0x%08x[at91sam4s series] )SAM4: Flash program failed to read page phys address: 0x%08xCannot read SAM4 register: %s @ 0x%08x, Err: %dSAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)SAM4 CHIPID_CIDR: 0x%08x decodes as followsCannot read SAM4 register: %s @ 0x%08x, Error: %dSAM4: Failed to write (buffer) page at phys address 0x%08xSAM4: Error performing Write page @ phys address 0x%08xSAM4: Page @ Phys address 0x%08x is lockedSAM4: Flash Command error @phys address 0x%08xsam4 does not auto-erase while programming (Erasing relevant sectors)sam4 First: 0x%08x Last: 0x%08xSAM4: Error performing Erase page @ lock region number %dSAM4: Lock Region %d is lockedSAM4: Flash Command error @lock region %dPrint information about the current at91sam4 chipand its flash configuration.ATSAM3A/SAM4A xC Series (100-pin version)ATSAM3X/SAM4X xC Series (100-pin version)ATSAM3X/SAM4X xE Series (144-pin version)ATSAM3X/SAM4X xG Series (208/217-pin version)ATSAM3S/SAM4S xA Series (48-pin version)ATSAM3S/SAM4S xB Series (64-pin version)ATSAM3S/SAM4S xC Series (100-pin version)`xHFLASHD_ClrGPNVMFLASHD_SetGPNVMFLASHD_GetGPNVMsam4_handle_gpnvm_commandsam4_handle_info_commandsam4_flash_bank_commandFLASHD_ErasePagesFLASHD_EraseEntireBanksam4_erasesam4_protectsam4_page_writesam4_page_readsam4_writesam4_writeEFC_GetResultFLASHD_GetLockBitssam4_protect_checkEFC_PerformCommandEFC_GetStatusEFC_StartCommandFLASHD_ReadUniqueIDsam4_GetDetailssam4_GetInfosam4_GetRegsam4_ReadThisRegsam4_explain_ckgr_morsam4_explain_ckgr_mcfrsam4_explain_ckgr_pllasam4_explain_mckrsam4_reg_fieldnamesam4_explain_chipid_cidrsam4_ReadAllRegs_sam4_probeunknownCouldn't read chip IDsrc/flash/nor/at91sam4l.cchip->page_size%s got error status 0x%08xsam4l_write_page address=%08x%s: can't clear page buffer%s: %dErasing the whole chipErase All failedErasing page %d failedQuick page read %u failedCouldn't read erase statusPage %d was not erased.at91sam4lat91sam4l flash command groupsmap_reset_deassertATSAM4LC8CATSAM4LC4CATSAM4LC2CATSAM4LC8BATSAM4LC4BATSAM4LC2BATSAM4LC8AATSAM4LC4AATSAM4LC2AATSAM4LS8CATSAM4LS4CATSAM4LS2CATSAM4LS8BATSAM4LS4BATSAM4LS2BATSAM4LS8AATSAM4LS4AATSAM4LS2ACouldn't read extended chip IDUnknown flash size (chip ID is %08x), assuming 128KCouldn't read Flash parametersSAM4L MCU: %s (Rev %c) (%uKB Flash with %d %dB pages, %uKB RAM)Address 0x%08x invalid bank address (try 0x%08x[at91sam4l series] )Protect range %d - %d not valid (%d sectors total)Can't %slock region containing page %dErase range %d - %d not valid (%d sectors total)Erasing sectors %d through %d... sam4l_write_page_partial address=%08x nb=%08xpage_offset + nb < chip->page_size(address % chip->page_size) == 0sam4l_write offset=%08x count=%08xdeasert internal reset held by SMAPsam4l_flash_bank_commandsam4l_check_page_erasedsam4l_erasesam4l_protectsam4l_write_page_partialsam4l_write_page_partialsam4l_flash_commandsam4l_write_pagesam4l_writesam4l_probesam4l_probesam4l_protect_check @0P @` at91sam7 driver information: Chip is %s Cidr: 0x%8.8x | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | Flashsize: 0x%8.8x Master clock (estimated): %u KHz | External clock: %u KHz Pagesize: %i bytes | Lockbits(%i): %i 0x%4.4x | Pages in lock region: %i Securitybit: %i | Nvmbits(%i): %i 0x%1.1x chip_width option value ('%s') is not validbus_width option value ('%s') is not validbanks_num option value ('%s') is not validnum_sectors option value ('%s') is not validpages_per_sector option value ('%s') is not validpage_size option value ('%s') is not validnum_nvmbits option value ('%s') is not validCannot identify target as an AT91SAMTarget autodetection failed! Please specify target parameters in configuration filenvptyp: 0x%3.3x, arch: 0x%4.4xLock Error Bit Detected, Operation AbortInvalid command and/or bad keyword, Operation AbortSecurity Bit Set, Operation AbortFlash command: 0x%x, flash bank: %i, page number: %ufirst_page: %i, last_page: %i, count %iWrite flash bank:%i page number:%inot an at91sam7 flash bank '%s'target has to be halted to perform flash operationbit option value ('%s') is not validgpnvm bit '#%s' is out of bounds for target %sat91sam7_handle_gpnvm_command: cmd 0x%x, value %d, status 0x%xset or clear one General Purpose Non-Volatile Memory (gpnvm) bitsrc/flash/nor/at91sam7.cfmcn[%i]: %isam7_probedAT91SAM7S128AT91SAM7S256AT91SAM7A3AT91SAM7S512AT91SAM7XC512AT91SAM7XC256AT91SAM7XC128AT91SAM7X256AT91SAM7X128AT91SAM7S64AT91SAM7S161/16AT91SAM7SE32AT91SAM7X512AT91SAM7SE128AT91SAM7S321/32AT91SAM7SE256AT91SAM7SE512status[%i]: 0x%xstatus register: 0x%xat91sam7gpnvm at91sam7 flash command groupbitnum ('set'|'clear')ARM946-EARM7TDMIARM920TARM926EJ-SIat91sam7_handle_gpnvm_commandat91sam7_eraseat91sam7_protectat91sam7_wait_status_busyat91sam7_flash_commandat91sam7_writeat91sam7_read_part_infoat91sam7_probeat91sam7_set_flash_modeat91sam7_erase_checkat91sam7_protect_checkhxdt`pAT91SAM9 NAND Device Commandsrc/flash/nand/at91sam9.cinvalid NAND chip address: %snand readyread blockwrite blockread datawrite dataError detected!Error in ECC bytes detectedat91sam9bank_id address_linerdy_busybank_id pio_base_addr pin_numparameters: %s target chip_addrchip option value ('%s') is not validecc option value ('%s') is not validinvalid ECC controller address: %sunable to allocate space for controller private datainvalid nand device number: %sbase_pioc option value ('%s') is not validpin_num option value ('%s') is not validaddress_line option value ('%s') is not validTarget must be halted to use NAND controller (%s)Unable to allocate space for OOBECC controller address must be set when not reading raw NAND dataMultiple errors encountered; unrecoverable!Data word %d, bit %d corrected.incorrect number of arguments for 'at91sam9 cle' commandUnable to write OOB data to NANDAT91SAM9 NAND flash controller commandsset command latch enable address line (default is 22)set address latch enable address line (default is 21)set the GPIO input pin connected to the RDY/~BUSY signal (no default)set the GPIO output pin connected to the chip enable signal (no default)at91sam9_nand_device_commandat91sam9_write_pageat91sam9_oob_initat91sam9_ecc_initat91sam9_read_pageat91sam9_haltedAddress 0x%08x invalid bank address (try 0x%08x[at91samd series] )Can't clear NVM error conditionsCouldn't read NVM Parameters registerCouldn't read Device ID registerCouldn't determine Flash page sizeSAMD: bank size doesn't match NVM parameters. Identified %uKB Flash but NVMCTRL reports %u %uB pagesSAMD MCU: %s (%uKB Flash, %uKB RAM)Couldn't find part corresponding to DID %08xpg_offset + 4 * nw <= chip->page_size%s: write failed at address 0x%08xsupply the "enable" argument to proceed.chip secured on next power-cycleFailed to erase row containing %08xSAMD: failed to erase sector %d. That sector is write-protectedSAMD: failed to erase sector %dCan't modify bits in the requested rangepage_size > 0 && page_size <= SAMD_PAGE_SIZE_MAXCan't modify bits outside the User Row page rangeSAMD: protect settings were not made persistent!Bootloader size is %u bytes (%u rows)Invalid bootloader size. Please see datasheet for a list valid sizes.Invalid EEPROM size. Please see datasheet for a list valid sizes.deasert internal reset held by DSUPrint information about the current at91samd chipand its flash configuration.Erase the entire Flash by using the ChipErase feature in the Device Service Unit (DSU).Secure the chip's Flash by setting the Security Bit.This makes it impossible to read the Flash contents.The only way to undo this is to issue the chip-erasecommand.Show or set the EEPROM size setting, stored in the User Row.Please see Table 20-3 of the SAMD20 datasheet for allowed values.Changes are stored immediately but take affect after the MCU isreset.Show or set the bootloader size, stored in the User Row.Please see Table 20-2 of the SAMD20 datasheet for allowed values.Changes are stored immediately but take affect after the MCU isreset.src/flash/nor/at91samd.cCan't read NVM statusSAMD: NVM ErrorSAMD: NVM lock errorSAMD: NVM programming errorchip erasedpg_offset % 4 == 0nb % 4 == 0failed to secure chipCouldn't erase user rowEEPROM is disabledEEPROM size is %u bytesat91samdat91samd flash command groupdsu_reset_deassertchip-eraseset-securityeeprom[size_in_bytes]bootloaderSAMC21J18ASAMC21J17ASAMC21J16ASAMC21J15ASAMC21G18ASAMC21G17ASAMC21G16ASAMC21G15ASAMC21E18ASAMC21E17ASAMC21E16ASAMC21E15ASAMC20J18ASAMC20J17ASAMC20J16ASAMC20J15ASAMC20G18ASAMC20G17ASAMC20G16ASAMC20G15ASAMC20E18ASAMC20E17ASAMC20E16ASAMC20E15ASAML22N18ASAML22N17ASAML22N16ASAML22J18ASAML22J17ASAML22J16ASAML22G18ASAML22G17ASAML22G16ASAML21J18ASAML21J17ASAML21J16ASAML21G18ASAML21G17ASAML21G16ASAML21E18ASAML21E17ASAML21E16ASAML21E15ASAML21J18BSAML21J17BSAML21J16BSAML21G18BSAML21G17BSAML21G16BSAML21E18BSAML21E17BSAML21E16BSAML21E15BSAMR21G18ASAMR21G17ASAMR21G16ASAMR21E18ASAMR21E17ASAMR21E16ASAMD21J18ASAMD21J17ASAMD21J16ASAMD21J15ASAMD21J14ASAMD21G18ASAMD21G17ASAMD21G16ASAMD21G15ASAMD21G14ASAMD21E18ASAMD21E17ASAMD21E16ASAMD21E15ASAMD21E14ASAMD21J16BSAMD21J15BSAMD21G16BSAMD21G15BSAMD21E16BSAMD21E15BSAMD20J18ASAMD20J17ASAMD20J16ASAMD20J15ASAMD20J14ASAMD20G18ASAMD20G17ASAMD20G16ASAMD20G15ASAMD20G14ASAMD20E18ASAMD20E17ASAMD20E16ASAMD20E15ASAMD20E14ASAMD11D14AMUSAMD11D13AMUSAMD11D12AMUSAMD11D14ASUSAMD11D13ASUSAMD11D12ASUSAMD11C14ASAMD11C13ASAMD11C12ASAMD10D14AMUSAMD10D13AMUSAMD10D12AMUSAMD10D14ASUSAMD10D13ASUSAMD10D12ASUSAMD10C14ASAMD10C13ASAMD10C12ASAMD09D14ASAMD09C13Asamd_handle_set_security_commandsamd_handle_eeprom_commandsamd_handle_bootloader_commandsamd_flash_bank_commandsamd_erasesamd_erase_rowsamd_modify_user_rowsamd_modify_user_rowsamd_protectsamd_check_errorsamd_issue_nvmctrl_commandsamd_writesamd_writesamd_get_flash_page_infosamd_probeflash bank commandsrc/flash/nor/atsamv.cflash controller is not readyerasing lock regions %d-%d...erasing lock region %dlock region %d is lockedpage at 0x%08x is lockedflash command error at 0x%08xinvalid gpnvm %d, max: %dsamv_get_gpnvm failedsamv-gpnvm%u: %uinvalid gpnvm: %umissing gpnvm numberget gpnvm failed: %dclear gpnvm result: %dunknown command: %soffset: 0x%08x, count: 0x%08xpage start: %d, page end: %dspecial case, all in one pagenon-aligned startoffset % SAMV_PAGE_SIZE == 0atsamvatsamv flash command groupflash program failed to read page @ 0x%08xstarting flash command: 0x%08xunexpected eproc code: %d was expecting 0 (Cortex-M7)unrecognized flash size code: %dCortex-M7 detected with %d kB flasherror performing erase page @ lock region number %dflash command error @lock region %dwrite page %u at address 0x%08xfailed to buffer page at 0x%08xerror performing write page at 0x%08xflash write error - past end of bank offset: 0x%08x, count 0x%08x, bank end: 0x%08xfull page loop: cur=%d, end=%d, count = 0x%08xfinal partial page, count = 0x%08xsamv_clear_gpnvmsamv_set_gpnvmsamv_get_gpnvmsamv_handle_gpnvm_commandsamv_flash_bank_commandsamv_erasesamv_protectsamv_page_writesamv_page_readsamv_writesamv_writesamv_probesamv_efc_start_commandsamv_efc_perform_commandsrc/flash/nor/avrf.ctarget device is %s0x%x is not support for avrpoll_value = 0x%04xavr mass erase completeavr mass erase failedoffset is 0x%08xcount is %d%s - Rev: 0x%xavrfAVR flash command group0x%x is invalid Manufacturer for avr, 0x%X is expectedoffset 0x%x breaks required %u-byte alignmentCannot identify target as a avr avrf_mass_eraseavrf_handle_mass_erase_commandavr_jtagprg_chiperaseavrf_eraseavrf_protectavr_jtagprg_writeflashpageavrf_writeavrf_probeavrf_protect_checkavrf_infoatmega128at90can128at90usb128atmega164p atmega324patmega324paatmega644p atmega1284pswapping reversed erase region information on cmdset 0002 deviceFixup %d unaligned read head bytesFixup %u unaligned read tail byteschip and bus width have to specified in bytesUnsupported bank buswidth %d, can't do block memory writes cfi flash bank not probed yet qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x typ. word write timeout: %u us, typ. buf write timeout: %u us, typ. block erase timeout: %u ms, typ. chip erase timeout: %u ms max. word write timeout: %u us, max. buf write timeout: %u us, max. block erase timeout: %u ms, max. chip erase timeout: %u ms size: 0x%x, interface desc: %i, max buffer write size: 0x%x intel primary algorithm extend information: pri: '%c%c%c', version: %c.%c feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x Vcc opt: %x.%x, Vpp opt: %u.%x protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i Spansion primary algorithm extend information: Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x Erase Suspend: 0x%x, Sector Protect: 0x%x cfi primary command set %i unsupportedBUG: sector list not yet builtnot enough working area available, can't do block memory writesflash write block failed status: 0x%xCFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2xUnsupported bank chipwidth %d, can't probe memoryFlash Manufacturer/Device: 0x%04x 0x%04xTry workaround w/0x555 instead of 0x55 to get QRY.qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4xsize: 0x%x, interface desc: %i, max buffer write size: 0x%xerase region[%i]: %u blocks of size 0x%xCould not read bank flash bank informationfeature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%xVcc opt: %x.%x, Vpp opt: %u.%xexpected one protection register field, but found %iprotection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %iCould not read atmel bank informationfeatures: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2xCould not read spansion bank informationSilicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%xTemporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%xBurst Mode: 0x%x, Page Mode: 0x%x, Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%xtyp. word write timeout: %u us, typ. buf write timeout: %u us, typ. block erase timeout: %u ms, typ. chip erase timeout: %u msmax. word write timeout: %u us, max. buf write timeout: %u us, max. block erase timeout: %u ms, max. chip erase timeout: %u mscalculated word write timeout: %u ms, buf write timeout: %u ms, block erase timeout: %u ms, chip erase timeout: %u msconfiguration specifies 0x%x size, but a 0x%x size flash was foundCFI size is 0x%x, but total sector size is 0x%xtimeout while waiting for WSM to become readyBlock Lock-Bit Detected, Operation AbortLow Programming Voltage Detected, Operation AbortedProgram Error / Error in Setting Lock-BitError in Block Erasure or Clear Lock-BitsNo working area available, can't do block memory writesUsing target buffer at 0x%08x and of size 0x%04xWrite 0x%04x bytes to flash at 0x%08xExecution of flash algorythm failed. Can't fall back. Please report.couldn't write word at base 0x%x, address 0x%xProgramming at 0x%08x, count 0x%08x bytes remainingWrite address at base 0x%x, address 0x%x not aligned to 2^%d boundaryNumber of data words %d exceeds available buffersize %dcouldn't start buffer write operation at base 0x%x, address 0x%xBuffer write at base 0x%x, address 0x%x failed.couldn't write block at base 0x%x, address 0x%x, size 0x%xcouldn't erase block %i of flash bank at base 0x%xlock/unlock not supported on flashcouldn't change block lock status (set = %i, block_status = 0x%2.2x)protect: cfi primary command set %i unsupportedsrc/flash/nor/cfi.cx16_as_x8data_swapbus_swapjedec_probe CFI flash: non-CFI flash: mfr: 0x%4.4x, id:0x%4.4x VppMin: %u.%x, VppMax: %u.%x Need DQ5 supportUnknown architectureUnknown ARM architectureCould not probe bank: no QRYpri: '%c%c%c', version: %c.%cWP# protection 0x%xProgram suspendedBlock Erase Suspended./src/target/arm.hdq5 timeout, status: 0x%xFixup %d unaligned head bytesBuffer Writes Not SupportedFixup %d unaligned tail bytesInvalid sector rangecficfi_flash_bank_commandcfi_spansion_erasecfi_intel_erasecfi_erasecfi_intel_protectcfi_protectcfi_spansion_write_wordcfi_intel_write_wordcfi_write_wordcfi_spansion_wait_status_busycfi_spansion_write_wordscfi_intel_write_wordscfi_write_wordscfi_spansion_write_block_mips ϥ&X*$X  hP$XKj&X*$X h&H)   <)5 ?pP0P`p%p $a `p%p P RP Pఐᰰ0P`p%p RP 0[0 '@:OPఐᰰ0P`p%p $a `p%p P RP 0[0 '@ '@O:OP0P`p%p $a `p%p P RP cfi_spansion_write_blockcfi_intel_wait_status_busycfi_command_valis_armtarget_to_arm@0@@pW R @0@@pW R @0@@pW R cfi_intel_write_blockbuf_bswap32buf_bswap16cfi_writecfi_readcfi_read_spansion_pri_extcfi_read_atmel_pri_extcfi_read_intel_pri_extcfi_query_stringcfi_fixup_0002_erase_regionscfi_probeflash_addresscfi_protect_checkget_cfi_infoUUU*aemif option value ('%s') is not validInvalid AEMIF controller address %sNAND address %08lx out of range?unrecognized AEMIF controller address %08lxchip address %08x not NAND-enabled?Missing NAND data; try 'nand raw_access enable'write operation failed, status: 0x%02xchip_addr hwecc_mode aemif_addrInvalid NAND chip address %ssrc/flash/nand/davinci.chwecc1hwecc4hwecc4_infixInvalid ecc mode %sread_pagewrite_pageread_blockread_datawrite_blockwrite_datadavinci0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~ !"#$%&'()*+,-./0123456789:;<=>? davinci_writepage_taildavinci_nand_device_commanddavinci_initdavinci_write_pagehaltedUVY ZZ YVUe03f_`+_dap_read_part_idtarget_to_armdap_lookup_cs_componentdap_find_apmem_ap_initdap_queue_dp_readdap_queue_dp_writedap_dp_poll_registerdap_dp_poll_registerdap_dp_initmem_ap_writemem_ap_readdap_rundap_queue_ap_readdap_queue_ap_writenot usedttbcr %xsrc/target/armv7a.cFailed to read VCR register Failed to write VCR register notvirt = phys : MMU disable !!outer: Non-Cacheableinner: Non-Cacheableinner: Strongly-orderedinner: Deviceinner: Write-Throughinner: %x ???multi coremono core%s cluster %x core %x %sD-Cache: %s, I-Cache: %scache_configl2xconfigure l2x cache [base_addr] [number_of_way]%s rev %x, partnum %x, arch %x, variant %x, implementor %xttbr1 %s, ttbr0_mask %x ttbr1_mask %xway option value ('%s') is not validouter cache already initialized smp target : outer cache already initialized ttb_mask %x va_mask %x ttbidx %iPhysical address does not fit into 32 bits%x : %x %s outer shareable %s securedouter: Write-Back, Write-Allocateouter: Write-Through, No Write-Allocateouter: Write-Back, no Write-Allocateinner: Write-Back, Write-Allocateinner: Write-Back, no Write-AllocateL%d I-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytesL%d D-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytesOuter unified cache Base Address 0x%x, %d waysctr %x ctr.iminline %d ctr.dminline %dNumber of cache levels to PoC %ddata/unified cache index %d << %d, way %d << %dcacheline %d bytes %d KBytes asso %d waysinstruction cache index %d << %d, way %d << %dMPIDR nonzero in ARMv7-R targetMPIDR not in multiprocessor formatBUG: called for a non-ARMv7A targetData fault registers DFSR: %8.8x, DFAR: %8.8xInstruction fault registers IFSR: %8.8x, IFAR: %8.8xcache configuration for a target0ww.vv.vv`wvarmv7a_l2x_cache_initarmv7a_show_fault_registersarmv7a_arch_statearmv7a_setup_semihostingarmv7a_read_mpidrarmv7a_identify_cachearmv7a_mmu_translate_va_paarmv7a_read_midrarmv7a_read_ttbcrarmv7a_mmu_translate_vaauto cache is %ssrc/target/armv7a_cache.cdata cache is not enabledclean invalidate failedcl %dd-cache invalidate failedi-cache invalidate failed(1|0)l1 cache command groupl1 d-cache command groupl1 i-cache command group [size]flush_allcleaninstruction cache is not enabledvirt option value ('%s') is not validdisable or enable automatic cache handling.print cache realted informationinvalidate complete l1 i-cacheinvalidate l1 i-cache by virtual address offset and range sizeflush (clean and invalidate) complete l1 d-cacheinvalidate l1 d-cache by virtual address offset and range sizeclean l1 d-cache by virtual address address offset and range sizearmv7a_l1_i_cache_inval_virtarmv7a_l1_i_cache_sanity_checkarmv7a_l1_i_cache_inval_allarmv7a_l1_d_cache_flush_virtarmv7a_l1_d_cache_clean_virtarmv7a_l1_d_cache_inval_virtarmv7a_l1_d_cache_flush_levelarmv7a_l1_d_cache_sanity_checkarmv7a_l1_d_cache_clean_inval_allL2 cache was already initialised smp target : cache l2 already initialized L2 unified cache Base Address 0x%x, %d waysflush (clean and invalidate) l2x cache by virtual address offset and range sizeinvalidate l2x cache by virtual address offset and range sizeclean l2x cache by virtual address address offset and range sizesrc/target/armv7a_cache_l2x.cl2x is not configured!l2x cache command groupconf flush complete l2x cachearmv7a_l2x_cache_initarmv7a_l2x_cache_inval_virtarmv7a_l2x_cache_clean_virtarmv7a_l2x_cache_flush_virtarm7a_l2x_sanity_checksrc/target/armv7m.cError setting registerInvalid exceptionExternal Interrupt(%i)restoring core_mode: 0x%2.2xarm v7m registersorg.gnu.gdb.arm.m-profilexPSRorg.gnu.gdb.arm.m-systemorg.gnu.gdb.arm.vfpfpscrResetNMIHardFaultMemManageBusFaultUsageFaultRESERVEDSVCallDebugMonitorPendSVSysTicknum < (int)armv7m->arm.core_cache->num_regscurrent target isn't an ARMV7M targetARM_MODE_HANDLER not currently supported, using ARM_MODE_THREAD insteadfailed algorithm halted at 0x%x, expected 0x%xtarget halted due to %s, current mode: %s %s xPSR: %#8.8x pc: %#8.8x %csp: %#8.8x%s%sunable to allocate feature listunable to allocate reg type listerror executing cortex_m crc algorithmSkipping over BKPT instructionarmv7m_maybe_skip_bkpt_instx0@9x0C9armv7m_checksum_memoryF C N F$ ] H@%(@p@@5-4Barmv7m_read_core_regarmv7m_write_core_regarmv7m_write_core_regtarget_to_armarmv7m_build_reg_cachearmv7m_arch_statearmv7m_wait_algorithmarmv7m_start_algorithmarmv7m_restore_context  Error writing to the trace destination fileTrace port frequency is 0, can't enable TPIUCan not obtain %u trace port frequency from %u TRACECLKIN frequency, using %u insteadCan't open trace destination filearmv7m->trace_config.port_size option value ('%s') is not validarmv7m->trace_config.formatter option value ('%s') is not validarmv7m->trace_config.traceclkin_freq option value ('%s') is not validarmv7m->trace_config.trace_freq option value ('%s') is not validTrace port frequency can't be omitted in external capture modeEnable or disable ITM stimulus portEnable or disable all ITM stimulus ports(disable | ((external | internal ) (sync | ((manchester | uart) )) []))src/target/armv7m_trace.cexternalinternalmanchesteruarttpiutpiu command groupitmitm command group (0|1|on|off)Configure TPIU featureshandle_tpiu_config_commandarmv7m_poll_tracearmv7m_trace_tpiu_configETB: target not using ETBETB: target '%s' not definedsrc/target/etb.cETB: '%s' isn't an ARMETB: TAP %s does not existETB register read failedETB: register write failedETB_identificationetb registerstrigger_percent[percent]ETB_ram_depthETB_ram_widthETB_statusETB_ram_dataETB_ram_read_pointerETB_ram_write_pointerETB_trigger_counterETB_controlETB: current target isn't an ARMETB: target has no ETM configurednew_value option value ('%s') is not validvalid percentages are 2%% to 100%%%d percent of tracebuffer fills after triggerETM: target has no ETM defined, ETB left unconfiguredETB can't run in demultiplexed mode with a 4 or 16 bit portETB: can't run in multiplexed modeBUG: error scheduling ETB register readETB: DFEmpty won't go high, status 0x%02xETB: trace complete without triggering?BUG: error scheduling ETB register writeEmbedded Trace Buffer command groupAssociate ETB with target and JTAG TAP.Set percent of trace buffer to be filled after the trigger occurs (2..100).handle_etb_config_commandis_armtarget_to_armetb_statusetb_start_captureetb_read_reg_w_checketb_get_regetb_write_regetb_set_regetb_set_reg_w_exec%s invalid target tapsrc/target/lakemont.cdr in 0x%02x%s error enabling paging%s error disabling paging%s failed to execute queuereg %s op=0x%016lx%s error submitting pirTS before PM exit = 0x%08xcore not in PMreg=%s, newval=0x%08xtarget running, halt it firstreg=%s, value=0x%08x%s error saving reg %s%s error reading regs%s error restoring reg %s%s error writing regsdsbasewrite %s 0x%08xdslimitwrite DSAR 0x%08xcsbasecslimitwrite DR7 0x%08xwrite CSAR_CPL to 0 0x%08xwrite SSAR_CPL to 0 0x%08xcaching enabled CR0 = 0x%08xeaxlakemont registersrealTS before PM enter = 0x%08xcore already in probemodeTS after PM enter = 0x%08x%s target not runningMEMRDB32MEMRDB16MEMRDH32MEMRDH16MEMRDW32MEMRDW16MEMWRB32MEMWRB16MEMWRH32MEMWRH16MEMWRW32MEMWRW16IORDB32IORDB16IORDH32IORDH16IORDW32IORDW16IOWRB32IOWRB16IOWRH32IOWRH16IOWRW32IOWRW16SRAMACCESSSRAM2PDRPDR2SRAMWBINVDorg.gnu.gdb.i386.coreecxedxebxespebpesiedieipeflagsst0st3st4st5st6st7fctrlftagfisegfiofffosegfoofffoporg.gnu.gdb.i386.sysidtbaseidtlimitidtargdtbasegdtlimitgdtarldtrldbaseldlimitldtarcsardsaresbaseeslimitesarfsbasefslimitfsargsbasegslimitgsartssbasetsslimittssarpmcr%s drscan failed to execute queue%s tap enabled but tap irlen=%d%s tap not enabled and irlen=%d%s transaction error tapstatus = 0x%08xreg=%s, op=0x%016lx, val=0x%08xread_all_core_hw_regs read %u registers okwrite_all_core_hw_regs wrote %u registers okEFLAGS = 0x%08x, VM86 = %d, IF = %dEFLAGS now = 0x%08x, VM86 = %d, IF = %dcleared paging CR0_PG = 0x%08xset CD, NW and PG, CR0 = 0x%08x%s unable to allocate feature list%s unable to allocate reg type listtapstatus invalid - scan_chain serialization or locked JTAG access issuestarget running for unknown reasonredirect to PM, tapstatus=0x%08xhit hardware breakpoint (hwreg=%u) at 0x%08xhit '%s' watchpoint for 0x%08x (hwreg=%u) at 0x%08xhit software breakpoint at 0x%08xhit unknown breakpoint at 0x%08xunknown break reason at 0x%08xtarget halted due to %s at 0x%08x in %s mode%s PM enter error, tapstatus = 0x%08xmodifying PMCR = 0x%08x and EFLAGS = 0x%08xEFLAGS [TF] [RF] bits set=0x%08x, PMCR=0x%08x, EIP=0x%08xstep done from EIP 0x%08x to 0x%08x%s target didn't stop after executing a single step%s stepping over a software breakpoint at 0x%08x failed to resume the targetlakemont_reset_deassertlakemont_reset_assertlakemont_stepexit_probemodewrite_all_core_hw_regsrestore_contextdo_resumelakemont_resumeenter_probemodelakemont_haltlakemont_arch_statelakemont_pollsubmit_instructiontransaction_statusdisable_pagingenable_paginglakemont_get_core_reglakemont_set_core_reglakemont_build_reg_cachewrite_hw_reghalt_prepdrscanirscansubmit_instruction_pirsubmit_reg_pirread_hw_regread_all_core_hw_regssave_contextcheck_not_haltedtarget is not an MIPS32src/target/mips32.cmips32 registersmips32mips32 command groupregnum select [value]org.gnu.gdb.mips.cpuorg.gnu.gdb.mips.cp0badvaddrcausef0org.gnu.gdb.mips.fpuf1f2f3f4f5f6f7f8f9f10f11f12f13f14f15f16f17f18f19f20f21f22f23f24f25f26f27f28f29f30f31fcsrfirtarget halted in %s mode due to %s, pc: 0x%8.8xcurrent target isn't a MIPS32 targetfailed algorithm halted at 0x%x DCR endianness settings does not match target settingsDCR 0x%x numinst %i numdata %iErase value 0x%02x not yet supported for MIPS32$0$$?pmips32_blank_check_memory$$$ $!.<& G4!0@@$(&H @$(`! Kk%?pmips32_configure_break_unitmips32_run_and_waitmips32_run_algorithmmips32_write_core_regmips32_build_reg_cachemips32_arch_stateDMA time outsrc/target/mips32_dmaacc.cDMA Read Addr = %08x Data = ERROR ON READDMA Write Addr = %08x Data = ERROR ON WRITEejtag_dma_writeejtag_dma_write_hejtag_dma_write_bejtag_dma_readejtag_dma_read_hejtag_dma_dstrt_pollejtag_dma_read_bDEBUGMODULE: No memory access in progress!unexpected write at address %xwriting at unexpected address %xreading at unexpected address %x, expected %xrestarting, without clean jumpunexpected second pass through pracc textunexpected read address in final check: %x, expected: %xfailed to jump back to pracc textexecution abandoned, store pending: %dwarning: store access pass pracc textInternal error, code count: %d > max code: %dError: access not pending count: %dNot a store/write access, count: %dStore address mismatch, read: %x expected: %x count: %dNot a fetch/read access, count: %dFetch addr mismatch, read: %x expected: %x count: %d%s using 0x%.8x for write handlermini program did not return to startsrc/target/mips32_pracc.crestarting codeUnknown release in cache codeclsiz must be power of 2fastdata load failedmips32_pracc_fastdata_xfer`@@@@@h@@`@  @@h@@mips32_pracc_synchronize_cachemips32_pracc_write_memmips32_pracc_read_memmips32_pracc_queue_execpracc_queue_freepracc_queue_initmips32_pracc_execwait_for_pracc_rwEDM does not support ACC_CTLsrc/target/nds32.cEDM does not support DALMMemory mode is not AUTOILM is not enabledDLM is not enablednds32_gdb_detach, virtual hostingAndes registersorg.gnu.gdb.nds32.coreorg.gnu.gdb.nds32.systemorg.gnu.gdb.nds32.audioorg.gnu.gdb.nds32.fpuUSB is disconnectedTarget is disconnectedHit syscall breakpointnds32_loginwrite_misc gen_port0 0x%x;Current privilege level: %dwrite_misc %s 0x%x;EDM version 0x%04xhit syscall ID: 0x%xreset halt as initSOFTWARE BREAKSOFTWARE BREAK_16HARDWARE BREAKPOINTDATA ADDR WATCHPOINT PRECISEDATA VALUE WATCHPOINT PRECISEDEBUG INTERRUPTHARDWARE SINGLE STEPLOAD STORE GLOBAL STOPnds32_gdb_attach, target coreid: %dreading register(cached) %i(%s), value: 0x%8.8xreading register %i(%s), value: 0x%8.8xwriting register %i(%s) with value 0x%8.8xREAD BUFFER: ADDR %08x SIZE %08xWRITE BUFFER: ADDR %08x SIZE %08xBUG: called for a non-Andes targettarget halted due to %s psw: 0x%8.8x pc: 0x%8.8x%swriting register %d with value 0x%8.8xnds32->leave_debug_state(nds32, true)nds32->enter_debug_state(nds32, true)nds32 examines debug reason: %snds32->leave_debug_state(nds32, false)nds32->enter_debug_state(nds32, false)Change target state to TARGET_HALTED.<-- TARGET WARNING! The debug target has been reset. -->Change target state to TARGET_RUNNING.current %d address %08x handle_breakpoints %d debug_execution %dTarget has not initial file-I/O data structuresyscall return code: 0x%x, errno: 0x%x , ctrl_c: %sDATA VALUE WATCHPOINT IMPRECISEDATA ADDR WATCHPOINT NEXT PRECISEDATA VALUE WATCHPOINT NEXT PRECISE8@8X8`8p878999:::99:::nds32_reset_haltnds32_gdb_fileio_endnds32_get_gdb_fileio_infonds32_gdb_detachnds32_gdb_attachnds32_assert_resetnds32_reach_max_interrupt_levelnds32_resumends32_pollnds32_haltnds32_loginnds32_step_without_watchpointnds32_examine_debug_reasonnds32_target_statends32_stepnds32_get_core_reg_64nds32_set_core_reg_64nds32_get_core_regnds32_set_core_regnds32_edm_confignds32_restore_contextnds32_arch_statends32_mmunds32_write_buffernds32_select_memory_modends32_read_buffertarget_to_nds32target_to_aice @ @d src/target/nds32_aice.caice_profilingaice_set_count_to_check_dbgeraice_set_custom_restart_scriptaice_set_custom_trst_scriptaice_set_custom_srst_scriptaice_executeaice_set_command_modeaice_program_edmaice_set_retry_timesaice_cache_ctlaice_read_tlbaice_write_reg_64aice_read_reg_64usage: %s
%s: virtual hosting: on%s: virtual hosting: offMEMilm%s does not support ILMdlm%s does not support DLM%s: memory mode: %s%s: $INT_MASK.DSSIM: %d%s: soft-reset-halt: onsrc/target/nds32_cmd.c%s: soft-reset-halt: off%s: global stop: on%s: global stop: offbus%s: memory access channel: %sinvalidate%s: No data cache%s: Data cache disabled%s: No instruction cache%s: No valid parameteredm_dtrusage: %s edmsw%s: BE%s: LEOCDCPUID: %sAndes command groupdssim['bus'|'cpu']mem_modedisplay/change memory mode['auto'|'mem'|'ilm'|'dlm']['invalidate']icache controldcache controlauto_breakvirtual_hostingturn on/off virtual hostingglobal_stopboot_timemillisecondslogin_edm_passcodelogin_edm_operationreset_halt_as_initreset halt as openocd init.keep_target_edm_ctldecodedecode instruction.address icountword_access_membulk_writeaddress count datamulti_writenum_of_pairs [address data]+bulk_readaddress countread_edmsrRead EDM system register['edmsw'|'edm_dtr']write_edmsrWrite EDM system register['edm_dtr'] valuequeryAndes query command groupquery target endiancpuidquery CPU IDBUSusage: %s
current target isn't an Andes core%s: convert sw break to hw break on ROM: on%s: convert sw break to hw break on ROM: off%s does not support ACC_CTL. Set memory mode to MEMORY%s does not support direct access local memory. Set memory mode to MEMORYmisc_reg_no option value ('%s') is not validdata option value ('%s') is not validinsn_count option value ('%s') is not validmemory access channel is changed to %s%s: Write back data cache...failed%s: Write back data cache...done%s: Invalidate data cache...failed%s: Invalidate data cache...done%s: Invalidate instruction cache...failed%s: Invalidate instruction cache...done%s: Instruction cache disabledusage: %s usage: %s # of pairs [
]+nds32->boot_time option value ('%s') is not validdisplay/change $INT_MASK.DSSIM statusdisplay/change memory access channel['invalidate'|'enable'|'disable'|'dump']convert software breakpoints to hardware breakpoints if neededturn on/off global stop. After turning on, every load/storeinstructions will be stopped to check memory access.as issuing rest-halt, to use soft-reset-halt or not.the feature is for backward-compatible.set the period to wait after srst.set EDM passcode for secure MCU debugging.add EDM operations for secure MCU debugging.login_edm_operation misc_reg_no valueBackup/Restore target EDM_CTL register.Always use word-aligned address to access memory.Write multiple 32-bit words to target memoryWrite multiple addresses/words to target memoryRead multiple 32-bit words from target memoryreply 'OCD' for gdb to identify server-side is OpenOCDhandle_nds32_memory_access_commandhandle_nds32_global_stop_commandhandle_nds32_soft_reset_halt_commandtarget_to_aiceis_nds32target_to_nds320x%8.8x 0x%8.8x ADD_SLLI $r%u,$r%u,$r%u,%d0x%8.8x 0x%8.8x ADD $r%u,$r%u,$r%u0x%8.8x 0x%8.8x SUB_SLLI $r%u,$r%u,$r%u,%d0x%8.8x 0x%8.8x SUB $r%u,$r%u,$r%u0x%8.8x 0x%8.8x AND_SLLI $r%u,$r%u,$r%u,%d0x%8.8x 0x%8.8x AND $r%u,$r%u,$r%u0x%8.8x 0x%8.8x XOR_SLLI $r%u,$r%u,$r%u,%d0x%8.8x 0x%8.8x XOR $r%u,$r%u,$r%u0x%8.8x 0x%8.8x OR_SLLI $r%u,$r%u,$r%u,%d0x%8.8x 0x%8.8x OR $r%u,$r%u,$r%u0x%8.8x 0x%8.8x NOR $r%u,$r%u,$r%u0x%8.8x 0x%8.8x SLT $r%u,$r%u,$r%u0x%8.8x 0x%8.8x SLTS $r%u,$r%u,$r%u0x%8.8x 0x%8.8x SLLI $r%u,$r%u,#%d0x%8.8x 0x%8.8x SRLI $r%u,$r%u,#%d0x%8.8x 0x%8.8x SRAI $r%u,$r%u,#%d0x%8.8x 0x%8.8x ROTRI $r%u,$r%u,#%d0x%8.8x 0x%8.8x SLL $r%u,$r%u,$r%u0x%8.8x 0x%8.8x SRL $r%u,$r%u,$r%u0x%8.8x 0x%8.8x SRA $r%u,$r%u,$r%u0x%8.8x 0x%8.8x ROTR $r%u,$r%u,$r%u0x%8.8x 0x%8.8x BITC $r%u,$r%u,$r%u0x%8.8x 0x%8.8x WSBH $r%u,$r%u0x%8.8x 0x%8.8x OR_SRLI $r%u,$r%u,$r%u,%d0x%8.8x 0x%8.8x DIVSR $r%u,$r%u,$r%u,$r%u0x%8.8x 0x%8.8x DIVR $r%u,$r%u,$r%u,$r%u0x%8.8x 0x%8.8x SVA $r%u,$r%u,$r%u0x%8.8x 0x%8.8x SVS $r%u,$r%u,$r%u0x%8.8x 0x%8.8x CMOVZ $r%u,$r%u,$r%u0x%8.8x 0x%8.8x CMOVN $r%u,$r%u,$r%u0x%8.8x 0x%8.8x ADD_SRLI $r%u,$r%u,$r%u,%d0x%8.8x 0x%8.8x SUB_SRLI $r%u,$r%u,$r%u,%d0x%8.8x 0x%8.8x AND_SRLI $r%u,$r%u,$r%u,%d0x%8.8x 0x%8.8x XOR_SRLI $r%u,$r%u,$r%u,%d0x%8.8x 0x%8.8x MAX $r%u,$r%u,$r%u0x%8.8x 0x%8.8x MIN $r%u,$r%u,$r%u0x%8.8x 0x%8.8x AVE $r%u,$r%u,$r%u0x%8.8x 0x%8.8x CLIPS $r%u,$r%u,#%d0x%8.8x 0x%8.8x CLIP $r%u,$r%u,#%d0x%8.8x 0x%8.8x BSET $r%u,$r%u,#%d0x%8.8x 0x%8.8x BCLR $r%u,$r%u,#%d0x%8.8x 0x%8.8x BTGL $r%u,$r%u,#%d0x%8.8x 0x%8.8x BTST $r%u,$r%u,#%d0x%8.8x 0x%8.8x BSE $r%u,$r%u,$r%u0x%8.8x 0x%8.8x BSP $r%u,$r%u,$r%u0x%8.8x 0x%8.8x FFB $r%u,$r%u,$r%u0x%8.8x 0x%8.8x FFMISM $r%u,$r%u,$r%u0x%8.8x 0x%8.8x FFZMISM $r%u,$r%u,$r%u0x%8.8x 0x%8.8x MFUSR $r%u,#%d0x%8.8x 0x%8.8x MTUSR $r%u,#%d0x%8.8x 0x%8.8x MUL $r%u,$r%u,$r%u0x%8.8x 0x%8.8x MULTS64 $D%u,$r%u,$r%u0x%8.8x 0x%8.8x MULT64 $D%u,$r%u,$r%u0x%8.8x 0x%8.8x MADDS64 $D%u,$r%u,$r%u0x%8.8x 0x%8.8x MADD64 $D%u,$r%u,$r%u0x%8.8x 0x%8.8x MSUBS64 $D%u,$r%u,$r%u0x%8.8x 0x%8.8x MSUB64 $D%u,$r%u,$r%u0x%8.8x 0x%8.8x DIVS $D%u,$r%u,$r%u0x%8.8x 0x%8.8x DIV $D%u,$r%u,$r%u0x%8.8x 0x%8.8x MULT32 $D%u,$r%u,$r%u0x%8.8x 0x%8.8x MADD32 $D%u,$r%u,$r%u0x%8.8x 0x%8.8x MSUB32 $D%u,$r%u,$r%u0x%8.8x 0x%4.4x LWI333 $r%u,[$r%u+(#%d)]0x%8.8x 0x%4.4x LWI333.BI $r%u,[$r%u],#%d0x%8.8x 0x%4.4x LHI333 $r%u,[$r%u+(#%d)]0x%8.8x 0x%4.4x LBI333 $r%u,[$r%u+(#%d)]0x%8.8x 0x%4.4x SWI333 $r%u,[$r%u+(#%d)]0x%8.8x 0x%4.4x SWI333.BI $r%u,[$r%u],#%d0x%8.8x 0x%4.4x SHI333 $r%u,[$r%u+(#%d)]0x%8.8x 0x%4.4x ADDRI36.SP $r%u,#%d0x%8.8x 0x%4.4x LWI45.FE $r%u,[#%d]0x%8.8x 0x%4.4x LWI450 $r%u,$r%u0x%8.8x 0x%4.4x SWI450 $r%u,$r%u0x%8.8x 0x%4.4x LWI37 $r%u,[fp+#%d]0x%8.8x 0x%4.4x SWI37 $r%u,[fp+#%d]0x%8.8x 0x%8.8x LB $r%u,[$r%u+($r%u<<%d)]0x%8.8x 0x%8.8x LH $r%u,[$r%u+($r%u<<%d)]0x%8.8x 0x%8.8x LW $r%u,[$r%u+($r%u<<%d)]0x%8.8x 0x%8.8x LB.bi $r%u,[$r%u],($r%u<<%d)0x%8.8x 0x%8.8x LH.bi $r%u,[$r%u],($r%u<<%d)0x%8.8x 0x%8.8x LW.bi $r%u,[$r%u],($r%u<<%d)0x%8.8x 0x%8.8x SB $r%u,[$r%u+($r%u<<%d)]0x%8.8x 0x%8.8x SH $r%u,[$r%u+($r%u<<%d)]0x%8.8x 0x%8.8x SW $r%u,[$r%u+($r%u<<%d)]0x%8.8x 0x%8.8x SB.bi $r%u,[$r%u],($r%u<<%d)0x%8.8x 0x%8.8x SH.bi $r%u,[$r%u],($r%u<<%d)0x%8.8x 0x%8.8x SW.bi $r%u,[$r%u],($r%u<<%d)0x%8.8x 0x%8.8x LBS $r%u,[$r%u+($r%u<<%d)]0x%8.8x 0x%8.8x LHS $r%u,[$r%u+($r%u<<%d)]0x%8.8x 0x%8.8x DPREF #%u,[$r%u+($r%u<<#%d)]0x%8.8x 0x%8.8x LBS.bi $r%u,[$r%u],($r%u<<%d)0x%8.8x 0x%8.8x LHS.bi $r%u,[$r%u],($r%u<<%d)0x%8.8x 0x%8.8x LLW $r%u,[$r%u+($r%u<<%d)]0x%8.8x 0x%8.8x SCW $r%u,[$r%u+($r%u<<%d)]0x%8.8x 0x%8.8x LBUP $r%u,[$r%u+($r%u<<%d)]0x%8.8x 0x%8.8x LWUP $r%u,[$r%u+($r%u<<%d)]0x%8.8x 0x%8.8x SBUP $r%u,[$r%u+($r%u<<%d)]0x%8.8x 0x%8.8x SWUP $r%u,[$r%u+($r%u<<%d)]0x%8.8x 0x%8.8x SMW $r%u,[$r%u],$r%u,%d0x%8.8x 0x%8.8x SMWA $r%u,[$r%u],$r%u,%d0x%8.8x 0x%8.8x SMWZB $r%u,[$r%u],$r%u,%d0x%8.8x 0x%8.8x LMW $r%u,[$r%u],$r%u,%d0x%8.8x 0x%8.8x LMWA $r%u,[$r%u],$r%u,%d0x%8.8x 0x%8.8x LMWZB $r%u,[$r%u],$r%u,%d0x%8.8x 0x%8.8x LHI.gp $r%u,[#%d]0x%8.8x 0x%8.8x LHSI.gp $r%u,[#%d]0x%8.8x 0x%8.8x SHI.gp $r%u,[#%d]0x%8.8x 0x%8.8x SWI.gp $r%u,[#%d]0x%8.8x 0x%8.8x LWI.gp $r%u,[#%d]0x%8.8x 0x%8.8x SBI.gp $r%u,[#%d]0x%8.8x 0x%8.8x ADDI.gp $r%u,#%dsrc/target/nds32_disassembler.c0x%8.8x 0x%4.4x MOV55 $r%u,$r%u0x%8.8x 0x%4.4x MOVI55 $r%u,#%d0x%8.8x 0x%4.4x ADD45 $r%u,$r%u0x%8.8x 0x%4.4x SUB45 $r%u,$r%u0x%8.8x 0x%4.4x ADDI45 $r%u,#%d0x%8.8x 0x%4.4x SUBI45 $r%u,#%d0x%8.8x 0x%4.4x SRAI45 $r%u,#%d0x%8.8x 0x%4.4x SRLI45 $r%u,#%d0x%8.8x 0x%4.4x SLLI333 $r%u,$r%u,#%d0x%8.8x 0x%4.4x ZEB33 $r%u,$r%u0x%8.8x 0x%4.4x ZEH33 $r%u,$r%u0x%8.8x 0x%4.4x SEB33 $r%u,$r%u0x%8.8x 0x%4.4x SEH33 $r%u,$r%u0x%8.8x 0x%4.4x XLSB33 $r%u,$r%u0x%8.8x 0x%4.4x XLLB33 $r%u,$r%u0x%8.8x 0x%4.4x BMSKI33 $r%u,$r%d0x%8.8x 0x%4.4x FEXTI33 $r%u,$r%d0x%8.8x 0x%4.4x ADD333 $r%u,$r%u,$r%u0x%8.8x 0x%4.4x SUB333 $r%u,$r%u,$r%u0x%8.8x 0x%4.4x ADDI333 $r%u,$r%u,#%d0x%8.8x 0x%4.4x SUBI333 $r%u,$r%u,#%d0x%8.8x 0x%4.4x BEQZ38 $r%u,#%d0x%8.8x 0x%4.4x BNEZ38 $r%u,#%d0x%8.8x 0x%4.4x BEQS38 $r%u,#%d0x%8.8x 0x%4.4x BNES38 $r%u,#%d0x%8.8x 0x%4.4x SLTS45 $r%u,$r%u0x%8.8x 0x%4.4x SLT45 $r%u,$r%u0x%8.8x 0x%4.4x SLTSI45 $r%u,#%d0x%8.8x 0x%4.4x SLTI45 $r%u,#%d0x%8.8x 0x%4.4x ADDI10.SP #%d0x%8.8x 0x%4.4x LWI37.SP $r%u,[+#%d]0x%8.8x 0x%4.4x SWI37.SP $r%u,[+#%d]0x%8.8x 0x%4.4x MOVPI45 $r%u,#%d0x%8.8x 0x%4.4x PUSH25 $r%u,#%d0x%8.8x 0x%4.4x POP25 $r%u,#%d0x%8.8x 0x%4.4x MOVD44 $r%u,$r%u0x%8.8x 0x%4.4x NEG33 $r%u,$r%u0x%8.8x 0x%4.4x NOT33 $r%u,$r%u0x%8.8x 0x%4.4x MUL33 $r%u,$r%u0x%8.8x 0x%4.4x XOR33 $r%u,$r%u0x%8.8x 0x%4.4x AND33 $r%u,$r%u0x%8.8x 0x%4.4x OR33 $r%u,$r%u0x%8.8x 0x%8.8x LBI $r%u,[$r%u+#%d]0x%8.8x 0x%8.8x LHI $r%u,[$r%u+#%d]0x%8.8x 0x%8.8x LWI $r%u,[$r%u+#%d]0x%8.8x 0x%8.8x LBI.bi $r%u,[$r%u],#%d0x%8.8x 0x%8.8x LHI.bi $r%u,[$r%u],#%d0x%8.8x 0x%8.8x LWI.bi $r%u,[$r%u],#%d0x%8.8x 0x%8.8x SBI $r%u,[$r%u+#%d]0x%8.8x 0x%8.8x SHI $r%u,[$r%u+#%d]0x%8.8x 0x%8.8x SWI $r%u,[$r%u+#%d]0x%8.8x 0x%8.8x SBI.bi $r%u,[$r%u],#%d0x%8.8x 0x%8.8x SHI.bi $r%u,[$r%u],#%d0x%8.8x 0x%8.8x SWI.bi $r%u,[$r%u],#%d0x%8.8x 0x%8.8x LBSI $r%u,[$r%u+#%d]0x%8.8x 0x%8.8x LHSI $r%u,[$r%u+#%d]0x%8.8x 0x%8.8x DPREFI.d %u,[$r%u+#%d]0x%8.8x 0x%8.8x DPREFI.w %u,[$r%u+#%d]0x%8.8x 0x%8.8x LBSI.bi $r%u,[$r%u],#%d0x%8.8x 0x%8.8x LHSI.bi $r%u,[$r%u],#%d0x%8.8x 0x%8.8x LBSI.gp $r%u,[#%d]0x%8.8x 0x%8.8x LBI.gp $r%u,[#%d]0x%8.8x 0x%8.8x SETHI $r%u,0x%8.8x0x%8.8x 0x%8.8x JRAL $r%u,$r%u0x%8.8x 0x%8.8x JRALNEZ $r%u,$r%u0x%8.8x 0x%8.8x BNE $r%u,$r%u,#%d0x%8.8x 0x%8.8x BEQ $r%u,$r%u,#%d0x%8.8x 0x%8.8x BGEZAL $r%u,#%d0x%8.8x 0x%8.8x BLTZAL $r%u,#%d0x%8.8x 0x%8.8x ADDI $r%u,$r%u,#%d0x%8.8x 0x%8.8x SUBRI $r%u,$r%u,#%d0x%8.8x 0x%8.8x ANDI $r%u,$r%u,#%d0x%8.8x 0x%8.8x XORI $r%u,$r%u,#%d0x%8.8x 0x%8.8x ORI $r%u,$r%u,0x%8.8x0x%8.8x 0x%8.8x SLTI $r%u,$r%u,#%d0x%8.8x 0x%8.8x SLTSI $r%u,$r%u,#%d0x%8.8x 0x%8.8x SEB $r%u,$r%u0x%8.8x 0x%8.8x SEH $r%u,$r%u0x%8.8x 0x%8.8x ZEH $r%u,$r%u0x%8.8x 0x%8.8x AVE $r%u,$r%u0x%8.8x 0x%8.8x CLO $r%u,$r%u0x%8.8x 0x%8.8x CLZ $r%u,$r%u0x%8.8x 0x%4.4x NOP0x%8.8x 0x%4.4x J8 #%d0x%8.8x 0x%4.4x JR5 $r%u0x%8.8x 0x%4.4x JRAL5 $r%u0x%8.8x 0x%4.4x EX9.IT #%d0x%8.8x 0x%4.4x RET5 $r%u0x%8.8x 0x%4.4x ADD5.PC $r%u0x%8.8x 0x%4.4x BEQZS8 #%d0x%8.8x 0x%4.4x BNEZS8 #%d0x%8.8x 0x%4.4x BREAK16 #%d0x%8.8x 0x%4.4x IFCALL9 #%d0x%8.8x 0x%8.8x MOVI $r%u,#%d0x%8.8x 0x%8.8x JAL #%d0x%8.8x 0x%8.8x J #%d0x%8.8x 0x%8.8x RET $r%u0x%8.8x 0x%8.8x JR $r%u0x%8.8x 0x%8.8x JRNEZ $r%u0x%8.8x 0x%8.8x JRALNEZ $r%u0x%8.8x 0x%8.8x BEQZ $r%u,#%d0x%8.8x 0x%8.8x BNEZ $r%u,#%d0x%8.8x 0x%8.8x BGEZ $r%u,#%d0x%8.8x 0x%8.8x BLTZ $r%u,#%d0x%8.8x 0x%8.8x BGTZ $r%u,#%d0x%8.8x 0x%8.8x BLEZ $r%u,#%d0x%8.8x 0x%8.8x STANDBY #%u0x%8.8x 0x%8.8x CCTL0x%8.8x 0x%8.8x MFSR $r%u,#%d0x%8.8x 0x%8.8x MTSR $r%u,#%d0x%8.8x 0x%8.8x IRET0x%8.8x 0x%8.8x TRAP #%d0x%8.8x 0x%8.8x TEQZ $r%u,#%d0x%8.8x 0x%8.8x TNEZ $r%u,#%d0x%8.8x 0x%8.8x DSB0x%8.8x 0x%8.8x ISB0x%8.8x 0x%8.8x BREAK #%d0x%8.8x 0x%8.8x SYSCALL #%d0x%8.8x 0x%8.8x MSYNC #%d0x%8.8x 0x%8.8x ISYNC $r%u0x%8.8x 0x%8.8x TLBOP KJPJJII@IIHHH`H HGG`G8GGFFF@FEE(ED`EDPDDCJUxUUTpT TSxS(SRR8RQhQQPHVHVHVHVHVHVHV0PHVHVHVHVHVHVHVHVOOHVHVHOHVHVHVNN@NMM8MLLHV0LHVKHV`KX[VhWWhXXhYY@ZZZUhVhVhVhV8bxbXbpa`btihhN\ugfCfted2\]dc+c$mqlk\%kji(utttuXtptm,wTx4ywwxvAۆuuC`GԌxe(X~}t}h|܂,t,LK`ˈyQ$`zzTtp{xpyTܑQ" ,,{/L,,,,i-ĔZ[ܑܑ֙e-nds32_read_opcodetarget_to_aice;tPftvuvYv0uw wH0w$@w}pw~wtxXuxluxuxuzu@{u{v|Lvp~vvv 0wpwwwwx`@x|xPxy0y@yyyzz`z {4{h{{{|К |L| x||М| |X}l}@}p}}@~P~Рd~x~~p~~~~С~@$p8ppУ@PФ4 H`0`P$p`00T`p`؂Pp`д$0@p0 TxPP,Pdx 0Ȇ@܆P`p,@Th|̇@Xp 0@P؈P(<XlpЉp0DXt`@Ԋ $P@|`ċ,d`p`,H|P`0t@P`܎ @8Pdpx `P| HБxPt0<pX ܖ (@ t,x`p<h`@ܙ t̚ 0'x`()@+L+,-/t002 38`3LP69Ğp9p<<>@?̟@B,EGtGI<IPpKKMNPȤ@RLTTĥW,W@YYp[$^x^_bܧc ed`ffgȨgr0 rD@r`Psttpu0w|0xz~H~\Ё@0ܬLd`| `hpP p0ȯp4а@h@Ա`$8Pdx0 г00,LlĴ4dPк hPض <`|0pзp(0``0@иP`\@8t`غ ,`T̻0 D0XPl`ؼ0`4\Ľ $D Ⱦ@ P`l`$P @ @\08,`LhP0P<XP ` p  P 8 L ` `PHP|Pp$``,@ t !p# %d&'`()0*4*P+P,,1L`2l0=?@?T@AAB(@FpGHPHJ@KXPKxKKLN<O`OPQ @Q pQ4Q`0R|@R@Sp^db0f8`fLfhfhhpi,jhjkpkk8ltPm no@oT`ppprtxPttuu@v,wpz|}}$@~t0`HphP0pp4`@Pp$ОHt@4@P0pЧ,P@t4 P t p$0@`е@Pp0DpPPT(@tP<X0`@,Xp@l0`@Ht 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6pL7@78 D8P8`8@9@\9909P 8:0 : $;p;@;< L<<<<0=D=@d===P4>l>>> ?pD? ?@!?P# @`#4@#X@$@0&@&@0'A'HA*A+A0/HB 0B0B`2C5LC 7C9C:D:$D`;XD =DP>D @E@@E@DEBE0DEE FEhF`JFN`G@OxGOGOGOG`RHR(HSDH0THTH@UHVI ZdI \I\I\I\ J\ J\4J]XJ0`J bJbKcKc8Kh8L0iLLiLuLu0MvlMxMyNpOOАP`PPPQdQQRR@HSdSSSStm>m?mA4nFn@GnpHnI0oJDoKxoLoLoNp0O,pPtpPpQpSpTqTP?GR@YPppq0HP\@zRx +zRx $XPFJ w?;*3$"D$\EAKH eFA ,(&JR4@AAD [ CAK  CAF UvK(PAFD ~ AAE 4@ AAG [ DAG z DAA 8xBDE \ ABF  ABD <fBDA A(G (A ABBJ ( S@ M s E iG8  pBKD A(D0@ (C ABBB <\ WLAG  AAI T AAA j )$  ARL$ BBA A(D0M (D ABBH U (D ABBJ 80 BBA A(D` (A ABBD 8l BBA A(GL (A ABBA Pl_BBB B(A0A8D 8A0A(B BBBA @x/BBB A(A0D@ 0A(A BBBD h@dBAA Gq  AABH cECCMuK]Am KN  1Dl1DlABBB B(A0D8D@ 8F0A(B BBBK DHNP_HA@I 8A0A(B BBBK HGPMHA@F 8A0A(B BBBJ M HNPS V HNPS Q HNPS D HNPS DHNP(AAG0t AAA (AAD0O AAI (|AAD0O AAI (4ADDP AAE 0`BAA D0o  AABE 8BGA D(D0v (A ABBA L JBB A(A0 (A BBBG g (C BBBH   4(LADF0c AAH (xl_BDC RABLwBEE F(F0r8M@HHCPAXB`I0A(A BBB#DBDY A \$ BED A(F0Y (C ABBE  (F ABBE (F ABB!!5Qc!%AM B P8!oBBA A(D0 (A ABBA ( !RBKD c CBG << ("vAEG Z FAJ D AAB jFA| h" d" p" |"WD\ H n " " " "!( ")< ">P #*4d 0#ADD0[ AAJ L8L@`8A0 #: $$, 0$dNHA CABA p$( l$uIDA h CBE (4 $9BDF iAB` $t $gH8 (%BBA A(D0D (A ABBA  %%8 %BBA A(D0D (A ABBA  &HDz E 4 @&KQmHP t&BEJ E(A0A8D@ 8A0A(B BBBE } 8A0A(B BBBI A 8A0A(B BBBE SHHPfHA@X 'BBB B(A0A8DMbAc 8A0A(B BBBH $4 P)5AEF fAA \ h)A{ D F A  )%Ac )@Sl *GDn F J, @*gBAA @ ABA (*A_ H F J  D h0,;BDA | HRS  ABF { CBH x ABE T ABI  ABN ..DY.)p.BBB B(A0A8G@ 8A0A(B BBBD HDPDXC`N@D 8A0A(B BBBG P0ZATl0 BBB B(A0A8D 8A0A(B BBBE cKAo^ACKDJBLDMwA&M\HYHsA(;cYL K lHL< \H<AF b AF <AF h AH P=uD| H T D T =_AG P AA (=AAF0t AAB \@D{ A 4@,Ai F A G XAAM B a G |HB DB @BBBB E(A0A8Dp 8A0A(B BBBD HxfQxAp(Dh(SBBB B(D0C8DPXE`MXAPyXS`]XAPD 8C0A(B BBBC | XS`Q D8A0A(B BBB(8)|{ACV b LAG d)ДD@x) BBB H(A0FP 0A(A BBBD 0)BIA K0  AABE )D`HO a X *BBB B(A0C8Dp 8A0A(B BBBJ (xgQxApHh*,BBB B(D0A8DP 8A0A(B BBBF @*p>BBE A(A0D@ 0A(A BBBG (*lAOH0 CAA 0$+BAC F0  AABH X+|BEB B(A0D8D@PHSPXHF@D 8A0A(B BBBE q 8C0A(B BBBK D HPPL t 8F0A(B BBBE +BBB E(D0E8D@HSPXHA@I 8A0A(B BBBD AHPP[HA@O 8C0A(B BBBH D HSPQ D 8F0A(B BBBE V8K0A(B BBB, ,BBB E(D0E8D@HSPXHA@I 8A0A(B BBBD AHPP[HA@O 8C0A(B BBBH D HSPQ D 8F0A(B BBBE V8K0A(B BBBh-< |-8BBB E(D0E8D@HSPXHA@I 8A0A(B BBBD AHPP[HA@O 8C0A(B BBBH D HSPQ D 8F0A(B BBBE V8K0A(B BBB0.d tD.` BEB B(A0A8F+dMALPXAY 8A0A(B BBBH l SL .IBBB E(D0C8F@ 8F0A(B BBBB Y 8H0D(G BBBN DHKP`HA@L8C0A(B BBB@/ԪBBE J(E0I8DPXg`HXAPrXS`XXAPI 8A0A(B BBBE D 8C0A(B BBBH D XS`I D 8F0A(B BBBA Q8I0A(B BBB/ IBBB E(D0C8F@ 8F0A(B BBBG Y 8H0D(G BBBF DHKP`HA@L8C0A(B BBB`x08BEE B(A0C8FpDxSXxAp] 8A0A(B BBBA t xSL 0Ȯ d0ĮmBEB B(A0C8FwSXA] 8A0A(B BBBA t SL X1̰ dl1Ȱ}BEB B(A0C8FSXA] 8A0A(B BBBI t SL 1 d1ܲBFI I(I0C8DPXAY 8A0A(B BBBH L SI PP2DbBEB B(D0A8D 8A0A(B BBBD 2`2\AI F ,2ܷAAG AAF @3LBNA A(D@ (A ABBA y HJPb @L3ȻBIB A(A0D@  0A(A BBBI 3oKD A 3Խn|q(3,AAG0n AAG 3оBAN E H4 BBB B(A0A8D 8A0A(B BBBG \4p4AZ@4 ACF v AAF d MVI D(K0`(A 4(4PhBAA ZADH5BAA S ABF D(Q0[(F D(P0X(F F(P0H\58bAQFHFK]RVA\ AA 5\BAN E T5BBB B(A0A8D@ 8D0A(B BBBA rHKPcHA@T6BBB B(A0A8D` 8A0A(B BBBD  hHpi t6p,6lGiK `CA A l A T6,BRA %(O0I8H@GHBPL I CBC d CBG gCB7$DO E K(07gAAD@ AAB L\7lBBB B(A0A8DN 8A0A(B BBBA X7(BEB D(A0s (A BBBH T8K@`8A0V (A BBBC 88BBD C(I (A ABBG 0D8BDC G^  AABF x8,[DS8tvti8vti$8DLh D b F fJ$8Lh D b F fJ894BGA H ABK D(N0](A DL9BDC g ABE A FBG A FBG 9D0 A (9AADpe AAC 89HFBGA C(F@ (A ABBA (:\\ATP0 AAC TD:jBBB A(A0G _ 0A(A BBBJ J ` U A (: AHF  AAE (:hBAA ZAD0:BAA F0N  AABD 4(;ACF } FAJ \(K0`(A H`;4hBBB B(A0A8D`' 8A0A(B BBBA (;XAg H U K Z F ;GAV I V J ;BAN E <LpAM0[ AA T<<UBBB B(A0A8D` 8A0A(B BBBI  hHpi h<!BBB B(A0A8D`P 8A0A(B BBBH hTpCxHN`uhJp[hF`L=dPBE D(C0@ (A BBBK Y (A BBBH P=41Rd=`3T|= =(=AAG R CAA t=4JBBB B(A0A8D@HBPAXC`N@HRP[HA@c 8A0A(B BBBG HLPYHF@dH> BFB B(A0A8DP 8D0A(B BBBH UX^`SXAPqXL`dXAPH>BEB B(A0A8D@ 8C0A(B BBBE (>wAHK O AAK ,(?,RMH  KLK X?ZHa G ix?<bHl D i(?AMD e AAA (?gAKD j AAA ?DAI ~ AG (@AFD0A AAB @@dbJj D i,`@DP L DO `AI E o@$%Ac@8D E G @vAi(@BAA j CBE 4ASAAF I FAH o AAG HHAbBBE E(A0H8IP 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