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Hl$HHH?HHHHL)91H*^.zH[A\A^A_]f.AWAVAUATSH II辐[IL8LpIcFTHtEHi@BHt$[x2HiL$@BHS㥛 Hl$HH?HHH1LHHIEHP`A~4tAI}A6AVMEHMeMI@AF@$L- IEI}H@`HLIEHHcHH~H@s11HHHZHHHHH)HHf1ffoodol ot0ffffffffffffHHuHtoo\fffffffffpNffpff~H9t!f.f1<@HH9u1E1MIIEHI~8Ht/~+1HGH4I~>HI~8HcGH9|1IF@Ht7x~11fH@H4I~>HIF@HcHH9|I~8Ht3HGHtHD[IF8H@I~8Ht *[IF8I~@Ht3HGHtH[IF@H@I~@Ht [IF@I~}I~HHt3HGHtHÌ[IFHH@I~HHt 詌[IFHI~PHt+HGHtH臌[IFPH@I~PHtm[LH[A^^[f.@AWAVSLAphMXEHpMcIE111fDK<9xxA9{~rI{LJHE(HID$HcHH9|ID$ xLl$D|$E11HL$Ld$ HHJ,HMLeLuLHAL3`(LHAL3p(H\$HLLdIIH)3Ld;D$4HEHD$@HEHD$8HL 3LrdALgdA9L|$@Lt$8IHHp(H2IHHc@$HHL$(9ALHI4Lt$LH HHA(Hu2HLd$ LLd$ L|$8Lt$@IHHp(HN2IHHc@$HHL$(?9A6LHI4Lt$LuH HHA(H1HHLd$ LHHHHH1HHH3p(HHHH3P(LGIH1HD$HD$L}(ID$ IHcHI9~S1Lt$D|$Ll$HHH HtQwHq(LI1ID$ HHcHH9|Lt$D|$Ll$LEtv11D{[DHH[A\A]A^A_]ÿMd|}[f.UAWAVAUATSPHIIHk$<t<uJLH[A\A]A^A_]-HcC$HA9EzIM4LH[A\A]A^A_]鹆Lc(M%I΃HsHLLcLcAI1HuqHcC$HA9EIM4L\LHLMHH/IcnA;.YI~H膀[HsHLLLHSH1LLEHHk/HcC$HrA9EhIM4xOL豅ILHH,$H\LIH!/IcnA;.=I~Hto[mIH9}|I~Ht`HH[^H9I~HtgHH[e}[IFA*}[IFA>HcH}[IFA.IFIcNQAVHE1>HcH}[IFA.IFIcNQAVL,LH4$3.L.Lc(LH[A\A]A^A_]ÿ TS]Uz[Md|z[UAWAVATSIHIH|[IHd |[IGtI{h1CpHK9AHIHH4LLL;kh|F{p~@1f.@HCHcHH9}|H@H4LLLMHHcCpH9|HC x~C1@HHH Ht#QwHq(Ht L,HC HHcHH9|L[A\A^A_]ÿMny[f.@UAWAVAUATSPIIIHH$HǂHIHC,Ap~}1f.IGHcHH9H@HHc@$Hx|A9F~vIN4LiHLLHBHH+LL+HIcGpIH9|LH.H$I$HHH[A\A]A^A_]ÿMd|Yx[M@x[UAWAVAUATSPAHIz[IWIF LchM~,LHpz[IGHXEE/As11 DƒHzHHH΃H8s1HH)H >H1(`&DD D0D@DPD`DpH@HuHt+H HH(%AH HuL9tf.HI9uEoANh~tIV1f.@A~l9zHjHcH|Hc$H9{HkHc|HA99|EtS~OIV1A~pxR9z~MHjHcH|Hc$HxQ9{~LHkHc|HxWA9~R9|LH[A\A]A^A_]ÿMu[Md|u[MdGu[du[fAWAVSII~H~~(1fH4L(HIcGIH9|HtIw[L[A^A_uVyA;Gl}ED$OGwAAH4@A;Gp}AAD$ AfDHHcH90MtLDDE s[EAAك|$ HD$pw1EDDn[w1Dn[)w1t$n[2w1n[;w1t$|n[Dw1nn[Mw1D_n[ H[A\A]A^A_]s[E1D$E1E1D$E1M'= 0int bmcg_sat_solver_minimize_assumptions(bmcg_sat_solver *, int *, int, int)nlits - pivot >= 1c restarts : %d (%d conflicts on average) c blocked restarts : %d (multiple: %d) c last block at restart : %d c nb ReduceDB : %-12d c nb removed Clauses : %-12d c nb learnts DL2 : %-12d c nb learnts size 2 : %-12d c nb learnts size 1 : %-12d c conflicts : %-12d (%.0f /sec) c decisions : %-12d (%4.2f %% random) (%.0f /sec) c propagations : %-12d (%.0f /sec) c conflict literals : %-12d (%4.2f %% deleted) c nb reduced Clauses : %-12d Memory used : %.2f MB c | Number of variables: %12d | c | Number of clauses: %12d | c Simplication removed %d variables and %d clauses. UNSATISFIABLEINDETERMINATE TimeCNF stats: Vars = %6d. Clauses = %7d. Literals = %8d. Vec_Int_t *Glucose_SolverFromAig2(Gia_Man_t *, Gluco::SimpSolver &)status == GLUCOSE_SATVec_Str_t *Glucose_GenerateCubes(bmcg_sat_solver **, Vec_Int_t *, Vec_Int_t *, int)Index >= 0 && Index < nSuppGia_ManCoNum(p) == 1Vec_Str_t *bmcg_sat_solver_sop(Gia_Man_t *, int)Gia_ManCiNum(pNew) == Vec_IntSize(vCisUsed)int bmcg_sat_solver_quantify2(Gia_Man_t *, int, int, int (*)(void *, int), void *, Vec_Int_t *)pFuncCiToKeepGia_ObjIsCand(pObj)int Gia_ManSatAndCollect_rec(Gia_Man_t *, int, Vec_Int_t *, Vec_Int_t *)void Gia_ManQuantLoadCnf(Gia_Man_t *, Vec_Int_t *, bmcg_sat_solver **)Gia_ManPiNum(pMan) == Vec_IntSize(vCiObjIds)int Gia_ManFactorSop(Gia_Man_t *, Vec_Int_t *, Vec_Str_t *, int)iVar == 0int bmcg_sat_solver_quantify(bmcg_sat_solver **, Gia_Man_t *, int, int, int (*)(void *, int), void *, Vec_Int_t *)Time1int bmcg_sat_solver_equiv_overlap_check(bmcg_sat_solver *, Gia_Man_t *, int, int, int)%s %s. EquivalenceholdsfailsVec_IntEntry(vCnfIds,Gia_ObjId(p, pObj))!=-1int Glucose_SolveAig(Gia_Man_t *, Glucose_Pars *)!inHeap(n)./src/sat/glucose/Heap.hvoid Gluco::Heap::insert(int) [Comp = Gluco::SimpSolver::ElimLt]Var >= 0 && !(c >> 1)./src/misc/util/abc_global.hint Abc_Var2Lit(int, int)%9.2f sec nSize == nAdded./src/misc/vec/vecStr.hchar *Vec_StrPrintF(Vec_Str_t *, const char *, ...)i >= 0 && i < p->nSize./src/misc/vec/vecInt.hint Vec_IntEntry(Vec_Int_t *, int)p->pArrayvoid Vec_IntGrow(Vec_Int_t *, int)p->nSize >= nSizeNewvoid Vec_IntShrink(Vec_Int_t *, int)int Abc_LitNot(int)int Abc_Lit2Var(int)int Abc_LitIsCompl(int)void Vec_IntWriteEntry(Vec_Int_t *, int, int)Vector has %d entries: {int Vec_IntAddToEntry(Vec_Int_t *, int, int)v >= 0 && v < p->nObjs./src/aig/gia/gia.hGia_Obj_t *Gia_ManObj(Gia_Man_t *, int)p->pObjs <= pObj && pObj < p->pObjs + p->nObjsint Gia_ObjId(Gia_Man_t *, Gia_Obj_t *)int Abc_LitNotCond(int, int)iLit0 >= 0 && Abc_Lit2Var(iLit0) < Gia_ManObjNum(p)int Gia_ManAppendAnd(Gia_Man_t *, int, int)iLit1 >= 0 && Abc_Lit2Var(iLit1) < Gia_ManObjNum(p)p->fGiaSimple || Abc_Lit2Var(iLit0) != Abc_Lit2Var(iLit1)p->nObjs < nObjNewGia_Obj_t *Gia_ManAppendObj(Gia_Man_t *)Extending GIA object storage: %d -> %d. p->nObjsAlloc > 0v < Gia_ManPoNum(p)Gia_Obj_t *Gia_ManPo(Gia_Man_t *, int)pObj->fTermint Gia_ObjCioId(Gia_Obj_t *)int Gia_ManAppendCo(Gia_Man_t *, int)!Gia_ObjIsCo(Gia_ManObj(p, Abc_Lit2Var(iLit0))) 1 %d N5Gluco20OutOfMemoryExceptionE-Verification FAILED.Verification passed.c ============================[ Problem Statistics ]=============================c | |Hard limit on the number of nodes (2^29) is reached. Quitting...ABC9&glucoseCpvhCommand line switch "-C" should be followed by an integer. Abc_CommandGlucose(): There is no AIG. usage: &glucose [-C num] [-pvh] run Glucose 3.0 by Gilles Audemard and Laurent Simon -C num : conflict limit [default = %d] -p : enable preprocessing [default = %d] -v : verbosity [default = %d] -h : print the command usage : (optional) CNF file to solve Error: @45AAh㈵>?@xD#B ;}Ô%IT0.++ffffff?{Gz??Y@????0.++0.++?@<incrementalUse incremental SAT solvingThe constant used to force restartThe constant used to block restartszLBDQueueThe size of moving average for LBD (restarts)szTrailQueueThe size of moving average for trail (block restarts)firstReduceDBThe number of conflicts before the first reduce DBincReduceDBIncrement for reduce DBspecialIncReduceDBSpecial increment for reduce DBminLBDFrozenClauseProtect clauses if their LBD decrease and is lower than (for one turn)minSizeMinimizingClauseThe min size required to minimize clauseminLBDMinimizingClauseThe min LBD required to minimize clausevar-decayThe variable activity decay factorcla-decayThe clause activity decay factorrnd-freqThe frequency with which the decision heuristic tries to choose a random variablernd-seedUsed by the random variable selectionccmin-modeControls conflict clause minimization (0=none, 1=basic, 2=deep)phase-savingControls the level of phase saving (0=none, 1=limited, 2=full)rnd-initRandomize the initial activityThe fraction of wasted memory allowed before a garbage collection is triggeredcertifiedCertified UNSAT using DRUP formatcertified-outputCertified UNSAT output file/dev/stdoutdecisionLevel() == 0src/sat/glucose/Glucose.cppbool Gluco::Solver::addClause_(vec &)%i c.size() > 1void Gluco::Solver::attachClause(Gluco::CRef)void Gluco::Solver::detachClause(Gluco::CRef, bool)confl != CRef_Undefvoid Gluco::Solver::analyze(Gluco::CRef, vec &, vec &, int &, unsigned int &, unsigned int &)value(c[1])==l_Truevalue(q) == l_Falsereason(var(analyze_stack.last())) != CRef_Undefbool Gluco::Solver::litRedundant(Gluco::Lit, uint32_t)level(x) > 0void Gluco::Solver::analyzeFinal(Gluco::Lit, vec &)value(p) == l_Undefvoid Gluco::Solver::uncheckedEnqueue(Gluco::Lit, Gluco::CRef)c[1] == false_litGluco::CRef Gluco::Solver::propagate()bool Gluco::Solver::simplify()Gluco::lbool Gluco::Solver::search(int)c | %8d %7d %5d | %7d %8d %8d | %5d %8d %6d %8d | %6.3f %% | learnts.size()>0c restarts : %ld c nb ReduceDB : %ld c nb removed Clauses : %ld c nb learnts DL2 : %ld c nb learnts size 2 : %ld c nb learnts size 1 : %ld c conflicts : %ld c decisions : %ld c propagations : %ld c SAT Calls : %d in %g seconds c UNSAT Calls : %d in %g seconds c | * LBD Queue : %6d | * First : %6d | * size < %3d | c | * Trail Queue : %6d | * Inc : %6d | * lbd < %3d | c | * K : %6.2f | * Special : %6d | | c | * R : %6.2f | * Protected : (lbd)< %2d | | c ==================================[ Search Statistics (every %6d conflicts) ]========================= callback_result == 0Gluco::lbool Gluco::Solver::solve_()%s%d wrcould not open file %s p cnf 1 2 1 0 -1 0 p cnf %d %d value(assumptions[i]) != l_Falsevoid Gluco::Solver::toDimacs(FILE *, const vec &)Wrote %d clauses with %d variables. | Garbage collection: %12d bytes => %12d bytes | CORE -%s, -no-%s(default: %s) %s CORE -- RESTARTERROR! value <%s> is too large for option "%s". ERROR! value <%s> is too small for option "%s". -%-12s = %-8s %c%4.2g .. %4.2g%c (default: %g) -%-12s = %-8s [imin .. imax] (default: %d) CORE -- REDUCECORE -- MINIMIZECORE -- CERTIFIED UNSAT -%-10s = %8s ./src/sat/glucose/Alloc.hvoid Gluco::RegionAllocator::capacity(uint32_t) [T = unsigned int]r >= 0 && r < szT &Gluco::RegionAllocator::operator[](Gluco::RegionAllocator::Ref) [T = unsigned int]const T *Gluco::RegionAllocator::lea(Gluco::RegionAllocator::Ref) const [T = unsigned int]void Gluco::Heap::insert(int) [Comp = Gluco::Solver::VarOrderLt]./src/sat/glucose/SolverTypes.hfloat &Gluco::Clause::activity()typename RegionAllocator::Ref Gluco::RegionAllocator::alloc(int) [T = unsigned int]T *Gluco::RegionAllocator::lea(Gluco::RegionAllocator::Ref) [T = unsigned int]nelems <= sz./src/sat/glucose/Vec.hvoid Gluco::vec::shrink(int) [T = Gluco::Lit]j < ts.size()./src/sat/glucose/Alg.hvoid Gluco::remove(V &, const T &) [V = Gluco::vec, T = Gluco::Solver::Watcher]sz > 0void Gluco::vec::pop() [T = Gluco::Solver::Watcher]void Gluco::vec::shrink(int) [T = int]index < heap.size()int Gluco::Heap::operator[](int) const [Comp = Gluco::Solver::VarOrderLt]void Gluco::vec::pop() [T = int]sz < capvoid Gluco::vec::push_(const T &) [T = Gluco::Lit]const T &Gluco::RegionAllocator::operator[](Gluco::RegionAllocator::Ref) const [T = unsigned int]void Gluco::vec::shrink(int) [T = Gluco::Solver::Watcher]void Gluco::vec::shrink(int) [T = unsigned int]last==first./src/sat/glucose/BoundedQueue.hvoid Gluco::bqueue::push(T) [T = unsigned int]@P@-A-AN5Gluco6SolverE- 4A@@AP@A@AN5Gluco10BoolOptionEN5Gluco6OptionE-X-4A`AA@7@@7@4A BA0BACAN5Gluco12DoubleOptionEX-04ACACADAN5Gluco9IntOptionEX-4AEAEAEAN5Gluco12StringOptionEX-c---------- Glucose Stats -------------------------c--------------------------------------------------c ========================================[ MAGIC CONSTANTS ]==============================================c | Constants are supposed to work well together :-) |c | however, if you find better choices, please let us known... |c |-------------------------------------------------------------------------------------------------------|c | - Restarts: | - Reduce Clause DB: | - Minimize Asserting: |c | | | |c | |c | RESTARTS | ORIGINAL | LEARNT | Progress |c | NB Blocked Avg Cfc | Vars Clauses Literals | Red Learnts LBD2 Removed | |c =========================================================================================================Can not use incremental and certified unsat in the same timeERROR! Unknown flag "%s". Use '--%shelp' for help. %s OPTIONS: HELP OPTIONS: --%shelp Print help message. --%shelp-verb Print verbose help message. 0C0E0C0E>asymmShrink clauses by asymmetric branching.rcheckCheck if a clause is already implied. (costly)elimPerform variable elimination.growAllow a variable elimination step to grow by a number of clauses.cl-limVariables are not eliminated if it produces a resolvent with a length above this limit. -1 means no limitsub-limDo not check if subsumption against a clause larger than this. -1 means no limit.simp-gc-fracThe fraction of wasted memory allowed before a garbage collection is triggered during simplification.!isEliminated(v)src/sat/glucose/SimpSolver.cppGluco::lbool Gluco::SimpSolver::solve_(bool, bool)!isEliminated(var(ps[i]))bool Gluco::SimpSolver::addClause_(vec &)bool Gluco::SimpSolver::strengthenClause(Gluco::CRef, Gluco::Lit)use_simplificationbool Gluco::SimpSolver::implied(const vec &)value(c[i]) == l_Undefbool Gluco::SimpSolver::backwardSubsumptionCheck(bool)subsumption left: %10d (%10d subsumed, %10d deleted literals) c.size() > 1 || value(c[0]) == l_Truebool Gluco::SimpSolver::asymm(Gluco::Var, Gluco::CRef)bool Gluco::SimpSolver::asymmVar(Gluco::Var)!frozen[v]bool Gluco::SimpSolver::eliminateVar(Gluco::Var)value(v) == l_Undefbool Gluco::SimpSolver::substitute(Gluco::Var, Gluco::Lit)bwdsub_assigns == trail.size()bool Gluco::SimpSolver::eliminate(bool)subsumption_queue.size() == 0n_touched == 0elimination left: %10d c | Eliminated clauses: %10.2f Mb | SIMP./src/sat/glucose/SimpSolver.hvoid Gluco::SimpSolver::updateElimHeap(Gluco::Var)void Gluco::remove(V &, const T &) [V = Gluco::Clause, T = Gluco::Lit]i <= size()void Gluco::Clause::shrink(int)void Gluco::Clause::calcAbstraction()!header.learntGluco::Lit Gluco::Clause::subsumes(const Gluco::Clause &) const!other.header.learntother.header.has_extrav_pos != -1void mkElimClause(vec &, Gluco::Var, Gluco::Clause &)void Gluco::remove(V &, const T &) [V = Gluco::vec, T = unsigned int]void Gluco::vec::pop() [T = unsigned int]./src/sat/glucose/Queue.hT &Gluco::Queue::operator[](int) [T = unsigned int]index < size()first != endT Gluco::Queue::peek() const [T = unsigned int]0cAeAAAN5Gluco10SimpSolverEX-===============================================================================c Too many clauses... No preprocessing/proc/%d/statmrb/proc/%d/statusVmPeak: %d kBERROR! Failed to parse memory statistics from "/proc".pNtkAig->vObjs->nSize == 0src/base/abc/abcAig.cAbc_Aig_t *Abc_AigAlloc(Abc_Ntk_t *)Vec_PtrSize( pMan->vStackReplaceOld ) == 0void Abc_AigFree(Abc_Aig_t *)Vec_PtrSize( pMan->vStackReplaceNew ) == 0Abc_AigCheck: Node "%s" has level that does not agree with the fanin levels. Abc_AigCheck: Node "%s" is not in the structural hashing table. Abc_AigCheck: Representative %s of choice node %s has %d fanouts. int Abc_AigLevel(Abc_Ntk_t *)Abc_ObjRegular(p0)->pNtk->pManFunc == pManAbc_Obj_t *Abc_AigAndLookup(Abc_Aig_t *, Abc_Obj_t *, Abc_Obj_t *)Abc_ObjRegular(p1)->pNtk->pManFunc == pManCounter == pMan->nEntriesvoid Abc_AigRehash(Abc_Aig_t *)Abc_Obj_t *Abc_AigConst1(Abc_Ntk_t *)vPairs->nSize % 2 == 0Abc_Obj_t *Abc_AigMiter(Abc_Aig_t *, Vec_Ptr_t *, int)Abc_Obj_t *Abc_AigMiter2(Abc_Aig_t *, Vec_Ptr_t *)Vec_PtrSize(pMan->vStackReplaceOld) == 0void Abc_AigReplace(Abc_Aig_t *, Abc_Obj_t *, Abc_Obj_t *, int)Vec_PtrSize(pMan->vStackReplaceNew) == 0!Abc_ObjIsComplement(pOld)void Abc_AigDeleteNode(Abc_Aig_t *, Abc_Obj_t *)Abc_ObjFaninNum(pNode) == 2Abc_ObjFanoutNum(pNode) == 0iFanin >= 0int Abc_AigNodeHasComplFanoutEdge(Abc_Obj_t *)int Abc_AigNodeHasComplFanoutEdgeTrav(Abc_Obj_t *)CI %4s%s. Constant 1 %s. (complemented)%7s%s * Node %d has incorrect ordering of fanins. Abc_NtkIsDfsOrdered(pNtk)void Abc_AigSetNodePhases(Abc_Ntk_t *)pMan->vAddedCells == NULLVec_Ptr_t *Abc_AigUpdateStart(Abc_Aig_t *, Vec_Ptr_t **)pMan->vAddedCells != NULLvoid Abc_AigUpdateStop(Abc_Aig_t *)void Abc_AigUpdateReset(Abc_Aig_t *)Counter = %d. Nodes = %d. Ave = %6.2f ./src/misc/vec/vecVec.hVec_Ptr_t *Vec_VecEntry(Vec_Vec_t *, int)./src/misc/vec/vecPtr.hAbc_NtkIsStrash(Abc_ObjRegular(pNode)->pNtk)int Abc_AigNodeIsConst(Abc_Obj_t *)int Abc_AigNodeIsChoice(Abc_Obj_t *)void Abc_AigResize(Abc_Aig_t *)p->nSize > 0void *Vec_PtrPop(Vec_Ptr_t *)void Abc_AigReplace_int(Abc_Aig_t *, Abc_Obj_t *, Abc_Obj_t *, int)Abc_ObjFanoutNum(pOld) > 0iFanin == 0 || iFanin == 1Abc_ObjRegular(pFanin1) != pFanoutAbc_ObjRegular(pFanin2) != pFanoutAbc_ObjRegular(pFanin1) != Abc_ObjRegular(pFanin2)Abc_AigNodeIsAcyclic(pFanout, pFanout)pFanout->fMarkA == 0pFanout->fMarkB == 0!Abc_ObjIsComplement(pAnd)Abc_Obj_t *Abc_AigAndCreateFrom(Abc_Aig_t *, Abc_Obj_t *, Abc_Obj_t *, Abc_Obj_t *)!Abc_ObjIsComplement(pThis)void Abc_AigAndDelete(Abc_Aig_t *, Abc_Obj_t *)Abc_ObjIsNode(pThis)Abc_ObjFaninNum(pThis) == 2pMan->pNtkAig == pThis->pNtkpAnd == pThisvoid Abc_AigUpdateLevel_int(Abc_Aig_t *)(int)pNode->Level == ipNode->fMarkA == 1LevelNew > ivoid Abc_AigUpdateLevelR_int(Abc_Aig_t *)Abc_ObjReverseLevel(pNode) == ipNode->fMarkB == 1pFanin->fMarkB == 0pNode->fMarkAvoid Abc_AigRemoveFromLevelStructure(Vec_Vec_t *, Abc_Obj_t *)m < Vec_PtrSize(vVecTemp)pNode->fMarkBvoid Abc_AigRemoveFromLevelStructureR(Vec_Vec_t *, Abc_Obj_t *)i >=0 && i < 2int Abc_ObjFaninC(Abc_Obj_t *, int)int Abc_AigNodeIsAnd(Abc_Obj_t *)Abc_ObjIsLatch(pLatch)int Abc_LatchIsInit1(Abc_Obj_t *)Hello, World!Abc_AigCheck: The number of nodes in the structural hashing table is wrong.Abc_AigCheck: The AIG has non-standard nodes.Abc_AigCheck: The AIG has single input nodes.Abc_AigCheck: The AIG has non-standard constant nodes.B"BBBBjB4BNetwork "%s" contains %d flops. Network "%s" contains box "%s" whose model "%s" is instantiated more than once. Abc_ObjIsNet(pNet)src/base/abc/abcBarBuf.cint Abc_NtkCollectPiPos_rec(Abc_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *)int Abc_NtkCollectPiPos(Abc_Ntk_t *, Vec_Ptr_t **, Vec_Ptr_t **)Abc_Obj_t *Abc_NtkToBarBufs_rec(Abc_Ntk_t *, Abc_Obj_t *)Abc_Ntk_t *Abc_NtkToBarBufs(Abc_Ntk_t *)pNtk->pDesign != NULL_%s_in_%s_outAbc_ObjIsNet(Abc_ObjFanout0(pLoMap))Hierarchy reader flattened %d instances of logic boxes and introduced %d barbufs. pNtkBase->pDesign != NULLAbc_Ntk_t *Abc_NtkFromBarBufs(Abc_Ntk_t *, Abc_Ntk_t *)Abc_NtkIsNetlist(pNtkBase)Abc_NtkLatchNum(pNtkBase) == 0Abc_NtkLatchNum(pNtk) == pNtk->nBarBufsAbc_NtkWhiteboxNum(pNtk) == 0Abc_NtkBlackboxNum(pNtk) == 0Abc_NtkPiNum(pNtk) == Abc_NtkPiNum(pNtkBase)Abc_NtkPoNum(pNtk) == Abc_NtkPoNum(pNtkBase)Vec_PtrEntry(pNtkNew->pDesign->vTops, 0) == pNtkNewVec_PtrSize(vLiMaps) == Abc_NtkLatchNum(pNtk)Vec_PtrSize(vLoMaps) == Abc_NtkLatchNum(pNtk)void Abc_NtkToBarBufsCollect_rec(Abc_Obj_t *, Vec_Ptr_t *)Vec_Ptr_t *Abc_NtkToBarBufsCollect(Abc_Ntk_t *)pNtk->nBarBufs > 0pNtk->nBarBufs == Abc_NtkLatchNum(pNtk)Vec_PtrSize(vNodes) == Abc_NtkObjNum(pNtk)Abc_Ntk_t *Abc_NtkBarBufsToBuffers(Abc_Ntk_t *)pNtk->pDesign == NULLAbc_NtkIsLogic(pNtkBase)Abc_Ntk_t *Abc_NtkBarBufsFromBuffers(Abc_Ntk_t *, Abc_Ntk_t *)pNtkBase->nBarBufs == Abc_NtkLatchNum(pNtkBase)nBarBufs == pNtkBase->nBarBufsvoid *Vec_PtrEntry(Vec_Ptr_t *, int)pObj->Type == ABC_OBJ_WHITEBOXAbc_Ntk_t *Abc_ObjModel(Abc_Obj_t *)p->nTravIds < (1<<30)void Abc_NtkIncrementTravId(Abc_Ntk_t *)Abc_NtkMvVar(pNtk) == NULLsrc/base/abc/abcBlifMv.cvoid Abc_NtkStartMvVars(Abc_Ntk_t *)nValues > 1void Abc_NtkSetMvVarValues(Abc_Obj_t *, int)int Abc_NodeStrashBlifMv(Abc_Ntk_t *, Abc_Obj_t *)Index < nValuesfree_var_DefIndex < Abc_ObjFaninNum(pObj)Def < nValues*pSop == '\n'Abc_NodeStrashBlifMv(): Cannot handle complement in the MV function of node %s. Abc_NodeStrashBlifMv(): Cannot handle braces in the MV function of node %s. Index < nValuesF*pSop == ')' || *pSop == ','Index != knValuesF == nValuesF2*pSop == ' 'nValuesF == nValuesDefIndex >= 0Abc_Ntk_t *Abc_NtkStrashBlifMv(Abc_Ntk_t *)Abc_NtkHasBlifMv(pNtk)Vec_PtrSize(vTemp) == Vec_PtrSize(pNtkNew->vPis)Vec_PtrSize(vTemp) == Vec_PtrSize(pNtkNew->vCis)nCount1 == nCount2Abc_NtkStrashBlifMv(): Network check has failed. Abc_Ntk_t *Abc_NtkSkeletonBlifMv(Abc_Ntk_t *)pNet->pCopy == NULLAbc_NtkSkeletonBlifMv(): Network check has failed. Abc_Ntk_t *Abc_NtkInsertBlifMv(Abc_Ntk_t *, Abc_Ntk_t *)Abc_NtkHasBlifMv(pNtkBase)Abc_NtkWhiteboxNum(pNtkBase) == 0Abc_NtkBlackboxNum(pNtkBase) == 0Abc_NtkIsNetlist(pNtkLogic)Abc_NtkHasBlifMv(pNtkLogic)Abc_NtkWhiteboxNum(pNtkLogic) == 0Abc_NtkBlackboxNum(pNtkLogic) == 0Abc_NtkWhiteboxNum(pNtkSkel) == 1Abc_ObjIsWhitebox(pBox)pBox->pData == NULLAbc_ObjFaninNum(pBox) == Abc_NtkPiNum(pNtkLogic)Abc_ObjFanoutNum(pBox) == Abc_NtkPoNum(pNtkLogic)int Abc_NtkConvertToBlifMv(Abc_Ntk_t *)pCur - pBlifMv == nSizechar *Abc_NodeConvertSopToMvSop(int, Vec_Int_t *, Vec_Int_t *)pCur - pMvSop == nSizevoid Vec_PtrWriteEntry(Vec_Ptr_t *, int, void *)p->pArrayPtr./src/misc/vec/vecAtt.hvoid *Vec_AttEntry(Vec_Att_t *, int)void Vec_AttWriteEntry(Vec_Att_t *, int, void *)p->pFuncStartObj == NULL*pStr >= '0' && *pStr <= '9'int Abc_StringGetNumber(char **)Abc_ObjIsTerm(pObj)void Abc_NtkConvertAssignName(Abc_Obj_t *, Abc_Obj_t *, int)void Abc_LatchSetInit0(Abc_Obj_t *)Converting logic functions to BDDs has failed.NetworkCheck: Unknown network type. NetworkCheck: Unknown functionality type. NetworkCheck: The library of the mapped network is not the global library. NetworkCheck: Number of CIs does not match number of PIs and latches. One possible reason is that latches are added twice: in procedure Abc_NtkCreateObj() and in the user's code. NetworkCheck: Number of COs does not match number of POs, asserts, and latches. NetworkCheck: Warning! Netlist has no nets. NetworkCheck: A network that is not a netlist has nets. NetworkCheck: Network contains a combinational loop. NetworkCheck: Object "%s" does not belong to the network. NetworkCheck: Object "%s" has incorrect ID. checkfioNodeCheck: Object "%s" has fanin "%s" but the fanin does not have it as a fanout. NodeCheck: Object "%s" has fanout "%s" but the fanout does not have it as a fanin. Warning: Node %s has duplicated fanin %s. duplicated fanout %s. Abc_NtkHasOnlyLatchBoxes(pNtk1)src/base/abc/abcCheck.cint Abc_NtkCompareBoxes(Abc_Ntk_t *, Abc_Ntk_t *, int)Abc_NtkHasOnlyLatchBoxes(pNtk2)Box #%d is different in network 1 ( "%s") and in network 2 ("%s"). int Abc_NtkIsAcyclicHierarchy_rec(Abc_Ntk_t *)pNtkNext != NULLAbc_NtkIsNetlist(pNtk) && pNtk->pDesignint Abc_NtkIsAcyclicHierarchy(Abc_Ntk_t *)int Abc_NtkCheckUniqueCiNames(Abc_Ntk_t *)Abc_NtkCheck: Repeated CI names: %s and %s. int Abc_NtkCheckUniqueCoNames(Abc_Ntk_t *)Abc_NtkCheck: Repeated CO names: %s and %s. int Abc_NtkCheckUniqueCioNames(Abc_Ntk_t *)!strcmp( Abc_ObjName(pObj), Abc_ObjName(pObjCi) )Abc_NtkCheck: A CI/CO pair share the name (%s) but do not link directly. The name of the CO fanin is %s. NetworkCheck: CI with ID %d is in the network but not in the name table. NetworkCheck: CO with ID %d is in the network but not in the name table. int Abc_NtkCheckNames(Abc_Ntk_t *)NetworkCheck: Object with ID %d is deleted but its name "%s" remains in the name table. NetworkCheck: Object "%s" (id=%d) is in the PI list but is not a PI. NetworkCheck: A PI "%s" has a logic function. NetworkCheck: A PI "%s" has fanins. NetworkCheck: Object "%s" (id=%d) is a PI but is not in the PI list. NetworkCheck: Net "%s" (id=%d) is in the PO list but is not a PO. NetworkCheck: A PO "%s" has a logic function. NetworkCheck: A PO "%s" does not have one fanin (but %d). NetworkCheck: A PO "%s" has %d fanout(s). NetworkCheck: Net "%s" (id=%d) is in a PO but is not in the PO list. NetworkCheck: Net "%s" is not driven. NetworkCheck: Net "%s" has more than one driver. Node (id = %d) has no net to drive. NodeCheck: An internal node "%s" does not have a logic function. NodeCheck: SOP check for node "%s" has failed. NodeCheck: BDD of the node "%s" has incorrect support size. int Abc_NtkCheckNode(Abc_Ntk_t *, Abc_Obj_t *)NodeCheck: Latch "%s" has incorrect reset value (%d). NodeCheck: Latch "%s" has wrong number (%d) of fanins. NodeCheck: Latch "%s" has wrong number (%d) of fanouts. NodeCheck: Input of latch "%s" has wrong number (%d) of fanins. NodeCheck: Input of latch "%s" has wrong number (%d) of fanouts. NodeCheck: Output of latch "%s" has wrong number (%d) of fanins. Primary input #%d is different in network 1 ( "%s") and in network 2 ("%s"). Primary output #%d is different in network 1 ( "%s") and in network 2 ("%s"). Networks have different number of latches.Networks have different number of primary inputs.Networks have different number of primary outputs.BBBBBBB!Abc_ObjIsNet(pNode)src/base/abc/abcDfs.cvoid Abc_NtkDfs_rec(Abc_Obj_t *, Vec_Ptr_t *)Abc_ObjIsNode( pNode ) || Abc_ObjIsBox( pNode )void Abc_NtkDfsReverse_rec(Abc_Obj_t *, Vec_Ptr_t *)Abc_ObjIsNode( pNode )void Abc_NtkDfsReverseNodes_rec(Abc_Obj_t *, Vec_Ptr_t *)Vec_Ptr_t *Abc_NtkDfsReverseNodes(Abc_Ntk_t *, Abc_Obj_t **, int)Vec_Ptr_t *Abc_NtkDfsReverseNodesContained(Abc_Ntk_t *, Abc_Obj_t **, int)pObj->Level == 0Vec_Ptr_t *Abc_NtkDfsSeq(Abc_Ntk_t *)Vec_Ptr_t *Abc_NtkDfsSeqReverse(Abc_Ntk_t *)void Abc_NtkDfs_iter(Vec_Ptr_t *, Abc_Obj_t *, Vec_Ptr_t *)void Abc_NtkDfsNets_rec(Abc_Obj_t *, Vec_Ptr_t *)void Abc_NtkDfsWithBoxes_rec(Abc_Obj_t *, Vec_Ptr_t *)Abc_ObjIsNet(pFanin)Abc_ObjIsNet(Abc_ObjFanin0(pObj))Vec_Ptr_t *Abc_NtkDfsWithBoxes(Abc_Ntk_t *)void Abc_NtkNodeSupport_rec(Abc_Obj_t *, Vec_Ptr_t *)Vec_PtrSize(vNodes) == Abc_NtkCiNum(pNtk)Vec_Ptr_t *Abc_NtkSupport(Abc_Ntk_t *)void Abc_NtkNodeSupportInt_rec(Abc_Obj_t *, Vec_Int_t *)int Abc_NtkFunctionalIsoGia_rec(Gia_Man_t *, Abc_Obj_t *)Vec_IntSize(vSupp1) == Vec_IntSize(vSupp2)Gia_Man_t *Abc_NtkFunctionalIsoGia(Abc_Ntk_t *, int, int, int)int Abc_NtkFunctionalIsoInt(Abc_Ntk_t *, int, int, int)Abc_ObjIsNode(pObj) || Abc_ObjIsBox(pObj)int Abc_ObjSuppSize_rec(Abc_Obj_t *)Nodes with small support %d (out of %d) Total supports = %d. void Abc_AigDfs_rec(Abc_Obj_t *, Vec_Ptr_t *)Vec_Ptr_t *Abc_AigDfs(Abc_Ntk_t *, int, int)Vec_Ptr_t *Abc_AigDfsMap(Abc_Ntk_t *)Abc_ObjIsLatch(Abc_ObjFanout0(pNode))void Abc_DfsLevelizedTfo_rec(Abc_Obj_t *, Vec_Vec_t *)fTfi == 0Vec_Vec_t *Abc_DfsLevelized(Abc_Obj_t *, int)!Abc_NtkIsNetlist(pNode->pNtk)int Abc_NtkLevel_rec(Abc_Obj_t *)Abc_ObjIsNode( pNode ) || pNode->Type == ABC_OBJ_CONST1int Abc_NtkLevelReverse_rec(Abc_Obj_t *)(int)pObj->Level <= nLevelsVec_Vec_t *Abc_NtkLevelize(Abc_Ntk_t *)int Abc_NtkIsAcyclic_rec(Abc_Obj_t *)!Abc_NodeIsTravIdPrevious(pNode)Network "%s" contains combinational loop! Node "%s" is encountered twice on the following path to the COs: pFanin->pNtk == pNode->pNtk %s -> (choice of %s) -> CO "%s" int Abc_NtkIsAcyclicWithBoxes_rec(Abc_Obj_t *)Abc_ObjIsNode(pNode) || Abc_ObjIsBox(pNode)Box "%s" is encountered twice on the following path to the COs: Abc_ObjIsNode(pFanin) || Abc_ObjIsBox(pFanin) PO "%s" int Abc_AigSetChoiceLevels(Abc_Ntk_t *)Vec_Ptr_t *Abc_AigGetLevelizedOrder(Abc_Ntk_t *, int)int Abc_NtkPrintSubraphSizes(Abc_Ntk_t *)!Abc_ObjIsComplement(pObj)src/base/abc/abcFanio.cvoid Abc_ObjAddFanin(Abc_Obj_t *, Abc_Obj_t *)pObj->pNtk == pFaninR->pNtkpObj->Id >= 0 && pFaninR->Id >= 0!Abc_ObjIsPi(pObj) && !Abc_ObjIsPo(pFaninR)!Abc_ObjIsCo(pObj) || !Abc_ObjFaninNum(pObj)!Abc_ObjIsNet(pObj) || !Abc_ObjFaninNum(pObj)void Abc_ObjDeleteFanin(Abc_Obj_t *, Abc_Obj_t *)!Abc_ObjIsComplement(pFanin)pObj->pNtk == pFanin->pNtkpObj->Id >= 0 && pFanin->Id >= 0The obj %d is not found among the fanins of obj %d ... The obj %d is not found among the fanouts of obj %d ... vFaninsOld->nSize == 0void Abc_ObjRemoveFanins(Abc_Obj_t *)void Abc_ObjPatchFanin(Abc_Obj_t *, Abc_Obj_t *, Abc_Obj_t *)!Abc_ObjIsComplement(pFaninOld)pFaninOld != pFaninNewRpObj->pNtk == pFaninOld->pNtkpObj->pNtk == pFaninNewR->pNtkNode %s is not among the fanins of node %s... the fanouts of its old fanin %s... k < Vec_IntSize(&pFanout->vFanins)void Abc_ObjPatchFanoutFanin(Abc_Obj_t *, int) the fanouts of node %s... !Abc_ObjIsComplement(pNodeFrom)void Abc_ObjTransferFanout(Abc_Obj_t *, Abc_Obj_t *)!Abc_ObjIsComplement(pNodeTo)!Abc_ObjIsPo(pNodeFrom) && !Abc_ObjIsPo(pNodeTo)pNodeFrom->pNtk == pNodeTo->pNtkpNodeFrom != pNodeTo!Abc_ObjIsNode(pNodeFrom) || Abc_ObjFanoutNum(pNodeFrom) > 0Abc_ObjFanoutNum(pNodeFrom) == 0Abc_ObjFanoutNum(pNodeTo) == nFanoutsOld + vFanouts->nSize!Abc_ObjIsComplement(pNodeOld)void Abc_ObjReplace(Abc_Obj_t *, Abc_Obj_t *)!Abc_ObjIsComplement(pNodeNew)pNodeOld->pNtk == pNodeNew->pNtkpNodeOld != pNodeNewAbc_ObjFanoutNum(pNodeOld) > 0Abc_NtkIsLogic(pNode->pNtk)void Abc_ObjReplaceByConstant(Abc_Obj_t *, int)!Abc_ObjIsCo(pNode)void Abc_ObjSetFaninC(Abc_Obj_t *, int)int Vec_IntRemove(Vec_Int_t *, int)void Abc_ObjXorFaninC(Abc_Obj_t *, int)Abc_NtkHasSop(pNtk)src/base/abc/abcFanOrder.cvoid Abc_NtkOrderFaninsById(Abc_Ntk_t *)nVars == Abc_ObjFaninNum(pNode)void Abc_NtkOrderFaninsBySortingColumns(Abc_Ntk_t *)void Abc_NtkOrderFaninsByLitCount(Abc_Ntk_t *)void Abc_NtkOrderFaninsByLitCountAndCubeCount(Abc_Ntk_t *)nCubes > 1void Abc_NodeSplitLarge(Abc_Obj_t *)void Abc_NtkSplitLarge(Abc_Ntk_t *, int, int)pCube[nVars] == ' 'void Abc_NodeSortCubes(Abc_Obj_t *, Vec_Ptr_t *, Vec_Str_t *, int)pCube[nVars] == 0void Abc_NtkSortCubes(Abc_Ntk_t *, int)Counter > 1void Abc_NodeCheckDist1Free(Abc_Obj_t *)int Abc_NtkMakeLegit(Abc_Ntk_t *)%d nodes were made dist1-cube-free and/or single-cube-containment-free. char *Vec_StrEntryP(Vec_Str_t *, int)fCont21 || fCont12int Abc_CubeContain(char *, char *, int)Warning: BCBCBC CCCCCCCC{CCCCCCCC{CC$DCDCDCDC-DCDCsrc/base/abc/abcFunc.cint Abc_NtkSopToBdd(Abc_Ntk_t *)pNode->pDataiVar == Abc_ObjFaninNum(pNode)bFuncOn == bFuncOnDc || Cudd_bddLeq( dd, bFuncOn, bFuncOnDc )char *Abc_ConvertBddToSop(Mem_Flex_t *, DdManager *, DdNode *, DdNode *, int, int, Vec_Str_t *, int)fAllPrimes == 0The number of cubes exceeded the predefined limit (%d). !Cudd_ReorderingStatus(dd, (Cudd_ReorderingType *)&nCubes)int Abc_NtkBddToSop(Abc_Ntk_t *, int, int)Abc_NtkHasBdd(pNtk)Node %d with level %d has %d fanins but its SOP has support size %d. Abc_ObjFaninNum(pNode) == Abc_SopGetVarNum((char *)pNode->pNext)Index < nFaninsvoid Abc_ConvertZddToSop_rec(DdManager *, DdNode *, char *, int, Vec_Str_t *, int, int *)Abc_NtkHasBdd(pNode->pNtk)void Abc_NodeBddToCnf(Abc_Obj_t *, Mem_Flex_t *, Vec_Str_t *, int, char **, char **)void Abc_NtkLogicMakeDirectSops(Abc_Ntk_t *)!Abc_SopIsComplement((char *)pNode->pData)Abc_NtkHasAig(pNtk)int Abc_NtkAigToBdd(Abc_Ntk_t *)Hop_ManPiNum(pMan) >= nFaninsMax!Hop_IsComplement(pObj)void Abc_ConvertAigToBdd_rec1(DdManager *, Hop_Obj_t *)!Hop_ObjIsMarkA(pObj)void Abc_ConvertAigToBdd_rec2(DdManager *, Hop_Obj_t *)int Abc_NtkSopToAig(Abc_Ntk_t *)void Abc_ConvertAigToGia_rec1(Gia_Man_t *, Hop_Obj_t *)void Abc_ConvertAigToGia_rec2(Hop_Obj_t *)!Hop_IsComplement(pRoot)int Abc_ConvertAigToGia(Gia_Man_t *, Hop_Obj_t *)Abc_NtkIsAigLogic(p)Gia_Man_t *Abc_NtkAigToGia(Abc_Ntk_t *, int)!Abc_ObjFaninC0(pNode)Abc_ObjFaninNum(pNode) <= Hop_ManPiNum(pHopMan)Gia_ManObjNum(pNew) <= nObjspNew->vMapping == NULLvoid Abc_ConvertAigToAig_rec(Abc_Ntk_t *, Hop_Obj_t *)pFanin->pCopy != NULLAbc_Obj_t *Abc_ConvertAigToAig(Abc_Ntk_t *, Abc_Obj_t *)int Abc_NtkMapToSop(Abc_Ntk_t *)pNtk->pManFunc == Abc_FrameReadLibGen()Abc_SopGetVarNum(pSop) == Abc_ObjFaninNum(pNode)!Abc_NtkIsStrash(pNtk)int Abc_NtkToSop(Abc_Ntk_t *, int, int)int Abc_NtkToBdd(Abc_Ntk_t *)int Abc_NtkToAig(Abc_Ntk_t *)iLit >= 0 && Abc_Lit2Var(iLit) < Gia_ManObjNum(p)int Gia_ManAppendBuf(Gia_Man_t *, int)Abc_NtkSopToBdd: Error while converting SOP into BDD.Abc_NtkAigToBdd: Error while converting AIG into BDD.Warning: The network has only constant nodes.Abc_NtkSopToAig: Error while converting SOP into AIG.Abc_NtkBoxNum(pNtk) == 1src/base/abc/abcHie.cvoid Abc_NtkFlattenLogicHierarchy2_rec(Abc_Ntk_t *, Abc_Ntk_t *, int *)Abc_ObjFaninNum(pObj->pCopy) == Abc_NtkPiNum(pNtk)Abc_ObjFanoutNum(pObj->pCopy) == Abc_NtkPoNum(pNtk)abc_propertyAbc_ObjFaninNum(pObj) == Abc_NtkPiNum(pNtkModel)Abc_ObjFanoutNum(pObj) == Abc_NtkPoNum(pNtkModel)Abc_Ntk_t *Abc_NtkFlattenLogicHierarchy2(Abc_Ntk_t *)Hierarchy reader flattened %d instances of logic boxes and left %d black boxes. Vec_PtrEntry(pNtk->pDesign->vTops, 0) == pNtkAbc_NtkFlattenLogicHierarchy2(): Network check has failed. void Abc_NtkFlattenLogicHierarchy_rec(Abc_Ntk_t *, Abc_Ntk_t *, int *, Vec_Str_t *)Num >= 0 && Num < Vec_PtrSize(vMods)void Abc_NtkPrintBoxInfo(Abc_Ntk_t *)MODULE PI=%6d PO=%6d BB=%6d ND=%6d Lev=%5d %15d : %s MODULE Abc_Ntk_t *Abc_NtkFlattenLogicHierarchy(Abc_Ntk_t *)Abc_NtkFlattenLogicHierarchy(): Network check has failed. Abc_Ntk_t *Abc_NtkConvertBlackboxes(Abc_Ntk_t *)Abc_ObjFanoutNum(pTerm) <= 1Abc_NtkConvertBlackboxes(): Network check has failed. Abc_NtkIsNetlist(pNtkH)Abc_Ntk_t *Abc_NtkInsertNewLogic(Abc_Ntk_t *, Abc_Ntk_t *)Abc_NtkWhiteboxNum(pNtkH) == 0Abc_NtkBlackboxNum(pNtkH) > 0Abc_NtkIsNetlist(pNtkL)Abc_NtkWhiteboxNum(pNtkL) == 0Abc_NtkBlackboxNum(pNtkL) == 0Error in Abc_NtkInsertNewLogic(): There is no PI corresponding to the PI %s. Error in Abc_NtkInsertNewLogic(): Primary input %s is repeated twice. Error in Abc_NtkInsertNewLogic(): There is no PI corresponding to the inpout %s of blackbox %s. Error in Abc_NtkInsertNewLogic(): Box output %s is repeated twice. Error in Abc_NtkInsertNewLogic(): There is no PO corresponding to the PO %s. There is no PO corresponding to the input %s of blackbox %s. Vec_PtrEntry( pDesign->vModules, 0 ) == pNtkHAbc_NtkInsertNewLogic(): Network check has failed. char Vec_StrPop(Vec_Str_t *)void Vec_StrShrink(Vec_Str_t *, int)EXDC is not transformed.src/base/abc/abcHieCec.cvoid Abc_NtkDfsBoxes_rec(Abc_Obj_t *, Vec_Ptr_t *)Vec_Ptr_t *Abc_NtkDfsBoxes(Abc_Ntk_t *)Abc_ObjFanout0(pTerm)->iTemp >= 0void Abc_NtkDeriveFlatGia_rec(Gia_Man_t *, Abc_Ntk_t *)Abc_ObjFaninNum(pObj) <= 16Abc_ObjFaninNum(pObj) == Abc_SopGetVarNum(pSop)gFanins[k] >= 0Abc_ObjFanin0(pTerm)->iTemp >= 0Gia_Man_t *Abc_NtkDeriveFlatGia(Abc_Ntk_t *)!Abc_NtkLatchNum(pNtk)int Abc_NtkCountAndNodes(Vec_Ptr_t *)Gia_Man_t *Abc_NtkDeriveFlatGia2Derive(Abc_Ntk_t *, Vec_Ptr_t *)Abc_ObjFaninNum(pObj) == Gia_ManPiNum(pGiaBox)Abc_ObjFanoutNum(pObj) == Gia_ManPoNum(pGiaBox)%8d -> Vec_Ptr_t *Abc_NtkCollectHie(Abc_Ntk_t *)Instances = %10d. Nodes = %.0f int Abc_NtkCheckRecursive(Abc_Ntk_t *)WARNING: Model "%s" contains a recursive definition. Reading fileGia_Man_t *Abc_NtkHieCecTest(char *, int)Abc_ObjIsPo(pObj) || Abc_ObjIsNode(pObj)Abc_Obj_t *Abc_ObjFaninReal(Abc_Obj_t *, int)v < Gia_ManPiNum(p)Gia_Obj_t *Gia_ManPi(Gia_Man_t *, int)There is no hierarchy information.Reading BLIF file has failed.C|C|CC|CbCsrc/base/abc/abcHieGia.cvoid Abc_NodeStrashToGia_rec(Gia_Man_t *, Hop_Obj_t *)int Abc_NodeStrashToGia(Gia_Man_t *, Abc_Obj_t *)Abc_NtkHasAig(pNode->pNtk) && !Abc_NtkIsStrash(pNode->pNtk)pFanin->iTemp != -1!Abc_ObjIsLatch(pObj)void Abc_NtkFlattenHierarchyGia2_rec(Gia_Man_t *, Abc_Ntk_t *, int *, Vec_Int_t *)Abc_NtkPiNum(pModel) == Abc_ObjFaninNum(pObj)Abc_NtkPoNum(pModel) == Abc_ObjFanoutNum(pObj)Abc_ObjIsNet(Abc_ObjFanin0(pTerm))Abc_ObjIsNet(Abc_ObjFanout0(pTerm))Gia_Man_t *Abc_NtkFlattenHierarchyGia2(Abc_Ntk_t *)Hierarchy reader flattened %d instances of logic boxes. void Gia_ManPrintBarBufDrivers(Gia_Man_t *)Detected %d const (out of %d) and %d shared (out of %d) barbufs with fanout. !Abc_ObjIsLatch(pBox)int Gia_ManFlattenLogicPrepare(Abc_Ntk_t *)Abc_ObjFaninNum(pBox) == Abc_NtkPiNum(pModel)int Abc_NtkFlattenHierarchyGia_rec(Gia_Man_t *, Vec_Ptr_t *, Abc_Obj_t *, Vec_Ptr_t *)pObj->iData >= 0 && pObj->iData < Abc_NtkPiNum(pModel)Abc_ObjIsBox(pBox)Abc_ObjFanoutNum(pBox) == Abc_NtkPoNum(pModel)pObj->iData >= 0 && pObj->iData < Abc_NtkPoNum(pModel)Gia_Man_t *Abc_NtkFlattenHierarchyGia(Abc_Ntk_t *, Vec_Ptr_t **, int)Hierarchy reader flattened %d instances of boxes and added %d barbufs (out of %d). Abc_ObjNtk(pObj) == pNewAbc_Obj_t *Gia_ManInsertOne_rec(Abc_Ntk_t *, Abc_Ntk_t *, Abc_Obj_t *)!Abc_NtkHasMapping(pNtk)void Gia_ManInsertOne(Abc_Ntk_t *, Abc_Ntk_t *)Abc_NtkHasMapping(pNew)!pObj->pCopy || Abc_ObjNtk(pObj->pCopy) == pNewGia_ManPiNum(pGia) == Abc_NtkPiNum(pNtk)void Abc_NtkInsertHierarchyGia(Abc_Ntk_t *, Abc_Ntk_t *, int)Gia_ManPiNum(pGia) == Abc_NtkPiNum(pNew)Gia_ManPoNum(pGia) == Abc_NtkPoNum(pNtk)Gia_ManPoNum(pGia) == Abc_NtkPoNum(pNew)Gia_ManBufNum(pGia) == Vec_PtrSize(vBuffers)Gia_ManBufNum(pGia) == pNew->nBarBufs2Gia_ObjIsBuf(pObjBuf)void Gia_ManPatchBufDriver(Gia_Man_t *, int, int)Gia_ObjId(p, pObjBuf) > Abc_Lit2Var(iLit0)%-30s: i/o =%6d/%6d lat =%5d nd =%6d box =%5d obj =%7d %5.1f %% %6.1f MBsrc/base/abc/abcHieNew.cvoid Au_ManFree(Au_Man_t *)Au_ManFindNtk(pMan, Au_NtkName(p)) == -1void Au_ManAddNtk(Au_Man_t *, Au_Ntk_t *)Design %-13s Different functions = %d. Memory = %.1f MBVec_IntEntryLast(vOrder) == pRoot->Idvoid Au_ManReorderModels(Au_Man_t *, Au_Ntk_t *)Vec_IntSize(vOrder) == Au_ManNtkNum(p)+1Vec_IntEntry(vOrder, 1) == pRoot->IdpBox->Func > 0!pBox->Func || pBox->Func >= (unsigned)pNtk->IdAu_ObjFaninNum(pBox) == Au_NtkPiNum(pBoxModel)Au_BoxFanoutNum(pBox) == Au_NtkPoNum(pBoxModel)void Au_ManCountThings(Au_Man_t *)pBoxModel->Id > pNtk->IdpBoxModel->nPorts > 0Total nodes = %15.0f. Total instances = %15.0f. Total ports = %15.0f. Total ANDs = %15.0f. Total XORs = %15.0f. Total MUXes = %15.0f. void Au_ManPrintBoxInfo(Au_Ntk_t *)Au_ObjIsNode(pObj) || Au_ObjIsBox(pObj) || Au_ObjIsFan(pObj)int Au_ObjSuppSize_rec(Au_Ntk_t *, int)((ABC_PTRINT_T)pMem & 0xF) == 0int Au_NtkAllocObj(Au_Ntk_t *, int, int)*((int *)pObj) == 0pTemp == pObjiModel > 0int Au_NtkCreateBox(Au_Ntk_t *, Vec_Int_t *, int, int) Cannot read directive in line %d: "%s". .and.xor.mux.subcktVec_IntSize(vFanins) == nInputsAu_Ntk_t *Au_NtkParseCBlif(char *).modelVec_IntSize(vFanins) == nOutputs.endUnknown directive in line %d: "%s". Au_ObjCopy(pTerm) >= 0void Au_NtkDeriveFlatGia_rec(Gia_Man_t *, Au_Ntk_t *)ref_egcdReplacing one instance of recursive model "%s" by a black box. Au_ObjFaninNum(pObj) <= 16Au_ObjFaninNum(pObj) == Abc_SopGetVarNum(pSop)pObj->Func >= 1 && pObj->Func <= 3Au_ObjFaninNum(pObj) == Au_NtkPiNum(pModel)Au_BoxFanoutNum(pObj) == Au_NtkPoNum(pModel)Collapsing model "%s"... Au_ObjGetXsim(pTerm) > 0void Au_NtkTerSimulate_rec(Au_Ntk_t *)p->pMan->pFuncs == NULLvoid Au_NtkTerSimulate(Au_Ntk_t *)Const0 outputs =%15d. Const1 outputs =%15d. Total outputs =%15d. Const0 ports = %.0f. Const1 ports = %.0f. Non-const ports= %.0f. Total ports = %.0f. Au_Ntk_t *Au_NtkDerive(Au_Man_t *, Abc_Ntk_t *, Vec_Ptr_t *)path_0_r_x_lhsCould not find module "%s". Time all Time new Time GIA int Vec_IntEntryLast(Vec_Int_t *)Au_ObjIsBox(p)int Au_BoxFanoutNum(Au_Obj_t *)i >= 0 && i < (int)p->nFanins && p->Fanins[i]int Au_ObjFaninId(Au_Obj_t *, int)void Au_NtkIncrementTravId(Au_Ntk_t *)(((ABC_PTRINT_T)(pMem + p->iHandle) & 0x3FF) >> 4) == 0void Au_NtkInsertHeader(Au_Ntk_t *)void *Vec_PtrEntryLast(Vec_Ptr_t *)f >= 0 && p->Fanins[i] == 0void Au_ObjSetFaninLit(Au_Obj_t *, int, int)pToken[0] >= '0' && pToken[0] <= '9'void Au_NtkParseCBlifNum(Vec_Int_t *, char *, Vec_Int_t *)Value0 == AU_VAL1 && Value1 == AU_VAL1int Au_XsimAnd(int, int)Value == AU_VALXint Au_XsimInv(int)p->Type == AU_OBJ_BOX && i >= 0 && i < p->Fanins[p->nFanins] && p->Fanins[i]int Au_ObjFanout(Au_Obj_t *, int)Reading CBLIF file has failed.src/base/abc/abcLatch.cint Abc_NtkLatchIsSelfFeed_rec(Abc_Obj_t *, Abc_Obj_t *)int Abc_NtkLatchIsSelfFeed(Abc_Obj_t *)char *Abc_NtkCollectLatchValuesStr(Abc_Ntk_t *)_lo_livoid Abc_NtkNodeConvertToMux(Abc_Ntk_t *, Abc_Obj_t *, Abc_Obj_t *, Abc_Obj_t *, Abc_Obj_t *)The number of converted latches with DC values = %d. Converted %d one-hot registers. Abc_Ntk_t *Abc_NtkConvertOnehot(Abc_Ntk_t *)Cannot reencode %d flops because it will lead to 2^%d states. Abc_NtkLatchNum(pNtkNew) == nStatesAbc_NtkPiNum(pNtkNew) == Abc_NtkPiNum(pNtk)Abc_NtkPoNum(pNtkNew) == Abc_NtkPoNum(pNtk)Abc_NtkCiNum(pNtkNew) == Abc_NtkPiNum(pNtkNew) + nStatesAbc_NtkCoNum(pNtkNew) == Abc_NtkPoNum(pNtkNew) + nStatesAbc_NtkCiNum(pNtk) == Abc_NtkPiNum(pNtk) + nFlopsAbc_NtkCoNum(pNtk) == Abc_NtkPoNum(pNtk) + nFlopsAbc_ObjFaninNum(pObjNew) == nStates/2Abc_NtkConvertOnehot(): Network check has failed. Gia_ManRegNum(pGia) == Vec_IntSize(vClasses)Aig_Man_t *Abc_NtkRetimeWithClassesAig(Aig_Man_t *, Vec_Int_t *, Vec_Int_t **, int)Abc_NtkPoNum(pNtkOld) == Abc_NtkPoNum(pNtkNew)void Abc_NtkTransformBack(Abc_Ntk_t *, Abc_Ntk_t *, Vec_Ptr_t *, Vec_Int_t *)Abc_ObjIsPo(pObj) && pObj->pNtk == pNtkOldAbc_NtkLatchNum(pNtkNew) == Vec_IntSize(vClasses)0-1 1 11- 1 Opposite phase enable is present in %d flops (out of %d). CountN = %4d. Count2 = %4d. Count1 = %4d. Count0 = %4d. Ctrls = %d. int Abc_NtkVerifyCex(Abc_Ntk_t *, Abc_Cex_t *)p->nPis == Abc_NtkPiNum(pNtk)iBit == p->nBitsvoid Abc_LatchSetInitDc(Abc_Obj_t *)void Abc_LatchSetInit1(Abc_Obj_t *)Cannot process logic network with don't-care init values. Run "zero".Vec_PtrSize(p->vTops) > 0src/base/abc/abcLib.cAbc_Des_t *Abc_DesDupBlackboxes(Abc_Des_t *, Abc_Ntk_t *)Vec_PtrSize(p->vModules) > 1Models of design %s: %2d : %20s nd = %6d lat = %6d whitebox = %3d blackbox = %3d %20s (whitebox) %20s (blackbox) pNtk->Id == 0int Abc_DesAddModel(Abc_Des_t *, Abc_Ntk_t *)Vec_PtrSize( p->vModules ) > 0int Abc_DesFindTopLevelModels(Abc_Des_t *)!Abc_ObjIsNet(pObj)void Abc_NodeStrashUsingNetwork_rec(Abc_Ntk_t *, Abc_Obj_t *)void Abc_NodeStrashUsingNetwork(Abc_Ntk_t *, Abc_Obj_t *)Abc_NtkIsNetlist(pNtkGate)Abc_NtkLatchNum(pNtkGate) == 0The design includes more than one module and is currently not used.src/base/abc/abcMinBase.cint Abc_NtkMinimumBase(Abc_Ntk_t *)Abc_NtkIsBddLogic(pNode->pNtk)int Abc_NodeMinimumBase(Abc_Obj_t *)int Abc_NtkRemoveDupFanins(Abc_Ntk_t *)int Abc_NodeRemoveDupFanins_int(Abc_Obj_t *)nSize <= dd->sizeDdNode *Abc_NodeCollapseFunc(Abc_Obj_t *, Abc_Obj_t *, Vec_Ptr_t *, int *, int *)Abc_NtkIsBddLogic(pFanin->pNtk)int Abc_NodeCollapse(Abc_Obj_t *, Abc_Obj_t *, Vec_Ptr_t *, int *, int *)Abc_ObjIsNode(pFanin)Abc_ObjIsNode(pFanout)Abc_ObjFanoutNum( pFanout ) == 0nMaxSize > 0int Abc_NtkEliminate(Abc_Ntk_t *, int, int, int)Converting to BDD has failed. Collapsing fanin %5d (supp =%2d) into fanout %5d (supp =%2d) resulting in node %5d (supp =%2d). iFanin >= 0 && iFanin < Hop_ManPiNum(pMan)int Abc_NodeCountAppearances(Abc_Obj_t *, Abc_Obj_t *)nSize + 1 <= Hop_ManPiNum(pMan)Hop_Obj_t *Abc_NodeCollapseFunc1(Abc_Obj_t *, Abc_Obj_t *, Vec_Ptr_t *, int *, int *)Abc_NtkIsAigLogic(pFanin->pNtk)int Abc_NodeCollapse1(Abc_Obj_t *, Abc_Obj_t *, Vec_Ptr_t *, int *, int *)int Abc_NtkEliminate1One(Abc_Ntk_t *, int, int, int, int)Converting to AIG has failed. int Abc_NtkEliminateSpecial(Abc_Ntk_t *, int, int)Converting to SOP has failed. RetValue >= 0 && RetValue < Abc_ObjFaninNum(pFanout)Abc_NodeFindCoFanout(pNode) == NULLpName != NULLsrc/base/abc/abcNames.cchar *Abc_ObjAssignName(Abc_Obj_t *, char *, char *)%s%0*dAbc_NtkPiNum(pNtk) == Abc_NtkPiNum(pNtkNew)void Abc_NtkTrasferNames(Abc_Ntk_t *, Abc_Ntk_t *)Abc_NtkPoNum(pNtk) == Abc_NtkPoNum(pNtkNew)Abc_NtkBoxNum(pNtk) == Abc_NtkBoxNum(pNtkNew)Nm_ManNumEntries(pNtk->pManName) > 0Nm_ManNumEntries(pNtkNew->pManName) == 0void Abc_NtkTrasferNamesNoLatches(Abc_Ntk_t *, Abc_Ntk_t *)Abc_NtkHasOnlyLatchBoxes(pNtk)void Abc_NtkOrderObjsByName(Abc_Ntk_t *, int)Abc_NamObjNumMax(pStrsCo) == i + 1Abc_Nam_t *Abc_NtkNameMan(Abc_Ntk_t *, int)Abc_NamObjNumMax(pStrsCi) == i + 1Abc_NtkPiNum(pNtkOld) == Abc_NtkPiNum(pNtkNew)void Abc_NtkTransferOrder(Abc_Ntk_t *, Abc_Ntk_t *)Abc_NtkLatchNum(pNtkOld) == Abc_NtkLatchNum(pNtkNew)pObj->iTemp > 0 && pObj->iTemp <= Abc_NtkCiNum(pNtkNew)pObj->iTemp > 0 && pObj->iTemp <= Abc_NtkCoNum(pNtkNew)CountMax < 100-2void Abc_NtkAddDummyBoxNames(Abc_Ntk_t *)void Abc_NtkRedirectCiCo(Abc_Ntk_t *)Abc_NodeIsBuf(pFanin)Redirected %d POs from buffers to PIs with the same name. void Abc_NtkStartNameIds(Abc_Ntk_t *)p->vNameIds == NULLstrlen(p->pSpec) < 1000%s_%s_names.txt%s p->vNameIds != NULLvoid Abc_NtkTransferNameIds(Abc_Ntk_t *, Abc_Ntk_t *)pNew->vNameIds == NULLAbc_ObjNtk(pObjNew) == pNew!Abc_NtkIsNetlist(p)void Abc_NtkUpdateNameIds(Abc_Ntk_t *)r+iVar < Vec_IntSize(vStarts)Saved %d names into file "%s". src/base/abc/abcNetlist.cAbc_Ntk_t *Abc_NtkToLogic(Abc_Ntk_t *)Abc_NtkToLogic(): Network check has failed. Abc_NtkIsLogic(pNtk) || Abc_NtkIsStrash(pNtk)Abc_Ntk_t *Abc_NtkToNetlist(Abc_Ntk_t *)Abc_Ntk_t *Abc_NtkToNetlistBench(Abc_Ntk_t *)Abc_Ntk_t *Abc_NtkAigToLogicSopNand(Abc_Ntk_t *)Abc_NtkAigToLogicSopBench(): Network check has failed. Abc_Ntk_t *Abc_NtkLogicToNetlist(Abc_Ntk_t *)silentmode!strcmp( Abc_ObjName(pDriver), Abc_ObjName(pObj) )Abc_ObjIsNode(pDriver)!strcmp( Abc_ObjName(pDriver->pCopy->pCopy), Abc_ObjName(pObj) )new_%s_Abc_NtkLogicToNetlist(): Network check has failed. Abc_Ntk_t *Abc_NtkAigToLogicSop(Abc_Ntk_t *)Abc_NtkAigToLogicSop(): Network check has failed. Abc_NtkLogicToNetlist() warning: The network is converted to have simple COs.Warning: The EXDc network is skipped.Warning: Choice nodes are skipped.,D8DbDVD,DDEEEEEE  src/base/abc/abcNtk.cAbc_Ntk_t *Abc_NtkAlloc(Abc_NtkType_t, Abc_NtkFunc_t, int)Abc_NtkCiNum(pNtk) == Abc_NtkCiNum(pNtkNew)Abc_Ntk_t *Abc_NtkStartFrom(Abc_Ntk_t *, Abc_NtkType_t, Abc_NtkFunc_t)Abc_NtkCoNum(pNtk) == Abc_NtkCoNum(pNtkNew)Abc_NtkLatchNum(pNtk) == Abc_NtkLatchNum(pNtkNew)Abc_NtkLatchNum(pNtk) == 0Abc_Ntk_t *Abc_NtkStartFromWithLatches(Abc_Ntk_t *, Abc_NtkType_t, Abc_NtkFunc_t, int)nLatches == Abc_NtkLatchNum(pNtkNew)Type != ABC_NTK_NETLISTAbc_Ntk_t *Abc_NtkStartFromNoLatches(Abc_Ntk_t *, Abc_NtkType_t, Abc_NtkFunc_t)unknownvoid Abc_NtkFinalizeRead(Abc_Ntk_t *)1'b01'b1Warning: Structural hashing during duplication reduced %d nodes (this is a minor bug). Abc_NtkDup(): Network check has failed. !Abc_NtkIsStrash(pNtk) && !Abc_NtkIsNetlist(pNtk)Abc_Ntk_t *Abc_NtkDupDfs(Abc_Ntk_t *)Abc_Ntk_t *Abc_NtkDupDfsNoBarBufs(Abc_Ntk_t *)pNtk->nBarBufs2 > 0Abc_Ntk_t *Abc_NtkRestrashWithLatches(Abc_Ntk_t *, int)Abc_Ntk_t *Abc_NtkDupTransformMiter(Abc_Ntk_t *)Abc_NtkPoNum(pNtk) == 2*Abc_NtkPoNum(pNtkNew)Abc_Ntk_t *Abc_NtkDouble(Abc_Ntk_t *)_2x2_Abc_Ntk_t *Abc_NtkBottom(Abc_Ntk_t *, int)_botAbc_NtkBottom(): Network check has failed. pNtkBottom != NULLAbc_Ntk_t *Abc_NtkAttachBottom(Abc_Ntk_t *, Abc_Ntk_t *)Abc_NtkPiNum(pNtkTop) == Abc_NtkCiNum(pNtkTop)Abc_NtkPiNum(pNtkBottom) == Abc_NtkCiNum(pNtkBottom)Abc_NtkPoNum(pNtkBottom) == Abc_NtkPiNum(pNtkTop)Abc_NtkPiNum(pNtkBottom) < Abc_NtkPiNum(pNtkTop)Abc_NtkPiNum(pNtkBottom) == Abc_NtkPiNum(pNtkTop)Abc_NtkAttachBottom(): Network check has failed. Abc_Ntk_t *Abc_NtkCreateCone(Abc_Ntk_t *, Abc_Obj_t *, char *, int)Abc_ObjIsNode(pNode) || (Abc_NtkIsStrash(pNtk) && (Abc_AigNodeIsConst(pNode) || Abc_ObjIsCi(pNode)))%s_%sAbc_NtkCreateCone(): Network check has failed. Abc_Ntk_t *Abc_NtkCreateConeArray(Abc_Ntk_t *, Vec_Ptr_t *, int)%s_partAbc_NtkCreateConeArray(): Network check has failed. Abc_NtkIsStrash(pNtkNew)void Abc_NtkAppendToCone(Abc_Ntk_t *, Abc_Ntk_t *, Vec_Ptr_t *)Abc_NtkAppendToCone(): Network check has failed. Abc_Ntk_t *Abc_NtkCreateMffc(Abc_Ntk_t *, Abc_Obj_t *, char *)Abc_NtkCreateMffc(): Network check has failed. Abc_Ntk_t *Abc_NtkCreateTarget(Abc_Ntk_t *, Vec_Ptr_t *, Vec_Int_t *)Abc_NtkCreateTarget(): Network check has failed. Abc_NtkCreateFromNode(): Network check has failed. Abc_NtkCreateWithNode(): Network check has failed. pObj->fMarkA == 0void Abc_NtkDelete(Abc_Ntk_t *)pObj->fMarkC == 0pNtk->pSCLib == NULL[_c1_]Warning: Constant-0 drivers added to %d non-driven nets in network "%s": void Abc_NtkMakeComb(Abc_Ntk_t *, int)Abc_NtkBoxNum(pNtk) == 0Abc_NtkBoNum(pNtk) == 0Abc_NtkBiNum(pNtk) == 0Abc_NtkMakeComb(): Network check has failed. void Abc_NtkMakeSeq(Abc_Ntk_t *, int)Abc_NtkMakeSeq(): Network check has failed. !Abc_NtkIsNetlist(pNtkInit)Abc_Ntk_t *Abc_NtkMakeOnePo(Abc_Ntk_t *, int, int)Abc_NtkHasOnlyLatchBoxes(pNtkInit)Vec_PtrSize(vCexes) == Abc_NtkPoNum(pNtk)void Abc_NtkDropSatOutputs(Abc_Ntk_t *, Vec_Ptr_t *, int)Abc_ObjChild0(pObj) == pConst0Logic cones of %d POs have been replaced by constant 0. void Abc_NtkDropOneOutput(Abc_Ntk_t *, int, int, int)Abc_ObjChild0(pObj1) == pChild2Oldvoid Abc_NtkSwapOneOutput(Abc_Ntk_t *, int)Abc_ObjChild0(pObj2) == pChild1OldFlop ID (%d) is out of range. The number of flops read in from file (%d) is different from the number of flops in the circuit (%d). Abc_NtkBoxNum(pNtk) == Abc_NtkLatchNum(pNtk)void Abc_NtkPermute(Abc_Ntk_t *, int, int, int, char *)void Abc_NtkUnpermute(Abc_Ntk_t *)Duplicated %d nodes. Gia_ManCoNum(pGia) == 1Abc_Ntk_t *Abc_NtkCreateFromGias(char *, Vec_Ptr_t *, Gia_Man_t *)void Vec_PtrShrink(Vec_Ptr_t *, int)Abc_NtkStrash: The network check has failed.The network is a not a combinational one.The number of latches is more or equal than the number of POs.The number of latches is more or equal than the number of PIs.Run sequential cleanup ("st; scl") to get rid of dangling logic.Run sequential cleanup ("scl") to get rid of dangling logic.PO index is incorrect.Abc_NtkUnpermute(): Initial permutation is not available.jEjEhEhE,iEhEjEjE2iE:iE:iEttEtEpEDmElrEDoEwsETpE0lE0lE0lEyEyEyEyEyEpEEEEpEE0ECEnE]E0E}E EHEE3EE0E EE=E5E5EGEEEE EEEELjE{EsEsEEsrc/base/abc/abcObj.cAbc_Obj_t *Abc_NtkCreateObj(Abc_Ntk_t *, Abc_ObjType_t)void Abc_NtkDeleteObj(Abc_Obj_t *)void Abc_NtkDeleteObjPo(Abc_Obj_t *)void Abc_NtkDeleteObj_rec(Abc_Obj_t *, int)!Abc_ObjIsPi(pObj)Abc_ObjFanoutNum(pObj) == 0void Abc_NtkDeleteAll_rec(Abc_Obj_t *)Abc_ObjIsLatch(Abc_ObjFanout0(pObj))Abc_Obj_t *Abc_NtkDupObj(Abc_Ntk_t *, Abc_Obj_t *, int)Abc_Obj_t *Abc_NtkDupBox(Abc_Ntk_t *, Abc_Obj_t *, int)Name "%s" is not found among CO or node names (internal names often look as "n"). The node "%s" with ID %d is not in the current network. The node "%s" with ID %d has been removed from the current network. Object with ID %d is not a node. Abc_Obj_t *Abc_NtkFindNet(Abc_Ntk_t *, char *)Abc_Obj_t *Abc_NtkFindCi(Abc_Ntk_t *, char *)Abc_Obj_t *Abc_NtkFindCo(Abc_Ntk_t *, char *)Abc_Obj_t *Abc_NtkFindOrCreateNet(Abc_Ntk_t *, char *)Abc_NtkIsLogic(pNtk) || Abc_NtkIsNetlist(pNtk)Abc_Obj_t *Abc_NtkCreateNodeConst0(Abc_Ntk_t *)Abc_Obj_t *Abc_NtkCreateNodeConst1(Abc_Ntk_t *)Abc_Obj_t *Abc_NtkCreateNodeInv(Abc_Ntk_t *, Abc_Obj_t *)Abc_Obj_t *Abc_NtkCreateNodeBuf(Abc_Ntk_t *, Abc_Obj_t *)Abc_Obj_t *Abc_NtkCreateNodeAnd(Abc_Ntk_t *, Vec_Ptr_t *)Abc_Obj_t *Abc_NtkCreateNodeOr(Abc_Ntk_t *, Vec_Ptr_t *)Abc_Obj_t *Abc_NtkCreateNodeExor(Abc_Ntk_t *, Vec_Ptr_t *)Abc_Obj_t *Abc_NtkCreateNodeMux(Abc_Ntk_t *, Abc_Obj_t *, Abc_Obj_t *, Abc_Obj_t *)Abc_NtkIsLogic(pNode->pNtk) || Abc_NtkIsNetlist(pNode->pNtk)int Abc_NodeIsConst(Abc_Obj_t *)int Abc_NodeIsConst0(Abc_Obj_t *)int Abc_NodeIsConst1(Abc_Obj_t *)int Abc_NodeIsBuf(Abc_Obj_t *)int Abc_NodeIsInv(Abc_Obj_t *)void Abc_NodeComplement(Abc_Obj_t *)Node %s should be amongvoid Abc_NodeComplementInput(Abc_Obj_t *, Abc_Obj_t *)i >= 0void Vec_PtrRemove(Vec_Ptr_t *, void *)src/base/abc/abcRefs.cint Abc_NodeMffcSize(Abc_Obj_t *)nConeSize1 == nConeSize2nConeSize1 > 0int Abc_NodeMffcSizeStop(Abc_Obj_t *)!Abc_ObjIsComplement( pNode )int Abc_NodeMffcLabelAig(Abc_Obj_t *)pFanin->vFanouts.nSize > 0int Abc_NodeDeref_rec(Abc_Obj_t *)void Abc_NodeMffcConeSupp(Abc_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *)Node = %6s : Supp = %3d Cone = %3d (Count1 == Count2int Abc_NodeMffcInside(Abc_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *)Vec_Ptr_t *Abc_NodeMffcInsideCollect(Abc_Obj_t *)int Abc_NodeMffcLabel(Abc_Obj_t *, Vec_Ptr_t *)pNode0->vFanouts.nSize > 0int Abc_NodeRefDeref(Abc_Obj_t *, int, int)pNode1->vFanouts.nSize > 0int Abc_NodeRefDerefStop(Abc_Obj_t *, int)temp.dotCannot open the intermediate file "%s". src/base/abc/abcShow.cvoid Abc_NodeShowBdd(Abc_Obj_t *, int)void Abc_NtkShowBdd(Abc_Ntk_t *, int)void Abc_NodeShowCut(Abc_Obj_t *, int, int)Abc_NtkIsStrash(pNtk0) || Abc_NtkIsLogic(pNtk0)void Abc_NtkShow(Abc_Ntk_t *, int, int, int)gvdotwindotunix%s.ps%s -Tps -o %s %sCommand "%s" did not succeed. Cannot open intermediate file "%s". gsviewwingsviewunix%s %s &Cannot execute "%s". Cannot open input file %s. # Flop dependency for "%s" generated by ABC on %s digraph G { graph [splines=true overlap=false]; size = "7.5,10"; center = true; edge [dir=forward]; { rank = same; %d [label="%d(%d)"]; } %4d -> %4d Abc_NtkIsStrash(pNtk) || Abc_NtkIsLogic(pNtk)void Abc_NtkShowFlopDependency(Abc_Ntk_t *)Construction of global BDDs has failed.Temporarily visualization of AIGs with choice nodes is disabled.  1111111111111111nVars == 2src/base/abc/abcSop.cchar *Abc_SopCreateXor(Mem_Flex_t *, int)01 1 10 1 pSop[nVars+2] == '\n'char *Abc_SopCreateXorSpecial(Mem_Flex_t *, int)char *Abc_SopCreateNxor(Mem_Flex_t *, int)11 1 00 1 char *Abc_SopCreateFromTruth(Mem_Flex_t *, int, unsigned int *)Vec_IntSize(vCover) > 0char *Abc_SopCreateFromIsop(Mem_Flex_t *, int, Vec_Int_t *)nVars < 16char *Abc_SopCreateFromTruthIsop(Mem_Flex_t *, int, word *, Vec_Int_t *)nVars > 0RetValue == 0 || RetValue == 1void Abc_SopToIsop(char *, Vec_Int_t *)int Abc_SopGetPhase(char *)void Abc_SopComplement(char *)void Abc_SopComplementVar(char *, int)int Abc_SopIsComplement(char *)int Abc_SopIsExorType(char *)Abc_SopCheck: SOP has a mismatch between its cover size (%d) and its fanin number (%d). Abc_SopCheck: SOP has a strange character (%c) in the output part of its cube. Abc_SopCheck: SOP has a cube without new line in the end. Abc_SopCheck: SOP has cubes in both phases. String %s does not look like a truth table of a %d-variable function. String %s does not look like a binary representation of the truth table. String %s does not look like a hexadecimal representation of the truth table. iValue < nValueschar *Abc_SopEncoderPos(Mem_Flex_t *, int, int)d0 %d 1 iBit < nBitschar *Abc_SopEncoderLog(Mem_Flex_t *, int, int)char *Abc_SopDecoderPos(Mem_Flex_t *, int)nValues > 1 && nValues <= (1<= 0 && nVars <= 6word Abc_SopToTruth(char *, int)nVars == nInputspSop[lit] == ' 'pSop[lit] == '\n'nVars >= 0 && nVars <= 7void Abc_SopToTruth7(char *, int, word *)nVars >= 0 && nVars <= 16void Abc_SopToTruthBig(char *, int, word **, word *, word *)Cannot create constant function.src/base/abc/abcUtil.cint Abc_NtkGetCubeNum(Abc_Ntk_t *)int Abc_NtkGetCubePairNum(Abc_Ntk_t *)int Abc_NtkGetLitNum(Abc_Ntk_t *)int Abc_NtkGetLitFactNum(Abc_Ntk_t *)int Abc_NtkGetMultiRefNum(Abc_Ntk_t *)int Abc_NtkGetBddNodeNum(Abc_Ntk_t *)Abc_NtkIsAigLogic(pNtk)int Abc_NtkGetAigNodeNum(Abc_Ntk_t *)int Abc_NtkGetClauseNum(Abc_Ntk_t *)double Abc_NtkGetMappedArea(Abc_Ntk_t *)Abc_ObjFaninNum(pFanout) == 1Abc_Obj_t *Abc_NodeHasUniqueCoFanout(Abc_Obj_t *)Abc_ObjFanin0(pFanout) == pNodeAbc_ObjFanoutNum(pDriverNew) == 1void Abc_NtkFixCoDriverProblem(Abc_Obj_t *, Abc_Obj_t *, int)int Abc_NtkLogicHasSimpleCos(Abc_Ntk_t *)int Abc_NtkLogicMakeSimpleCos2(Abc_Ntk_t *, int)Abc_NtkLogicHasSimpleCos(pNtk)c%d = %d i%d = %d int Abc_NtkLogicMakeSimpleCos(Abc_Ntk_t *, int)fHasInvVec_PtrSize(vFanouts) > 0Abc_ObjIsCi(pDriver) || Abc_ObjFanoutNum(pDriver) > 0int Abc_NodeIsExorType(Abc_Obj_t *)Abc_ObjFaninId0(pNode0) != Abc_ObjFaninId1(pNode1) || Abc_ObjFaninId0(pNode1) != Abc_ObjFaninId1(pNode0)int Abc_NodeIsMuxType(Abc_Obj_t *)int Abc_NodeIsMuxControlType(Abc_Obj_t *)Abc_Obj_t *Abc_NodeRecognizeMux(Abc_Obj_t *, Abc_Obj_t **, Abc_Obj_t **)Abc_NodeIsMuxType(pNode)Empty current network. The external spec is not given. Cannot open the external spec file "%s". Wrong number of arguments. void Abc_NtkReassignIds(Abc_Ntk_t *)pConst1->Id == 0Vec_PtrSize(vObjsNew) == pNtk->nObjsnCutSize == 0int Abc_NtkCrossCut(Abc_Ntk_t *)Max cross cut size = %6d. Ratio = %6.2f %% 4varfs.txtread_truth ; clp; st; w 1.blif; map; cec 1.blif Abc_ObjIsCo(pTemp)void Abc_NtkCompareCones(Abc_Ntk_t *)%4d CO %5d : Supp = %5d. Lev = %3d. Cone = %5d. Rev = %5d. COs = %3d (%3d). void Abc_NtkCompareSupports(Abc_Ntk_t *)Choice orig = %3d Choice new = %3d %c=%d Level - 1 >= Abc_ObjLevel(pFanin)Abc_Obj_t *Abc_NtkAddBuffsOne(Vec_Ptr_t *, Abc_Obj_t *, int, int)nLevelMax < (1<<18)Abc_Ntk_t *Abc_NtkAddBuffsInt(Abc_Ntk_t *, int, int, int)pFanin->Level < pObj->LevelShifted %5d nodes down with total gain %5d. pObj->Level <= (unsigned)nLevelMaxpFanin->Level > pObj->LevelShifted %5d nodes up with total gain %5d. Abc_ObjLevel(pObj) - 1 >= Abc_ObjLevel(pFanin)nFaninMax > 1 && nFaninMax < 15float Abc_NtkComputeDelay(Abc_Ntk_t *)pNodeOld->pCopy == pNodeNewvoid Abc_NodeSopToCubes(Abc_Obj_t *, Abc_Ntk_t *, int)pNodeOld->pCopy == NULLAbc_NtkIsSopLogic(pNtk)Abc_Ntk_t *Abc_NtkSopToCubes(Abc_Ntk_t *, int)void Abc_NtkReverseTopoOrder_rec(Abc_Obj_t *, int)!Abc_NtkTopoHasEnd(pNext)p->vTopo == NULLvoid Abc_NtkReverseTopoOrder(Abc_Ntk_t *)Nodes = %d. Size = %d. Ratio = %f. Abc_SopGetVarNum((char*)pNode->pData) == nInputsAbc_Ntk_t *Abc_NtkFromPla(char **, int, int)Abc_NtkFromPla(): Network check has failed. 1000 1 0110 1 0011 1 Abc_Ntk_t *Abc_NtkSplitSop(Abc_Ntk_t *, int, int)Node %d is out of topo order. Topological order does not hold for %d internal nodes. pNtk->vPhases != NULLvoid Abc_NtkTransferPhases(Abc_Ntk_t *, Abc_Ntk_t *)Vec_IntSize(pNtk->vPhases) == Abc_NtkObjNumMax(pNtk)pNtkNew->vPhases == NULLmonitorAbc_NtkPoNum(pNtkNew) == 1Abc_Ntk_t *Abc_NtkDeriveWithOnePo(Abc_Ntk_t *, Vec_Int_t *, Vec_Int_t *)Abc_NtkCiNum(pNtkNew) == Abc_NtkCiNum(pNtk)Abc_NtkLatchNum(pNtkNew) == Abc_NtkLatchNum(pNtk)Abc_NtkIsLogic(p)Abc_Ntk_t *Abc_NtkCreatePropertyMonitor(Abc_Ntk_t *, Vec_Int_t *, Vec_Int_t *)Abc_NtkLatchNum(p) > 0Vec_IntSize(vNodeIds) > 0Vec_IntSize(vNodeIds) == Vec_IntSize(vNodeValues)int Abc_GateToType(Abc_Obj_t *)fx; strash; balance; dc2; map -aVec_WecSize(vRes) == iNodeVec_Wec_t *Abc_SopSynthesize(Vec_Ptr_t *)compress2rs; dch; map -a; strash; compress2rs; dch; map -a; strash; compress2rs; dch; map -aVec_Wec_t *Abc_GiaSynthesize(Vec_Ptr_t *, Gia_Man_t *)balance; collapse; muxes; strash; dc2int Abc_NtkClpOneGia_rec(Gia_Man_t *, Abc_Obj_t *)Gia_Man_t *Abc_NtkStrashToGia(Abc_Ntk_t *)pSop[1] == '0' || pSop[1] == '1'Gia_Man_t *Abc_SopSynthesizeOne(char *, int)clp; sopfx; strash; balance; dc2./src/misc/vec/vecWec.hVec_Int_t *Vec_WecEntry(Vec_Wec_t *, int)??@p= ף@@(\ @p= ף @{Gz@@Gz@HzG@ףp= @RQ@@= ףp=@p= ף@@\(\@Gz@@Node without mapping is encountered.Abc_NtkSopToCubes: The network check has failed.FӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFӺFSFFXFӺF^FcFӺFӺFӺFӺFrFxFӺFӺFFӺFӺFFFFFFFFFF"FFFF(FFFFFF/FIFFFPF`FpFFF FF#F0F2FFFFFFFFFFFFFFFFFFF\F0F0F0F0F0F0F0F0FF0F0F0F0F0F0F0F0F0F0F0F0F0FF0F0F0F0F0F0F0F0FF0F0F0F0F0F0F0F0F0F0F0F0F0F0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF=FFFFFFFFFFFFFFFFFNFFFFFFOFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFyG?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?G?GG?G?G?G?G?G?G?G?G;GdG?GG?G?GG?G?G?GG?G?G?G?G?G?G?G?G?G?G?G4G>G?G?G?G?G?G?G?G?G?GHG?G?G?G?GQG?G?G[GFeG?GoGGfGfGfGfG GfGfGfGfGfGfGfGFGfGfGfGfGfGfGfGfGfGfGfGfGfGfGfGfGGfGfGfGfGfGfGfGfGfGfGGG G G G G G G G G G G G" G G G G( GCG1GG1G1GG1GG1G1G1G1G1G1G1G1G1G1G1G1G1G1G1G1G1G1G?G1G1G1G1G1G1G1G1GSG1G1G1GgG1G1G{GG1G1GGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGG*GdGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGGG 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K&KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK*KdKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK~KKn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn KKn Kn K:Kn Kn Kn Kn KbKn KKKn KKn Kn KKn Kn Kn K5Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn Kn KtKKn Kn Kn Kn Kn Kn Kn Kn KKn Kn K~Kn Kn Kn Kn Kn KKK-K.K.K.K.K.K.K.K.K.K.K.K.K.K-K.K.K.K.K.K.K.K.K.K.K.K.K.K(.K.K.K.K.K.K.K.K.K.K.K.K.K.K1.K.K.K9.K2K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K20Ka1K1K1K1K0K4K4K4K4K4KI1K32K4K4K 1K2K2Km0K0K4K4K4K4K4K4K4K4K4K4K4K4K0K0K1Kb2K4Kf0K4K4K4K4K4K4K51KV0K4K0K?1Kv2Kl2KX2K0KL0K\0KlwJX@eAxxxxd2zC? #<?Abc_FrameUpdateGia(): Tranformation has failed. The current GIA has no primary outputs. Some commands may not work correctly. Printingprint_statsprint_exdcprint_ioprint_latchprint_fanioprint_mffcprint_factorprint_levelprint_suppprint_mintprint_symmprint_unateprint_autoprint_kmapprint_gatesprint_sharingprint_xcutprint_dsdprint_coneprint_miterprint_statusprint_delayshow_bddshow_cutSynthesiscollapsebalancemux_structmultirenodefxcheliminatesparsifylutpacklutminmfs2mfs3mfselogicpushglitchpowerdownaddbuffstestdectestnpnLogiCStestrpotesttruthrunecorungenrunsimruntestrewriterefactorresubextractvarminfaultclassesExact synthesisbms_startbms_stopbms_psmajexacttwoexactlutexactallexacttestexactmajgenVariousorposandposzeroposwapposremovepodropsataddpiputontopdframesreordermuxesexpandsplitsopext_seq_dcstopmostmove_namesexdc_freeexdc_getexdc_setcare_setespressogenfsmcoverdoublebb2wboutdecnodeduptestcolorqrelqreachsenseinputnpnloadnpnsavesend_aigsend_statusbackupminisatminisimpNew AIGistrashicutirwdrwdrfdchoicedrwsatirwsiresynifraigdfraigcsweepFraigingfraig_trustfraig_storefraig_restorefraig_cleanfraig_sweepdump_equivChoicingrec_start3rec_stop3rec_ps3rec_add3rec_dump3rec_merge3SC mappingamapphase_mapattachsupercsupercltimescaleFPGA mappingififDSD managerdsd_savedsd_loaddsd_freedsd_psdsd_matchdsd_mergedsd_filterSequentialundconehotdretimefretimecretimessweeptestsswtestscorrscleanupphasesynchclockgateextwininswinsymfununpermutecubeenumpathenumfunenumVerificationdcecdsecdproveabsecsimsecdsatxsat&satoko&sat3iprovebmc2bmc3indcutenlargetemporindunfoldunfold2bm2saucy3testcexpdrreconcilecexsavecexloadcexcutcexmergedualrailblockpo&get&save2&saveaig&load2&loadaig&r&read&read_blif&read_cblif&read_stg&read_ver&write_ver&write&wlut&pfan&psig&status&profile&muxpos&muxstr&print_truth&unate&rex2gia&rexwalk&show&setregnum&st&topand&add1hot&cof&trim&dfs&sim&sim3&mlgen&mltest&sim_read&sim_write&sim_print&sim_gen&simrsb&resim&speci&equiv&equiv2&equiv3&semi×&frames&retime&enable&dc2&dsd&bidec&shrink&fx&blut&syn2&syn3&syn4&synch2&false&miter&miter2&append&scl&lcorr&scorr&choice&sat&satenum&fraig&cfraig&srm&srm2&filter&reduce&equiv_mark&equiv_filter&cec&verify&sweep&force&embed&flow&flow2&flow3&if&iff&iiff&if2&jf&kf&lf&mf&nf&of&pack&edge&satlut&unmap&struct&trace&speedup&era&dch&rpm&back_reach&posplit&permute&reachm&reachp&reachn&reachy&undo&mesh&iso&isonpn&isost&cexinfo&cycle&cone&slice&popart&gprove&mprove&splitprove&bmc&bmcs&chainbmc&bcore&icheck&sattest&fftest&qbf&qvar&genqbf&homoqbf&satfx&satclp&inse&maxi&bmci&poxsim&demiter&fadds&atree&polyn&acec&anorm&decla&esop&exorcism&mfs&mfsd&deepsynAbstraction&abs_create&abs_derive&abs_refine&gla_derive&gla_refine&gla_shrink&gla&vta&vta_gla&gla_vta&fla_gla&gla_flaLivenessl2sl2ssiml3skcsnck&gen&cfs&testCommand line switch "-R" should be followed by an integer. Unknown switch. There is no current cex. Main AIG: There is no current network. Main AIG: The current network is not an AIG. Main AIG: The number of PIs (%d) is different from cex (%d). Main AIG: The cex does not fail any outputs. Main AIG: The cex refined PO %d instead of PO %d. usage: cexmin [-CR num] [-vh] reduces the length of the counter-example -C num : the maximum number of conflicts [default = %d] -R num : the number of minimization rounds [default = %d] -v : toggle printing optimization summary [default = %s] yesno -h : print the command usage SDLUmvhCommand line switch "-S" should be followed by an integer. Command line switch "-D" should be followed by an integer. Command line switch "-L" should be followed by an integer. Command line switch "-U" should be followed by an integer. Abc_CommandAbc9PoPart(): There is no AIG. usage: &popart2 [-SDLU num] [-mvh] extracting multi-output sequential logic cones -S num : the index of the PO to start the cluster [default = %d] -D num : the max increase in flop count after adding one PO [default = %d] -L num : the minimum number of POs in a cluster [default = %d] -U num : the maximum number of POs in a cluster [default = %d] -m : toggle selecting the largest cluster [default = %s] -v : toggle printing verbose information [default = %s] FGvhCommand line switch "-F" should be followed by an integer. Command line switch "-G" should be followed by an integer. There is no saved cex. Current CEX does not allow to shorten the saved CEX. Merging CEXes has failed. usage: &cexmerge [-FG num] [-vh] merges the current CEX into the saved one and sets the resulting CEX as the saved one -F num : 0-based number of the starting frame [default = %d] -G num : 0-based number of the ending frame [default = %d] FNjavhCommand line switch "-N" should be followed by an integer. Abc_CommandAbc9CexMin(): There is no AIG. Abc_CommandAbc9CexMin(): The network is combinational. Abc_CommandAbc9CexMin(): There is no counter-example. usage: &cexmin [-FN num] [-javh] minimizes a deep counter-example -F num : starting timeframe for minimization [default = %d] -N num : the number of real primary inputs [default = %d] -j : toggle computing all justifying assignments [default = %s] -a : toggle using all terminal objects [default = %s] fbdltmpgscuhEmpty network. Cannot print LUT delay for a non-logic network. elapse: %3.2f seconds, total: %3.2f seconds usage: print_stats [-fbdltmpgscuh] prints the network statistics -f : toggles printing the literal count in the factored forms [default = %s] -b : toggles saving the best logic network in "best.blif" [default = %s] -d : toggles dumping statistics about the network into file [default = %s] -l : toggles printing delay of LUT mapping using LUT library [default = %s] -t : toggles printing runtime statistics [default = %s] -m : toggles printing MUX statistics [default = %s] -p : toggles printing power dissipation due to switching [default = %s] -g : toggles printing percentage of increased power due to glitching [default = %s] -s : toggles not counting single-output nodes as nodes [default = %s] -c : toggles not counting constants and single-output nodes as nodes [default = %s] -u : toggles printing memory usage [default = %s] -h : print the command usage sdhNetwork has no EXDC. EXDC network statistics: %.6f %% don't-cares) EXDC network statistics: usage: print_exdc [-dh] prints the EXDC network statistics -d : toggles printing don't-care percentage [default = %s] Wrong number of auguments. Cannot find node "%s". usage: print_io [-fh] prints the PIs/POs/flops or fanins/fanouts of a node -f : toggles printing flops [default = %s] node : the node to print fanins/fanouts usage: print_latch [-sh] prints information about latches -s : toggles printing SCCs of registers [default = %s] fiscmvhusage: print_fanio [-fiscmvh] prints the statistics about different objects in the network -f : toggles considering fanins/fanouts of all nodes [default = %s] -i : toggles considering fanins/fanouts of CI/CO [default = %s] -s : toggles considering TFO/TFI support sizes of CI/CO [default = %s] -c : toggles considering TFO/TFI cone sizes of CI/CO [default = %s] -m : toggles printing MFFC sizes instead of fanouts [default = %s] -v : toggles verbose way of printing the stats [default = %s] usage: print_mffc [-h] prints the MFFC of each node in the network Printing factored forms can be done for SOP networks. usage: print_factor [-nh] prints the factored forms of nodes -n : toggles real/dummy fanin names [default = %s] realdummy node : (optional) one node to consider npvhThis command works only for AIGs (run "strash"). usage: print_level [-npvh] prints information about node level and cone size -n : toggles printing nodes by levels [default = %s] -p : toggles printing level profile [default = %s] -v : enable verbose output [default = %s]. This command works only for combinational networks (run "comb"). usage: print_supp [-svwh] prints the supports of the CO nodes -s : toggle printing structural support only [default = %s]. -w : enable printing CI/CO dependency matrix [default = %s]. This command works only for logic networks (run "clp"). This command works only for logic networks with local functions represented by BDDs. ObjId %3d : SuppSize = %5d MintCount = %32.0f usage: print_mint [-svwh] prints the number of on-set minterms in the PO functions bnrvhusage: print_symm [-bnrvh] computes symmetries of the PO functions -b : toggle BDD-based or SAT-based computations [default = %s]. BDD -n : enable naive BDD-based computation [default = %s]. -r : enable dynamic BDD variable reordering [default = %s]. -v : enable verbose output [default = %s]. bnvhusage: print_unate [-bnvh] computes unate variables of the PO functions -n : toggle naive BDD-based computation [default = %s]. OnvhCommand line switch "-O" should be followed by an integer. usage: print_auto [-O ] [-nvh] computes autosymmetries of the PO functions -O : (optional) the 0-based number of the output [default = all] -n : enable naive BDD-based computation [default = %s]. -v : enable verbose output [default = %s]. -h : print the command usage Visualization of Karnaugh maps works for logic networks. The driver "%s" of the first PO is not an internal node. usage: print_kmap [-nh] shows the truth table of the node : the node to consider (default = the driver of the first PO) luhPrinting gates does not work for AIGs and sequential AIGs. usage: print_gates [-luh] prints statistics about gates used in the network -l : used library gate names (if mapped) [default = %s] -u : update profile before printing it[default = %s] usage: print_sharing [-h] prints the number of shared nodes in the TFI cones of the COs usage: print_xcut [-h] prints the size of the cross cut of the current network NpcdhCurrently works only for logic networks. The fanin of the first PO node does not have a logic function. Currently works only for up to 16 inputs. usage: print_dsd [-pcdh] [-N ] print DSD formula for a single-output function with less than 16 variables -p : toggle printing profile [default = %s] -c : toggle recursive cofactoring [default = %s] -d : toggle printing decompositions [default = %s] -N : the number of levels to cofactor [default = %d] nVars >= 0./src/misc/util/utilTruth.hword Abc_Tt6Stretch(word, int)nVars == 6usage: print_cone [-h] prints cones of influence info for each primary output The network is should be structurally hashed. usage: print_miter [-h] prints the status of the miter LoshCommand line switch "-L" should be followed by a file name. Status = %d Frames = %d Cex is not defined. Cannot open file "%s" for writing. STATUS: ABORTED STATUS: SAT STATUS: UNSAT Status array contains %d SAT, %d UNSAT, and %d UNDEC entries (out of %d).%d=%d usage: print_status [-L file] [-osh] prints verification status -L file : the log file name [default = %s] no logging -o : toggle printing output status [default = %s] -s : toggle using short print-out [default = %s] -h : print the command usage Delay trace works only for network mapped into standard cells. Cannot find combinational output "%s". Cannot find combinational input "%s". usage: print_delay [-h] prints one critical path of the mapped network -h : print the command usage : (optional) the sink of the critical path (primary output or flop input) : (optional) the source of the critical path (primary input or flop output) (if CO and/or CI are not given, uses the most critical ones) rsgfhusage: show [-srgfh] -s : toggles visualization of sequential networks [default = %s]. -r : toggles ordering nodes in reverse order [default = %s]. -g : toggles printing gate names for mapped network [default = %s]. -f : toggles visualizing flop dependency graph [default = %s]. cghVisualizing BDDs can only be done for logic BDD networks (run "bdd"). usage: show_bdd [-cgh] uses DOT and GSVIEW to visualize the global BDDs of primary outputs in terms of primary inputs or the local BDD of a node in terms of its fanins : (optional) the node to consider [default = the driver of the first PO] -c : toggle visualizing BDD with complemented edges [default = %s]. -g : toggle visualizing the global BDDs of primary outputs [default = %s]. NChVisualizing cuts only works for AIGs (run "strash"). usage: show_cut [-N ] [-C ] [-h] visualizes the cut of a node using DOT and GSVIEW -N : the max size of the cut to be computed [default = %d] -C : the max support of the containing cone [default = %d] : the node to consider BLrodvhCommand line switch "-B" should be followed by an integer. Can only collapse a logic network or an AIG. Collapsing has failed. usage: collapse [-B ] [-L file] [-rodvh] collapses the network by constructing global BDDs -B : limit on live BDD nodes during collapsing [default = %d] -r : toggles dynamic variable reordering [default = %s] -o : toggles reverse variable ordering [default = %s] -d : toggles dual-rail collapsing mode [default = %s] -v : print verbose information [default = %s] CLZcrsvhCommand line switch "-Z" should be followed by an integer. usage: satclp [-CLZ num] [-crsvh] performs SAT based collapsing -C num : the limit on the SOP size of one output [default = %d] -L num : the limit on the number of conflicts in one SAT call [default = %d] -Z num : the limit on the cost of the largest output [default = %d] -c : toggles using canonical ISOP computation [default = %s] -r : toggles using reverse veriable ordering [default = %s] -s : toggles shared CNF computation (non-canonical only) [default = %s] -v : toggles printing verbose information [default = %s] acrihStrashing has failed. usage: strash [-acrih] transforms combinational logic into an AIG -a : toggles between using all nodes and DFS nodes [default = %s] DFS -c : toggles cleanup to remove the dagling AIG nodes [default = %s] -r : toggles using the record of AIG subgraphs [default = %s] -i : toggles complementing the POs of the AIG [default = %s] ./src/base/abc/abc.hldsxvhStrashing before balancing has failed. Balancing has failed. usage: balance [-ldsxvh] transforms the current network into a well-balanced AIG -l : toggle minimizing the number of levels [default = %s] -d : toggle duplication of logic [default = %s] -s : toggle duplication on the critical paths [default = %s] -x : toggle balancing multi-input EXORs [default = %s] -v : print verbose information [default = %s] Does not work for a logic network. MUX restructuring has failed. usage: mux_struct [-vh] performs MUX restructuring of the current network TFmcsfhCommand line switch "-T" should be followed by an integer. Cannot renode a network that is not an AIG (run "strash"). Renoding has failed. usage: multi [-TF ] [-msfch] transforms an AIG into a logic network by creating larger nodes -F : the maximum fanin size after renoding [default = %d] -T : the threshold for AIG node duplication [default = %d] (an AIG node is the root of a new node after renoding if this leads to duplication of no more than %d AIG nodes, that is, if [(numFanouts(Node)-1) * size(MFFC(Node))] <= %d) -m : creates multi-input AND graph [default = %s] -s : creates a simple AIG (no renoding) [default = %s] -f : creates a factor-cut network [default = %s] -c : performs renoding to derive the CNF [default = %s] KCFAabscivhCommand line switch "-F" should be followed by a positive integer. Command line switch "-A" should be followed by a positive integer. Cannot optimize two parameters at the same time. Incorrect LUT size (%d). Incorrect number of cuts. usage: renode [-KCFA ] [-sbciav] transforms the AIG into a logic network with larger nodes while minimizing the number of FF literals of the node SOPs -K : the max cut size for renoding (2 < num < %d) [default = %d] -C : the max number of cuts used at a node (0 < num < 2^12) [default = %d] -F : the number of area flow recovery iterations (num >= 0) [default = %d] -A : the number of exact area recovery iterations (num >= 0) [default = %d] -s : toggles minimizing SOP cubes instead of FF lits [default = %s] -b : toggles minimizing BDD nodes instead of FF lits [default = %s] -c : toggles minimizing CNF clauses instead of FF lits [default = %s] -i : toggles minimizing MV-SOP instead of FF lits [default = %s] -a : toggles area-oriented mapping [default = %s] Cleanup for PIs and POs is not enabled. Cleanup has failed. usage: cleanup [-iovh] for logic networks, removes dangling combinatinal logic for AIGs, removes PIs w/o fanout and POs driven by const-0 -i : toggles removing PIs without fanout [default = %s] -o : toggles removing POs with const-0 drivers [default = %s] The classical (SIS-like) sweep can only be performed on a logic network. usage: sweep [-svh] removes dangling nodes; propagates constant, buffers, inverters -s : toggle sweeping buffers/inverters only [default = %s] -v : toggle printing verbose information [default = %s] SDNWMPsdzcnxvwhCommand line switch "-W" should be followed by an integer. Command line switch "-M" should be followed by an integer. Command line switch "-P" should be followed by an integer. The network does not have internal nodes. Fast extract can only be applied to a logic network (run "renode" or "if"). Fast extract can only be applied to a logic network with SOP local functions (run "bdd; sop"). Cannot perform "fx" because the number cube pairs exceeds the limit (%d). usage: fx [-SDNWMP ] [-sdzcnxvwh] performs unate fast extract on the current network -S : max number of single-cube divisors to consider [default = %d] -D : max number of double-cube divisors to consider [default = %d] -N : max number of divisors to extract during this run [default = %d] -W : lower bound on the weight of divisors to extract [default = %d] -M : upper bound on literal count of divisors to extract [default = %d] -P : skip "fx" if cube pair count exceeds this limit [default = %d] -s : use only single-cube divisors [default = %s] -d : use only double-cube divisors [default = %s] -z : use zero-weight divisors [default = %s] -c : use complement in the binary case [default = %s] -n : use new implementation of fast extract [default = %s] -x : use only canonical divisors (AND, XOR, MUX) [default = %s] -v : print verbose information [default = %s] -w : print additional information [default = %s] Nvwhusage: fxch [-N ] [-svwh] performs fast extract with cube hashing on the current network -N : max number of divisors to extract during this run [default = unused] This command was contributed by Bruno Schmitt from UFRGS in May 2016. The author can be contacted as boschmitt at inf.ufrgs.br VNIgrsvhCommand line switch "-V" should be followed by an integer that is -1 or larger. Command line switch "-N" should be followed by a positive integer. Command line switch "-I" should be followed by a positive integer. This command can only be applied to a logic network (run "renode" or "if"). usage: eliminate [-VNI ] [-grsvh] traditional "eliminate -1", which collapses the node into its fanout if the node's variable appears in the fanout's factored form only once -V : the "value" parameter used by "eliminate" in SIS [default = %d] -N : the maximum node support after collapsing [default = %d] -I : the maximum number of iterations [default = %d] -g : toggle using greedy eliminate (without "value") [default = %s] -r : use the reverse topological order [default = %s] -s : toggle eliminating similar nodes [default = %s] grvpshGlobal DSD has failed. This command is only applicable to logic BDD networks. Performing recursive DSD and MUX decomposition of local functions. Recursive DSD has failed. This command is only applicable to logic BDD networks (run "bdd"). Performing simple non-recursive DSD of local functions. Simple DSD of local functions has failed. usage: dsd [-grvpsh] decomposes the network using disjoint-support decomposition -g : toggle DSD of global and local functions [default = %s] globallocal -r : toggle recursive DSD/MUX and simple DSD [default = %s] recursive DSD/MUXsimple DSD -v : prints DSD statistics and runtime [default = %s] -p : prints DSD structure to the standard output [default = %s] -s : use short PI names when printing DSD structure [default = %s] The number of primary inputs is more than 16. usage: sparsify [-N num] [-vh] creates incompletely-specified function -N : the percentage of on-set and off-set minterms (1 <= num <= 100) [default = %d] -v : prints verbose information [default = %s] NQSLszfovwhCommand line switch "-Q" should be followed by an integer. This command can only be applied to a logic network. The number of shared variables (%d) is not in the range 0 <= S <= 3. Resynthesis has failed. usage: lutpack [-NQSL ] [-szfovwh] performs "rewriting" for LUT network; determines LUT size as the max fanin count of a node; if the network is not LUT-mapped, packs it into 6-LUTs (there is another command for resynthesis after LUT mapping, "mfs2") -N : the max number of LUTs in the structure (2 <= num) [default = %d] -Q : the max number of LUTs not in MFFC (0 <= num) [default = %d] -S : the max number of LUT inputs shared (0 <= num <= 3) [default = %d] -L : max level increase after resynthesis (0 <= num) [default = %d] -s : toggle iteration till saturation [default = %s] -z : toggle zero-cost replacements [default = %s] -f : toggle using only first node and first cut [default = %s] -o : toggle using old implementation [default = %s] -v : toggle verbose printout [default = %s] -w : toggle detailed printout of decomposed functions [default = %s] Command line switch "-K" should be followed by an integer. The command has failed. usage: lutmin [-K ] [-vh] perform FPGA mapping while minimizing the LUT count as described in the paper T. Sasao and A. Mishchenko: "On the number of LUTs to implement logic functions". -K : the LUT size to use for the mapping (2 <= num) [default = %d] WFDMLCdraestpgvwhusage: mfs [-WFDMLC ] [-draestpgvh] performs don't-care-based optimization of logic networks -W : the number of levels in the TFO cone (0 <= num) [default = %d] -F : the max number of fanouts to skip (1 <= num) [default = %d] -D : the max depth nodes to try (0 = no limit) [default = %d] -M : the max node count of windows to consider (0 = no limit) [default = %d] -L : the max increase in node level after resynthesis (0 <= num) [default = %d] -C : the max number of conflicts in one SAT run (0 = no limit) [default = %d] -d : toggle performing redundancy removal [default = %s] -r : toggle resubstitution and dc-minimization [default = %s] dc-min -a : toggle minimizing area or area+edges [default = %s] area+edges -e : toggle high-effort resubstitution [default = %s] -s : toggle evaluation of edge swapping [default = %s] -t : toggle using artificial one-hotness conditions [default = %s] -p : toggle power-aware optimization [default = %s] -g : toggle using new SAT solver [default = %s] -v : toggle printing optimization summary [default = %s] -w : toggle printing detailed stats for each node [default = %s] WFDMLCZNIdaeijvwhCommand line switch "-I" should be followed by an integer. The number of k-inductive frames is not specified. The set of k-inductive flops is not specified. The saved flop count (%d) does not match that of the current network (%d). usage: mfs2 [-WFDMLCZNI ] [-daeijvwh] -Z : treat the first logic nodes as fixed (0 = none) [default = %d] -N : the max number of nodes to try (0 = all) [default = %d] -i : toggle using inductive don't-cares [default = %s] -j : toggle using all flops when "-i" is enabled [default = %s] -I : the number of additional frames inserted [default = %d] IOVFKLHRMCNPWDEarmzoespdlvwhThe number of TFI levels (switch "-I") should be at least 1. Command line switch "-V" should be followed by an integer. Command line switch "-H" should be followed by an integer. Command line switch "-E" should be followed by an integer. This command can only be applied to a mapped logic network. usage: mfs3 [-IOVFKLHRMCNPWDE ] [-armzespdlvwh] performs don't-care-based optimization of mapped networks -I : the number of levels in the TFI cone (1 <= num) [default = %d] -O : the number of levels in the TFO cone (0 <= num) [default = %d] -V : the number of levels in the TFI/TFO cone (1 <= num) [default = %d] -K : the max number of variables (2 <= num <= 8 ) [default = %d] -L : the min size of max fanout-free cone (MFFC) (area-only) [default = %d] -H : the max size of max fanout-free cone (MFFC) (area-only) [default = %d] -R : the max number of decomposition rounds (1 <= num <= 4) [default = %d] -P : one particular node to try (0 = none) [default = %d] -W : size of timing window in percents (0 <= num <= 100) [default = %d] -D : size of critical-timing delay-delta (in picoseconds) [default = %d] -E : delay-area tradeoff (in picoseconds per area-unit) [default = %d] -a : toggle area minimization [default = %s] -r : toggle using reverse topo order for area minimization [default = %s] -m : toggle detecting multi-input AND/OR gates [default = %s] -e : toggle using more effort [default = %s] -s : toggle using simulation [default = %s] -p : toggle printing decompositions [default = %s] -d : toggle printing delay profile statistics [default = %s] -l : toggle printing library usage statistics [default = %s] IOWFLCadvwhCommand is only applicable to LUT size no more than 6. Command "mfse" has failed. usage: mfse [-IOWFLC ] [-advwh] -I : the number of levels in the TFI cone (2 <= num) [default = %d] -W : the max number of nodes in the window (1 <= num) [default = %d] -a : toggle minimizing area [default = %s] -d : toggle using Ashenhurst decomposition [default = %s] Command line switch "-K" should be followed by a positive integer. usage: logicpush [-K num] [-vh] performs logic pushing to reduce structural bias -K : the LUT size used in the mapping [default = %d] usage: trace [-lvh] performs delay trace of LUT-mapped network -l : toggle using unit- or LUT-library-delay model [default = %s] NPvhGlitching adds %7.2f %% of signal transitions, compared to switching. usage: glitch [-NP ] [-vh] comparing glitching activity to switching activity -N : the number of random patterns to use (0 < num < 1000000) [default = %d] -P : once in how many cycles an input changes its value [default = %d] PNlvwhusage: speedup [-PN ] [-lvwh] transforms LUT-mapped network into an AIG with choices; the choices are added to speedup the next round of mapping -P : delay delta defining critical path for library model [default = %d%%] -N : the max critical path degree for resynthesis (0 < num < 6) [default = %d] usage: powerdown [-PN ] [-vwh] the choices are added to power down the next round of mapping -P : switching propability delta defining power critical edges [default = %d%%] (e.g. 5% means hot wires switch with probability: 0.45 <= p <= 0.50 (max) Idrvhusage: addbuffs [-I num] [-drvh] adds buffers to create balanced CI/CO paths -I : the number of refinement iterations [default = %d] -d : toggle using only CI-to-CO levelized order [default = %s] -r : toggle using only CO-to-C1 levelized order [default = %s] NSDLFscvwhAbc_CommandMerge(): There is no mapped network to merge LUTs. usage: merge [-NSDLF ] [-scwvh] creates pairs of topologically-related LUTs -N : the max LUT size for merging (1 < num) [default = %d] -S : the max total support size after merging (1 < num) [default = %d] -D : the max distance in terms of LUTs (0 < num) [default = %d] -L : the max difference in levels (0 <= num) [default = %d] -F : the max number of fanouts to stop traversal (0 < num) [default = %d] -s : toggle the use of nodes without support overlap [default = %s] -c : toggle the use of TFI/TFO nodes as candidates [default = %s] ANvhCommand line switch "-A" should be followed by an integer. Input file is not given. The number of variables cannot be less than 6. usage: testdec [-AN ] [-vh] testbench for Boolean decomposition algorithms -A : decomposition algorithm [default = %d] 0: none (reading and writing the file) 1: algebraic factoring applied to ISOP 2: bi-decomposition with cofactoring 3: disjoint-support decomposition with cofactoring 4: updated disjoint-support decomposition with cofactoring 5: enumerating decomposable variable sets 6: disjoint-support decomposition with cofactoring and boolean difference analysis from V. Callegaro, F. S. Marranghello, M. G. A. Martins, R. P. Ribas and A. I. Reis, "Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis," ICCD'15. -N : the number of support variables (binary files only) [default = unused] : a text file with truth tables in hexadecimal, listed one per line, or a binary file with an array of truth tables (in this case, -N is required to determine how many functions are stored) ANdbvhusage: testnpn [-AN ] [-dbvh] testbench for computing (semi-)canonical forms of completely-specified Boolean functions up to 16 varibles -A : semi-caninical form computation algorithm [default = %d] 0: uniqifying truth tables 1: exact NPN canonical form by brute-force enumeration 2: semi-canonical form by counting 1s in cofactors 3: Jake's hybrid semi-canonical form (fast) 4: Jake's hybrid semi-canonical form (high-effort) 5: new fast hybrid semi-canonical form 6: new phase canonical form 7: new hierarchical matching 8: hierarchical matching by XueGong Zhou at Fudan University, Shanghai 9: adjustable algorithm (heuristic) by XueGong Zhou at Fudan University, Shanghai 10: adjustable algorithm (exact) by XueGong Zhou at Fudan University, Shanghai 11: new cost-aware exact algorithm by XueGong Zhou at Fudan University, Shanghai -d : toggle dumping resulting functions into a file [default = %s] -b : toggle dumping in binary format [default = %s] TNvhusage: testrpo [-NT ] [-vh] RPO algorithm developed and implemented by Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas and Andre' I. Reis at Federal University of Rio Grande do Sul, Porto Alegre, Brazil -T : the number of recursions accepted before abort [default = INFINITE] usage: testtruth [-vh] printing truth table stats crvwhExpecting three file names on the command line. usage: runeco [-crvwh] performs computation of patch functions during ECO, as described in the following paper: A. Q. Dao et al "Efficient computation of ECO patch functions", Proc. DAC'18 https://people.eecs.berkeley.edu/~alanmi/publications/2018/dac18_eco.pdf (currently only applicable to benchmarks from 2017 ICCAD CAD competition http://cad-contest-2017.el.cycu.edu.tw/Problem_A/default.html as follows: "runeco unit1/F.v unit1/G.v unit1/weight.txt; cec -n out.v unit1/G.v") -c : toggle checking that the problem has a solution [default = %s] -r : toggle using random permutation of support variables [default = %s] -w : toggle printing more verbose information [default = %s] usage: rungen [-vh] experimental command WBLUofbruvwhExpecting two or three file names on the command line. usage: runsim [-WBLU] [-ofbruvwh] [-N ] experimental simulation command -W : the number of words of simulation info [default = %d] -B : the beam width parameter [default = %d] -L : the lower bound on level [default = %d] -U : the upper bound on level [default = %d] -o : toggle using a different node ordering [default = %s] -f : toggle using experimental feature [default = %s] -b : toggle using buffers [default = %s] -r : toggle using random permutation of support variables [default = %s] -u : toggle using topological info to select support variables [default = %s] -v : toggle printing verbose information [default = %s] -w : toggle printing more verbose information [default = %s] usage: runtest [-fvh] lxzvwhThis command can only be applied to an AIG (run "strash"). AIG resynthesis cannot be applied to AIGs with choice nodes. Rewriting has failed. usage: rewrite [-lzvwh] performs technology-independent rewriting of the AIG -l : toggle preserving the number of levels [default = %s] -z : toggle using zero-cost replacements [default = %s] -v : toggle verbose printout [default = %s] -w : toggle printout subgraph statistics [default = %s] NlzvhThe cone size cannot exceed 15. For don't-care to work, containing cone should be larger than collapsed node. Refactoring has failed. usage: refactor [-N ] [-lzvh] performs technology-independent refactoring of the AIG -N : the max support of the collapsed node [default = %d] -l : toggle preserving the number of levels [default = %s] -z : toggle using zero-cost replacements [default = %s] KNFlzvwhCan only compute cuts for %d <= K <= %d. Can only resubstitute at most 3 nodes. usage: resub [-KN ] [-lzvwh] performs technology-independent restructuring of the AIG -K : the max cut size (%d <= num <= %d) [default = %d] -N : the max number of nodes to add (0 <= num <= 3) [default = %d] -F : the number of fanout levels for ODC computation [default = %d] -w : toggle verbose printout of ODC computation [default = %s] KcvhCascade synthesis has failed. usage: cascade [-K ] [-cvh] performs LUT cascade synthesis for the current network -K : the number of LUT inputs [default = %d] -c : check equivalence after synthesis [default = %s] A lookup-table cascade is a programmable architecture developed by Professor Tsutomu Sasao (sasao@cse.kyutech.ac.jp) at Kyushu Institute of Technology. This work received Takeda Techno-Entrepreneurship Award: http://www.lsi-cad.com/sasao/photo/takeda.html Kavhusage: extract [-K ] [-avh] extracts shared logic from multi-input gates -K : the minimum gate size to consider for extraction [default = %d] -a : toggle multi-input XOR vs multi-input AND [default = %s] MNocvhusage: varmin [-MN ] [-ocvh] performs support minimization -M : the number of ones in the combination [default = %d] -N : the number of variables in the problem [default = %d] -o : toggle computing reduced difference matrix [default = %s] -c : toggle verifying the final result [default = %s] gcsvwhOnly applicable to a logic network. _faults.txtusage: faultclasses [-gcsvwh] computes equivalence classes of faults in the given mapped netlist; the fault list with faults in the format: should be read by command "read_fins" before calling this command -g : toggle generating a fault list for the current mapped network [default = %s] -c : toggle using only stuck-at faults in the generated fault list [default = %s] -s : toggle detecting sequential equivalence classes [default = %s] -v : toggle verbose printout during computation [default = %s] -w : toggle printing of resulting fault equivalence classes [default = %s] DASCatvhToo many functions (at most 16 supported). Only 8-variable functions are supported. All functions need to have the same size. Could not find AIG within given resource constraints, retry with different value for -C. Could not find network within given resource constraints, retry with different value for -C. usage: exact [-DSC ] [-A ] [-atvh] ... finds optimum networks using SAT-based exact synthesis for hex truth tables ... -D : constrain maximum depth (if too low, algorithm may not terminate) -A : input arrival times (comma separated list) -S : number of start gates in search [default = %d] -C : the limit on the number of conflicts; turn off with 0 [default = %d] -a : toggle create AIG [default = %s] -t : run test suite -v : toggle verbose printout [default = %s] This command was contributed by Mathias Soeken from EPFL in July 2016. The author can be contacted as mathias.soeken at epfl.ch Digit >= 0 && Digit < 16int Abc_TtReadHex(word *, char *)int Abc_TtReadHexDigit(char)CavwhBMS manager is already started.usage: bms_start [-C ] [-avwh] [] starts BMS manager for recording optimum networks if is specified, store entries are read from that file -C : the limit on the number of conflicts [default = %d] -a : toggle create AIG [default = %s] -w : toggle very verbose printout [default = %s] This command was contributed by Mathias Soeken from EPFL in July 2016. The author can be contacted as mathias.soeken at epfl.ch BMS manager is not started.usage: bms_stop [-C ] [-vh] [] stops BMS manager for recording optimum networks if is specified, store entries are written to that file usage: bms_ps [-h] shows statistics about BMS manager INRfcrgvhCannot sythesize MAJ gate with an even number of inputs (%d). usage: majexact [-INR ] [-fcrgvh] exact synthesis of multi-input MAJ using MAJ3 gates -I : the number of input variables [default = %d] -N : the number of MAJ3 nodes [default = %d] -R : the number of additional connections [default = %d] -f : toggle using constant fanins [default = %s] -c : toggle using cascade topology [default = %s] -r : toggle using random topology [default = %s] -g : toggle using Glucose 3.0 by Gilles Audemard and Laurent Simon [default = %s] INTaogvhTruth table should be given on the command line. Truth table is expected to have %d hex digits (instead of %d). Function with %d variales cannot be implemented with %d two-input gates. Function should not have more than 10 inputs. usage: twoexact [-INT ] [-aogvh] exact synthesis of multi-input function using two-input gates -N : the number of two-input nodes [default = %d] -T : the runtime limit in seconds [default = %d] -a : toggle using only AND-gates (without XOR-gates) [default = %s] -o : toggle using additional optimizations [default = %s] : truth table in hex notation For example, command line "twoexact -g -I 5 -N 12 169AE443" synthesizes the smallest circuit composed of two-input gates for the only NPN class of 5-input functions that requires 12 gates; all other functions can be realized with 11 two-input gates or less (see Section 7.1.2 "Boolean evaluation" in the book by Donald Knuth http://www.cs.utsa.edu/~wagner/knuth/fasc0c.pdf) INKTiaogvhFunction with %d variales cannot be implemented with %d %d-input LUTs. Node size should not be more than 6 inputs. usage: lutexact [-INKT ] [-iaogvh] exact synthesis of I-input function using N K-input gates -N : the number of K-input nodes [default = %d] -K : the number of node fanins [default = %d] -i : toggle using incremental solving [default = %s] -a : toggle using only AND-gates when K = 2 [default = %s] MINKiaoegvhCurrently only support majority with 5, 7 or 9 inputs. The number of variables (-I num) needs to be specified on the command line. The number of nodes (-N num) needs to be specified on the command line. Cannot synthesize majority in the non-incremental mode (use '-i'). Cannot synthesize LUT4 and larger in non-incremental mode (use '-i'). usage: allexact [-MIKN ] [-iaoevh] -M : the majority support size (overrides -I and -K) [default = %d] -o : toggle using node ordering by fanins [default = %s] -e : toggle enumerating all solutions [default = %s] File name is not given on the command line. usage: testexact tests solution of the exact synthesis problem : file name in the specified format Ndvhusage: majgen [-N ] [-dvh]> generates networks for majority gates -N : the maximum number of variables [default = %d] -d : toggle dumping functions into a file [default = %s] This command is only applicable to strashed networks. Converting to a logic network has failed. usage: logic [-h] transforms an AIG into a logic network with SOPs LlhThe network is already combinational. usage: comb [-L ] [-lh] converts comb network into seq, and vice versa -L : number of latches to add to comb network (0 = do not add) [default = %d] -l : toggle converting latches to PIs/POs or removing them [default = %s] removeconvertPcmitnhAbc_CommandMiter(): The number of outputs should be even. The miter (current network) is transformed by XORing POs pair-wise. Miter computation has failed. unusedusage: miter [-P ] [-cimtnh] computes the miter of the two circuits -P : output partition size [default = %s] -c : toggles deriving combinational miter (latches as POs) [default = %s] -i : toggles deriving implication miter (file1 => file2) [default = %s] -m : toggles creating multi-output miter [default = %s] -t : toggle XORing pair-wise POs of the miter [default = %s] -n : toggle ignoring names when matching CIs/COs [default = %s] file1 : (optional) the file with the first network file2 : (optional) the file with the second network if no files are given, uses the current network and its spec if one file is given, uses the current network and the file The file with node names is not given. The base network should be logic network from BLIF file. Cannot read node names from file "%s". usage: miter2 [-h] derives specialized miter : file name with node names The network is not strashed. The number of POs should be even. Demitering has failed. usage: demiter [-dvh] splits sequential miter into two circuits -d : expects a dual-output miter (without XORs) [default = %s] -v : toggles outputting verbose information [default = %s] rxhExpanded %d outputs into %d outputs using OR decomposition. The output(s) cannot be structurally decomposed. ORing the POs has failed. usage: orpos [-rxh] creates single-output miter by ORing the POs of the current network -r : performs the reverse transform (OR decomposition) [default = %s] -x : toggles combining the PO using XOR [default = %s] The network already has one PO. The miter has latches. ORing is not performed. ANDing the POs has failed. usage: andpos [-h] creates single-output miter by ANDing the POs of the current network NsohThe output index is not specified. The output index is larger than the allowed POs. usage: zeropo [-N ] [-soh] replaces the PO driver by constant 0 -N : the zero-based index of the PO to replace [default = %d] -s : performs comb sweep after removimg a PO [default = %s] -o : toggles using const 1 instead of const 0 [default = %s] usage: swappos [-N ] [-h] swap the 0-th PO with the -th PO -N : the zero-based index of the PO to swap [default = %d] Nzhusage: removepo [-N ] [-zh] remove PO with number if it is const0 -N : the zero-based index of the PO to remove [default = %d] -z : toggle removing const1 instead of const0 [default = %s] const0const1CEX array is not defined. Run "bmc3 -az", "sim3 -az", or "pdr -az". CEX array size (%d) does not match the number of outputs (%d). Removing SAT outputs has failed. usage: dropsat [-sh] replaces satisfiable POs by constant 0 and cleans up the AIG -s : toggles skipping sequential sweep [default = %s] -v : toggles verbose output [default = %s] dummy_piusage: addpi [-h] if the network has no PIs, add one dummy PI The network to append is not given. The base network should be strashed for the appending to work. The second network has latches. Appending does not work for such networks. Appending the networks failed. usage: append [-h] appends a combinational network on top of the current network : file name with the second network The base network should be in the logic form. The current network has latches. This command does not work for such networks. The second network has latches. This command does not work for such networks. The PO count (%d) of the first network is not equal to PI count (%d) of the second network. usage: putontop [-h] connects PIs of network in to POs of current network Unrolling the network has failed. usage: frames [-F ] [-ivh] unrolls the network for a number of time frames -F : the number of frames to unroll [default = %d] -i : toggles initializing the first frame [default = %s] -v : toggles outputting verbose information [default = %s] NFivhPrefix (%d) cannot be more than the number of frames (%d). usage: dframes [-NF ] [-ivh] unrolls the network with simplification -N num : the number of frames to use as prefix [default = %d] -F num : the number of frames to unroll [default = %d] -i : toggles initializing the first frame [default = %s] -v : toggles outputting verbose information [default = %s] CdnhConverting to SOP is possible only for logic networks. usage: sop [-C num] [-dnh] converts node functions to SOP -C num : the limit on the number of cubes at a node [default = %d] -d : toggles using only positive polarity [default = %s] -n : toggles using only negative polarity [default = %s] Converting to BDD is possible only for logic networks. The logic network is already in the BDD form. usage: bdd [-rsh] converts node functions to BDD -r : toggles enabling dynamic variable reordering [default = %s] -s : toggles constructing BDDs directly from SOPs [default = %s] Converting to AIG is possible only for logic networks. The logic network is already in the AIG form. usage: aig [-h] converts node functions to AIG Variable reordering is possible when node functions are BDDs (run "bdd"). usage: reorder [-vh] reorders local functions of the nodes using sifting Bi-decomposition only works when node functions are AIGs (run "aig"). usage: bidec [-vh] applies bi-decomposition to local functions of the nodes Cannot open file "%s" with the BDD variable order. usage: order [-rvh] computes a good static CI variable order -r : toggle reverse ordering [default = %s] : (optional) file with the given variable order BghThe current network should be an AIG. Only a BDD logic network can be converted to MUXes. Converting to MUXes has failed. usage: muxes [-B num] [-gh] converts the current network into a network derived by replacing all nodes by DAGs isomorphic to the local BDDs -g : toggle visualizing the global BDDs of primary outputs [default = %s]. Only a SOP logic network can be transformed into cubes. Converting to cubes has failed. usage: cubes [-xh] converts the current network into a network derived by creating a separate node for each product and sum in the local SOPs -x : toggle using XOR instead of OR [default = %s] The number of logic levels is more than 1 (collapse the network and try again). Using the complement of the current network as its offset. Failed to read the current network from file "%s". usage: expand [-vh] expands cubes against the offset -v : toggle verbose output [default = %s] file : (optional) representation of on-set plus dc-set usage: splitsop [-N num] [-vh] splits nodes whose SOP size is larger than the given one -N num : the maximum number of cubes after splitting [default = %d] The current network has no latches. Extracting sequential don't-cares works only for AIGs (run "strash"). Extracting sequential don't-cares has failed. usage: ext_seq_dcs [-vh] create EXDC network using unreachable states TBFLproyvhReachability analysis works only for AIGs (run "strash"). The miters is already solved; skipping the command. usage: reach [-TBF num] [-L file] [-proyvh] verifies sequential miter using BDD-based reachability -T num : approximate time limit in seconds (0=infinite) [default = %d] -B num : max number of nodes in the intermediate BDDs [default = %d] -F num : max number of reachability iterations [default = %d] -L file: the log file name [default = %s] -p : enable partitioned image computation [default = %s] -r : enable dynamic BDD variable reordering [default = %s] -o : toggles BDD variable reordering during image computation [default = %s] -y : skip checking property outputs [default = %s] ORmashCurrently can only be applied to the logic network or an AIG. The node is not specified. The 0-based output number (%d) is larger than the number of outputs (%d). Writing the logic cone of one node has failed. usage: cone [-OR num] [-amsh] replaces the current network by one logic cone -a : toggle keeping all CIs or structral support only [default = %s] structural -m : toggle keeping only MFFC or complete TFI cone [default = %s] MFFCTFI cone -s : toggle comb or sequential cone (works with "-O num") [default = %s] -O num : (optional) the 0-based number of the CO to extract -R num : (optional) the number of outputs to extract name : (optional) the name of the node to extract Currently can only be applied to a logic network. Splitting one node has failed. usage: node [-h] replaces the current network by the network composed of one node name : the node name Constant should be 0 or 1. usage: cof [-h] replaces one node in a logic network by constant 0 or 1 : the node to replace : the constant to replace the node with name : the node name Currently only works for structurally hashed circuits. Currently can only works for combinational circuits. Currently expects a single-output miter. usage: topmost [-N num] [-h] replaces the current network by several of its topmost levels -N num : max number of levels [default = %d] The PO driver is complemented. AND-decomposition is impossible. The PO driver is not a node. AND-decomposition is impossible. usage: topand [-h] performs AND-decomposition of single-output combinational miter Trimming works only for AIGs (run "strash"). usage: trim [-h] removes POs fed by constants and PIs w/o fanout usage: short_names [-h] replaces PI/PO/latch names by short char strings The network to take names from is not given. The PI count (%d) of the first network is not equal to PI count (%d) of the second network. The PO count (%d) of the first network is not equal to PO count (%d) of the second network. The flop count (%d) of the first network is not equal to flop count (%d) of the second network. usage: move_names [-h] moves PI/PO/latch names from the other network : file with network that has required names The network has no EXDC. usage: exdc_free [-h] frees the EXDC network of the current network usage: exdc_get [-h] replaces the current network by the EXDC of the current network Cannot open input file "%s". .mv.eqnDid you mean "%s"?Reading network from file has failed. usage: exdc_set [-h] sets the network from file as EXDC for the current network : file with the new EXDC network usage: care_set [-h] sets the network from file as a care for the current network : file with the new care network KMtfdxyglzamjvoshCut computation is available only for AIGs (run "strash"). Can only compute the cuts for %d <= K <= %d. Cannot compute both DAG cuts and tree cuts at the same time. pCutOraclesrc/base/abci/abc.cint Abc_CommandCut(Abc_Frame_t *, int, char **)usage: cut [-K num] [-M num] [-tfdcovamjsvh] computes k-feasible cuts for the AIG -K num : max number of leaves (%d <= num <= %d) [default = %d] -M num : max number of cuts stored at a node [default = %d] -t : toggle truth table computation [default = %s] -f : toggle filtering of duplicated/dominated [default = %s] -d : toggle dropping when fanouts are done [default = %s] -x : toggle computing only DAG cuts [default = %s] -y : toggle computing only tree cuts [default = %s] -g : toggle computing only global cuts [default = %s] -l : toggle computing only local cuts [default = %s] -z : toggle fancy computations [default = %s] -a : toggle recording cut functions [default = %s] -m : toggle delay-oriented FPGA mapping [default = %s] -j : toggle removing fanouts due to XOR/MUX [default = %s] -s : toggle creating library of 6-var functions [default = %s] The espresso command is currently disabled. This command is currently disabled. NAKLatsembfnrvhThe number of variables should be a positive integer. Generating adder tree with %d arguments and %d bits. %%read %s; %%blast; &putType of circuit is not specified. read %susage: gen [-NAKL num] [-atsembfnrvh] generates simple circuits -N num : the number of variables [default = %d] -A num : the number of agruments (for adder tree) [default = %d] -K num : the LUT size (to be used with switch -f) [default = %d] -L num : the LUT count (to be used with switch -f) [default = %d] -a : generate ripple-carry adder [default = %s] -t : generate an adder tree [default = %s] -s : generate a sorter [default = %s] -e : generate a mesh [default = %s] -m : generate a multiplier [default = %s] -b : generate a signed Booth multiplier [default = %s] -f : generate a LUT FPGA structure [default = %s] -n : generate one-hotness conditions [default = %s] -r : generate random single-output function [default = %s] : output file name IOSLPQvhThe number of inputs. states, lines, and probablity should be positive integers. usage: genfsm [-IOSLPQ num] [-vh] generates random FSM in KISS format -I num : the number of input variables [default = %d] -O num : the number of output variables [default = %d] -S num : the number of state variables [default = %d] -L num : the number of lines (product terms) [default = %d] -P num : percentage propability of a variable present in the input cube [default = %d] -Q num : percentage propability of a variable present in the output cube [default = %d] IPsxivhOnly works for strashed networks. usage: cover [-IP num] [-sxvh] decomposition into a network of SOP/ESOP PLAs (this command is known to have bugs) -I num : maximum number of inputs [default = %d] -P num : maximum number of products [default = %d] -s : toggle the use of SOPs [default = %s] -x : toggle the use of ESOPs [default = %s] Deriving new circuit structure for the current network. Computation of interplants as a relation only works for single-output functions. Use command "cone" to extract one output cone from the multi-output network. usage: inter [-rvh] derives interpolant of two networks representing onset and offset; -r : toggle computing interpolant as a relation [default = %s] Comments: The networks given on the command line should have the same CIs/COs. If only one network is given on the command line, this network is assumed to be the offset, while the current network is the onset. If no network is given on the command line, the current network is assumed to be the onset and its complement is taken to be the offset. The resulting interpolant is stored as the current network. To verify that the interpolant agrees with the onset and the offset, save it in file "inter.blif" and run the following: (a) "miter -i ; iprove" (b) "miter -i ; iprove" where is the network derived by complementing the outputs of : "r ; st -i; w " Only works for logic SOP networks. usage: double [-vh] puts together two parallel copies of the current network Expecting two files names on the command line. usage: bb2wb [-svh] replaces black boxes by white boxes with AND functions (file names should have standard extensions, e.g. "blif") -s : toggle using sequential white boxes [default = %s] -v : toggle verbose output [default = %s] : input file with design containing black boxes : output file with design containing white boxes Currently, command "outdec" works for 1-lit and 2-lit primes only. usage: outdec [-Lvh] performs prime decomposition of the first output -L num : the number of literals in the primes [default = %d] Only works for logic networks. The fanout limit should be more than 1. usage: nodedup [-Nvh] duplicates internal nodes with high fanout -N num : the number of fanouts to start duplication [default = %d] CKDNMaovwhusage: test [-CKDNM] [-aovwh] testbench for new procedures -C num : the max number of cuts [default = %d] -K num : the max number of leaves [default = %d] -D num : the max number of divisors [default = %d] -N num : the max number of node inputs [default = %d] -M num : the max number of ones in the vector [default = %d] -a : toggle using new algorithm [default = %s] -o : toggle using new ordering [default = %s] -w : toggle printing very verbose information [default = %s] IuvhThis command cannot be applied to an AIG with choice nodes. usage: qvar [-I num] [-uvh] quantifies one variable using the AIG -I num : the zero-based index of a variable to quantify [default = %d] -u : toggle universal quantification [default = %s] IqvhThis command works only for sequential circuits. usage: qrel [-qvh] computes transition relation of the sequential network -q : perform quantification of inputs [default = %s] This command works only for combinational transition relations. This command works only for strashed networks. The transition relation should have one output. The transition relation should have an even number of inputs. usage: qreach [-I num] [-vh] computes unreachable states using AIG-based quantification assumes that the current network is a transition relation assumes that the initial state is composed of all zeros -I num : the number of image computations to perform [default = %d] The network should have at least two outputs. usage: senseinput [-C num] [-vh] computes sensitivity of POs to PIs under constraint constraint should be represented as the last PO -C num : the max number of conflicts at a node [default = %d] usage: istrash [-h] perform sequential structural hashing Khusage: icut [-K num] [-h] computes sequential cuts of the given size -K num : the number of cut inputs (2 <= num <= 6) [default = %d] usage: irw [-lzvh] perform combinational AIG rewriting CNflzrvwhusage: drw [-C num] [-N num] [-lfzrvwh] performs combinational AIG rewriting -C num : the max number of cuts at a node [default = %d] -N num : the max number of subgraphs tried [default = %d] -f : toggle representing fanouts [default = %s] -r : toggle using cut recycling [default = %s] -w : toggle very verbose printout [default = %s] MKCelzvwhThis command only works for cut sizes 4 <= K <= 15. usage: drf [-M num] [-K num] [-C num] [-elzvwh] performs combinational AIG refactoring -M num : the min MFFC size to attempt refactoring [default = %d] -K num : the max number of cuts leaves [default = %d] -C num : the max number of cuts to try at a node [default = %d] -e : toggle extending tbe cut below MFFC [default = %s] blfpvhusage: dc2 [-blfpvh] performs combinational AIG optimization -b : toggle internal balancing [default = %s] -l : toggle updating level [default = %s] -p : toggle power-aware rewriting [default = %s] CLblcvhusage: dchoice [-C num] [-L num] [-blcvh] performs partitioned choicing using new AIG package -L num : the max level of nodes to consider (0 = not used) [default = %d] -c : toggle constructive computation of choices [default = %s] WCSsptgcfrvhusage: dch [-WCS num] [-sptgcfrvh] computes structural choices using a new approach -W num : the max number of simulation words [default = %d] -S num : the max number of SAT variables [default = %d] -s : toggle synthesizing three snapshots [default = %s] -t : toggle simulation of the TFO classes [default = %s] -g : toggle using GIA to prove equivalences [default = %s] -c : toggle using circuit-based SAT vs. MiniSat [default = %s] -f : toggle using faster logic synthesis [default = %s] -r : toggle skipping choices with redundant support [default = %s] usage: drwsat [-bvh] performs combinational AIG optimization for SAT usage: irws [-zvh] perform sequential AIG rewriting usage: iresyn [-lvh] performs combinational resynthesis Clzvhusage: isat [-C num] [-vh] tries to prove the miter constant 0 -C num : limit on the number of conflicts [default = %d] PCLspvhusage: ifraig [-P num] [-C num] [-L num] [-spvh] performs fraiging using a new method -P num : partition size (0 = partitioning is not used) [default = %d] -L num : limit on node level to fraig (0 = fraig all nodes) [default = %d] -s : toggle considering sparse functions [default = %s] -p : toggle proving the miter outputs [default = %s] Csprcvhusage: dfraig [-C num] [-sprcvh] -r : toggle speculative reduction [default = %s] -c : toggle accumulation of choices [default = %s] CKvhThe number of cuts cannot be less than 2. The number of leaves is infeasible. usage: csweep [-C num] [-K num] [-vh] performs cut sweeping using a new method -C num : limit on the number of cuts (C >= 2) [default = %d] -K num : limit on the cut size (3 <= K <= 16) [default = %d] NCFGMILrfbvhThe network has registers. Use "dprove". ERROR in Abc_NtkMiterProve(): Generated counter-example is invalid. UNDECIDED SATISFIABLE (output = %d) UNSATISFIABLE usage: iprove [-NCFGMI num] [-L file] [-rfbvh] performs CEC using a new method -N num : max number of iterations [default = %d] -C num : max starting number of conflicts in mitering [default = %d] -F num : max starting number of conflicts in fraiging [default = %d] -G num : multiplicative coefficient for fraiging [default = %d] -M num : max last-gasp number of conflicts in mitering [default = %d] -I num : max number of clause inspections in all SAT calls [default = %d] -r : toggle the use of rewriting [default = %s] -f : toggle the use of FRAIGing [default = %s] -b : toggle the use of BDDs [default = %s] PIdvhWorks only for combinational networks. The miter should have one primary output. The number of parameter variables is invalid (should be > 0 and < PI num). usage: qbf [-PI num] [-dvh] solves QBF problem EpVxM(p,x) -P num : number of parameters p (should be the first PIs) [default = %d] -I num : quit after the given iteration even if unsolved [default = %d] -d : toggle dumping QDIMACS file instead of solving [default = %s] -v : toggle verbose output [default = %s] usage: npnload loads previously saved 6-input function library from file usage: npnsave saves current 6-input function library into file The bridge mode is not available. There is no AIG in the &-space. There is no network in the main-space. The main-space network is not an AIG. usage: send_aig -a sends current AIG to the bridge -a : toggle sending AIG from &-space [default = %s] -b : toggle sending netlist tagged as "abstraction". [default = %s] Status is "sat", but current CEX is not available. usage: send_status sends current status to the bridge usage: backup [-h] backs up the current network There is no backup network. usage: restore [-h] restores the current network RDCrscptvaehCan only fraig a logic network or an AIG. Fraiging has failed. usage: fraig [-R num] [-D num] [-C num] [-rscpvtah] transforms a logic network into a functionally reduced AIG (known bugs: takes an UNSAT miter and returns a SAT one) (there are newer fraiging commands, "ifraig" and "dfraig") -R num : number of random patterns (127 < num < 32769) [default = %d] -D num : number of systematic patterns (127 < num < 32769) [default = %d] -C num : number of backtracks for one SAT problem [default = %s] infinity -r : toggle functional reduction [default = %s] -e : toggle functional sweeping using EXDC [default = %s] -a : toggle between all nodes and DFS nodes [default = %s] -t : toggle using partitioned representation [default = %s] Fraiging in the trust mode has failed. usage: fraig_trust [-h] transforms the current network into an AIG assuming it is FRAIG with choices Fraig storing has failed. usage: fraig_store [-h] saves the current network in the AIG database RDChFraig restoring has failed. usage: fraig_restore [-RDC num] [-h] makes the current network by fraiging the AIG database -R num : number of random patterns (127 < num < 32769) [default = design-dependent] -D num : number of systematic patterns (127 < num < 32769) [default = design-dependent] -C num : number of backtracks for one SAT problem [default = %d] usage: fraig_clean [-h] cleans the internal FRAIG storage ievwhCannot sweep AIGs (use "fraig"). Transform the current network into a logic network. Sweeping has failed. usage: fraig_sweep [-evwh] performs technology-dependent sweep -e : toggle functional sweeping using EXDC [default = %s] -v : prints verbose information [default = %s] -w : prints equivalence class information [default = %s] This command works only for logic networks. The current network has no spec. usage: dress [-C num] [-vh] transfers internal node names from file to the current network : network with names (if not given, the current network spec is used) -C num : the maximum number of conflicts at each node [default = %d] Cnvhusage: dump_equiv [-C num] [-nvh] computes equivalence classes of nodes in and By default this procedure performs matching of primary inputs by name. Those inputs that cannot be matched are treated as free variables. There is no effort to match primary outputs. Indeed, if two outputs are equivalent, they will belong to the same equivalence class in the end. -C num : the maximum number of conflicts at each node [default = %d] -n : enable matching of primary inputs by name [default = %s] -v : prints verbose information [default = %s] : first network whose nodes are considered : second network whose nodes are considered : text file with node equivalence classes KCfvhThe range of allowed values is 3 <= K <= 16. The AIG subgraph recording is already started. File name is not given on the command line. Starting a new record. Reading AIGER has failed. usage: rec_start3 [-K num] [-C num] [-fvh] starts recording AIG subgraphs (should be called for an empty network or after reading in a previous record) -K num : the largest number of inputs [default = %d] -C num : the max number of cuts used at a node (0 < num < 2^12) [default = %d] -f : toggles recording functions without AIG subgraphs [default = %s] -v : toggles additional verbose output [default = %s] : AIGER file with the library This command works only after calling "rec_start3". usage: rec_stop3 [-h] cleans the internal storage for AIG subgraphs This command works for AIGs only after calling "rec_start2". usage: rec_ps3 [-h] prints statistics about the recorded AIG subgraphs This command works for AIGs. This command works for AIGs after calling "rec_start2". usage: rec_add3 [-h] adds subgraphs from the current network to the set abhThe AIG subgraph recording is not started. Library AIG is not available. No structure in the library. usage: rec_dump3 [-abh] -a : toggles dumping TTs into an ASCII file [default = %s] -b : toggles dumping TTs into a binary file [default = %s] : AIGER file to write the library This command works for AIGs only after calling "rec_start3". usage: rec_merge3 [-h] merge libraries DABFSGMarspfuovhCommand line switch "-D" should be followed by a floating point number. Command line switch "-A" should be followed by a floating point number. Command line switch "-B" should be followed by a floating point number. Command line switch "-F" should be followed by a floating point number. Command line switch "-S" should be followed by a floating point number. Command line switch "-G" should be followed by a floating point number. Command line switch "-M" should be followed by a positive integer. Strashing before mapping has failed. Balancing before mapping has failed. The network was strashed and balanced before mapping. not used%.3fusage: map [-DABFSG float] [-M num] [-arspfuovh] performs standard cell mapping of the current network -D float : sets the global required times [default = %s] -A float : "area multiplier" to bias gate selection [default = %.2f] -B float : "delay multiplier" to bias gate selection [default = %.2f] -F float : the logarithmic fanout delay parameter [default = %.2f] -S float : the slew parameter used to generate the library [default = %.2f] -G float : the gain parameter used to generate the library [default = %.2f] -M num : skip gate classes whose size is less than this [default = %d] -a : toggles area-only mapping [default = %s] -r : toggles area recovery [default = %s] -s : toggles sweep after mapping [default = %s] -p : optimizes power by minimizing switching [default = %s] -f : do not use large gates to map high-fanout nodes [default = %s] -u : use standard-cell profile [default = %s] -o : toggles using buffers to decouple combinational outputs [default = %s] -v : toggles verbose output [default = %s] FACEQmxisvhCommand line switch "-C" should be followed by a floating point number. Command line switch "-E" should be followed by a floating point number. Command line switch "-Q" should be followed by a floating point number. usage: amap [-FAC ] [-EQ ] [-mxisvh] -F num : the number of iterations of area flow [default = %d] -A num : the number of iterations of exact area [default = %d] -C num : the maximum number of cuts at a node [default = %d] -E float : sets epsilon used for tie-breaking [default = %f] -Q float : area/delay preference ratio [default = %.2f (area-only)] -m : toggles using MUX matching [default = %s] -x : toggles using XOR matching [default = %s] -i : toggles assuming inverters are free [default = %s] Cannot unmap the network that is not mapped. usage: phase_map [-vh] tries to replace each gate by its complement (area-only) -v : toggles verbose output [default = %s] Unmapping has failed. usage: unmap [-h] replaces the library gates by the logic nodes represented using SOPs Can only attach gates if the nodes have SOP representations. Attaching gates has failed. usage: attach [-h] replaces the SOP functions by the gates from the library Superchoicing works only for the AIG representation (run "strash"). Superchoicing has failed. usage: superc [-h] performs superchoicing (accumulate: "r file.blif; rsup; b; sc; f -ac; wb file_sc.blif") (map without supergate library: "r file_sc.blif; ft; map") -h : print the command usage KNhusage: supercl [-K num] [-N num] [-vh] performs superchoicing for K-LUTs (accumulate: "r file.blif; b; scl; f -ac; wb file_sc.blif") (FPGA map: "r file_sc.blif; ft; read_lut lutlibK; fpga") -K num : the number of LUT inputs [default = %d] -N num : the max size of the cut [default = %d] ThCommand line switch "-T" should be followed by a positive integer. Timing manager is not defined. usage: timescale [-T float] [-vh] scales timing information of the current network -T float : multiplicative factor [default = %f] KCFAGRNTXYDEWSqaflepmrsdbgxyuojiktncvhCommand line switch "-C" should be followed by a positive integer. Command line switch "-G" should be followed by a positive integer no less than 3. Command line switch "-R" should be followed by a floating point number. Command line switch "-N" should be followed by a positive integer no less than 3. Command line switch "-T" should be followed by a positive integer 0,1,or 2. Command line switch "-X" should be followed by a positive integer 0,1,or 2. Command line switch "-Y" should be followed by a positive integer 0,1,or 2. Command line switch "-W" should be followed by a floating point number. Command line switch "-S" should be followed by string. Command line switch "-S" should be followed by a 2- or 3-char string (e.g. "44" or "555"). The LUT library is not given. This feature only works for {4,5,6}-LUTs. Only one additional check can be performed at the same time. This feature only works for {6,7}-LUTs. This feature only works for odd-sized LUTs. DSD manager is not available. LUT size (%d) is more than the number of variables in the DSD manager (%d). DSD manager is not matched with any particular cell. Incompatible options (-S and -x). This feature only works for [6;16]-LUTs. Size of required DSD manager (%d) exceeds the precompiled limit (%d) (change parameter DAU_MAX_VAR). The number of library inputs (%d) is different from the K parameters (%d). The number of library inputs (%d) is smaller than the K parameters (%d). Truth tables cannot be computed for LUT larger than %d inputs. Strashing before FPGA mapping has failed. Balancing before FPGA mapping has failed. The network was strashed and balanced before FPGA mapping. best possibleusage: if [-KCFAGRNTXY num] [-DEW float] [-S str] [-qarlepmsdbgxyuojiktncvh] performs FPGA technology mapping of the network -K num : the number of LUT inputs (2 < num < %d) [default = %s] -C num : the max number of priority cuts (0 < num < 2^12) [default = %d] -F num : the number of area flow recovery iterations (num >= 0) [default = %d] -A num : the number of exact area recovery iterations (num >= 0) [default = %d] -G num : the max AND/OR gate size for mapping (0 = unused) [default = %d] -R num : the delay relaxation ratio (num >= 0) [default = %d] -N num : the max size of non-decomposable nodes [default = unused] -T num : the type of LUT structures [default = any] -X num : delay of AND-gate in LUT library units [default = %d] -Y num : area of AND-gate in LUT library units [default = %d] -D float : sets the delay constraint for the mapping [default = %s] -W float : sets wire delay between adjects LUTs [default = %f] -S str : string representing the LUT structure [default = %s] -q : toggles preprocessing using several starting points [default = %s] -a : toggles area-oriented mapping [default = %s] -r : enables expansion/reduction of the best cuts [default = %s] -l : optimizes latch paths for delay, other paths for area [default = %s] -e : uses edge-based cut selection heuristics [default = %s] -p : uses power-aware cut selection heuristics [default = %s] -m : enables cut minimization by removing vacuous variables [default = %s] -s : toggles delay-oriented mapping used with -S [default = %s] -d : toggles deriving local AIGs using bi-decomposition [default = %s] -b : toggles the use of one special feature [default = %s] -g : toggles delay optimization by SOP balancing [default = %s] -x : toggles delay optimization by DSD balancing [default = %s] -y : toggles delay optimization with recorded library [default = %s] -u : toggles delay optimization with SAT-based library [default = %s] -j : toggles enabling additional check [default = %s] -i : toggles using cofactoring variables [default = %s] -k : toggles matching based on precomputed DSD manager [default = %s] -t : toggles optimizing average rather than maximum level [default = %s] -n : toggles computing DSDs of the cut functions [default = %s] -c : toggles computing truth tables in a new way [default = %s] -h : prints the command usage DNcvwhCommand line switch "-N" should be followed by a floating point number. Need mapped network. The max node size (%d) exceeds the LUT size (%d). Node size (%d) is less than LUT size (%d). Wire delay (%.2f) exceeds pin+wire delay (%.2f) for pin %d in the LUT library. usage: ifif [-DNcvwh] technology mapper into N-node K-LUT structures (takes a LUT network and maps it into a delay-optimal network of N-node K-LUT structures using the current LUT library) -D float : wire delay (should be less than the LUT delay) [default = %.2f] -N num : degree of the LUT structure [default = %d] -c : toggles using LUT cascade vs LUT cluster [default = %s] cluster -w : toggles very verbose output [default = %s] The DSD manager is not started. usage: dsd_save [-bh] saves DSD manager into a file -b : toggles processing second manager [default = %s] : (optional) file name to write usage: dsd_load [-bh] loads DSD manager from file : file name to read usage: dsd_free [-bh] deletes DSD manager NSotbvhusage: dsd_ps [-NS num] [-obvh] prints statistics of the DSD manager -N num : show structures whose ID divides by N [default = %d] -S num : show structures whose support size is S [default = %d] -o : toggles printing occurence distribution [default = %s] -t : toggles dumping truth tables [default = %s] KCPSfasvhCommand line switch "-K" should be followed by a floating point number. Command line switch "-P" should be followed by a floating point number. DSD manager matched with cell %s should be cleaned by "dsd_filter -m" before matching with cell %s. usage: dsd_match [-KCP num] [-fasvh] [-S str] matches DSD structures with the given cell -K num : LUT size used for tuning [default = %d] -P num : the maximum number of processes [default = %d] -f : toggles using fast check [default = %s] -a : toggles adding tuning to the current one [default = %s] -s : toggles using specialized check [default = %s] -S str : string representing programmable cell [default = %s] usage: dsd_merge [-h] merges DSD manager from file with the current one LKomiutsvhCommand line switch "-L" should be followed by a floating point number. usage: dsd_filter [-LK num] [-omiutsvh] filtering structured and modifying parameters of DSD manager -L num : remove structures with fewer occurrences that this [default = %d] -K num : new LUT size to set for the DSD manager [default = %d] -o : toggles cleaning occurrence counters [default = %s] -m : toggles cleaning matching marks [default = %s] -i : toggles inverting matching marks [default = %s] -u : toggles marking unate functions [default = %s] -t : toggles marking threshold functions [default = %s] -s : toggles marking threshold functions heuristically [default = %s] Option "dsd_filter -s" was contributed by Augusto Neutzling and Jody Matos from Federal University of Rio Grande do Sul, Brazil. The paper describing the method: A. Neutzling, J. M. Matos, A. Mishchenko, R. Ribas, and A. Reis, "Threshold logic synthesis based on cut pruning". Proc. ICCAD 2015. SzordcnhCommand line switch "-S" should be followed by a file name. The current network is combinational. The length of init string (%d) differs from the number of flops (%d). The two options (-c and -n) are incompatible. The current CEX is not available. The initial states remain unchanged. usage: init [-zordcnh] [-S ] resets initial states of all latches -z : set zeros initial states [default = %s] -o : set ones initial states [default = %s] -d : set don't-care initial states [default = %s] -r : set random initial states [default = %s] -c : set failure current state from the CEX (and run "zero") [default = %s] -n : set next state after failure from the CEX (and run "zero") [default = %s] -S str : (optional) initial state [default = unused] This command works only for AIGs. Converting to sequential AIG has failed. usage: zero [-h] converts latches to have const-0 initial value Current CEX is not available. The number of PIs (%d) plus X-valued flops (%d) in the original network does not match the number of PIs in the current CEX (%d). pAbc->pCex->nPis == Abc_NtkPiNum(pAbc->pNtkCur)int Abc_CommandUndc(Abc_Frame_t *, int, char **)pAbc->pCex->nRegs == Abc_NtkLatchNum(pAbc->pNtkCur)usage: undc [-ch] converts latches with DC init values into free PIs -c : toggles transforming CEX after "logic;undc;st;zero" [default = %s] Converting to one-hot encoding has failed. usage: onehot [-h] converts natural encoding into one-hot encoding MDfbsovhCommand line switch "-D" should be followed by a positive integer. Only one switch "-f" or "-b" can be selected at a time. The mode (%d) is incorrect. Retiming is not performed. Retiming with choice nodes is not implemented. Converting to SOPs has failed. The network is not a logic network. Retiming is not performed. usage: retime [-MD num] [-fbsovh] retimes the current network using one of the algorithms: 1: most forward retiming 2: most backward retiming 3: forward and backward min-area retiming 4: forward and backward min-delay retiming 5: mode 3 followed by mode 4 6: Pan's optimum-delay retiming using binary search -M num : the retiming algorithm to use [default = %d] -D num : the minimum delay target (0=unused) [default = %d] -f : enables forward-only retiming in modes 3,4,5 [default = %s] -b : enables backward-only retiming in modes 3,4,5 [default = %s] -s : enables retiming one step only in mode 4 [default = %s] -o : enables usind old flop naming conventions [default = %s] -v : enables verbose output [default = %s] NSmfbiavhCommand line switch "-S" should be followed by a positive integer. This command works only for structrally hashed networks. Run "st". Retiming has failed. usage: dretime [-NS num] [-mfbiavh] new implementation of min-area (or most-forward) retiming -m : toggle min-area retiming and most-forward retiming [default = %s] min-areamost-fwd -f : enables forward-only retiming [default = %s] -b : enables backward-only retiming [default = %s] -i : enables init state computation [default = %s] -N num : the max number of one-frame iterations to perform [default = %d] -S num : the max number of forward retiming steps to perform [default = %d] -a : enables a fast most-forward algorithm [default = %s] MDfcgbkivhInitial state guarantee (-g) requires initial state computation (-i). The network has no latches. Retiming is not performed. usage: fretime [-M num] [-D num] [-fbvih] retimes the current network using flow-based algorithm -M num : the maximum number of iterations [default = %d] -D num : the maximum delay [default = none] -k : blocks retiming over const nodes [default = %s] -g : guarantees init state computation [default = %s] -c : very fast (but conserv.) delay constraints [default = %s] -f : enables forward-only retiming [default = %s] Sequential cleanup has failed. usage: cretime [-vh] performs most-forward retiming with equiv classes PQNFILirfletvhThe network is combinational (run "fraig" or "fraig_sweep"). Currrently can only use one-hotness for simple induction (K=1). Currrently can only use one-hotness without prefix. Sequential sweeping has failed. usage: ssweep [-PQNFL ] [-lrfetvh] performs sequential sweep using K-step induction -P num : max partition size (0 = no partitioning) [default = %d] -Q num : partition overlap (0 = no overlap) [default = %d] -N num : number of time frames to use as the prefix [default = %d] -F num : number of time frames for induction (1=simple) [default = %d] -L num : max number of levels to consider (0=all) [default = %d] -l : toggle latch correspondence only [default = %s] -r : toggle AIG rewriting [default = %s] -f : toggle fraiging (combinational SAT sweeping) [default = %s] -e : toggle writing implications as assertions [default = %s] -t : toggle using one-hotness conditions [default = %s] PQFCLSIVMNcmplkodsefqvwhThis command works only for designs with primary inputs. The network already has %d constraints. Setting the number of constraints to be %d. Command cannot be applied because the network has only constraint outputs (no primary outputs). Performing scorr with %d constraints. Performing constraint-based scorr without constraints. Command line switches '-e' and '-f' cannot be used at the same time. usage: scorr [-PQFCLSIVMN ] [-cmplkodsefqvwh] -C num : max number of conflicts at a node (0=inifinite) [default = %d] -N num : number of last POs treated as constraints (0=none) [default = %d] -S num : additional simulation frames for c-examples (0=none) [default = %d] -I num : iteration number to stop and output SR-model (-1=none) [default = %d] -V num : min var num needed to recycle the SAT solver [default = %d] -M num : min call num needed to recycle the SAT solver [default = %d] -N num : set last POs to be constraints (use with -c) [default = %d] -c : toggle using explicit constraints [default = %s] -m : toggle full merge if constraints are present [default = %s] -p : toggle aligning polarity of SAT variables [default = %s] -l : toggle doing latch correspondence [default = %s] -k : toggle doing constant correspondence [default = %s] -o : toggle doing 'PO correspondence' [default = %s] -d : toggle dynamic addition of constraints [default = %s] -s : toggle local simulation in the cone of influence [default = %s] -e : toggle dumping disproved internal equivalences [default = %s] -f : toggle dumping proved internal equivalences [default = %s] -q : toggle quitting when PO is not a constant candidate [default = %s] -w : toggle printout of flop equivalences [default = %s] File name should be given on the command line. usage: testssw [-PQNFL num] [-lrfetvh] (outputs a file with a set of pairs of equivalent nodes) CSnfsvhThese two options (-f and -s) are incompatible. usage: testscorr [-CS num] [-nfsvh] outputs the list of sequential equivalences into a file (if is in BENCH, init state file should be the same directory) -C num : limit on the number of conflicts [default = %d] -S num : limit on refinement iterations (-1=no limit, 0=after BMC, etc) [default = %d] -n : toggle between "scorr" and "&scorr" [default = %s] -f : toggle reporting only flop/flop equivs [default = %s] -s : toggle reporting only flop/flop and flop/node equivs [default = %s] : input file with design for sequential equivalence computation : output file with the list of pairs of equivalent signals PCSnvhusage: lcorr [-PCS num] [-nvh] computes latch correspondence using 1-step induction -P num : number of time frames to use as the prefix [default = %d] -n : toggle using new algorithm [default = %s] cenmFSvwhOnly works for structrally hashed networks. usage: scleanup [-cenmFSvwh] performs sequential cleanup of the current network by removing nodes and latches that do not feed into POs -c : sweep stuck-at latches detected by ternary simulation [default = %s] -e : merge equal latches (same data inputs and init states) [default = %s] -n : toggle preserving latch names [default = %s] -m : toggle using hybrid ternary/symbolic simulation [default = %s] -F num : the number of first frames simulated symbolically [default = %d] -S num : the number of frames when symbolic saturation begins [default = %d] -w : toggle very verbose output [default = %s] FxvhOnly works for strashed networks or logic SOP networks. X-valued simulation only works for AIGs. Run "strash". usage: cycle [-F num] [-xvh] cycles sequential circuit for the given number of timeframes to derive a new initial state (which may be on the envelope) -F num : the number of frames to simulate [default = %d] -x : use x-valued primary inputs [default = %s] Fisvhusage: xsim [-F num] [-isvh] performs X-valued simulation of the AIG -i : toggle X-valued representation of inputs [default = %s] -s : toggle X-valued representation of state [default = %s] FWTALnmvhCommand line switch "-A" should be followed by a file name. Currently simulation with user-specified patterns works only for comb miters. usage: sim [-FWT num] [-AL file] [-nmvh] performs random simulation of the sequential miter -F num : the number of frames to simulate [default = %d] -W num : the number of words to simulate [default = %d] -T num : approximate runtime limit in seconds [default = %d] -A file : text file name with user's patterns [default = random simulation] (patterns are listed, one per line, as sequences of 0s and 1s) -n : toggle new vs. old implementation [default = %s] -m : toggle miter vs. any circuit [default = %s] circuit -v : toggle printing verbose information [default = %s] FWBRSNTGLadivzhOnly works for sequential networks. The array of counter-examples is not available. The array size does not match the number of outputs. usage: sim3 [-FWBRSNTG num] [-L file] [-advzh] performs random simulation of the sequential miter -W num : the number of words to simulate [default = %d] -B num : the number of flops in one bin [default = %d] -R num : the number of simulation rounds [default = %d] -S num : the number of rounds before a restart [default = %d] -N num : random number seed (1 <= num <= 1000) [default = %d] -T num : approximate runtime limit in seconds [default = %d] -G num : approximate runtime gap in seconds since the last CEX [default = %d] -a : toggle solving all outputs (do not stop when one is SAT) [default = %s] -d : toggle dropping (replacing by 0) SAT outputs [default = %s] -i : toggle changing init state to a last rare state [default = %s] -z : toggle suppressing report about solved outputs [default = %s] FPipcvhPI count of the CEX is not a multiple of PI count of the current AIG. The counter-example does not fail any of the outputs of the original AIG. usage: phase [-FP ] [-ipcvh] -F num : the number of frames to abstract [default = %d] -P num : the number of prefix frames to skip [default = %d] -i : toggle ignoring the initial state [default = %s] -p : toggle printing statistics about generators [default = %s] -c : update the current CEX derived for a new AIG after "phase" to match the current AIG (the one before "phase") [default = %s] WvhThe network has no latches.. Synchronization has failed. usage: synch [-W ] [-vh] derives and applies synchronization sequence -W num : the number of simulation words [default = %d] file1 : (optional) the file with the first design file2 : (optional) the file with the second design If no designs are given on the command line, assumes the current network has no initial state, derives synchronization sequence and applies it. If two designs are given on the command line assumes both of them have no initial state, derives sequences for both designs, synchorinizes them, and creates SEC miter comparing two designs. If only one design is given on the command line, considers the second design to be the current network, and derives SEC miter for them, as described above. LNDCVKavwhReading care network has failed. Clock gating has failed. usage: clockgate [-LNDCVK ] [-avwh] sequential clock gating with observability don't-cares -L num : max level number of a clock gate [default = %d] -N num : max number of candidates for a flop [default = %d] -D num : max number of ODC levels to consider [default = %d] -C num : max number of conflicts at a node [default = %d] -V num : min number of vars to recycle SAT solver [default = %d] -K num : min number of flops to recycle SAT solver [default = %d] -a : toggle minimizing area-only [default = %s] -w : toggle even more detailed output [default = %s] file : (optional) constraints for primary inputs and register outputs NDvhNot enough command-line arguments. Extracting sequential window has failed. usage: extwin [-ND ] [-vh] extracts sequential window from the AIG -N num : the ID of the object to use as the center [default = %d] -D num : the "radius" of the window [default = %d] Inserting sequential window has failed. usage: inswin [-ND ] [-vh] inserts sequential window into the AIG file : file with the AIG to be inserted Command line switch "-N" should be followed by a file name. Cannot generate functions for less than 1 and more than %d variables. The string should be composed of zeros and ones. Generated truth table of the %d-variable function and set it as the current network. Generated truth table of the %d-variable function (%s) and set it as the current network read_truth %susage: symfun [-N num] [-vh] generated a single-output symmetric function -N : prints truth tables of all N-var symmetric functions [default = not used] -v : toggle verbose output [default = %s] : the string of N+1 zeros and ones, where N is the number of variables For example, to get 3-input NAND-gate, use "symfun 1000". To get 5-input majority gate, use "symfun 000111". (int)strlen(pOnes) == nVars + 1word *Abc_TtSymFunGenerate(char *, int)FiofnxhCommand line switch "-F" should be followed by a file name. Currently "permute -x" works only for combinational networks. To permute nodes, the network should be structurally hashed. Command "permute" has failed. usage: permute [-iofnxh] [-F filename] performs random permutation of inputs/outputs/flops -i : toggle permuting primary inputs [default = %s] -o : toggle permuting primary outputs [default = %s] -f : toggle permuting flip-flops [default = %s] -n : toggle deriving new topological ordering of nodes [default = %s] -x : toggle permuting inputs based on their fanout count [default = %s] -h : print the command usage -F : (optional) file with the flop permutation Command "unpermute" has failed. usage: unpermute [-h] restores inputs/outputs/flops before the last permutation usage: cubeenum [-vh] enumerates reachable states of 2x2x2 cube (http://en.wikipedia.org/wiki/Pocket_Cube) -z : toggle using ZDD-based algorithm [default = %s] Nzvhusage: pathenum [-N num] [-vh] enumerates self-avoiding paths on the NxN grid -N num : the size of the grid to consider [default = %d] SIMtrldmpvhThe number of inputs should be 3 <= I <= 5. Lflib%d.txtLflibThe number of inputs should be 2 <= I <= 6. The intermediate support size should be I <= S <= 6. usage: funenum [-SIM num] [-trldmvph] enumerates minimum 2-input-gate implementations -S num : the maximum intermediate support size [default = %d] -I num : the number of inputs of Boolean functions [default = %d] -M num : the maximum number of 2-input gates [default = %d] -t : toggle adding combination of two gates [default = %s] -r : toggle reducing the last level [default = %s] -l : toggle generating L(f) rather than C(f) [default = %s] -d : toggle generating D(f) rather than C(f) [default = %s] -m : toggle generating multiplicity statistics [default = %s] -p : toggle dumping result library (formula and AIG) [default = %s] TCIPpsnvhCannot compare networks with phases defined. usage: cec [-T num] [-C num] [-I num] [-P num] [-psnvh] performs combinational equivalence checking -I num : limit on the number of clause inspections [default = %d] -P num : partition size for multi-output networks [default = %s] -p : toggle automatic partitioning [default = %s] -s : toggle "SAT only" and "FRAIG + SAT" [default = %s] SAT onlyFRAIG + SAT -n : toggle how CIs/COs are matched (by name or by order) [default = %s] by orderby name file1 : (optional) the file with the first network file2 : (optional) the file with the second network if no files are given, uses the current network and its spec if one file is given, uses the current network and the file TCIpmsvhCurrently this command only works for networks without latches. Run "comb". usage: dcec [-T num] [-C num] [-I num] [-mpsvh] -m : toggle working on two networks or a miter [default = %s] two networks -s : toggle "SAT only" (miter) or "FRAIG + SAT" [default = %s] FTarmfncvwhThe network has no latches. Used combinational command "cec". usage: dsec [-F num] [-T num] [-armfncvwh] performs inductive sequential equivalence checking -F num : the limit on the depth of induction [default = %d] -T num : the approximate runtime limit (in seconds) [default = %d] -a : toggles the use of phase abstraction [default = %s] -r : toggles forward retiming at the beginning [default = %s] -m : toggles min-register retiming [default = %s] -f : toggles the internal use of fraiging [default = %s] -n : toggles how CIs/COs are matched (by name or by order) [default = %s] -c : toggles performing internal netlist check [default = %s] -w : toggles additional verbose output [default = %s] cbAEFCGDVBRTLarmfijkoupwvhsm%02d.aigCannot read back unsolved reduced sequential miter "%s", usage: dprove [-AEFCGDVBRT num] [-L file] [-cbarmfijoupvwh] performs SEC on the sequential miter -A num : the limit on the depth of BMC [default = %d] -E num : the conflict limit during BMC [default = %d] -C num : the conflict limit at a node during induction [default = %d] -G num : the global conflict limit during induction [default = %d] -D num : the conflict limit during interpolation [default = %d] -V num : the flop count limit for BDD-based reachablity [default = %d] -B num : the BDD size limit in BDD-based reachablity [default = %d] -R num : the max number of reachability iterations [default = %d] -T num : the timeout for property directed reachability [default = %d] -c : toggles using CEC before attempting SEC [default = %s] -b : toggles using BMC before attempting SEC [default = %s] -i : toggles the use of induction [default = %s] -j : toggles the use of interpolation [default = %s] -k : toggles applying interpolation to each output [default = %s] -o : toggles using BDD variable reordering during image computation [default = %s] -u : toggles reading back unsolved reduced sequential miter [default = %s] -p : toggles trying property directed reachability in the end [default = %s] Command "dprove" can also be used for sequential synthesis (dprove -brjopu) FmvhThe miter cannot be given on the command line. Use "read". The miter should be structurally hashed. Use "st" usage: absec [-F num] [-mv] performs SEC by applying CEC to several timeframes -F num : the total number of timeframes to use [default = %d] -m : toggles miter vs. two networks [default = %s] FDcymvhusage: simsec [-FD num] [-mcyv] performs SEC using structural similarity -D num : the distance for extending islands [default = %d] -c : uses partial vs. full signal correspondence [default = %s] partialfull -y : dumps speculatively reduced miter of the classes [default = %s] DmvhMatching has failed. usage: match [-D num] [-mv] detects structural similarity using simulation replaces the current network by the miter of differences -D num : the distance for extending differences [default = %d] CIvhCurrently can only solve the miter for combinational circuits. int Abc_CommandSat(Abc_Frame_t *, int, char **)ERROR in Abc_NtkMiterSat(): Generated counter example is invalid. SATISFIABLE usage: sat [-C num] [-I num] [-vh] solves the combinational miter using SAT solver MiniSat-1.14 derives CNF from the current network and leave it unchanged (there is also a newer SAT solving command "dsat") -I num : limit on the number of inspections [default = %d] CILDEpansvwhERROR in mapping PIs into SAT vars: Generated CEX is invalid. usage: dsat [-CILDE num] [-pansvh] derives CNF from the current network and leaves it unchanged -L num : starting value for learned clause removal [default = %d] -D num : delta value for learned clause removal [default = %d] -E num : ratio percentage for learned clause removal [default = %d] -p : align polarity of SAT variables [default = %s] -a : toggle ANDing/ORing of miter outputs [default = %s] ANDingORing -n : toggle using new solver [default = %s] -s : enable silent computation (no reporting) [default = %s] CILDEhvusage: xsat [-CILDE num] [-hv].cnf usage: satoko [-CPDEFGHIJKLMNOQRS num] [-hv].cnf -P num : limit on the number of propagations [default = %d] Constants used for restart heuristic: -D num : Constant value used by restart heuristics in forcing restarts [default = %f] -E num : Constant value used by restart heuristics in blocking restarts [default = %f] -F num : Lower bound n.of conflicts for start blocking restarts [default = %d] -G num : Size of the moving avarege queue for LBD (force restart) [default = %d] -H num : Size of the moving avarege queue for Trail size (block restart) [default = %d] Constants used for clause database reduction heuristic: -I num : N.of conflicts before first clause databese reduction [default = %d] -J num : Increment to reduce [default = %d] -K num : Special increment to reduce [default = %d] -L num : Protecs clauses from deletion for one turn if its LBD is lower [default = %d] -M num : Percentage of learned clauses to remove [default = %d] -N num : Max percentage of garbage in clause database [default = %d] Constants used for binary resolution (clause minimization): -O num : Max clause size for binary resolution [default = %d] -Q num : Min clause LBD for binary resolution [default = %d] Constants used for branching (VSIDS heuristic): -R num : Clause activity decay factor (when using float clause activity) [default = %f] -S num : Varibale activity decay factor [default = %f] -v : prints verbose information [default = %s] CsivhAbc_CommandAbc9Satoko(): There is no AIG. usage: &satoko [-C num] [-sivh] run Satoko by Bruno Schmitt -s : split multi-output miter into individual outputs [default = %s] -i : split multi-output miter and solve incrementally [default = %s] -v : prints verbose information [default = %s] Abc_CommandAbc9Sat3(): There is no AIG. usage: &sat3 [-C num] [-sivh] -s : split multi-output miter into individual outputs [default = %s] -i : split multi-output miter and solve incrementally [default = %s] APCpsvhusage: psat [-APC num] [-psvh] solves the combinational miter using partitioning (derives CNF from the current network and leave it unchanged) for multi-output miters, tries to prove that the AND of POs is always 0 (if POs should be ORed instead of ANDed, use command "orpos") -A num : partitioning algorithm [default = %d] 0 : no partitioning 1 : partitioning by level 2 : DFS post-order 3 : DFS pre-order 4 : bit-slicing partitions are ordered by level (high level first) -P num : limit on the partition size [default = %d] -s : apply logic synthesis to each partition [default = %s] NCFGLIrfbvhCurrently can only solve the miter with one output. usage: prove [-NCFGLI num] [-rfbvh] solves combinational miter by rewriting, FRAIGing, and SAT replaces the current network by the cone modified by rewriting (there is also newer CEC command "iprove") -L num : max last-gasp number of conflicts in mitering [default = %d] This command is applicable to logic networks. usage: debug [-h] performs automated debugging of the given procedure usage: eco [-h] performs experimental ECO computation FNCGDLrsvhDoes not work for combinational networks. usage: bmc [-FNC num] [-L file] [-rcsvh] performs bounded model checking with static unrolling -F num : the number of time frames [default = %d] -N num : the max number of nodes in the frames [default = %d] -s : toggle using Satoko by Bruno Schmitt [default = %s] SFNTCGDLrusvhusage: bmc2 [-SFTCGD num] [-L file] [-usvh] performs bounded model checking with dynamic unrolling -S num : the starting time frame [default = %d] -F num : the max number of time frames (0 = unused) [default = %d] -G num : the max number of conflicts globally [default = %d] -D num : the delta in the number of nodes [default = %d] -u : toggle performing structural OR-decomposition [default = %s] SFTHGCDJIPQRLWaxdursgvzhCommand line switch "-J" should be followed by an integer. Command line switch "-W" should be followed by a file name. Constraints have to be folded (use "fold"). usage: bmc3 [-SFTHGCDJIPQR num] [-LW file] [-axdursgvzh] -T num : runtime limit, in seconds [default = %d] -H num : runtime limit per output, in miliseconds (with "-a") [default = %d] -G num : runtime gap since the last CEX, in seconds [default = %d] -C num : max conflicts at an output [default = %d] -D num : max conflicts after jumping (0 = infinity) [default = %d] -J num : the number of timeframes to jump (0 = not used) [default = %d] -I num : the number of PIs to abstract [default = %d] -P num : the max number of learned clauses to keep (0=unused) [default = %d] -Q num : delta value for learned clause removal [default = %d] -R num : percentage to keep for learned clause removal [default = %d] -W file: the log file name with per-output details [default = %s] -a : solve all outputs (do not stop when one is SAT) [default = %s] -x : toggle storing CEXes when solving all outputs [default = %s] -r : toggle disabling periodic restarts [default = %s] -g : toggle using Glucose 3.0 by Gilles Audemard and Laurent Simon [default = %s] CFTKLIrtpomcgbqkdivhCommand line switch "-I" should be followed by a file name. Cannot run interpolation with constraints. Use "fold". Each of %d outputs will be solved separately. Generating resulting network has failed. All %d outputs will be ORed together. ORing outputs has failed. usage: int [-CFTK num] [-LI file] [-irtpomcgbqkdvh] uses interpolation to prove the property -C num : the limit on conflicts for one SAT run [default = %d] -F num : the limit on number of frames to unroll [default = %d] -T num : the limit on runtime per output in seconds [default = %d] -K num : the number of steps in inductive checking [default = %d] (K = 1 works in all cases; K > 1 works without -t and -b) -I file: the file name for dumping interpolant [default = "%s"] invar.aig -i : toggle dumping interpolant/invariant into a file [default = %s] -r : toggle rewriting of the unrolled timeframes [default = %s] -t : toggle adding transition into the initial state [default = %s] -p : toggle using original Pudlak's interpolation procedure [default = %s] -o : toggle using optimized Pudlak's interpolation procedure [default = %s] -m : toggle using MiniSat-1.14p (now, Windows-only) [default = %s] -c : toggle using inductive containment check [default = %s] -g : toggle using bias for global variables using SAT [default = %s] -b : toggle using backward interpolation (works with -t) [default = %s] -q : toggle using property in two last timeframes [default = %s] -k : toggle solving each output separately [default = %s] -d : toggle dropping (replacing by 0) SAT outputs (with -k is used) [default = %s] FPCMLNBsbrtvwhThe cut size should be not exceed 12. usage: indcut [-FPCMLNB num] [-sbrtvh] K-step induction strengthened with cut properties -P num : number of time frames in the prefix (0=no prefix) [default = %d] -C num : the max number of clauses to use for strengthening [default = %d] -M num : the cut size (2 <= M <= 12) [default = %d] -L num : the max number of levels for cut computation [default = %d] -N num : the max number of cuts to compute at a node [default = %d] -B num : the max number of invariant batches to try [default = %d] -s : toggle increment cut size in each batch [default = %s] -b : toggle enabling BMC check [default = %s] -r : toggle enabling register clauses [default = %s] -t : toggle proving target / computing don't-cares [default = %s] Target enlargement has failed. usage: enlarge [-F ] [-vh] performs structural K-step target enlargement -F : the number of timeframes to unroll ( > 0) [default = %d] FTCbscvwhThe current network is not an AIG (run "strash"). The current network does not have primary inputs. Use "addpi". Temporal decomposition has failed. usage: tempor [-FTC ] [-bscvwh] performs temporal decomposition -F : init logic timeframe count (0 = use leading length) [default = %d] -T : runtime limit in seconds for BMC (0=unused) [default = %d] -C : max number of SAT conflicts in BMC (0=unused) [default = %d] -b : toggle running BMC2 on the init frames [default = %s] -s : toggle using transient signals [default = %s] -c : update the current CEX derived for a new AIG after "tempor" to match the current AIG (the one before "tempor") [default = %s] -v : toggle printing verbose output [default = %s] -w : toggle printing ternary state space [default = %s] FCTuaxvwhCurrently this command works only for single-output miter. Only one of the options, "-u" or "-a", should be selected. The current CEX in ABC is set to be the CEX to induction. usage: ind [-FCT num] [-uaxvwh] runs the inductive case of the K-step induction -F num : the max number of timeframes [default = %d] -C num : the max number of conflicts by SAT solver [default = %d] -u : toggle adding uniqueness constraints on demand [default = %s] -a : toggle adding uniqueness constraints always [default = %s] -x : toggle returning CEX to induction for the top frame [default = %s] -w : toggle printing additional verbose information [default = %s] FCPNrsiavhConstraints are not defined. Constraints are converted to be primary outputs. The network currently has %d constraints. The number of constraints specified (%d) should be less than POs (%d). Setting the last %d POs as constraint outputs. The output of %d constraint is complemented. The outputs of %d constraints are complemented. usage: constr [-FCPN num] [-risavh] a toolkit for constraint manipulation if constraints are absent, detect them functionally if constraints are present, profiles them using random simulation (constraints fail when any of them becomes 1 in any timeframe) -F num : the max number of timeframes to consider [default = %d] -C num : the max number of conflicts in SAT solving [default = %d] -P num : the max number of propagations in SAT solving [default = %d] -N num : manually set the last POs to be constraints [default = %d] -r : manually remove the constraints [default = %s] -i : toggle inverting already defined constraints [default = %s] -s : toggle using structural detection methods [default = %s] -a : toggle fast implication detection [default = %s] FCPsavhCombinational miter has more than one PO. Cannot extract constrains from the miter. Constraints are already extracted. Functional constraint extraction works for single-output miters (use "orpos"). usage: unfold [-FCP num] [-savh] unfold hidden constraints as separate outputs -P num : the max number of constraint propagations [default = %d] -s : toggle detecting structural constraints [default = %s] The network has no constraints. The network has no primary outputs (only constraints). usage: fold [-cvh] folds constraints represented as separate outputs -c : toggle complementing constraints while folding [default = %s] Mismatch in the number of inputs or outputs usage: bm [-P] performs Boolean matching (P-equivalence & PP-equivalence) for equivalent circuits, I/O matches are printed in IOmatch.txt -P : performs P-equivalnce checking default is PP-equivalence checking (when -P is not provided) file1 : the file with the first network file2 : the file with the second network This command was contributed by Hadi Katebi from U Michigan. The paper describing the method: H. Katebi and I. L. Markov. "Large-scale Boolean matching". Proc. DATE 2010. http://www.eecs.umich.edu/~imarkov/pubs/conf/date10-match.pdf *** Networks are NOT equivalent *** N1:N2:usage: bm2 performs Boolean matching (PP-equivalence) for equivalent circuits, permutation that maps one circuit to another is printed to standard output (PIs and POs of the first network have prefix "N1:", while PIs and POs of the second network have prefix "N2:") The paper describing the method: H. Katebi, K. Sakallah and I. L. Markov. "Generalized Boolean Symmetries Through Nested Partition Refinement". Proc. ICCAD 2013. OFiosqvhCommand line switch "-O" should be followed by an output name or the keyword all. Cannot create output file "%s". hadi.txtOuput %s Output not found usage: saucy3 [-O ] [-F ] [-iosqvh] computes functional symmetries of the netowrk prints symmetry generators to the standard output -O : (optional) compute symmetries only for output given by name only inputs in the output cone are permuted (special case) name=all, compute symmetries for each output, but only one output at a time [default = compute symmetries by permuting all I/Os] -F : print symmetry generators to file [default = stdout] -i : permute just the inputs (fix the outputs) [default = no] -o : permute just the outputs (fix the inputs) [default = no] -s : only look for swaps of inputs [default = no] -q : quiet (do not print symmetry generators) [default = no] -v : verbose (print the search tree) [default = no] This command was contributed by Hadi Katebi from U Michigan. The paper describing the method: H. Katebi, K. Sakallah and I. L. Markov. "Generalized Boolean Symmetries Through Nested Partition Refinement". Proc. ICCAD 2013. Saucy webpage: http://vlsicad.eecs.umich.edu/BK/SAUCY/ OahMain AIG: The cex is correct. And AIG: There is no current network. And AIG: The number of PIs (%d) is different from cex (%d). And AIG: The cex does not fail any outputs. And AIG: The cex refined PO %d instead of PO %d. And AIG: The cex is correct. usage: testcex [-O num] [-ah] tests the current cex against the current AIG or the &-AIG -O num : the number of real POs in the PO list [default = %d] -a : toggle checking the current AIG or the &-AIG [default = %s] &-AIGcurrent AIGMFCDQTHGSLIaxrmuyfqipdegjonctkvwzhusage: pdr [-MFCDQTHGS ] [-LI ] [-axrmuyfqipdegjonctkvwzh] model checking using property directed reachability (aka IC3) pioneered by Aaron R. Bradley (http://theory.stanford.edu/~arbrad/) with improvements by Niklas Een (http://een.se/niklas/) -M num : limit on unused vars to trigger SAT solver recycling [default = %d] -F num : limit on timeframes explored to stop computation [default = %d] -C num : limit on conflicts in one SAT call (0 = no limit) [default = %d] -D num : limit on conflicts during ind-generalization (0 = no limit) [default = %d] -Q num : limit on proof obligations before a restart (0 = no limit) [default = %d] -T num : runtime limit, in seconds (0 = no limit) [default = %d] -G num : runtime gap since the last CEX (0 = no limit) [default = %d] -S num : * value to seed the SAT solver with [default = %d] -I file: the invariant file name [default = %s] default name -a : toggle solving all outputs even if one of them is SAT [default = %s] -r : toggle using more effort in generalization [default = %s] -m : toggle using monolythic CNF computation [default = %s] -u : toggle updated X-valued simulation [default = %s] -y : toggle using structural flop priorities [default = %s] -f : toggle ordering flops by cost before generalization [default = %s] -q : toggle creating only shortest counter-examples [default = %s] -i : toggle clause pushing from an intermediate timeframe [default = %s] -p : toggle reusing proof-obligations in the last timeframe [default = %s] -d : toggle dumping invariant (valid if init state is all-0) [default = %s] -e : toggle using only support variables in the invariant [default = %s] -g : toggle skipping expensive generalization step [default = %s] -j : toggle using simplified generalization step [default = %s] -o : toggle using property output as inductive hypothesis [default = %s] -n : * toggle skipping 'down' in generalization [default = %s] -c : * toggle handling CTGs in 'down' [default = %s] -t : toggle using abstraction [default = %s] -k : toggle using simplified refinement [default = %s] -w : toggle printing detailed stats default = %s] -h : print the command usage * Implementation of switches -S, -n, and -c is contributed by Zyad Hassan. The theory and experiments supporting this work can be found in the following paper: Zyad Hassan, Aaron R. Bradley, Fabio Somenzi, "Better Generalization in IC3", FMCAD 2013. (http://www.cs.utexas.edu/users/hunt/FMCAD/FMCAD13/papers/85-Better-Generalization-IC3.pdf) Does not seen to have two files names as arguments. There is no current counter-example. There is no AIG in the main-space. int Abc_CommandReconcile(Abc_Frame_t *, int, char **)Counter-example computation has failed. usage: reconcile [-h] reconciles current CEX with More specifically: (i) assumes that is an AIG derived by input reparametrization of without seq synthesis; (ii) assumes that current CEX is valid for ; (iii) derives new CEX for and sets this CEX and to be current CEX and current network : file name with the original AIG : file name with the reparametrized AIG (if both file names are not given on the command line, original/reparam AIG has to be in the main-space/&-space) Current CEX is not available.. usage: cexsave [-h] saves the current CEX into the internal storage Saved CEX is not available. usage: cexload [-h] loads the current CEX from the internal storage FGcnmvhCurrent network is not an AIG. usage: cexcut [-FG num] [-cnmvh] creates logic for bad states using the current CEX -c : toggle outputting unate combinational circuit [default = %s] -n : toggle generating only one bad state [default = %s] -m : toggle generating bad states for all frames after G [default = %s] usage: cexmerge [-FG num] [-vh] Itxfczovhusage: dualrail [-I num] [-txfczovh] transforms the current AIG into a dual-rail miter expressing the property "at least one PO has ternary value" (to compute an initialization sequence, use switches "-tfc") -I num : the number of first PIs interpreted as ternary [default = %d] -t : toggle ternary flop init values for all flops [default = %s] const0 init values -x : toggle ternary flop init values for DC-valued flops [default = %s] -f : toggle mitering flops instead of POs [default = %s] flopsPOs -c : toggle complementing the miter output [default = %s] -z : toggle checking PO==0 instead of PO==X [default = %s] -o : toggle checking PO==1 instead of PO==X [default = %s] The number of time frame is 0. The circuit is left unchanged. usage: blockpo [-F num] [-fvh] forces the miter outputs to be "true" in the first F frames Current AIG has only one PO. Transformation is not performed. usage: iso [-vh] removes POs with isomorphic sequential COI Network has no mapping. usage: save [-ah] compares and possibly saves network with mapping -a : toggle using area as the primary metric [default = %s] Updating the best network (Area = %10.2f Delay = %10.2f Nodes = %6d Level = %6d). Abc_CommandAbcLoad(): There is no best design saved. usage: load [-h] loads mapped network previously saved by "save" csmlvhThere is no file name. usage: &r [-csmlvh] reads the current AIG from the AIGER file -c : toggles reading simple AIG [default = %s] -s : toggles structural hashing while reading [default = %s] -m : toggles reading MiniAIG rather than AIGER file [default = %s] -l : toggles reading MiniLUT rather than AIGER file [default = %s] : the file name usage: &read_blif [-vh] a specialized reader for hierarchical BLIF files (for general-purpose BLIFs, please use "read_blif") Command line switch "-M" should be followed by a file name. .cblifusage: &read_cblif [-M name] [-vh] reads CBLIF file and collapse it into an AIG -M name: module name to collapse [default = ] usage: &read_stg [-K ] [-vh] reads STG file and generates K-hot-encoded AIG -K num : the K parameter for hotness of the encoding (1 <= K <= 5) [default = %d] -v : toggles printing state codes [default = %s] Reading hierarchical Verilog has failed. usage: &read_ver [-vh] a specialized reader for hierarchical Verilog files cmnvhThere is no current network Abc_NtkIsLogic(pAbc->pNtkCur)int Abc_CommandAbc9Get(Abc_Frame_t *, int, char **)usage: &get [-cmnvh] converts the current network into GIA and moves it to the &-space (if the network is a sequential logic network, normalizes the flops to have const-0 initial values, equivalent to "undc; st; zero") -c : toggles allowing simple GIA to be imported [default = %s] -m : toggles preserving the current mapping [default = %s] -n : toggles saving CI/CO names of the AIG [default = %s] seovhi >= Abc_NtkPoNum(pNtk)int Abc_CommandAbc9Put(Abc_Frame_t *, int, char **)_li%0*dusage: &put [-seovh] transfer the current network into the old ABC -s : toggle clearning verification status [default = %s] -e : toggle extracting MUXes for flop enables [default = %s] -o : toggles using buffers to decouple combinational outputs [default = %s] ./src/misc/vec/vecFlt.hfloat Vec_FltEntry(Vec_Flt_t *, int)GIA has no mapping. usage: &save [-ah] compares and possibly saves AIG with mapping usage: &save2 [-ah] usage: &saveaig [-ah] saves the current AIG into the internal storage -a : toggle saving AIG with the smaller area [default = %s] Abc_CommandAbc9Load(): There is no best design saved. usage: &load [-h] loads AIG with mapping previously saved by &save (after loading the previously saved AIG can be loaded again) Abc_CommandAbc9Load2(): There is no best design saved. usage: &load2 [-h] loads AIG with mapping previously saved by &save2 (after loading the previously saved AIG cannot be loaded again) Abc_CommandAbc9LoadAig(): There is no design saved. usage: &loadaig [-h] loads AIG previously saved by &saveaig Expecting output file name on the command line. There is no mapped file to write. The specification file is not given. Reading hierarchical Verilog for the specification has failed. usage: &write_ver [-S ] [-vh] writes hierarchical Verilog after mapping -S file : file name for the original hierarchical design (required) -v : toggle verbose output [default = %s] : the file name upmlnvhAbc_CommandAbc9Write(): There is no AIG to write. usage: &w [-upmlnvh] writes the current AIG into the AIGER file -u : toggle writing canonical AIG structure [default = %s] -p : toggle writing Verilog with 'and' and 'not' [default = %s] -m : toggle writing MiniAIG rather than AIGER [default = %s] -l : toggle writing MiniLUT rather than AIGER [default = %s] -n : toggle writing '\n' after 'c' in the AIGER file [default = %s] Abc_CommandAbc9WriteLut(): There is no AIG to write. Abc_CommandAbc9WriteLut(): AIG has no mapping. usage: &wlut [-umvh] writes the the current LUT mapping into a binary file DtpcnlmaszxbhCommand line switch "-D" should be followed by a file name. Abc_CommandAbc9Ps(): There is no AIG. usage: &ps [-tpcnlmaszxbh] [-D file] prints stats of the current AIG -t : toggle printing BMC tents [default = %s] -p : toggle printing switching activity [default = %s] -c : toggle printing the size of frontier cut [default = %s] -n : toggle printing NPN classes of functions [default = %s] -l : toggle printing LUT size profile [default = %s] -m : toggle printing MUX/XOR statistics [default = %s] -a : toggle printing miter statistics [default = %s] -s : toggle printing slack distribution [default = %s] -z : skip mapping statistics even if mapped [default = %s] -n : toggle using no color in the printout [default = %s] -x : toggle printing saved AIG statistics [default = %s] -D file : file name to dump statistics [default = none] Abc_CommandAbc9PFan(): There is no AIG. usage: &pfan [-N num] [-h] prints fanin/fanout statistics -N num : the number of high-fanout nodes to explore [default = %d] Abc_CommandAbc9PSigs(): There is no AIG. Abc_CommandAbc9PSigs(): Works only for sequential circuits. usage: &psig [-rh] prints enable/set/reset statistics -r : toggle printing set/reset signals [default = %s] Abc_CommandAbc9Status(): There is no AIG. usage: &status [-h] prints status of the miter NnmavhAbc_CommandAbc9MuxProfile(): There is no AIG. Abc_CommandAbc9MuxProfile(): Expecting AIG mapped into 3-LUTs. usage: &profile [-N num] [-nmavh] profile gate structures appearing in the AIG -N num : limit on class size to show [default = %d] -n : toggle profiling NPN-classes (for 3-LUT mapped AIGs) [default = %s] -m : toggle profiling MUX structures [default = %s] -a : toggle profiling adder structures [default = %s] Abc_CommandAbc9MuxPos(): There is no AIG. usage: &muxpos [-vh] create additional POs to preserve MUXes Abc_CommandAbc9MuxStr(): There is no AIG. usage: &muxstr [-vh] performs restructuring ORvhAbc_CommandAbc9PrintTruth(): There is no AIG. The number of inputs of the AIG exceeds 6. Abc_CommandAbc9PrintTruth(): Range of outputs to extract is incorrect. Output %8d : usage: &print_truth [-OR num] [-vh] prints truth tables of outputs in hex notation -O num : the index of first PO to print [default = %d] -R num : (optional) the number of outputs to extract [default = all] Abc_CommandAbc9Unate(): There is no AIG. usage: &unate [-avh] prints info about unatements of CO funcs in terms of CI vars -a : toggle using efficient computation for all pairs [default = %s] No regular expression is entered on the command line. usage: &rex2gia [-avh] [string] converts a regular expression into a sequential AIG -a : toggle ordering input symbols alphabetically [default = %s] string : representation of a regular expression Special symbols: parentheses '(' and ')', Kleene closure '*', union '|' All other characters are treated as symbols of the input alphabet. For example, ((A*B|AC)D) is defined over the alphabet {A, B, C, D} and generates the following language: {BD, ABD, AABD, AAABD, ..., ACD} A known limitation: For the command to work correctly, each two-input union should have a dedicated pair of parentheses: ((A|B)|C) rather than (A|B|C) SRvhAbc_CommandAbc9Show(): There is no AIG. usage: &rexwalk [-SR] [-vh] performs simulation of an AIG representing a regular expression -S num : the number of steps to take [default = %d] -R num : the number of walks to make [default = %d] afphAbc_CommandAbc9Show(): Cannot show GIA with barrier buffers. usage: &show [-afph] shows the current GIA using GSView -a : toggle visualazing adders [default = %s] -f : toggle showing only full-adders with "-a" [default = %s] -p : toggle showing the critical path of a LUT mapping [default = %s] Abc_CommandAbc9SetRegNum(): There is no AIG. Abc_CommandAbc9SetRegNum(): The number of registers should be less than the number of CIs. Abc_CommandAbc9SetRegNum(): The number of registers should be less than the number of COs. usage: &setregnum [-N num] [-h] manually sets the number of registers to combine the last PI/PO pairs -N num : set the number of registers to be the given number [default = %d] LacmrshAbc_CommandAbc9Strash(): There is no AIG. Restructing the current AIG destroys the LUT mapping. Finished AIG restructing to enable efficient mapping of 4:1 MUXes into 4-LUTs. Abc_CommandAbc9Strash(): The AIG already has MUXes. !Gia_ManBufNum(pAbc->pGia)int Abc_CommandAbc9Strash(Abc_Frame_t *, int, char **)usage: &st [-L num] [-acmrsh] performs structural hashing -a : toggle additional hashing [default = %s] -c : toggle collapsing hierarchical AIG [default = %s] -m : toggle converting to larger gates [default = %s] -L num : create MUX when sum of refs does not exceed this limit [default = %d] (use L = 1 to create AIG with XORs but without MUXes) -r : toggle rehashing AIG while preserving mapping [default = %s] -s : toggle using MUX restructuring [default = %s] Abc_CommandAbc9Topand(): There is no AIG. Abc_CommandAbc9Topand(): Can only be applied to a combinational miter. usage: &topand [-vh] performs AND decomposition for combinational miter Abc_CommandAbc9Add1Hot(): There is no AIG. usage: &add1hot [-vh] adds 1-hotness constraints as additional primary outputs VLvhAbc_CommandAbc9Cof(): There is no AIG. Cofactoring all variables whose fanout count is higher than %d. Cofactoring one variable with object ID %d. One of the parameters, -V or -L , should be set on the command line. usage: &cof [-VL num] [-vh] performs cofactoring w.r.t. variable(s) -V num : the zero-based ID of one variable to cofactor [default = %d] -L num : cofactor vars with fanout count higher than this [default = %d] ViocdhAbc_CommandAbc9Trim(): There is no AIG. usage: &trim [-V num] [-iocdh] removes PIs without fanout and PO driven by constants -V num : the value (0 or 1) of POs to remove [default = both] -i : toggle removing PIs [default = %s] -o : toggle removing POs [default = %s] -c : toggle additionally removing POs fed by PIs [default = %s] -d : toggle using dual-output miter [default = %s] Abc_CommandAbc9Dfs(): There is no AIG. AIG objects are reordered as follows: CIs, ANDs, COs. AIG objects are reordered in the reserve DFS order. AIG objects are reordered in the DFS order. usage: &dfs [-nrvh] orders objects in the DFS order -n : toggle using normalized ordering [default = %s] -r : toggle using reverse DFS ordering [default = %s] FWNTImvhAbc_CommandAbc9Sim(): There is no AIG. strlen(pNameGeneric) < 900int Abc_CommandAbc9Sim(Abc_Frame_t *, int, char **)%s_out.%susage: &sim [-FWNT num] [-mvh] -I (if candidate equivalences are defined, performs refinement) -m : toggle miter vs. any circuit [default = %s] -I file: (optional) file with input patterns (one line per frame, as many as PIs) FWBRSNTGgvhAbc_CommandAbc9Sim3(): There is no AIG. Abc_CommandAbc9Sim3(): This command works only for sequential AIGs. usage: &sim3 [-FWBRNT num] [-gvh] -g : toggle heuristic flop grouping [default = %s] WSbvhAbc_CommandAbc9MLGen(): There is no AIG. Abc_CommandAbc9MLGen(): This command works only for combinational AIGs. usage: &mlgen [-WS num] [-bvh] generates data files for machine learning -S num : the random seed for simulation data (num < 10000) [default = %d] -b : toggle using binary data files [default = %s] : file to store the simulation info Abc_CommandAbc9MLTest(): There is no AIG. Abc_CommandAbc9MLTest(): This command works only for combinational AIGs. Abc_CommandAbc9MLTest(): Expecting data file name on the command line. usage: &mltest [-vh] [-D file] testing command for machine learning data file : file with input simulation info WovhAbc_CommandAbc9ReadSim(): There is no AIG. Abc_CommandAbc9ReadSim(): This command works only for combinational AIGs. File size (%d words) does not match the number of AIG inputs (%d %% %d != %d). usage: &sim_read [-W num] [-ovh] reads simulation patterns from file -o : toggle reading output information [default = %s] Abc_CommandAbc9WriteSim(): There is no AIG. Abc_CommandAbc9WriteSim(): This command works only for combinational AIGs. Abc_CommandAbc9WriteSim(): Does not have simulation information available. Vec_WrdSize(pAbc->pGia->vSimsPo) % Gia_ManCoNum(pAbc->pGia) == 0int Abc_CommandAbc9WriteSim(Abc_Frame_t *, int, char **)Vec_WrdSize(pAbc->pGia->vSimsPi) % Gia_ManCiNum(pAbc->pGia) == 0usage: &sim_write [-vh] writes simulation patterns into a file -o : toggle writing output information [default = %s] Abc_CommandAbc9PrintSim(): There is no AIG. Abc_CommandAbc9PrintSim(): This command works only for combinational AIGs. Abc_CommandAbc9PrintSim(): Simulation patterns are not defined. usage: &sim_print [-vh] WRsdvhAbc_CommandAbc9GenSim(): There is no AIG. Abc_CommandAbc9GenSim(): This command works only for combinational AIGs. Abc_CommandAbc9GenSim(): Does not have simulation information available. Generated %d random patterns (%d 64-bit data words) for each input of the AIG. usage: &sim_gen [-WR num] [-sdvh] generates random simulation patterns -W num : the number of 64-bit words of simulation info [default = %d] -R num : the rarity parameter used to define scope [default = %d] -s : toggle using SAT-based improvement of available patterns [default = %s] -d : toggle using one improvement of available patterns [default = %s] Abc_CommandAbc9SimRsb(): There is no AIG. Abc_CommandAbc9SimRsb(): This command works only for combinational AIGs. Abc_CommandAbc9SimRsb(): Does not have simulation information available. usage: &simrsb [-N num] [-vh] performs resubstitution -C num : the number of candidates to try [default = %d] Abc_CommandAbc9Resim(): There is no AIG. usage: &resim [-F num] [-mvh] resimulates equivalence classes using counter-example -F num : the number of additinal frames to simulate [default = %d] FCfmvhAbc_CommandAbc9SpecI(): There is no AIG. usage: &speci [-FC num] [-fmvh] refines equivalence classes using speculative reduction -F num : the max number of time frames [default = %d] -f : toggle starting BMC from a later frame [default = %s] WFRSTsmdvhAbc_CommandAbc9Equiv(): There is no AIG. usage: &equiv [-WFRST num] [-smdvh] computes candidate equivalence classes -R num : the max number of simulation rounds [default = %d] -S num : the max number of rounds w/o refinement to stop [default = %d] -s : toggle seq vs. comb simulation [default = %s] -d : toggle using two POs intead of XOR [default = %s] FCRTSxlvhAbc_CommandAbc9Equiv2(): There is no AIG. Abc_CommandAbc9Equiv2(): There is no flops. Nothing is done. Abc_CommandAbc9Equiv2(): Counter-example is not available. Abc_CommandAbc9Equiv2(): The number of PIs differs in cex (%d) and in AIG (%d). usage: &equiv2 [-FCRTS num] [-xlvh] -F num : the max number of frames for BMC [default = %d] -R num : the max number of BMC rounds [default = %d] -T num : runtime limit in seconds for all rounds [default = %d] -S num : runtime limit in seconds for one round [default = %d] -x : toggle using the current cex to perform refinement [default = %s] -l : toggle considering only latch output equivalences [default = %s] FWBRSNTmxlvhAbc_CommandAbc9Equiv3(): There is no AIG. Abc_CommandAbc9Equiv3(): There is no flops. Nothing is done. Abc_CommandAbc9Equiv3(): Considering the miter as a circuit because the CEX is given. Abc_CommandAbc9Equiv3(): Counter-example is not available. Abc_CommandAbc9Equiv3(): The number of PIs differs in cex (%d) and in AIG (%d). usage: &equiv3 [-FWRSNT num] [-mxlvh] -x : toggle using the current CEX to perform refinement [default = %s] WRFSMCTmdvhusage: &semi [-WRFSMCT num] [-mdvh] performs semiformal refinement of equivalence classes -R num : the max number of rounds to simulate [default = %d] -F num : the max number of frames to unroll [default = %d] -M num : the min number of outputs of bounded SRM [default = %d] Abc_CommandAbc9Times(): There is no AIG. usage: × [-N ] [-vh] creates several "parallel" copies of the design -N num : number of copies to create [default = %d] FLsoibavhAbc_CommandAbc9Frames(): There is no AIG. usage: &frames [-FL ] [-soibavh] unrolls the design for several timeframes -L num : the limit on fanout count of resets/enables to cofactor [default = %d] -s : toggle disabling structural hashing [default = %s] -o : toggle ORing corresponding POs [default = %s] -i : toggle initializing registers [default = %s] -b : toggle computing special AIG for BMC [default = %s] Abc_CommandAbc9Retime(): There is no AIG. usage: &retime [-N ] [-vh] performs most-forward retiming -N num : the number of incremental iterations [default = %d] Abc_CommandAbc9Enable(): There is no AIG. usage: &enable [-rvh] adds or removes flop enable signals -r : toggle adding vs. removing enables [default = %s] Abc_CommandAbc9Dc2(): There is no AIG. usage: &dc2 [-lvh] performs heavy rewriting of the AIG -l : toggle level update during rewriting [default = %s] Abc_CommandAbc9Dsd(): There is no AIG. usage: &dsd [-vh] performs DSD-based collapsing Abc_CommandAbc9Bidec(): There is no AIG. Abc_CommandAbc9Bidec(): Mapping of the AIG is not defined. usage: &bidec [-vh] NlvhCommand line switch "-N" should be followed by a char string. Abc_CommandAbc9Shrink(): There is no AIG. Abc_CommandAbc9Shrink(): Mapping of the AIG is not defined. Abc_CommandAbc9Shrink(): Works only for 4-LUTs and 6-LUTs. usage: &shrink [-N num] [-lvh] performs fast shrinking using current mapping -N num : the max fanout count to skip a divisor [default = %d] -l : toggle level update during shrinking [default = %s] NMrvwhAbc_CommandAbc9Fx(): Command has failed. usage: &fx [-NM ] [-vh] extract shared logic using the classical "fast_extract" algorithm -r : reversing variable order during ISOP computation [default = %s] -w : toggle printing additional information [default = %s] NdaslvwhAbc_CommandAbc9Balance(): There is no AIG. usage: &b [-N num] [-dasvwh] performs AIG balancing to reduce delay and area -d : toggle delay only balancing [default = %s] -a : toggle using AND instead of AND/XOR/MUX [default = %s] -s : toggle strict control of area in delay-mode ("&b -d") [default = %s] -w : toggle printing additional information [default = %s] KCnmravwhCommand line switch "-K" should be followed by a char string. Command line switch "-C" should be followed by a char string. Abc_CommandAbc9BalanceLut(): There is no AIG. usage: &blut [-KC num] [-mravh] performs AIG balancing for the given LUT size -K num : LUT size for the mapping (2 <= K <= %d) [default = %d] -C num : the max number of priority cuts (1 <= C <= %d) [default = %d] -m : toggle performing MUX restructuring [default = %s] -r : toggle performing recursive restructuring [default = %s] -a : toggle performing area-oriented restructuring [default = %s] RakmdvwhAbc_CommandAbc9Syn2(): There is no AIG. usage: &syn2 [-R num] [-akmdvh] performs AIG optimization -a : toggles using the old algorithm [default = %s] -k : toggles coarsening the subject graph [default = %s] -m : toggles cut minimization [default = %s] -d : toggles additional delay optimization [default = %s] -v : toggles printing verbose information [default = %s] -w : toggles printing additional information [default = %s] WCSKRfrvhAbc_CommandAbc9Dch(): There is no AIG. usage: &synch2 [-WCSKR num] [-frvh] -K num : the target LUT size for downstream mapping [default = %d] -R num : the delay relaxation ratio (num >= 0) [default = %d] -f : toggle using lighter logic synthesis [default = %s] Abc_CommandAbc9Syn3(): There is no AIG. usage: &syn3 [-lvh] performs AIG optimization Abc_CommandAbc9Syn4(): There is no AIG. usage: &syn4 [-lvh] STvwhCommand line switch "-S" should be followed by a char string. Command line switch "-T" should be followed by a char string. Abc_CommandAbc9False(): There is no AIG. usage: &false [-ST num] [-vwh] detecting and elimintation false paths -S num : maximum slack to identify false paths [default = %d] IdstxyzvhCommand line switch "-I" should be followed by a char string. Abc_CommandAbc9Miter(): There is no AIG. Abc_CommandAbc9Miter(): The number of outputs should be even. The miter (current AIG) is transformed by XORing POs pair-wise. The miter (current AIG) is transformed by XORing POs of two word-level outputs. The dual-output miter (current AIG) is transformed by ordering sides. The miter (current AIG) is transformed from two-word to dual-output. usage: &miter [-I num] [-dstxyzvh] creates miter of two designs (current AIG vs. ) -I num : the number of last PIs to replicate [default = %d] -d : toggle creating dual-output miter [default = %s] -s : toggle creating sequential miter [default = %s] -t : toggle XORing POs of dual-output miter [default = %s] -x : toggle XORing POs of two-word miter [default = %s] -y : toggle convering two-word miter into dual-output miter [default = %s] -z : toggle odering sides of the dual-output miter [default = %s] : AIGER file with the design to miter 01xXInit string length (%d) differs from PI and flop count (%d). usage: &miter2 [-vh] creates miter of two copies of the design : file name with flop initial values (0/1/x/X) [default = required] usage: &append [-vh] appends to the current AIG using new PIs and POs cevwhAbc_CommandAbc9Scl(): There is no AIG. usage: &scl [-cevwh] performs structural sequential cleanup -c : toggle removing stuck-at constant registers [default = %s] -e : toggle removing equivalent-driver registers [default = %s] -w : toggle printing verbose info about equivalent flops [default = %s] FCPrcvwhAbc_CommandAbc9Lcorr(): There is no AIG. usage: &lcorr [-FCP num] [-rcvwh] performs latch correpondence computation -F num : the number of timeframes in inductive case [default = %d] -P num : the number of timeframes in the prefix [default = %d] -r : toggle using implication rings during refinement [default = %s] -c : toggle using circuit-based SAT solver [default = %s] FCPpkrecqwvhAbc_CommandAbc9Scorr(): There is no AIG. usage: &scorr [-FCP num] [-pkrecqwvh] performs signal correpondence computation -p : toggle using partitioning for the input AIG [default = %s] -k : toggle using constant correspondence [default = %s] -e : toggle using equivalences as choices [default = %s] CcvhAbc_CommandAbc9Choice(): There is no AIG. usage: &choice [-C num] [-cvh] performs computation of structural choices CSNanmtcxvhAbc_CommandAbc9Sat(): There is no AIG. usage: &sat [-CSN ] [-anmctxvh] performs SAT solving for the combinational outputs -S num : the min number of variables to recycle the solver [default = %d] -N num : the min number of calls to recycle the solver [default = %d] -a : toggle solving all outputs and saving counter-examples [default = %s] -n : toggle using non-chronological backtracking [default = %s] -t : toggle using learning in curcuit-based solver [default = %s] -x : toggle using new solver [default = %s] Abc_CommandAbc9SatEnum(): There is no AIG. usage: &satenum [-CT ] [-vh] enumerates solutions of the combinational miter -T num : global timeout [default = %d] WRILDCrmdckngwvhAbc_CommandAbc9Fraig(): There is no AIG. usage: &fraig [-WRILDC ] [-rmdckngwvh] performs combinational SAT sweeping -I num : the number of sweeping iterations [default = %d] -L num : the max number of levels of nodes to consider [default = %d] -D num : the max number of steps of speculative reduction [default = %d] -r : toggle the use of AIG rewriting [default = %s] -d : toggle using double output miters [default = %s] -c : toggle using circuit-based solver [default = %s] -k : toggle using logic cones in the SAT solver [default = %s] -n : toggle using new implementation [default = %s] -g : toggle using another new implementation [default = %s] -w : toggle printing even more verbose information [default = %s] WCacvhAbc_CommandAbc9CFraig(): There is no AIG. usage: &cfraig [-WC ] [-acvh] performs combinational SAT sweeping under constraints which are present in the AIG or set manually using "constr" (constraints are listed as last POs and true when they are 0) -a : toggle appending constraints to the result [default = %s] -c : toggle performing internal verification [default = %s] AdrsfvhAbc_CommandAbc9Srm(): There is no AIG. gsrm%s.aiggsyn%s.aigSpeculatively reduced model was written into file "%s". Reduced original network was written into file "%s". usage: &srm [-A file] [-drsfvh] writes speculatively reduced model into file "%s" -A file : file name for dumping speculative-reduced model [default = "gsrm.aig"] -d : toggle creating dual-output miter [default = %s] -r : toggle writing reduced network for synthesis [default = %s] -s : toggle using speculation at the internal nodes [default = %s] -f : toggle filtering to remove redundant equivalences [default = %s] abvhAbc_CommandAbc9Srm2(): There is no AIG. Equivalences are not defined. Abc_CommandAbc9Srm2(): Expecting two file names on the command line. gsrm.aigFiltering equivalences has failed. usage: &srm2 [-abvh] writes speculatively reduced model into file "%s" only preserves equivalences across PartA and PartB -a : toggle using latches only in PartA [default = %s] -b : toggle using latches only in PartB [default = %s] fgivhFiltering equivalences using PartA and PartB has failed. usage: &filter [-fgivh] performs filtering of equivalence classes (if Parts A/B are given, removes classes composed of one part) -f : toggle removing all elements except flops [default = %s] -g : toggle removing classes without flops [default = %s] -i : toggle using flop inputs instead of flop outputs [default = %s] Abc_CommandAbc9Reduce(): There is no AIG. usage: &reduce [-advh] reduces the circuit using equivalence classes -a : toggle merging all equivalences [default = %s] -d : toggle using dual-output merging [default = %s] Abc_CommandAbc9EquivMark(): There is no AIG. usage: &equiv_mark [-fvh] marks equivalences using an external miter -f : toggle the use of filtered equivalences [default = %s] -v : toggle printing verbose information [default = %s] -h : print the command usage : file with the external miter to read The external miter should be generated by &srm -s and (partially) solved by any verification engine(s). The external miter should have as many POs as the number of POs in the current AIG plus the number of equivalences in the current AIG. If some POs are proved, the corresponding equivs are marked as proved, to be reduced by &reduce. Abc_CommandAbc9EquivFilter(): There is no AIG. usage: &equiv_filter [-vh] filters equivalence candidates after disproving some SRM outputs (the array of disproved outputs should be given as pAbc->vAbcObjIds) CTnmdasvhAbc_CommandAbc9Cec(): A miter cannot be given as an argument of command &cec and should be entered using &r. The dual-output miter should have an even number of outputs. Assuming the current network is a double-output miter. Assuming the current network is a single-output miter. Abc_CommandAbc9Cec(): Wrong number of command-line arguments. Reading AIGER from file "%s" has failed. Abc_CommandAbc9Cec(): There is no current AIG. nArgcNew == 0int Abc_CommandAbc9Cec(Abc_Frame_t *, int, char **)The verification miter is written into file "%s". cec_miter.aigusage: &cec [-CT num] [-nmdasvh] new combinational equivalence checker -n : toggle using naive SAT-based checking [default = %s] -m : toggle miter vs. two circuits [default = %s] two circuits -d : toggle using dual output miter [default = %s] -a : toggle writing dual-output miter [default = %s] -s : toggle silent operation [default = %s] CTsdvhTaking spec from file "%s". usage: &verify [-CT num] [-sdvh] performs verification of combinational design -s : toggle using sequential verification [default = %s] -d : toggle dumping AIGs to be compared [default = %s] : optional file name with the spec [default = not used] WCStvhAbc_CommandAbc9Sweep(): There is no AIG. usage: &sweep [-WCS num] [-tvh] performs SAT sweeping for AIG with boxes IcvhAbc_CommandAbc9Force(): There is no AIG. usage: &force [-I ] [-cvh] one-dimensional placement algorithm FORCE introduced by F. A. Aloul, I. L. Markov, and K. A. Sakallah (GLSVLSI�03). -I num : the number of refinement iterations [default = %d] -c : toggle clustered representation [default = %s] DIrcdlsvhAbc_CommandAbc9Embed(): There is no AIG. usage: &embed [-DI ] [-rdlscvh] fast placement based on high-dimensional embedding from D. Harel and Y. Koren, "Graph drawing by high-dimensional embedding", J. Graph Algs & Apps, 2004, Vol 8(2), pp. 195-217 -D num : the number of dimensions for embedding [default = %d] -r : toggle the use of refinement [default = %s] -d : toggle dumping placement into a Gnuplot file [default = %s] -l : toggle dumping Gnuplot for large placement [default = %s] -s : toggle showing image if Gnuplot is installed [default = %s] LWCRvhAbc_CommandAbc9Sopb(): There is no AIG. usage: &sopb [-LWCR num] [-vh] performs SOP balancing -L num : optimize paths above this level [default = %d] -W num : optimize paths falling into this window [default = %d] -C num : the number of cuts at a node [default = %d] LWKCRvhAbc_CommandAbc9Dsdb(): There is no AIG. Abc_CommandAbc9Dsdb(): Size of the required DSD manager (%d) exceeds the precompiled limit (%d) (change parameter DAU_MAX_VAR). usage: &dsdb [-LWKCR num] [-vh] performs DSD balancing -K num : the number of LUT inputs (LUT size) [default = %d] KCtmvhAbc_CommandAbc9Flow(): There is no AIG. usage: &flow [-KC num] [-tmvh] integration optimization and mapping flow -t : toggle minimizing average rather than max delay [default = %s] -m : toggle using "mfs2" in the script [default = %s] KCbtmvhAbc_CommandAbc9Flow2(): There is no AIG. usage: &flow2 [-KC num] [-btmvh] -b : toggle using SOP balancing during synthesis [default = %s] -t : toggle minimizing average (not maximum) level [default = %s] KCbtmlvhAbc_CommandAbc9Flow3(): There is no AIG. Abc_CommandAbc9Flow3(): Please enter LUT library using 'read_lut'. usage: &flow3 [-KC num] [-btmlvh] -l : toggle using previously entered LUT library [default = %s] LUT library is not given. Using default LUT library. KCFAGRDEWSTXYqalepmrsdbgxyofuijkztncvwhEmpty GIA network. Current AIG has mapping. Run "&st". Switches -f and -u are not compatible. This feature only works for {6,7,8}-LUTs. The number of library inputs (%d) different from the K parameters (%d). Design has boxes but box library is not entered. Abc_CommandAbc9If(): Mapping of GIA has failed. usage: &if [-KCFAGRTXY num] [-DEW float] [-S str] [-qarlepmsdbgxyofuijkztnchvw] -l : toggle restricting the type of 6-input lookup tables [default = %s] -d : toggles deriving specialized matching step [default = %s] -f : toggles enabling additional check [default = %s] -u : toggles enabling additional check [default = %s] -j : toggles using AND bi-decomposition [default = %s] -z : toggles deriving LUTs when mapping into LUT structures [default = %s] -h : toggles rehashing AIG after mapping [default = %s] -w : toggles printing delay trace [default = %s] Abc_CommandAbc9Iff(): There is no AIG to map. Abc_CommandAbc9Iff(): Mapping of the AIG is not defined. Abc_CommandAbc9Iff(): LUT library is not defined. usage: &iff [-vh] performs structural mapping into LUT structures KCgclvhAbc_CommandAbc9Iiff(): There is no AIG to map. Abc_CommandAbc9Iiff(): Mapping has failed. usage: &iiff [-KC num] [-gclvh] performs techology mapping -K num : the maximum LUT size [default = %d] -C num : the maximum cut count [default = %d] -g : toggle using gates [default = %s] -c : toggle using cells [default = %s] -l : toggle using LUTs [default = %s] : (optional) output file name KCDtmzrcuxvwhLUT size %d is not supported. There is no SCL library available. Currently DSD can only be used with 6-input cuts. pPars->pLib == NULLint Abc_CommandAbc9If2(Abc_Frame_t *, int, char **)There is no GENLIB library available. Abc_CommandAbc9If2(): Mapping into standard cells has failed. Abc_CommandAbc9If2(): Mapping into LUTs has failed. usage: &if2 [-KCD num] [-tmzrcuxvwh] performs technology mapping of the network -K num : sets the LUT size for the mapping [default = %d] -D num : sets the delay constraint for the mapping [default = %s] -t : enables using AND/XOR/MUX nodes instead of simple AIG [default = %s] -r : toggles using one round of mapping [default = %s] -c : toggles mapping for CNF computation [default = %s] -u : toggles mapping for AIG computation [default = %s] -x : toggles mapping for standard cells [default = %s] KCDWaekmdcgvwhThis number of cuts (%d) is not supported. Command line switch "-W" should be followed by a positive integer. Abc_CommandAbc9Jf(): This command does not work with barrier buffers. Abc_CommandAbc9Jf(): DSD computation works for LUT6 or less. Abc_CommandAbc9Jf(): Cannot input DSD data from file. Abc_CommandAbc9Jf(): Mapping into LUTs has failed. usage: &jf [-KCDW num] [-akmdcgvwh] -W num : min frequency when printing functions with "-w" [default = %d] -e : toggles edge vs node minimization [default = %s] -d : toggles using DSD to represent cut functions [default = %s] -c : toggles mapping for CNF generation [default = %s] -g : toggles generating AIG without mapping [default = %s] KCPDWaekmdcgtsvwhCommand line switch "-P" should be followed by a positive integer. Abc_CommandAbc9Kf(): Mapping into LUTs has failed. usage: &kf [-KCPDW num] [-akmdcgtsvwh] -P num : the number of cut computation processes (0 <= P <= %d) [default = %d] -t : toggles cut computation using hash table [default = %s] -s : toggles cut computation using a simple method [default = %s] KCFARLEDWMekmupstgvwhFlags "-M" and "-u" are incompatible. This feature works only for LUT size equal to 4, 5, and 6. Using cut grouping for %d-LUTs. Considering cuts up to %d. Abc_CommandAbc9Lf(): Mapping into LUTs has failed. usage: &lf [-KCFARLEDM num] [-kmupstgvwh] -F num : the number of area flow rounds [default = %d] -A num : the number of exact area rounds [default = %d] -L num : the fanout limit for coarsening XOR/MUX (num >= 2) [default = %d] -E num : the area/edge tradeoff parameter (0 <= num <= 100) [default = %d] -M num : LUT size when cofactoring is performed (0 <= num <= 100) [default = %d] -u : toggles using additional MUXes [default = %s] -p : toggles power-aware cut selection heuristics [default = %s] -s : toggles generating AIG without mapping [default = %s] -g : toggles using cut splitting [default = %s] KCFARLEDWaekmcgvwhusage: &mf [-KCFARLED num] [-akmcgvwh] KCFARLEDQWakpqfvwhCommand line switch "-R" should be followed by an integer number. Command line switch "-E" should be followed by an integer number. Command line switch "-D" should be followed by an integer number. Current library is not available. Abc_CommandAbc9Nf(): Mapping into LUTs has failed. usage: &nf [-KCFARLEDQ num] [-akpqfvwh] -A num : the number of exact area rounds (when '-a' is used) [default = %d] -Q num : internal parameter impacting area of the mapping [default = %d] -a : toggles SAT-based area-oriented mapping (experimental) [default = %s] -p : toggles pin permutation (more matches - better quality) [default = %s] -q : toggles quick mapping (fewer matches - worse quality) [default = %s] -f : toggles filtering matches (useful with unit delay model) [default = %s] KCFARLEDNMQekmpgtvwhCommand line switch "-Q" should be followed by a positive integer. Abc_CommandAbc9Of(): Mapping into LUTs has failed. usage: &of [-KCFARLEDNMQ num] [-kmpgtvwh] -N num : delay of the first LUT [default = %d] -M num : delay of the second LUT [default = %d] -Q num : the number of fast non-routable edges [default = %d] NRDvhLUT block size (%d) should be more than 1. Rounting delay (%d) should be more than 0. Direct delay (%d) should be more than 0. Current AIG has no mapping. Run "&if". Current AIG has mapping into %d-LUTs. usage: &pack [-NRD num] [-vh] performs packing for the LUT mapped network -N num : the number of LUTs in the block [default = %d] -R num : the routable delay of a LUT [default = %d] -D num : the direct (non-routable) delay of a LUT [default = %d] CDFErpomdvhCommand line switch "-E" should be followed by a positive integer. Edge limit (%d) should be 1 or 2. Packing information is not present. Reverse computation does not work when boxes are present. usage: &edge [-CDFE num] [-rpomdvh] find edge assignment of the LUT-mapped network -C num : the SAT solver conflict limit (0 = unused) [default = %d] -D num : the upper bound on delay [default = %d] -F num : skip using edge if fanout higher than this [default = %d] -E num : the limit on the number of edges (1 <= num <= 2) [default = %d] -r : toggles using reverse order [default = %s] -p : toggles deriving edges from packing [default = %s] -o : toggles using old algorithm [default = %s] -m : toggles combining edge assignment with mapping [default = %s] -d : toggles dynamic addition of clauses [default = %s] NICDQdrwvhThe number of AIG nodes should not exceed 128. Current AIG is mapped into %d-LUTs (only 6-LUT mapping is currently supported). usage: &satlut [-NICDQ num] [-drwvh] performs SAT-based remapping of the LUT-mapped network -N num : the limit on AIG nodes in the window (num <= 128) [default = %d] -I num : the limit on the number of improved windows [default = %d] -C num : the limit on the number of conflicts [default = %d] -D num : the user-specified required times at the outputs [default = %d] -Q num : the maximum number of edges [default = %d] -d : toggles delay optimization [default = %s] -r : toggles using reverse search [default = %s] Abc_CommandAbc9Struct(): There is no AIG to map. usage: &unmap [-vh] removes mapping from the current network Abc_CommandAbc9Struct(): Mapping of the AIG is not defined. Abc_CommandAbc9Struct(): Can only handle nodes with less than 8 inputs. usage: &struct [-vh] checks decomposition structures of the current mapping Abc_CommandAbc9Speedup(): There is no AIG to map. Abc_CommandAbc9Speedup(): Mapping of the AIG is not defined. usage: &trace [-lvh] usage: &speedup [-P num] [-N num] [-lvwh] SmcdvhAbc_CommandAbc9Era(): There is no AIG. Abc_CommandAbc9Era(): The network is combinational. Abc_CommandAbc9Era(): The number of PIs (%d) should be no more than 12 when cubes are not used. usage: &era [-S num] [-mcdvh] explicit reachability analysis for small sequential AIGs -S num : the max number of states (num > 0) [default = %d] -m : stop when the miter output is 1 [default = %s] -c : use state cubes instead of state minterms [default = %s] -d : toggle dumping STG into a file [default = %s] WCSsptfremvhAbc_CommandAbc9Dch(): This command does not work with barrier buffers. Gia_ManObjNum(pAbc->pGia) == Aig_ManObjNum(pNew)int Abc_CommandAbc9Dch(Abc_Frame_t *, int, char **)usage: &dch [-WCS num] [-sptfremvh] -e : toggle computing and merging equivalences [default = %s] -m : toggle minimizing logic level after merging equivalences [default = %s] CnavwhAbc_CommandAbc9Rpm(): There is no AIG. usage: &rpm [-C num] [-navwh] performs structural reparametrization -C num : max cut size for testing range equivalence [default = %d] -n : toggle using naive reparametrization [default = %s] -a : toggle using old algorithm [default = %s] FCTvhAbc_CommandAbc9BackReach(): There is no AIG. Abc_CommandAbc9BackReach(): The number of POs is different from 1. usage: &back_reach [-FCT ] [-vh] performs backward reachability by circuit cofactoring Abc_CommandAbc9Posplit(): There is no AIG. usage: &posplit [-N num] [-vh] cofactors the property output w.r.t. a support subset (the OR of new PO functions is equal to the original property) -N num : the number of random cofactoring variables [default = %d] usage: &permute [-vh] permutes primary inputs TBFCHSLripcsyzvwhAbc_CommandAbc9ReachM(): There is no AIG. Abc_CommandAbc9ReachM(): The current AIG has no latches. Abc_CommandAbc9ReachM(): Currently cannot handle AIGs with more than %d objects. usage: &reachm [-TBFCHS num] [-L file] [-ripcsyzvwh] model checking via BDD-based reachability (dependence-matrix-based) -C num : max number of variables in a cluster [default = %d] -H num : max number of hints to use [default = %d] -S num : the number of the starting hint [default = %d] -i : enable extraction of inductive constraints [default = %s] -p : enable partitions for internal cut-points [default = %s] -c : enable clustering of partitions [default = %s] -s : enable scheduling of clusters [default = %s] -z : skip reachability (run preparation phase only) [default = %s] -w : prints dependency matrix [default = %s] NBFTLrbyzdvwhAbc_CommandAbc9ReachP(): There is no AIG. Abc_CommandAbc9ReachP(): The current AIG has no latches. Abc_CommandAbc9ReachP(): Currently cannot handle AIGs with more than %d objects. usage: &reachp [-NFT num] [-L file] [-rbyzdvwh] model checking via BDD-based reachability (partitioning-based) -N num : partitioning value (MinVol=nANDs/N/2; MaxVol=nANDs/N) [default = %d] -r : enable additional BDD var reordering before image [default = %s] -b : perform backward reachability analysis [default = %s] -d : dump BDD of reached states into file "reached.blif" [default = %s] -w : prints additional information [default = %s] BFTLryzvwhAbc_CommandAbc9ReachN(): There is no AIG. Abc_CommandAbc9ReachN(): The current AIG has no latches. Abc_CommandAbc9ReachN(): Currently cannot handle AIGs with more than %d objects. usage: &reachn [-BFT num] [-L file] [-ryzvh] model checking via BDD-based reachability (non-linear-QS-based) -B num : the BDD node increase when hints kick in [default = %d] BCFTLbcryzvwhusage: &reachy [-BCFT num] [-L file] [-bcryzvh] -B num : the max BDD size to introduce cut points [default = %d] -C num : the max BDD size to reparameterize/cluster [default = %d] -b : enable using backward enumeration [default = %s] -c : enable reparametrization clustering [default = %s] Abc_CommandAbc9Undo(): There is no design. Abc_CommandAbc9Undo(): There is no previously saved network. usage: &undo [-h] reverses the previous AIG transformation XYTshCommand line switch "-X" should be followed by an integer. Command line switch "-Y" should be followed by an integer. Abc_CommandAbc9Mesh(): There is no design. Currently this command expects AIG with one output. Currently this command expects AIG with no more than 20 nodes. The depth of the AIG (%d) cannot be larger than the latency (%d). usage: &mesh [-XYT num] [-sh] creates a mesh architecture for the given AIG -X num : horizontal size of the mesh (X >= 3) [default = %d] -Y num : vertical size of the mesh (Y >= 3) [default = %d] -T num : the latency of the mesh (T >= 2) [default = %d] -s : toggle using new SAT solver Satoko [default = %s] neqdvwhAbc_CommandAbc9Iso(): There is no AIG. Abc_CommandAbc9Iso(): The AIG has only one PO. Isomorphism detection is not performed. Abc_CommandAbc9Iso(): Transformation has failed. usage: &iso [-neqdvwh] -n : toggle using new fast algorithm [default = %s] -e : toggle computing lower bound on equivalence classes [default = %s] -q : toggle improving quality at the expense of runtime [default = %s] -d : toggle treating the current AIG as a dual-output miter [default = %s] Abc_CommandAbc9IsoNpn(): There is no AIG. Abc_CommandAbc9IsoNpn(): The AIG has only one PO. Isomorphism detection is not performed. Abc_CommandAbc9IsoNpn(): ISO-NPN does not work with sequential AIGs. Abc_CommandAbc9IsoNpn(): Transformation has failed. usage: &isonpn [-vh] removes POs with functionally isomorphic combinational COI (currently ignores POs whose structural support is more than 16) Abc_CommandAbc9IsoSt(): There is no AIG. Abc_CommandAbc9IsoSt(): The AIG has only one PO. Isomorphism detection is not performed. Abc_CommandAbc9IsoSt(): ISO-ST does not work with sequential AIGs. Abc_CommandAbc9IsoSt(): Transformation has failed. usage: &isost [-vh] (this command relies exclusively on structural hashing) Abc_CommandAbc9CexInfo(): There is no AIG. Abc_CommandAbc9CexInfo(): There is no CEX. usage: &cexinfo [-vh] prints information about the current counter-example FcvhAbc_CommandAbc9Cycle(): There is no AIG. usage: &cycle [-F num] [-cvh] -c : toggle using PI values from the current CEX [default = %s] ORPLWaevhAbc_CommandAbc9Cone(): There is no AIG. %s_%0*d.aigAbc_CommandAbc9Cone(): Parameters -L (max level) and -W (timing window) cannot be specified at the same time. Abc_CommandAbc9Cone(): Partitions are not defined. Abc_CommandAbc9Cone(): Partition index exceed the array size. Abc_CommandAbc9Cone(): Range of outputs to extract is incorrect. usage: &cone [-ORPLW num] [-aevh] -O num : the index of first PO to extract [default = %d] -R num : (optional) the number of outputs to extract [default = %d] -P num : (optional) the partition number to extract [default = %d] -L num : (optional) extract cones with higher level [default = %d] -W num : (optional) extract cones falling into this window [default = %d] -e : toggle writing all outputs into individual files [default = %s] Abc_CommandAbc9Slice(): There is no AIG. usage: &slice [-S num] [-vh] cuts the lower part of the AIG with nodes using their support -S num : the largest support size to keep in the slide [default = %d] Simvhusage: &popart [-S num] [-imvh] partitioning of POs into equivalence classes -S num : random seed to select the set of pivot nodes [default = %d] : (if the seed is 0, the nodes with max fanout counts are used) -i : toggle allowing only CIs to be the pivots [default = %s] -m : toggle using the largest part as the current network [default = %s] GSvhAbc_CommandAbc9GroupProve(): There is no AIG. Abc_CommandAbc9GroupProve(): Command line is not given. usage: &gprove [-GS num] [-vh] proves multi-output testcase by splitting outputs into groups (currently, group size more than one works only for "bmc3" and "pdr") -G num : the size of one group [default = %d] -S str : the command line to be executed for each group [default = %s] noneTLMGHsdvwhAbc_CommandAbc9MultiProve(): There is no AIG. Abc_CommandAbc9MultiProve(): The problem is combinational. usage: &mprove [-TLMGH num] [-sdvwh] proves multi-output testcase by applying several engines -T num : approximate global runtime limit in seconds [default = %d] -L num : approximate local runtime limit in seconds [default = %d] -M num : percentage of local runtime limit increase [default = %d] -G num : approximate gap runtime limit in seconds [default = %d] -H num : timeout per output in miliseconds [default = %d] -s : toggle using combinational synthesis [default = %s] -d : toggle dumping invariant into a file [default = %s] PTILsvwhLook-ahead value ("-L ") should be between 1 and 100. Abc_CommandAbc9SplitProve(): There is no AIG. Abc_CommandAbc9SplitProve(): The problem is sequential. usage: &splitprove [-PTIL num] [-svwh] proves CEC problem by case-splitting -P num : the number of concurrent processes [default = %d] -T num : runtime limit in seconds per subproblem [default = %d] -I num : the max number of iterations (0 = infinity) [default = %d] -L num : maximum look-ahead during cofactoring [default = %d] SFATKdscvwhAbc_CommandAbc9Bmc(): There is no AIG. usage: &bmc [-SFATK num] [-dscvwh] performs bounded model checking -S num : the starting timeframe [default = %d] -F num : the maximum number of timeframes [default = %d] -A num : the number of additional frames to unroll [default = %d] -T num : approximate timeout in seconds [default = %d] -K num : the maximum cut size for CNF computation [default = %d] -d : toggle dumping unfolded timeframes [default = %s] -s : toggle synthesizing unrolled timeframes [default = %s] -c : toggle using old CNF computation [default = %s] -w : toggle printing information about unfolding [default = %s] PCFATgevwhAbc_CommandAbc9Bmcs(): There is no AIG. Abc_CommandAbc9Bmcs(): Currently this command can run at most 4 concurrent solvers. usage: &bmcs [-PCFAT num] [-gevwh] -P num : the number of parallel solvers [default = %d] -C num : the SAT solver conflict limit [default = %d] GlucoseSatoko -e : toggle using variable eliminatation [default = %s] FCvwhAbc_CommandAbc9ChainBmc(): There is no AIG. Abc_CommandAbc9ChainBmc(): The AIG is combinational. usage: &chainbmc [-FC ] [-vwh] runs a specialized flavor of BMC -F : the max number of timeframes (0 = unused) [default = %d] -C : the max number of conflicts (0 = unused) [default = %d] -w : toggle printing even more information [default = %s] FOTVvhCommand line switch "-V" should be followed by a file name. Abc_CommandAbc9BCore(): There is no AIG. Abc_CommandAbc9BCore(): AIG has no registers. Abc_CommandAbc9BCore(): Cannot open file "%s" with pivot node IDs. Abc_CommandAbc9BCore(): Cannot open file "%s" for writing the proof. usage: &bcore [-FOTV num] [-vh] records UNSAT core of the BMC instance -F num : the zero-based index of a timeframe [default = %d] -O num : the zero-based index of a primary output [default = %d] -V file: file name with AIG IDs of pivot variables [default = no pivots] : file name to write the resulting proof [default = stdout] MTesrbdvhAbc_CommandAbc9ICheck(): There is no AIG. Abc_CommandAbc9ICheck(): The AIG is combinational. usage: &icheck [-MT num] [-esrbdvh] performs specialized induction check -M num : the number of timeframes used for induction [default = %d] -e : toggle using empty set of next-state functions [default = %s] -s : toggle searching for a minimal subset [default = %s] -r : toggle searching in the reverse order [default = %s] -b : toggle searching in backward order from POs [default = %s] -d : toggle printing out the resulting set [default = %s] Abc_CommandAbc9SatTest(): There is no AIG. usage: &sattest [-cvh] performs testing of dynamic CNF loading -c : toggle dynamic CNF loading [default = %s] ATNKSGFkbsfcdeunvhCommand line switch "-S" should be followed by a string. Command line switch "-G" should be followed by a file name. Abc_CommandAbc9FFTest(): File name "%s" with formula is invalid. Using formula "%s" from file "%s". Formula string (-S ) should be selected when algorithm is 0 (-A 0). Algorithm should be 0 (-A 0) when formula string is selected (-S ). Cannot open file "%s" with the input test patterns. Abc_CommandAbc9FFTest(): There is no AIG. Abc_CommandAbc9FFTest(): For delay testing, AIG should be sequential. Abc_CommandAbc9FFTest(): File name "%s" with golden model is invalid. Abc_CommandAbc9FFTest(): Cannot read file "%s" with golden model. Abc_CommandAbc9FFTest(): Old model and gold model have different number of PIs. Abc_CommandAbc9FFTest(): Old model and gold model have different number of POs. Entered spec AIG from file "%s". usage: &fftest [-ATNK num] [-kbsfcdeunvh] [-GF file] [-S str] performs functional fault test generation -A num : selects fault model for all gates [default = %d] 0: fault model is not selected (use -S str) 1: delay fault testing for sequential circuits 2: traditional stuck-at fault: -S (((a&b)&~p)|q) 3: complement fault: -S ((a&b)^p) 4: functionally observable fault -T num : specifies approximate runtime limit in seconds [default = %d] -N num : specifies iteration to check for fixed parameters [default = %d] -K num : specifies cardinality constraint (num > 0) [default = unused] -k : toggles non-strict cardinality (n <= K, instead of n == K) [default = %s] -b : toggles testing for single faults (the same as "-K 1") [default = %s] -s : toggles starting with the all-0 and all-1 patterns [default = %s] -f : toggles faults at flop inputs only with "-A 1" and "-S str" [default = %s] -c : toggles checking if there are untestable faults [default = %s] -d : toggles dumping test patterns into file "_tests.txt" [default = %s] -e : toggles dumping test pattern pairs (delay faults only) [default = %s] -u : toggles dumping untestable faults into "_untest.txt" [default = %s] -n : toggles dumping faults not detected by a given test set [default = %s] -v : toggles printing verbose information [default = %s] : (optional) file name with input test patterns -G file : (optional) file name with the golden model -F file : (optional) file name with the fault model in BLIF format -S str : (optional) string representing the fault model The following notations are used: Functional variables: {a,b} (both a and b are always present) Parameter variables: {p,q,r,s,t,u,v,w} (any number from 1 to 8) Boolean operators: AND(&), OR(|), XOR(^), MUX(?:), NOT(~) Parentheses should be used around each operator. Spaces not allowed. Complement (~) is only allowed before variables (use DeMorgan law). Examples: (((a&b)&~p)|q) stuck-at-0/1 at the output (((a&~p)|q)&b) stuck-at-0/1 at input a (((a|p)&(b|q))&~r) stuck-at-1 at the inputs and stuck-at-0 at the output (((a&~p)&(b&~q))|r) stuck-at-0 at the inputs and stuck-at-1 at the output ((a&b)^p) complement at the output (((a^p)&(b^q))^r) complement at the inputs and at the output (a?(b?~s:r):(b?q:p)) functionally observable fault at the output (p?(a|b):(a&b)) replace AND by OR If the BLIF file is used for the formula with option '-F', following rules apply: - the network should be combinational and have exactly one primary output - input names should have only one character: {a, b} (for functional variables) {p,q,r,s,t,u,v,w} (for parameter variables) PICTKdgvhThere is no current GIA. usage: &qbf [-PICTK num] [-dgvh] -C num : conflict limit per problem [default = %d] -K num : the number of input bits (for encoding miters only) [default = %d] Puevhusage: &qvar [-P num] [-uevh] derives cofactors w.r.t. the last NumPi- variables -u : toggle ANDing cofactors (universal quantification) [default = %s] -e : toggle ORing cofactors (existential quantification) [default = %s] FKNSovhWorks only for sequential networks. The number of flops (%d) is less than required (%d). Currently this commands works for one frame and one LUT. usage: &genqbf [-FKN num] [-ovh] generates QBF miter for computing an inductive invariant -F num : the number of time frames for induction [default = %d] -K num : the LUT size [default = %d] -N num : the number of LUTs [default = %d] -o : toggle using the last output [default = %s] KNvhusage: &homoqbf [-KN num] [-vh] generates QBF miter for the encoding problem IDdvhAbc_CommandAbc9SatFx(): There is no AIG. usage: &satfx [-ID num] [-dvh] performs SAT based shared logic extraction -I num : the number of iterations of divisor extraction [default = %d] -D num : the number of divisors to extract in each iteration [default = %d] -d : toggles decomposing the first output [default = %s] CLcvhAbc_CommandAbc9SatClp(): There is no AIG. usage: &satclp [-CL num] [-cvh] FWTsvhAbc_CommandAbc9Inse(): There is no AIG. Abc_CommandAbc9Inse(): AIG is combinational. Abc_CommandAbc9Inse(): All-0 initial state is assumed. usage: &inse [-FWT num] [-svh] experimental procedure -F num : the number of timeframes [default = %d] -W num : the number of machine words [default = %d] -s : toggles using ternary simulation [default = %s] Abc_CommandAbc9Maxi(): There is no AIG. Abc_CommandAbc9Maxi(): AIG is combinational. usage: &maxi [-FWT num] [-svh] Abc_CommandAbc9Bmci(): There is no AIG. Abc_CommandAbc9Bmci(): AIG is combinational. Abc_CommandAbc9Bmci(): Init array is not given. usage: &bmci [-FWT num] [-svh] usage: &poxsim [-F num] [-vh] X-valued simulation of the multi-output sequential miter ftdvhAbc_CommandAbc9Demiter(): There is no AIG. Abc_CommandAbc9Demiter(): Does not look like a dual-output miter. %s_1.aig%s_2.aigTwo parts of the two-word miter are dumped into files "%s" and "%s". Two parts of the dual-output miter are dumped into files "%s" and "%s". Abc_CommandAbc9Demiter(): Miter should have one output. usage: &demiter [-ftdvh] decomposes a miter (by default, tries to extract an OR gate) -f : write files with two sides of a dual-output miter [default = %s] -t : write files with two sides of a two-word miter [default = %s] -d : take single-output and decompose into dual-output [default = %s] NBSLPnafxbvhAbc_CommandAbc9Fadds(): There is no AIG. usage: &fadds [-NBSLP num] [-nafxvh] detects full-adder chains and puts them into white boxes -n : toggles detecting natural full-adder chains [default = %s] -N num : minimum length of a natural full-adder chain to detect [default = %d] -a : toggles detecting artificial full-adder chains [default = %s] -B num : full-adder box delay (percentage of AND-gate delay) [default = %d] -S num : minimum length of an artificial full-adder chain [default = %d] -L num : maximum length of an artificial full-adder chain [default = %d] -P num : maximum number of artificial full-adder chains to detect [default = %d] -f : toggles allowing external fanouts in artificial chains [default = %s] -x : toggles using XOR to generate fanouts in artificial chains [default = %s] -b : toggles ignoring boxes when computing delays [default = %s] ecvwhAbc_CommandAbc9Esop(): There is no AIG. usage: &atree [-ecvwh] extracts adder tree rooting in primary outputs -e : toggles adding extra outputs [default = %s] -c : toggles duplicating complete AIG [default = %s] -w : toggles printing very verbose information [default = %s] NSoasvwhCommand line switch "-S" should be followed by a char string without spaces. Trailing symbols on the command line ("%s"). usage: &polyn [-N num] [-oasvwh] [-S str] derives algebraic polynomial from AIG -N num : the number of additional primary outputs (-1 = unused) [default = %d] -o : toggles old computation [default = %s] -a : toggles simple computation [default = %s] -s : toggles signed computation [default = %s] -S str : (optional) the output signature as a character string The format used to represent the output signature is very restrictive. It should be a string without spaces containing monomials in terms of inputs (i) and outputs (o) where is 0-based. Coefficients are degrees of two, represented by log2 of their value: for example, "2" is 2^2 = 4, "-4" is -2^4=-16, "-0" is -2^0=-1, etc Two types of signature are accepted: (1) a sequence of monomials without parentheses (for example, "-2*o0+1*o1+0*o2") (2) a product of two sequences followed by a sum with a sequence (for example, "(4*o0+2*o1+1*o2)*(4*i3+2*i4+1*i5)+(4*o3+2*o4+1*o5)") Here is the signature of a signed 2-bit multiplier: "(0*o0+1*o1+2*o2-3*o3)" CTmdtbvhAbc_CommandAbc9Acec(): If the input is a miter, it cannot be given on the command line. Abc_CommandAbc9Acec(): There is no AIG. Assuming the current network is a double-output miter. (Conflict limit = %d.) The two-output miter should have an even number of outputs. Assuming the current network is a two-word miter. (Conflict limit = %d.) Assuming the current network is a regular single- or multi-output miter. (Conflict limit = %d.) Too many command-line arguments. usage: &acec [-CT num] [-mdtbvh] combinational equivalence checking for arithmetic circuits -t : toggle using two-word miter [default = %s] -b : toggle working with Booth multipliers [default = %s] Abc_CommandAbc9Anorm(): There is no AIG. usage: &anorm [-bvh] normalize adder trees in the current AIG -b : toggles working with Booth multipliers [default = %s] Abc_CommandAbc9Decla(): There is no AIG. usage: &decla [-bvh] removes carry look ahead adders usage: &esop [-vh] derives Exclusive Sum of Products from AIG QVCqvhAbc_CommandAbc9Exorcism(): Argument error. Abc_CommandAbc9Exorcism(): There is neither an AIG nor an ESOP-PLA file. usage: &exorcism [-Q N] [-V N] [-C N] -q [file_in] performs heuristic exclusive sum-of-project minimization -Q N : minimization quality [default = %d] increasing this number improves quality and adds to runtime -V N : verbosity level [default = %d] 0 = no output; 1 = outline; 2 = verbose -C N : maximum number of cubes in startign cover [default = %d] -q : toggle using quantum cost [default = %s] [file_in] : optional input file in ESOP-PLA format (otherwise current AIG is used) : output file in ESOP-PLA format WFDMLCNdaebvwhAbc_CommandAbc9Mfs(): There is no AIG. Abc_CommandAbc9Mfs(): This command does not work with barrier buffers. Abc_CommandAbc9Mfs(): The current AIG has no mapping. Abc_CommandAbc9Mfs(): The current mapping has nodes with more than 15 inputs. Cannot use "mfs". usage: &mfs [-WFDMLCN ] [-daebvwh] -b : toggle preserving all white boxes [default = %s] KSNPWFMCmcdpvwhAbc_CommandAbc9Mfsd(): There is no AIG. Abc_CommandAbc9Mfsd(): This command does not work with barrier buffers. The current AIG has mapping, which can be used to determine critical path if "-p" is selected. usage: &mfsd [-KSNPWFMC ] [-mcdpvwh] performs SAT-based delay-oriented AIG optimization -K : the LUT size for delay minimization (2 <= num <= 6) [default = %d] -S : the LUT structure size (1 <= num <= 2) [default = %d] -N : the cut size considered for optimization (2 <= num <= 10) [default = %d] -P : the number of cuts computed at a node (1 <= num <= 500) [default = %d] -m : toggle generating delay-oriented mapping [default = %s] -c : toggle using several cuts at each node [default = %s] -d : toggle additional search for good divisors [default = %s] -p : toggle optimizing critical path only [default = %s] TASvhAbc_CommandAbc9DeepSyn(): There is no AIG. usage: &deepsyn [-TAS ] [-vh] performs synthesis -T : the timeout in seconds (0 = no timeout) [default = %d] -A : the number of nodes to stop (0 = no limit) [default = %d] -S : user-specified random seed (0 <= num <= 100) [default = %d] Abc_CommandAbc9AbsCreate(): There is no AIG. Abstraction flop map is already defined. Flop list should be specified on the command line. iFlop >= 0 && iFlop < Gia_ManRegNum(pAbc->pGia)int Abc_CommandAbc9AbsCreate(Abc_Frame_t *, int, char **)usage: &abs_create [-vh] creates new flop map by reading user's input Abc_CommandAbc9AbsDerive(): There is no AIG. Abstraction flop map is missing. usage: &abs_derive [-vh] derives abstracted model using the pre-computed flop map MtsvhAbc_CommandAbc9AbsRefine(): There is no AIG. Abc_CommandAbc9AbsRefine(): There is no counter-example. usage: &abs_refine [-M ] [-tsvh] refines the pre-computed flop map using the counter-example -M num : the max number of flops to add (0 = not used) [default = %d] -t : toggle trying four abstractions instead of one [default = %s] -s : toggle using the path sensitization algorithm [default = %s] Abc_CommandAbc9GlaDerive(): There is no AIG. usage: &gla_derive [-vh] derives abstracted model using the pre-computed gate map FGmvhAbc_CommandAbc9GlaRefine(): There is no AIG. Abc_CommandAbc9GlaRefine(): There is no counter-example. usage: &gla_refine [-FG num] [-vh] refines the pre-computed gate map using the counter-example -F num : starting timeframe for suffix refinement [default = %d] -G num : the number of additional timeframes to try [default = %d] FTpsbvhAbc_CommandAbc9GlaShrink(): There is no AIG. Abc_CommandAbc9GlaShrink(): There is no gate-level abstraction. usage: &gla_shrink [-FT num] [-psbvh] shrinks the abstraction by removing redundant objects -F num : the maximum timeframe to check to [default = %d] -T num : the timeout per call, in seconds [default = %d] -p : toggle using PDR for checking [default = %s] -s : toggle using BMC for checking [default = %s] -b : toggle using BDDs for checking [default = %s] FSCMDETRQPBALtfardmnscbpquwvhThe number of starting frames should be a positive integer. The starting frame is larger than the max number of frames. Vec_IntSize(vStatuses) == Gia_ManPoNum(pAbc->pGia)int Abc_CommandAbc9Gla(Abc_Frame_t *, int, char **)usage: &gla [-FSCMDETRQPB num] [-AL file] [-fardmnscbpquwvh] fixed-time-frame gate-level proof- and cex-based abstraction -F num : the max number of timeframes to unroll [default = %d] -S num : the starting time frame (0=unused) [default = %d] -C num : the max number of SAT solver conflicts (0=unused) [default = %d] -M num : the max number of learned clauses to keep (0=unused) [default = %d] -D num : delta value for learned clause removal [default = %d] -E num : ratio percentage for learned clause removal [default = %d] -T num : an approximate timeout, in seconds [default = %d] -R num : stop when abstraction size exceeds num %% (0<=num<=100) [default = %d] -Q num : stop when abstraction size exceeds num %% during refinement (0<=num<=100) [default = %d] -P num : maximum percentage of added objects before a restart (0<=num<=100) [default = %d] -B num : the number of stable frames to call prover or dump abstraction [default = %d] -A file : file name for dumping abstrated model (&gla -d) or abstraction map (&gla -m) -f : toggle propagating fanout implications [default = %s] -a : toggle refinement by adding one layers of gates [default = %s] -r : toggle using improved refinement heuristics [default = %s] -d : toggle dumping abstracted model into a file [default = %s] -m : toggle dumping abstraction map into a file [default = %s] -n : toggle using new algorithms [default = %s] -s : toggle skipping previously proved timeframes [default = %s] -c : toggle using naive (2-input AND node) CNF encoding [default = %s] -b : toggle CNF construction without hashing [default = %s] -p : toggle using full-proof for UNSAT cores [default = %s] -q : toggle calling the prover [default = %s] -u : toggle enabling simplifation before calling the prover [default = %s] -w : toggle printing more verbose information [default = %s] FSPCLDETRAtradvhThe network is more than one PO (run "orpos"). usage: &vta [-FSPCLDETR num] [-A file] [-tradvh] variable-time-frame gate-level proof- and cex-based abstraction -P num : the number of previous frames for UNSAT core [default = %d] -L num : the max number of learned clauses to keep (0=unused) [default = %d] -R num : minimum percentage of abstracted objects (0<=num<=100) [default = %d] -A file : file name for dumping abstrated model [default = "vabs.aig"] -t : toggle using terminal variables [default = %s] -r : toggle using rollback after the starting frames [default = %s] Abc_CommandAbc9Vta2Gla(): There is no AIG. Abc_CommandAbc9Vta2Gla(): There is no variable-time-frame abstraction is defined. usage: &vta_gla [-vh] maps variable- into fixed-time-frame gate-level abstraction Abc_CommandAbc9Gla2Vta(): There is no AIG. Abc_CommandAbc9Gla2Vta(): There is no gate-level abstraction is defined. Abc_CommandAbc9Gla2Vta(): The number of timeframes (%d) should be a positive integer. usage: &gla_vta [-F num] [-vh] maps fixed- into variable-time-frame gate-level abstraction -F num : timeframes in the resulting variable-time-frame abstraction [default = %d] Abc_CommandAbc9Fla2Gla(): There is no AIG. Abc_CommandAbc9Fla2Gla(): There is no gate-level abstraction is defined. usage: &fla_gla [-vh] maps flop-level into gate-level abstraction Abc_CommandAbc9Gla2Fla(): There is no AIG. Abc_CommandAbc9Gla2Fla(): There is no gate-level abstraction is defined. usage: &gla_fla [-vh] maps gate-level into flop-level abstraction AKNDLBMxvhusage: &gen [-AKNDLBMxvh] generates network -A num : the generation algorithm [default = %d] -K num : the number of LUT inputs [default = %d] -N num : the number of LUTs on one level [default = %d] -D num : the number of LUT levels [default = %d] -L num : limit below which we randomize [default = %d] -B num : select best fanins among this many tries [default = %d] -M num : the multiplier type (1=array, 2=booth) [default = %d] -x : toggle using XOR gates [default = %s] LNURPrcdvhAbc_CommandAbc9Cfs(): There is no AIG. usage: &cfs [-LNURPrcdvh] performs simulation -L num : the limit on the number of occurrences [default = %d] -N num : the number of repetions of each pattern [default = %d] -U num : what to do with unseen patterns [default = %d] -R num : what to do with rare patterns [default = %d] -P num : base2-log of ramdom flip probability [default = %f] -r : toggle replacing rare patterns [default = %s] -c : toggle inserting constants [default = %s] -d : toggle using only DAG nodes [default = %s] WPFsvhusage: &test [-FW num] [-svh] testing various procedures -F num: the number of timeframes [default = %d] -W num: the number of machine words [default = %d] -s : toggle enable (yes) vs. disable (no) [default = %s] CPvhusage: unfold2 [-FCP num] [-savh] Exactly one of the switches "-f", "-i", "-s", "-c" should be enabled.Currently computes glitching only for K-LUT networks with K <= 6.run test suite, ignore all other settingsThis command is currently disabled.BMS manager is not running (use "bms_start").----------------------------------------Generated AIG from AND/XOR/MUX graph.Collapsed AIG with boxes and logic of the boxes.Generated AND/XOR/MUX graph.Default file names will be used.DSD manager has incompatible number of variables. Delay minimization is not performed.Timing manager is given but there is no GIA of boxes.Abc_CommandAbc9Dsdb(): Incompatible size of the DSD manager (run "dsd_free -b").LMS manager is not running (use "rec_start3").DSD manager has different LUT size.DSD manager has incompatible number of variables.DSD only works for LUT structures XY.Dumped all outputs into individual AIGER files.The formula BLIF file contains the network with more one output.Converting PLA to ESOP failed.Reading PLA file has failed.x`src/base/abci/abcAttach.cint Abc_NtkAttach(Abc_Ntk_t *)Cannot attach gate with more than 6 inputs to node %s. Could not attach the library gate to node %s. Library gates are successfully attached to the nodes.Abc_NtkAttach: The network check has failed.Some elementary gates (constant, buffer, or inverter) are missing in the library.The current library is not available.$tIShared BDD size = %6d nodes. Cudd_ReadSize(dd) == 2 * nInputssrc/base/abci/abcAuto.cvoid Abc_NtkAutoPrint(Abc_Ntk_t *, int, int, int)Output #%3d: Inputs = %2d. AutoK = %2d. Ins=%3d InMax=%3d Outs=%3d Auto=%3d SumK=%3d KMax=%2d Supp=%3d Time=%4.2f The cumulative statistics for all outputs:Spaces are NOT EQUAL!src/base/abci/abcBalance.cAbc_Ntk_t *Abc_NtkBalance(Abc_Ntk_t *, int, int, int)Abc_ObjRegular(pNodeLeft)->Level == Abc_ObjRegular(pNodeRight)->Levelint Abc_NodeBalanceFindLeft(Vec_Ptr_t *)LeftBound <= RightBoundvoid Abc_NodeBalancePermute(Abc_Ntk_t *, Vec_Ptr_t *, int)int Abc_NodeBalanceConeExor_rec(Abc_Obj_t *, Vec_Ptr_t *, int)pNode->fExorVec_Ptr_t *Abc_NodeFindCone_rec(Abc_Obj_t *)vNodes->nSize > 1int Abc_NtkBalanceLevel_rec(Abc_Obj_t *)vSuper != NULLAbc_Obj_t *Abc_NodeBalance_rec(Abc_Ntk_t *, Abc_Obj_t *, Vec_Vec_t *, int, int, int, int)Abc_ObjIsNode(pNodeOld)vSuper->nSize > 1Vec_Ptr_t *Abc_NodeBalanceCone(Abc_Obj_t *, Vec_Vec_t *, int, int, int)int Abc_NodeBalanceCone_rec(Abc_Obj_t *, Vec_Ptr_t *, int, int, int)The number of nodes on the critical paths = %6d (%5.2f %%) BUG!Abc_NtkBalance: The network check has failed.?src/base/abci/abcBidec.cHop_Obj_t *Abc_NodeIfNodeResyn(Bdc_Man_t *, Hop_Man_t *, Hop_Obj_t *, int, Vec_Int_t *, unsigned int *, float)Prob >= 0.0 && Prob <= 0.5void Abc_NtkBidecResyn(Abc_Ntk_t *, int)Total gain in AIG nodes = %d. Total runtimeResynthesis is not performed for nodes with more than 15 inputs.WARNING! Integer overflow!%s_%s_miterAbc_NtkIsDfsOrdered(pNtk1)src/base/abci/abcBm.cAbc_Ntk_t *Abc_NtkMiterBm(Abc_Ntk_t *, Abc_Ntk_t *, Vec_Ptr_t *, Vec_Ptr_t *)Abc_NtkIsDfsOrdered(pNtk2)Abc_NtkCiNum(pNtk1) == Abc_NtkCiNum(pNtk2)void Abc_NtkVerifyReportError(Abc_Ntk_t *, Abc_Ntk_t *, int *, Vec_Int_t *)Abc_NtkCoNum(pNtk1) == Abc_NtkCoNum(pNtk2)int Abc_NtkMiterSatBm(Abc_Ntk_t *, ABC_INT64_T, ABC_INT64_T, int, ABC_INT64_T *, ABC_INT64_T *)Miter computation has failed.Renoding for CNF has failed.subNtkIOmatch.txtI/O = %d / %d {%s} {%s} ----------------------------------------- I/O dependencies of two circuits are different. Refining IOs by dependencies ...Refining IOs by simulation ...Input refinement by simulation finds two circuits different. Init Time = %4.2f Simulation Time = %4.2f SAT Time = %4.2f Overall Time = %4.2f int Vec_IntPop(Vec_Int_t *) done!*** Circuits are NOT equivalent ****** Circuits are equivalent ***Network strashing is done!Getting dependencies is done!Initializing match lists is done!SAT-based search started ...Frames have %6d nodes. Fraig has %6d nodes. src/base/abci/abcCas.cAbc_Ntk_t *Abc_NtkCascade(Abc_Ntk_t *, int, int, int)Shared BDD size = %6d nodes. BDD construction timeAbc_NtkCollapse: The network check has failed.UUUUUUUUUUUUUUUU3333333333333333src/base/abci/abcCascade.cDdNode *Abc_ResBuildBdd(Abc_Ntk_t *, DdManager *)Abc_NtkCoNum(pNtk) <= 3Count == nInputsvoid Abc_ResStartPart(int, unsigned int *, int)void Abc_ResStartPart2(int, unsigned int *, int)int Abc_ResCofCount(DdManager *, DdNode *, unsigned int, int *)(uParts[iPart1] & uParts[iPart2]) == 0int Abc_ResMigrate(DdManager *, DdNode *, int, unsigned int *, int, int) %2d %d-%d %6d n=%2d c=%2d l=%d-%d %6d Ins =%3d. Outs =%2d. Nodes =%3d. Supp =%2d. Inputs = %2d. Nodes = %2d. LutSize = %2d. [%2d %2d] : %3d : %2d bFunc0 == bConst0 || bFunc1 == bConst0DdNode *Abc_NtkBddFindAddConst(DdManager *, DdNode *, int)bFunc == bConst1!Cudd_IsComplement(bFunc)DdNode *Abc_NtkBddToAdd_rec(DdManager *, DdNode *, int, stmm_table *, int)Cudd_ReadPerm(dd, bFunc->index) >= Cudd_ReadSize(dd) - nOuts!Cudd_IsComplement(aFunc)DdNode *Abc_NtkAddToBdd_rec(DdManager *, DdNode *, int, int, stmm_table *)Cudd_ReadSize(dd) >= nIns + nOutsaFunc->index < nInsCount == nBitsDdNode *Abc_NtkBddDecCharFunc(DdManager *, DdNode **, int, int, int)Abc_NtkCreateFromCharFunc(): Network check has failed. Abc_Ntk_t *Abc_NtkBddDec(Abc_Ntk_t *, int)Abc_NtkCoNum(pNtk) <= BDD_FUNC_MAXConstruction of global BDDs has failed. dd->size == Abc_NtkCiNum(pNtk)Randomizing... Support is less or equal than 6src/base/abci/abcCollapse.cint Abc_NodeMinimumBase2(Abc_Obj_t *)int Abc_NtkMinimumBase2(Abc_Ntk_t *)Abc_NtkIsStrash(pNtk->pExdc)Abc_Ntk_t *Abc_NtkFromGlobalBdds(Abc_Ntk_t *, int)Abc_NtkCoNum(pNtk->pExdc) == 1Abc_Ntk_t *Abc_NtkCollapse(Abc_Ntk_t *, int, int, int, int, int)int Abc_NtkClpGia_rec(Gia_Man_t *, Abc_Obj_t *)Gia_Man_t *Abc_NtkClpGia(Abc_Ntk_t *)iClaBeg < iClaEndsat_solver *Abc_NtkClpDeriveSatSolver(Cnf_Dat_t *, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, sat_solver **, sat_solver **, sat_solver **)nVars == sat_solver_nvars(pSat)Output %4d: Supp = %4d. Cone =%6d. Supp new = %4d. Sop = %4d. Vec_IntSize(vAnds) > 0Vec_Str_t *Abc_NtkClpGiaOne2(Cnf_Dat_t *, Gia_Man_t *, int, int, int, int, int, Vec_Int_t *, Vec_Int_t *, int, Vec_Int_t *, Vec_Wec_t *)Considering %d (out of %d) outputs. Reduction timeVec_IntSize( Vec_WecEntry(vSupps, iCoThis) ) == Abc_SopGetVarNum(Vec_StrArray(vSop))Vec_Ptr_t *Abc_GiaDeriveSops(Abc_Ntk_t *, Gia_Man_t *, Vec_Wec_t *, int, int, int, int, int, int, int)Vec_PtrCountZero(vSops) == 0Cost of the largest output cone exceeded the limit (%d * %d * %d > %d). pNodeNew->pData != (void *)(ABC_PTRINT_T)1Abc_Ntk_t *Abc_NtkFromSopsInt(Abc_Ntk_t *, int, int, int, int, int, int, int)Abc_Ntk_t *Abc_NtkCollapseSat(Abc_Ntk_t *, int, int, int, int, int, int, int)void Vec_StrWriteEntry(Vec_Str_t *, int, char)int Abc_Lit2LitV(int *, int)Abc_NtkCollapseSat: The network check has failed.pFanC->vFanouts.nSize > 1src/base/abci/abcCut.cvoid Abc_NtkCutsSubtractFanunt(Abc_Ntk_t *)pFan0->vFanouts.nSize > 1Substracted %d fanouts Added %d fanouts Cut_Man_t *Abc_NtkCuts(Abc_Ntk_t *, Cut_Params_t *)TOTALTotal cuts = %d. Good cuts = %d. Ratio = %5.2f void Abc_NtkCutsOracle(Abc_Ntk_t *, Cut_Oracle_t *)Abc_ObjFaninNum(pObj) == 2void *Abc_NodeGetCuts(void *, Abc_Obj_t *, int, int)int Abc_NtkSubDagSize_rec(Abc_Obj_t *, Vec_Int_t *)Vec_Int_t *Abc_NtkGetNodeAttributes2(Abc_Ntk_t *)Total nodes = %d. Total MFFC nodes = %d. Warning: %d registers in this network have don't-care init values. The don't-care are assumed to be 0. The result may not verify. Use command "print_latch" to see the init values of registers. Use command "zero" to convert or "init" to change the values. Abc_NtkToDarBmc: AIG check has failed. src/base/abci/abcDar.cAig_Man_t *Abc_NtkToDar(Abc_Ntk_t *, int, int)Abc_NtkToDar(): Unexpected %d dangling nodes when converting to AIG! Abc_NtkToDar: AIG check has failed. pMan->nAsserts == 0Abc_Ntk_t *Abc_NtkFromDar(Abc_Ntk_t *, Aig_Man_t *)Abc_NtkFromDar(): Network check has failed. Abc_Ntk_t *Abc_NtkFromDarSeqSweep(Abc_Ntk_t *, Aig_Man_t *)pNtkOld->nBarBufs == 0Abc_NtkCiNum(pNtkNew) == Aig_ManCiNum(pMan) - Aig_ManRegNum(pMan)Abc_NtkCoNum(pNtkNew) == Aig_ManCoNum(pMan) - Aig_ManRegNum(pMan)Abc_NtkBoxNum(pNtkOld) == Abc_NtkLatchNum(pNtkOld)Abc_Ntk_t *Abc_NtkFromAigPhase(Aig_Man_t *)Abc_NtkFromAigPhase(): Network check has failed. Hop_Obj_t *Abc_ObjHopFromGia_rec(Hop_Man_t *, Gia_Man_t *, int, Vec_Ptr_t *)Gia_ObjIsLut(p, GiaId)Hop_Obj_t *Abc_ObjHopFromGia(Hop_Man_t *, Gia_Man_t *, int, Vec_Ptr_t *)Gia_ObjLutSize(p, GiaId) > 0Gia_ManHasMapping(p) || p->pMuxes || fFindEnablesAbc_Ntk_t *Abc_NtkFromMappedGia(Gia_Man_t *, int, int)!fFindEnables || !p->pMuxespObj->Value == ~0Gia_ManPiNum(p) == Abc_NtkPiNum(pNtkNew)Gia_ManPoNum(p) == Abc_NtkPoNum(pNtkNew)Gia_ManRegNum(p) == Abc_NtkLatchNum(pNtkNew)Abc_NtkFromMappedGia(): Network check has failed. Gia_ManHasCellMapping(p)Abc_Ntk_t *Abc_NtkFromCellMappedGia(Gia_Man_t *, int)pNtkNew->pManFunc == Abc_FrameReadLibGen()Abc_ObjIsBarBuf(pObjNew)Vec_IntEntry(vCopyLits, iLitNot) == -1Gia_ObjCellId(p, iLitNot) > 0Vec_IntEntry(vCopyLits, iLitNot) != -1Gia_ObjCellId(p, iLit) >= 0Vec_IntEntry(vCopyLits, iLit) == -1Abc_Ntk_t *Abc_NtkAfterTrim(Aig_Man_t *, Abc_Ntk_t *)Aig_ManRegNum(pMan) <= Abc_NtkLatchNum(pNtkOld)Saig_ManPiNum(pMan) <= Abc_NtkCiNum(pNtkOld)Saig_ManPoNum(pMan) == Abc_NtkPoNum(pNtkOld)pMan->vCiNumsOrig != NULLAbc_NtkAfterTrim(): Network check has failed. pMan->pEquivs != NULLAbc_Ntk_t *Abc_NtkFromDarChoices(Abc_Ntk_t *, Aig_Man_t *)Aig_ManBufNum(pMan) == 0pTemp->pData != NULLAbc_Ntk_t *Abc_NtkFromDarSeq(Abc_Ntk_t *, Aig_Man_t *)Abc_NtkFromIvySeq(): Network check has failed. Vec_Int_t *Abc_NtkGetLatchValues(Abc_Ntk_t *)Abc_Ntk_t *Abc_NtkDar(Abc_Ntk_t *)Abc_NtkDar: The network check has failed. Abc_Ntk_t *Abc_NtkDRewrite(Abc_Ntk_t *, Dar_RwrPar_t *)Abc_Ntk_t *Abc_NtkDRefactor(Abc_Ntk_t *, Dar_RefPar_t *)Abc_Ntk_t *Abc_NtkDC2(Abc_Ntk_t *, int, int, int, int, int)Abc_Ntk_t *Abc_NtkDChoice(Abc_Ntk_t *, int, int, int, int, int, int)Abc_Ntk_t *Abc_NtkDch(Abc_Ntk_t *, Dch_Pars_t *)Abc_Ntk_t *Abc_NtkDrwsat(Abc_Ntk_t *, int, int)Abc_NtkConstructFromCnf(): Network check has failed. Abc_Ntk_t *Abc_NtkDarToCnf(Abc_Ntk_t *, char *, int, int, int)Abc_NtkDarToCnf: AIG check has failed. CNF stats: Vars = %6d. Clauses = %7d. Literals = %8d. int Abc_NtkDSat(Abc_Ntk_t *, ABC_INT64_T, ABC_INT64_T, int, int, int, int, int, int, int)int Abc_NtkPartitionedSat(Abc_Ntk_t *, int, int, int, int, int, int, int)Abc_NtkDarCec(): Switching to non-partitioned CEC for the miter. Networks are NOT EQUIVALENT after structural hashing. Networks are equivalent after structural hashing. Converting miter into AIG has failed. Networks are equivalent. Networks are NOT EQUIVALENT. Networks are UNDECIDED. Initial fraiging timeHere are the flop equivalences: Original flop %s is proved equivalent to constant. Saig_ObjIsLo( pAig, pRepr )void Abc_NtkPrintLatchEquivClasses(Abc_Ntk_t *, Aig_Man_t *)Original flop %s is proved equivalent to flop %s. The following flops have been deemed irrelevant: pMan->nRegs > 0int Abc_NtkDarBmc(Abc_Ntk_t *, int, int, int, int, int, int, int, int, int, int, int, int, int *, int)vMap == NULL || Vec_IntSize(vMap) == Saig_ManPoNum(pMan)Incorrect return value. No output asserted in %d frames. Resource limit reached (timeout %d sec). (conf limit %d). Output %d of miter "%s" was asserted in frame %d. Abc_NtkDarBmc(): Counter-example verification has FAILED. int Abc_NtkDarBmc3(Abc_Ntk_t *, Saig_ParBmc_t *, int)Explored all reachable states after completing %d frames. The total of %d outputs asserted in %d frames. Resource limit reached None of the %d outputs is found to be SATAll %d outputs are found to be SATSome outputs are SAT (%d out of %d) while others timed out (%d out of %d) after %d framesAbc_NtkDarBmc3(): Counter-example verification has FAILED. int Abc_NtkDarBmcInter_int(Aig_Man_t *, Inter_ManParams_t *, Aig_Man_t **)Solving output %2d (out of %2d): Output %d proved SAT in frame %d (replacing by const 0 and continuing...) Solving output %3d (out of %3d) using interpolation. Interpolation left %d (out of %d) outputs unsolved The total of %d outputs proved SAT and replaced by const 0 in this run. Property proved. Output %d of miter "%s" was asserted in frame %d. Property UNDECIDED. Converting network into AIG has failed. part0.aigpart1.aigDemitering produced two files "%s" and "%s". part0part1The network has no latches. Running CEC. SOLUTION: FAIL SOLUTION: PASS int Abc_NtkDarProve(Abc_Ntk_t *, Fra_Sec_t *, int, int)Networks are not equivalent. Output %d of miter "%s" was asserted in frame %d. Abc_NtkDarProve(): Counter-example verification has FAILED. int Abc_NtkDarSec(Abc_Ntk_t *, Abc_Ntk_t *, Fra_Sec_t *)Properties: All = %d. Proved = %d. Disproved = %d. Undecided = %d. Abc_NtkDarPdr(): Counter-example is not available. Abc_NtkDarPdr(): Counter-example verification has FAILED. int Abc_NtkDarPdr(Abc_Ntk_t *, Pdr_Par_t *)Aig_ManRegNum(pMan1) > 0int Abc_NtkDarAbSec(Abc_Ntk_t *, Abc_Ntk_t *, int, int)Aig_ManRegNum(pMan2) > 0The networks have different number of PIs. The networks have different number of POs. The networks have different number of flops. int Abc_NtkDarSimSec(Abc_Ntk_t *, Abc_Ntk_t *, Ssw_Pars_t *)Abc_Ntk_t *Abc_NtkDarMatch(Abc_Ntk_t *, Abc_Ntk_t *, int, int)Abc_Ntk_t *Abc_NtkDarRetimeStep(Abc_Ntk_t *, int)Removing %d choices from the AIG. Simulation of %d frames with %d words asserted output %d in frame %d. Abc_NtkDarSeqSim(): Counter-example verification has FAILED. Simulation of %d frames with %d words did not assert the outputs. int Abc_NtkDarSeqSim(Abc_Ntk_t *, int, int, int, int, int, int, char *)Simulation of %d frame%s with %d word%s asserted output %d in frame %d. The number of outputs should be 1. Currently works only for single-output networks. The number of PIs should be the same. Interpolant computation failed. Gia_ManCiNum(pNtkOn) == Gia_ManCiNum(pNtkOff)Gia_Man_t *Gia_ManInterOne(Gia_Man_t *, Gia_Man_t *, int)Gia_ManCoNum(pNtkOn) == 1Gia_ManCoNum(pNtkOff) == 1Currently works only for networks with equal number of POs. Aig_ManRegNum(pMan) > 0int Abc_NtkDarPrintCone(Abc_Ntk_t *)Abc_Ntk_t *Abc_NtkBalanceExor(Abc_Ntk_t *, int, int)Selected object %d as a window pivot. The ID is too large. Object with ID %d does not exist. Object with ID %d is not a node or reg output. Cleanup removed %d primary inputs without fanout. Cleanup removed %d primary outputs driven by const-0. Current library does not contain gate "%s". iPis == Abc_NtkCiNum(pNtkNew)Abc_Ntk_t *Amap_ManProduceNetwork(Abc_Ntk_t *, Vec_Ptr_t *)iPos == Abc_NtkCoNum(pNtkNew)Abc_Ntk_t *Abc_NtkDarAmap(Abc_Ntk_t *, Amap_Par_t *)void Abc_NtkDarConstr(Abc_Ntk_t *, int, int, int, int, int, int)Abc_Ntk_t *Abc_NtkDarOutdec(Abc_Ntk_t *, int, int)Abc_Ntk_t *Abc_NtkDarUnfold(Abc_Ntk_t *, int, int, int, int, int, int)Abc_Ntk_t *Abc_NtkDarFold(Abc_Ntk_t *, int, int)void Abc_NtkDarConstrProfile(Abc_Ntk_t *, int)Abc_NtkConstrNum(pNtk)TwoFrameSatValue = %d. void Abc_NtkDarTest(Abc_Ntk_t *, int)Abc_Ntk_t *Abc_NtkDarTestNtk(Abc_Ntk_t *)src/base/abci/abcDarUnfold2.cAbc_Ntk_t *Abc_NtkDarUnfold2(Abc_Ntk_t *, int, int, int, int, int, int)Abc_Ntk_t *Abc_NtkDarFold2(Abc_Ntk_t *, int, int, int)p->pEquivs./src/aig/aig/aig.hvoid Aig_ObjSetEquiv(Aig_Man_t *, Aig_Obj_t *, Aig_Obj_t *)!Aig_IsComplement(pObj)Aig_Obj_t *Aig_ObjChild0Copy(Aig_Obj_t *)Id < p->nTravIdsAllocint Gia_ObjIsTravIdCurrentId(Gia_Man_t *, int)void Gia_ObjSetTravIdCurrentId(Gia_Man_t *, int)int *Vec_IntEntryP(Vec_Int_t *, int)Gia_Obj_t *Gia_ObjRiToRo(Gia_Man_t *, Gia_Obj_t *)Abc_Obj_t *Abc_NtkFromCellRead(Abc_Ntk_t *, Vec_Int_t *, int, int)int Aig_ObjIsConst1(Aig_Obj_t *)!Aig_ObjIsNode(pObj)int Aig_ObjCioId(Aig_Obj_t *)bug_found.blifsrc/base/abci/abcDebug.cvoid Abc_NtkAutoDebug(Abc_Ntk_t *, int (*)(Abc_Ntk_t *))bug_temp.blifIter %6d : Latches = %6d. Nodes = %6d. Steps = %6d. Error step = %3d. Final network written into file "%s". Total timeAbc_NtkNodeNum(pNtk) == Abc_NtkNodeNum(pNtkInit)Abc_Ntk_t *Abc_NtkAutoDebugModify(Abc_Ntk_t *, int, int)The original network does not cause the bug. Quitting.V}M@}M@}M@}M@}M@}M@}M@}M@}M@}M`}M@}M@}M`}M@}M@}M@}M@}M@}M@}M@}M@}M@}M@}M@}M@}M@}M@}M@}M@}M@}M@}M`}M~M}M)M{~M)M)M)M~M)M)M)M)M)M)M)M~M)M)M)M)M)M)M)M)M)M)M)M)M)M)M)M~M)M)M)M)M)M)M)M)M)M)M)M)M)M)M)M)M)M)M)M)M)M)M)M)M)M)M)M)M)M)M)M~MBMMMMMUUUUUUUU33333333]W%].]7]EndSymbol == ' ' || EndSymbol == '\n' || EndSymbol == '\r' || EndSymbol == '\0'src/base/abci/abcDec.cvoid Abc_TruthReadHex(word *, char *, int)Cannot open file "%s" for reading. p->nFuncs >= nLinesvoid Abc_TruthStoreRead(char *, Abc_TtStore_t *)nVarNum >= 6Abc_TtStore_t *Abc_TtStoreLoad(char *, int)The file size (%d) is divided by the truth table size (%d) with remainder (%d). _binary.dataInput file "%s" was copied into output file "%s". Len == (1 << nVars)void Abc_TtStoreLoadSaveBin(char *)nVarsAll == nVarspBuffer[i] == '0'Value == (int)sizeof(int) * nIntsbi-decompfast DSDanalysisDSD ICCD'15Applying %-10s to %8d func%s of %2d vars... %7d : void Abc_TruthDecPerform(Abc_TtStore_t *, int, int)AIG nodes =%9d Using truth tables from file "%s"... Unknown decomposition type value (%d). int Abc_TruthReadHexDigit(char)Does not look like the input file contains truth tables...Strange, the input file does not have spaces and new-lines...MMjMMMMMMM MMMOM%NMMMM?MMMM N'Nz N N N N N N N N NQ`fja a*a2a;aDaNaWasrc/base/abci/abcDetect.cvoid Abc_NtkGenFaultList(Abc_Ntk_t *, char *, int)%d %s %s SA0Generated fault list "%s" for network "%s" with %d nodes and %d %sfaults. stuck-at Cannot find gate "%s" in the current library. RDOB_ANDRDOB_NANDRDOB_ORRDOB_NORRDOB_XORRDOB_NXORRDOB_NOTRDOB_BUFFUnknownCannot open input file "%s" for reading. The same name "%s" appears twice among CIs and internal nodes. Vec_IntSize(vMap) == Abc_NamObjNumMax(pNam)Vec_Int_t *Io_ReadFins(Abc_Ntk_t *, char *, int) Cannot find object with name "%s". Cannot read type "%s" of object "%s". Vec_IntSize(vPairs) == 2 * nLinesFinished reading %d lines from the fault list file "%s". %-10d%-10s%-10s Abc_NtkPiNum(pNtk) >= pNtk->nConstrsvoid Abc_NtkFrameExtend(Abc_Ntk_t *)Abc_NtkPoNum(pNtk) >= pNtk->nConstrs * 4_frame1Abc_ObjIsCi(pObj) || Abc_ObjIsNode(pObj)int Abc_NtkDetectObjClasses_rec(Abc_Obj_t *, Vec_Int_t *, Hsh_VecMan_t *, Vec_Int_t *)Vec_Wec_t *Abc_NtkDetectObjClasses(Abc_Ntk_t *, Vec_Int_t *, Vec_Wec_t **)SetId == 0SetId >= 0Abc_ObjIsNode( pObj )void Abc_NtkFinMiterCollect_rec(Abc_Obj_t *, Vec_Int_t *, Vec_Int_t *)void Mio_LibGateSimulate(Mio_Gate_t *, word **, int, word *)Index0 < nVarsint Mio_LibGateSimulateGia(Gia_Man_t *, Mio_Gate_t *, int *, Vec_Int_t *)nItems == Vec_WecSizeSize(vMap2)void Abc_NtkFinSimulateOne(Abc_Ntk_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Wec_t *, Vec_Int_t *, Vec_Wrd_t *, int, Vec_Int_t *, Vec_Wec_t *, int, int)nItems <= 128 * nWordsVec_IntSize(vPat) == Vec_IntSize(vCis)Index < 64iObj == (int)Abc_ObjId(pObj)Type == ABC_FIN_NEG || Type == ABC_FIN_SA0 || Type == ABC_FIN_SA1Index < 64 * nWordsnItems == 2*CounterVec_IntEntry(vClass, k) == iFinint Abc_NtkFinRefinement(Abc_Ntk_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Wec_t *, Vec_Wec_t *)Vec_IntSize(vClass) <= k || Vec_IntEntry(vClass, k) != iFinVec_IntSize(vArray) % 2 == 0Abc_NtkIsSopLogic(pNtk) || Abc_NtkIsMappedLogic(pNtk)Vec_Wec_t *Abc_NtkDetectFinClasses(Abc_Ntk_t *, int)Current network contains unsupported gate types (for example, see node "%s"). Current network has mismatch between mapped gate size and fault gate size (for example, see node "%s"). Group %4d : Obj =%4d. Fins =%4d. CI =%5d. CO =%5d. Node =%6d. SAT calls =%5d. Computed %d equivalence classes with %d item pairs. vArr->nSize <= vArr->nCapvoid Vec_IntTwoMerge2Int(Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)vArr->nSize >= vArr1->nSizevArr->nSize >= vArr2->nSizeVec_IntSize(p->vData) % 2 == 0./src/misc/vec/vecHsh.hint Hsh_VecManAdd(Hsh_VecMan_t *, Vec_Int_t *)Vec_Int_t *Vec_WecEntryLast(Vec_Wec_t *) %4d : {Type != ABC_FIN_NEGint Abc_NtkFinSimOneLit(Gia_Man_t *, Abc_Obj_t *, int, Vec_Int_t *, int, Vec_Int_t *)./src/misc/vec/vecWrd.hword *Vec_WrdEntryP(Vec_Wrd_t *, int)int Abc_NtkFinSimOneBit(Abc_Obj_t *, int, Vec_Wrd_t *, int, int)Type == -1void Abc_NtkFinSimOneWord(Abc_Obj_t *, int, Vec_Wrd_t *, int)i1 != i2int Abc_NtkFinCompareSimTwo(Abc_Ntk_t *, Vec_Int_t *, Vec_Wrd_t *, int, int, int)v >= 0 && v < s->size./src/sat/bsat/satSolver.hint sat_solver_var_value(sat_solver *, int)i >= 0 && i < Vec_IntSize(p)void Vec_IntDrop(Vec_Int_t *, int)11 0 00 0 Line numbers are not consecutive. Quitting.Current network does not have the required info.Abc_NtkIsLogic(pNtkLogic)src/base/abci/abcDress.cvoid Abc_NtkDress(Abc_Ntk_t *, char *, int)Abc_NtkIsNetlist(pNtkOrig)Logic: Nodes = %5d. Copy = %5d. Orig: Nodes = %5d. Copy = %5d. stmm_table *Abc_NtkDressDeriveMapping(Abc_Ntk_t *)void Abc_NtkDressTransferNames(Abc_Ntk_t *, stmm_table *, int)_invTotal number of names collected = %5d. Total number of names assigned = %5d. (Dir = %5d. Compl = %5d.) After fraiging:After mitering:Aig_ManCiNum(p1) == Aig_ManCiNum(p2)src/base/abci/abcDress2.cAig_Man_t *Aig_ManCreateDualOutputMiter(Aig_Man_t *, Aig_Man_t *)Aig_ManCoNum(p1) == Aig_ManCoNum(p2)Class > 0Vec_Int_t *Abc_ObjDressClass(Vec_Ptr_t *, Vec_Int_t *, int)ClassNumber != 0!Abc_NtkIsStrash(pNtk1)Vec_Ptr_t *Abc_NtkDressComputeEquivs(Abc_Ntk_t *, Abc_Ntk_t *, int, int)!Abc_NtkIsStrash(pNtk2)Class %5d : Num =%5d %5d%c%d Total number of equiv classes = %7d. Participating nodes from both networks = %7d. Participating nodes from the first network = %7d. (%7.2f %% of nodes) Participating nodes from the second network = %7d. (%7.2f %% of nodes) Node pairs (any polarity) = %7d. (%7.2f %% of names can be moved) Node pairs (same polarity) = %7d. (%7.2f %% of names can be moved) src/base/abci/abcDress3.cvoid Abc_ConvertHopToGia_rec1(Gia_Man_t *, Hop_Obj_t *)void Abc_ConvertHopToGia_rec2(Hop_Obj_t *)int Abc_ConvertHopToGia(Gia_Man_t *, Hop_Obj_t *)void Abc_NtkAigToGiaOne(Gia_Man_t *, Abc_Ntk_t *, Vec_Int_t *)Abc_NtkIsAigLogic(pNtk1)Gia_Man_t *Abc_NtkAigToGiaTwo(Abc_Ntk_t *, Abc_Ntk_t *, int)Abc_NtkIsAigLogic(pNtk2)Index == Abc_NtkCiNum(pNtk1)Num < 0 || Abc_ObjIsCi(Abc_NtkObj(pNtk1, Num))Matched %d vars by name. Netlist1 has %d unmatched vars. Netlist2 has %d unmatched vars.Matched %d vars by order. The last %d vars of Netlist2 are unmatched vars. The last %d vars of Netlist1 are unmatched vars.Cannot open file %s for writing. # Node equivalences computed by ABC for networks "%s" and "%s" on %s %d:%s:%s%s NOT:Computing equivalences for networks "%s" and "%s" with conflict limit %d. NNNN Nsrc/base/abci/abcDsd.cAbc_Ntk_t *Abc_NtkDsdGlobal(Abc_Ntk_t *, int, int, int)int Abc_NtkDsdLocal(Abc_Ntk_t *, int, int)Inputs = %d. Functions = %6d. Inputs > %d. Functions = %6d. _on_offAbc_ObjFaninNum(pObj) > 0Abc_Ntk_t *Abc_NtkSparsifyInternal(Abc_Ntk_t *, int, int)Abc_NtkIsComb(pNtk)Abc_Ntk_t *Abc_NtkSparsify(Abc_Ntk_t *, int, int)void Abc_NtkDsdConstruct(Dsd_Manager_t *, Abc_Ntk_t *, Abc_Ntk_t *)nDecs > 1Abc_Obj_t *Abc_NtkDsdConstructNode(Dsd_Manager_t *, Dsd_Node_t *, Abc_Ntk_t *, int *)Type == DSD_NODE_OR || !Dsd_IsComplement(pFaninDsd)int Abc_NodeIsForDsd(Abc_Obj_t *)pRootvoid Abc_NodeDecompDsdAndMux(Abc_Obj_t *, Vec_Ptr_t *, Dsd_Manager_t *, int, int *)Abc_NtkDsdGlobal: The network check has failed.Abc_NtkDsdRecursive: The network check has failed.Number of non-decomposable functions:Abc_NtkSparsify: The network check has failed.N7N7NNXND+O+O`,O3O+OUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU33333333333333333333333333333333A 5 nVars >= 2 && nVars <= 8src/base/abci/abcExact.cAbc_Ntk_t *Abc_NtkFindExact(word *, int, int, int, int *, int, int, int)Gia_Man_t *Gia_ManFindExact(word *, int, int, int, int *, int, int, int)pNtk2void Abc_ExactTestSingleOutput(int)Abc_NtkNodeNum( pNtk2 ) == 6pNtk3Abc_NtkLevel( pNtk3 ) <= 3pNtk4Abc_NtkLevel( pNtk4 ) <= 9!Abc_NtkFindExact( pTruth, 4, 1, 2, NULL, 50000, 0, fVerbose )!Abc_NtkFindExact( pTruth, 4, 1, 8, pArrTimeProfile, 50000, 0, fVerbose )void Abc_ExactTestSingleOutputAIG(int)!Gia_ManFindExact( pTruth, 4, 1, 2, NULL, 50000, 0, fVerbose )!Gia_ManFindExact( pTruth, 4, 1, 8, pArrTimeProfile, 50000, 0, fVerbose )bms.debugnumber of considered cuts :%10lu%10lu - trivial : - synth (imp) : - synth (res) : - not synth (imp) : - not synth (res) : - cache hits :number of entries : %d number of valid entries : %d number of invalid entries : %d number of SAT calls : %lu number of UNSAT calls : %lu number of UNDEF calls : %lu Exact %9.2f sec (%6.2f %%) Sat Sat Unsat Undef InstanceALL invalid truth table size %d int Abc_ExactDelayCost(word *, int, int *, char *, int *, int) [%d]@%d:%d%s%d*Cost == ABC_INFINITYSes_StoreGetEntry( s_pSesStore, pTruth, nVars, pNormalArrTime, &pSol )Abc_Obj_t *Abc_ExactBuildNode(word *, int, int *, Abc_Obj_t **, Abc_Ntk_t *)pSol[ABC_EXACT_SOL_NVARS] == nVarspSol[ABC_EXACT_SOL_NFUNC] == 1pFanins[i]*p == 2!Abc_ExactBuildNode( pTruth, 4, pArrTimeProfile, pFanins, pNtk )void Abc_ExactStoreTest(int)Abc_ExactDelayCost( pTruth, 4, pArrTimeProfile, pPerm, &Cost, 12 ) == 1cannot open file "%s" for writing nBits >= 0 && nBits <= nWords * 64void Abc_TtMask(word *, int, int)nBits >= 0 && nBits <= 64word Abc_Tt6Mask(int)iVar < 8int Abc_TtIsTopDecomposable(word *, word *, int, int)find optimum circuit for %d %d-variable functions: func %d: max depth = %d arrival times =try with %d gates create variables for network with %d functions over %d variables and %d/%d gates i < pSes->nGatesint Ses_ManSelectVar(Ses_Man_t *, int, int, int)k < pSes->nSpecVars + iint Ses_ManDepthVar(Ses_Man_t *, int, int)j <= pSes->nArrTimeMax + ih < pSes->nSpecFuncint Ses_ManOutputVar(Ses_Man_t *, int, int)SAT CL: %7d VA: %5d RE: %2d ST: %4.f CO: %7.0f DE: %6.0f PR: %6.0f func: %d int Ses_ManCreateClauses(Ses_Man_t *)variables %d and %d are symmetric int Ses_ManSimVar(Ses_Man_t *, int, int)t < pSes->nRowsvoid Vec_IntGrowResize(Vec_Int_t *, int)int Ses_ManGateVar(Ses_Man_t *, int, int, int)p < 2q < 2p > 0 || q > 0add gate %d with operation %d and operands %d and %d and depth vector output %d points to gate %d and has normalized delay %d (nArrTimeDelta = %d) pin-to-pin arrival time from input %d is %d (pArrTimeProfile = %d) ( p - pSol ) == nSolchar *Ses_ManExtractSolution(Ses_Man_t *)give up due to impossible arrival time (depth = %d, input = %d, arrival time = %d)give up due to impossible decomposition (depth = %d, input = %d, arrival time = %d)nLevel == Vec_IntSize( pSes->vStairDecVars )int Ses_CheckDepthConsistency(Ses_Man_t *)give up due to impossible decomposition at level %dgive up due to impossible stair decomposition at level %d: give up due to impossible decomposition at second level (depth = %d, input = %d, arrival time = %d)give up due to impossible decomposition at third level (depth = %d, input = %d, arrival time = %d) (%d/%d)give up due to impossible depth (depth = %d, gates = %d)give up due to impossible depth and arrival times (depth = %d, gates = %d)give up due to impossible depth in AND-dec structure (depth = %d, gates = %d)give up due to impossible number of gatesword *Ses_ManDeriveTruth(Ses_Man_t *, char *, int)*p++ == 2Abc_Lit2Var( *p ) == nGates - 1Abc_Ntk_t *Ses_ManExtractNtk(const char *)ALL p[1] == 2Gia_Man_t *Ses_ManExtractGia(const char *)( *p >> 2 ) & 1cannot open file "%s" for reading read %lu entries from file void Abc_TtPrintHexRev(FILE *, word *, int)abc -c "exact -v -C %d -S %d -D %d -A" # no solution found before Ses_ManExtractSolution(): Network check has failed.BMS manager already startedBMS manager has not been started 0 1 2 3 4 5 6 7 8 total-------------------------------------------------------------------------------------------------------------------------------Runtime breakdown:resource limit reachedsrc/base/abci/abcExtract.cVec_Wrd_t *Abc_NtkShareSuperXor(Abc_Obj_t *, int *, int *)Abc_NodeIsExorType(pObj)Num < NumNextpObj1 == Abc_ObjNot(pObj0)Num <= NumNextVec_Wrd_t *Abc_NtkShareSuperAnd(Abc_Obj_t *, int *)Abc_ObjIsNode(pRoot)Abc_ObjIsNode(Abc_ObjRegular(pObj0)) || Abc_ObjIsCi(Abc_ObjRegular(pObj0))Abc_ObjIsNode(Abc_ObjRegular(pObj1)) || Abc_ObjIsCi(Abc_ObjRegular(pObj1))void Abc_NtkTraverseSupersXor_rec(Abc_ShaMan_t *, Abc_Obj_t *, Vec_Ptr_t *)void Abc_NtkTraverseSupersAnd_rec(Abc_ShaMan_t *, Abc_Obj_t *, Vec_Ptr_t *)p->vBuckets == NULLvoid Abc_NtkTraverseSupers(Abc_ShaMan_t *, int)ObjId < Vec_IntSize(p->vObj2Lit)void Abc_NtkSharePrint(Abc_ShaMan_t *)%4d%3d: %s %d=%d Total = %d. Gates = %d. Bucket contents: multi_and.blif.model %s multi_and o%d.names o%d .end !fAnd || !Abc_LitIsCompl(iLit)Abc_Ntk_t *Abc_NtkUpdateNetwork(Abc_ShaMan_t *, int)Total gates collected = %d. Total gates constructed = %d. Abc_Ntk_t *Abc_NtkShareXor(Abc_Ntk_t *, int, int, int)void Vec_WrdGrow(Vec_Wrd_t *, int)word Vec_WrdEntry(Vec_Wrd_t *, int)int Vec_WrdRemove(Vec_Wrd_t *, word)void Vec_WrdWriteEntry(Vec_Wrd_t *, int, word)void Vec_WrdShrink(Vec_Wrd_t *, int)Cannot open output file.src/base/abci/abcFraig.cvoid *Abc_NtkToFraig(Abc_Ntk_t *, void *, int, int)pObj->pCopy != NULLFraig_Node_t *Abc_NtkToFraigExdc(Fraig_Man_t *, Abc_Ntk_t *, Abc_Ntk_t *)Warning: The resulting AIG contains %d choice nodes. nPoFinal % nStored == 0void Abc_NtkFraigStoreCheck(Abc_Ntk_t *)Verification for PO #%d of network #%d has failed. The PO function is not used. pNtk->pExdcvoid Abc_NtkFraigRemapUsingExdc(Fraig_Man_t *, Abc_Ntk_t *)Fraig_NodeReadData1(pNodeTemp) == NULLAbc_Obj_t *Abc_NodeFromFraig_rec(Abc_Ntk_t *, Fraig_Node_t *)pResCur*ppTail == NULLAbc_Ntk_t *Abc_NtkFromFraig2(Fraig_Man_t *, Abc_Ntk_t *)void Abc_NtkFromFraig2_rec(Abc_Ntk_t *, Abc_Obj_t *, Vec_Ptr_t *)void Abc_NtkFraigTrustOne(Abc_Ntk_t *, Abc_Ntk_t *)pObj->pCopy == NULLAbc_Obj_t *Abc_NodeFraigTrust(Abc_Ntk_t *, Abc_Obj_t *)nFanins == Abc_SopGetVarNum((char *)pNode->pData)Abc_SopIsOrType((char *)pNode->pData)Abc_NtkFraig: The network check has failed.Warning: Networks has no EXDC.Abc_NtkFraigTrust: Trust mode works for netlists and logic SOP networks.Abc_NtkFraigTrust: The network does not look like an AIG with choice nodes.Abc_NtkFraigTrust: The network check has failed.Trying to store the network with different primary inputs.The previously stored networks are deleted and this one is added.Abc_NtkFraigStore: Initial strashing has failed.There are no network currently in storage.MbP?H}Msrc/base/abci/abcFx.cVec_Wec_t *Abc_NtkFxRetrieve(Abc_Ntk_t *)void Abc_NtkFxInsert(Abc_Ntk_t *, Vec_Wec_t *)Vec_IntSize(vCube) > 0Lit <= Vec_IntEntry(vCube, 0)i == (int)Abc_ObjId(pNode)Vec_IntEntry(vCount, i) > 0Vec_IntEntry( vCube, 0 ) == iiFanin >= 0 && iFanin < Abc_ObjFaninNum(pNode)int Abc_NtkFxPerform(Abc_Ntk_t *, int, int, int, int, int)!Abc_LitIsCompl(Vec_IntEntry(vCubeFree, 0))int Fx_ManDivFindCubeFree(Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, int *)void Fx_ManCreateLiterals(Fx_Man_t *, int)p->nVars < nVarsLit < Lit2int Fx_ManCubeSingleCubeDivisors(Fx_Man_t *, Vec_Int_t *, int, int)iDiv < Vec_FltSize(p->vWeights)void Fx_ManCubeDoubleCubeDivisors(Fx_Man_t *, int, Vec_Int_t *, int, int, int *)p->pHash == NULLvoid Fx_ManCreateDivisors(Fx_Man_t *)p->nDivsS == Vec_FltSize(p->vWeights)Diff > 0.0 && Diff < 1.0void Fx_ManUpdate(Fx_Man_t *, int, int *)Lit0 >= 0 && Lit1 >= 0Vec_IntSize(p->vVarCube) == iVarNewVec_IntSize(p->vLevels) == iVarNewRetValue == 2Vec_IntSize(p->vCubesD) % 2 == 0Vec_IntSize(p->vCubesD) == 2 * Vec_IntSize(p->vCompls)RetValue == Vec_IntSize(vDiv) || RetValue == Vec_IntSize( vDiv ) + 1k == Vec_IntSize(p->vCubesD) / 2void Vec_FltAddToEntry(Vec_Flt_t *, int, float)./src/misc/vec/vecQue.hp->pOrder[v] != -1int Vec_QueMoveUp(Vec_Que_t *, int)p->pHeap[i] == vchild < p->nSizevoid Vec_QueMoveDown(Vec_Que_t *, int)p->nSize < p->nCapvoid Vec_QuePush(Vec_Que_t *, int)p->pOrder[v] == -1p->pHeap[p->nSize] == -1p->pArray <= vLevel && vLevel < p->pArray + p->nSizeint Vec_WecLevelId(Vec_Wec_t *, Vec_Int_t *)Vec_IntSize(vCubeFree) == 4int Fx_ManDivNormalize(Vec_Int_t *)Abc_LitIsCompl(L[1]) == Abc_LitIsCompl(L[3])Abc_LitIsCompl(L[0]) == Abc_LitIsCompl(L[3])Abc_LitIsCompl(L[1]) == Abc_LitIsCompl(L[2])LitA0 == Abc_LitNot(LitB0)!Abc_LitIsCompl(LitA0)!Vec_WecIntHasMark( vCube )void Vec_WecMarkLevels(Vec_Wec_t *, Vec_Int_t *)void Vec_WecUnmarkLevels(Vec_Wec_t *, Vec_Int_t *)Vec_IntSize(vCube2) == 3void Fx_ManDivAddLits(Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)!fCompl || Vec_IntSize(vDiv) == 4int Fx_ManDivRemoveLits(Vec_Int_t *, Vec_Int_t *, int)Cubes =%8d Lits =%8d Divs =%8d Divs+ =%8d Compl =%8d Extr =%7d int Vec_QueSize(Vec_Que_t *)Div %7d : Weight %12.5f Divs =%8d %d(1) + %d(2)void Vec_WecShrink(Vec_Wec_t *, int)QThe network is unchanged by fast extract.Abc_NtkFastExtract: Nodes have duplicated fanins. FX is not performed.Abc_NtkFxPerform: The network check has failed.The SOP has duplicated cubes.@B N0usrc/base/abci/abcFxu.cint Abc_NtkFastExtract(Abc_Ntk_t *, Fxu_Data_t *)p->vFanins->nSize < p->vFaninsNew->nSizevoid Abc_NtkFxuReconstruct(Abc_Ntk_t *, Fxu_Data_t *)i == (int)pNode->IdpNode->pData != NULLAbc_NtkFastExtract(): Converting to SOPs has failed.Abc_NtkFastExtract: Nodes have duplicated or complemented fanins. FXU is not performed.Warning: The network has not been changed by "fx".Abc_NtkFastExtract: The network check has failed..model FA .inputs a b cin .outputs s cout 1-1 1 .names a b and1 .names a b and1_ .names and1 and1_ xor .names cin xor and2 .names cin xor and2_ .names and2 and2_ s .names and1 and2 cout src/base/abci/abcGen.cvoid Abc_WriteAdder(FILE *, int).model ADD%d a%0*d b%0*d s%0*d.names c .subckt FA a=a0 b=b0 cin=c s=y0 cout=s1 .subckt FA a=a%0*d b=b%0*d cin=c s=s%0*d cout=%0*d .subckt FA a=a%0*d b=b%0*d cin=%0*d s=s%0*d cout=%0*d .subckt FA a=a%0*d b=b%0*d cin=%0*d s=s%0*d cout=s%0*d void Abc_GenAdder(char *, int)# %d-bit ripple-carry adder generated by ABC on %s void Abc_WriteMulti(FILE *, int).model Multi%d m%0*d.names x%0*d_%0*d .names b%0*d a%0*d y%0*d_%0*d 11 1 .names y%0*d_%0*d .subckt ADD%d a%0*d=x%0*d_%0*d b%0*d=y%0*d_%0*d s%0*d=x%0*d_%0*d.names x%0*d_%0*d m%0*d 1 1 void Abc_GenMulti(char *, int)# %d-bit multiplier generated by ABC on %s .model Comp .inputs a b .outputs x y .names a b x .names a b y .model Layer%d x%02d y%02d.names x00 y00 .subckt Comp a=x%02d b=x%02d x=y%02d y=y%02d .names x%02d y%02d nVars > 1void Abc_GenSorter(char *, int)# %d-bit sorter generated by ABC on %s .model Sorter%02d .subckt Comp a=x00 b=x01 x=y00 y=y01 .subckt Layer0 x%02d=x%02d y%02d=%0*d.subckt Layer%d x%02d=%0*d y%02d=y%02d.model cell .inputs px1 px2 py1 py2 x y .outputs fx fy .names x y a .names px1 a x nx .names py1 a y ny .names px2 nx fx .names py2 ny fy void Abc_GenMesh(char *, int)# %dx%d mesh generated by ABC on %s .model mesh%d p%d%dx1 p%d%dx2 p%d%dy1 p%d%dy2 v%02d v%02d fx00.subckt cell px1=p%d%dx1 px2=p%d%dx2 py1=p%d%dy1 py2=p%d%dy2 x=v%02d x=fx%d%d y=v%02d y=fy%d%d fx=fx%d%d fy=fy%d%d.model lut%d p%02d.outputs o .names n01 o .names i%d p%02d p%02d n%02d .names i%d n%02d n%02d n%02d void Abc_GenFpga(char *, int, int, int)# Structure with %d %d-LUTs for %d-var function generated by ABC on %s .model struct%dx%d_%d pl%02d pv%02d.names Gnd .names v%02d func out 00 1 11 1 func .subckt lut%d p%02d=pl%02d i%d=s%02d o=v%02d p%02d=v%02d p%02d=Gnd i%d=pv%02d o=s%02d# One-hotness condition for %d vars generated by ABC on %s .model 1hot_%dvars i%0*d o%0*d.names i%0*d i%0*d o%0*d # One-hotness with %d vars and %d regs generated by ABC on %s # Used %d intervals of 1-hot registers: { .model 1hot_%dvars_%dregs Counter == Counter2void Abc_GenOneHotIntervals(char *, int, int, Vec_Ptr_t *)# Random function with %d inputs generated by ABC on %s .model rand%d .outputs f # This random FSM was generated by ABC on %s # Command line was: "genfsm -I %d -O %d -S %d -L %d -P %d -Q %d %s" # FSM has %d inputs, %d outputs, %d states, and %d products .i %d .o %d .p %d .s %d %0*d .enArgs > 1 && nBits > 1void Abc_AdderTree(FILE *, int, int)module adder_tree_%d_%d ( i%0*d_%0*d, z input i%0*d_%0*d%s output [%d:0] z; wire [%d:0] t%d = { }; wire [%d:0] s%d = t%d + %s%d; assign z = s%d; // %d-argument %d-bit adder-tree generated by ABC on %s booth.names pp%0*d .names a%0*d pp%0*d 1 1 .names b%0*d pp%0*d 1 1 void Abc_WriteBoothPartialProducts(FILE *, int).names pp%0*d y%0*d_%0*d %d 1 .names pp%0*d pp%0*d pp%0*d %d%d 1 void Abc_WriteBooth(FILE *, int)void Abc_GenBooth(char *, int)# %d-bit signed Booth multiplier generated by ABC on %s ./src/aig/miniaig/miniaig.hId >= 0 && 2*Id < p->nSizeint Mini_AigNodeFanin0(Mini_Aig_t *, int)p->pArray[2*Id] == 0x7FFFFFFF || p->pArray[2*Id] < 2*Idint Mini_AigNodeFanin1(Mini_Aig_t *, int)p->pArray[2*Id+1] == 0x7FFFFFFF || p->pArray[2*Id+1] < 2*IdpRepr->pData == NULLsrc/base/abci/abcHaig.cVec_Ptr_t *Abc_NtkHaigCreateClasses(Vec_Ptr_t *)((Hop_Obj_t *)pObj->pData)->Id <= pObj->IdpRepr->pData == pReprThe number of class members with fanouts = %5d. int Abc_NtkHaigCheckTfi_rec(Abc_Obj_t *, Abc_Obj_t *)int Abc_NtkHaigCheckTfi(Abc_Ntk_t *, Abc_Obj_t *, Abc_Obj_t *)!Abc_ObjIsComplement(pNew)p->nCreated == Vec_PtrSize(p->vObjs)Abc_Ntk_t *Abc_NtkHaigRecreateAig(Abc_Ntk_t *, Hop_Man_t *)!Hop_IsComplement(pObj->pNext)pObjAbcThis->pData == NULLAbc_ObjFanoutNum(pObjAbcThis) == 0pObjAbcRepr != pObjAbcThisCollected %6d class members. Collected %6d classes. (Ave = %5.2f) pObj->pData == pReprint Abc_NtkHaigResetReprs(Hop_Man_t *)pRepr->Id <= pObj->IdpObj->pNext != NULLHop_Obj_t *Hop_ObjReprHop(Hop_Obj_t *)Abc_NtkHaigReconstruct: Check for History AIG has failed.Abc_NtkHaigUse: The network check has failed.>(kn(kn(kn(knpIfMan->vSwitching == NULLsrc/base/abci/abcIf.cvoid If_ManComputeSwitching(If_Man_t *)Vec_IntSize(vCopy) == If_ManObjNum(pIfMan)Computing switching activityAbc_Ntk_t *Abc_NtkIf(Abc_Ntk_t *, If_Par_t *)pPars->nLutSize <= If_DsdManVarNum(p)(pPars->pLutStruct == NULL && If_DsdManLutSize(p) == 0) || (pPars->pLutStruct && pPars->pLutStruct[0] - '0' == If_DsdManLutSize(p))If_Man_t *Abc_NtkToIf(Abc_Ntk_t *, If_Par_t *)Warning: The mapper will allocate %.1f GB for to represent the subject graph with %d AIG nodes. InitialIf_ObjId(Abc_ObjIfCopy(pNode)) > If_ObjId(Abc_ObjIfCopy(Abc_ObjEquiv(pNode)))Vec_IntSize(vAig) > 0Hop_Obj_t *Abc_NodeBuildFromMiniInt(Hop_Man_t *, Vec_Int_t *, int)Vec_IntEntryLast(vAig) < 2nLeaves == 0Vec_IntEntry(vAig, 0) == 0Vec_IntSize(vAig) & 1i == Vec_IntSize(vAig) - 1Delay >= 0Hop_Obj_t *Abc_NodeBuildFromMini(Hop_Man_t *, If_Man_t *, If_Cut_t *, int)pIfObj->Type == IF_ANDAbc_Obj_t *Abc_NodeFromIf_rec(Abc_Ntk_t *, If_Man_t *, If_Obj_t *, Vec_Int_t *)RetValue == 0If_CutData(pCut) == NULLHop_Obj_t *Abc_NodeIfToHop_rec(Hop_Man_t *, If_Man_t *, If_Obj_t *, Vec_Ptr_t *)FinalAdded %d buffers/inverters to decouple the CO drivers. Duplicated %d gates to decouple the CO drivers. pCut->iCutFunc >= 0./src/map/if/if.hword *If_CutTruthW(If_Man_t *, If_Cut_t *)i >= 0 && i < p->nEntries./src/misc/vec/vecMem.hword *Vec_MemReadEntry(Vec_Mem_t *, int)Hop_Obj_t *Abc_NodeIfToHop(Hop_Man_t *, If_Man_t *, If_Obj_t *)Abc_NtkIf: The network check has failed.The AIG-node delay is not set. Assuming unit-delay.Abc_NodeIfToHop(): Computing local AIG has failed.Delay1 > 0src/base/abci/abcIfif.cfloat Abc_ObjDelay1(Abc_IffMan_t *, Abc_Obj_t *)d >= 0 && d <= p->pPars->nDegreefloat Abc_ObjDelayDegree(Abc_IffMan_t *, Abc_Obj_t *, int)pPars->pLutLib->LutMax >= 0 && pPars->pLutLib->LutMax <= IFIF_MAX_LEAVESvoid Abc_NtkPerformIfif(Abc_Ntk_t *, Ifif_Par_t *)pPars->nLutSize >= 0 && pPars->nLutSize <= IFIF_MAX_LEAVESpPars->nDegree >= 0 && pPars->nDegree <= IFIF_MAX_LEAVESPin+Wire: { %3.2f } Wire %3.2f Degree %d Type: %s CascadeClusterNode %3d : Lev =%3d Del%d =%4.2f Critical delay %5.2f. Critical outputs %5.2f %% i >= 0 && i < p->nObjsAbc_IffObj_t *Abc_IffObj(Abc_IffMan_t *, int)Running mapper into LUT structures with the following parameters:%d, // %3d 0x%02X Total number of MUXes = %d. src/base/abci/abcIvy.cIvy_Man_t *Abc_NtkIvyBefore(Abc_Ntk_t *, int, int)Warning: The network has %d self-feeding latches. Warning: AIG cleanup removed %d nodes (this is not a bug). int Abc_NtkIvyProve(Abc_Ntk_t **, void *)cecmiter.aigIntermediate reduced miter is written into file "%s". Attempting BDDs with node limit %d ... Abc_Ntk_t *Abc_NtkIvy(Abc_Ntk_t *)Warning: The network has %d self-feeding latches. Quitting. Abc_NtkFromIvy(): Network check has failed. Abc_Ntk_t *Abc_NtkFromIvySeq(Abc_Ntk_t *, Ivy_Man_t *, int)!Ivy_IsComplement(pNode->pEquiv)Abc_NtkHasSop(pNtkOld) || Abc_NtkIsStrash(pNtkOld)Ivy_Man_t *Abc_NtkToIvy(Abc_Ntk_t *)Ivy_Obj_t *Abc_NodeStrashAig(Ivy_Man_t *, Abc_Obj_t *)nFanins == Abc_SopGetVarNum(pSop)Ivy_Obj_t *Abc_NodeStrashAigSopAig(Ivy_Man_t *, Abc_Obj_t *, char *)Vec_Int_t *Abc_NtkCollectLatchValuesIvy(Abc_Ntk_t *, int)Abc_NtkIvyBefore(): Converting to SOPs has failed.AIG check has failed.Warning: The choice nodes in the initial AIG are removed by strashing.Abc_NtkIvy(): Converting to SOPs has failed.Cannot open log file for writing "%s". snl_UNSATsnl_SATsnl_UNKpCex->nBits - pCex->nRegs == pCex->nPis * (pCex->iFrame + 1)src/base/abci/abcLog.cvoid Abc_NtkWriteLogFile(char *, Abc_Cex_t *, int, int, char *)Cannot open log file for reading "%s". Vec_IntSize(vNums) == pCex->nBitsint Abc_NtkReadLogFile(char *, Abc_Cex_t **, int *)Abc_NtkWriteLogFile(): Cannot recognize solving status.Incorrect number of bits.Cannot read counter example.Cannot read register number.Unrecognized status.src/base/abci/abcLut.cint Abc_NtkSuperChoiceLut(Abc_Ntk_t *, int, int, int)LUT size (%d) does not belong to the interval: 3 <= LUT size <= %d Cut size (%d) does not belong to the interval: LUT size (%d) < Cut size <= %d Try = %d. Dec = %d. Exist = %d. Use = %d. SUPER = %d levels of %d-LUTs. void Abc_NodeSuperChoiceCollect2_rec(Abc_Obj_t *, Vec_Ptr_t *)void Abc_NodeSuperChoiceCollect_rec(Abc_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *)Vec_PtrSize(vLeaves) == nLeavesvoid Abc_NodeSuperChoiceCollect(Abc_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *)nLutSize < nVarsvoid Abc_NodeDecomposeSort(Abc_Obj_t **, int, int *, int)nVars <= SCL_VARS_MAXpCut != NULLvoid Abc_NodeLutMap(Cut_Man_t *, Abc_Obj_t *)pObj->Level < LARGE_LEVELVec_PtrEntryLast(p->vVolume) == pObjAbc_Obj_t *Abc_NodeSuperChoiceLut(Abc_ManScl_t *, Abc_Obj_t *)nSuppVars <= nVarsi < nVarsint Abc_NodeDecomposeStep(Abc_ManScl_t *)((Abc_Obj_t *)Vec_PtrEntry(p->vLeaves, p->pBSet[0]))->Level <= ((Abc_Obj_t *)Vec_PtrEntry(p->vLeaves, p->pBSet[1]))->Levelc == (2 << p->nLutSize)nVarsNew < p->nLutSize!Extra_TruthVarInSupport( p->uTruth, nVars, nVars - p->nLutSize + nVarsNew )Abc_NtkSuperChoiceLut: The network check has failed.Abc_ObjIsNode(pObj) && Abc_ObjIsNode(pPivot)src/base/abci/abcLutmin.cint Abc_ObjCheckAbsorb(Abc_Obj_t *, Abc_Obj_t *, int, Vec_Ptr_t *)Absorted = %6d. (%6.2f %%) Fully = %6d. (%6.2f %%) Level > 0 && Level < 10Vec_Ptr_t *Abc_NtkBddCofactors(DdManager *, DdNode *, int)Abc_ObjFaninNum(pNode) > LevelAbc_Obj_t *Abc_NtkCreateCofLut(Abc_Ntk_t *, DdManager *, DdNode *, Abc_Obj_t *, int)nBits + 2 <= nLutSizeAbc_Obj_t *Abc_NtkBddCurtis(Abc_Ntk_t *, Abc_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *)nLutSize < Abc_ObjFaninNum(pNode)u < Vec_PtrSize(vUniq)Abc_ObjFaninNum(pNode) == nLutSize + 1Abc_Obj_t *Abc_NtkBddFindCofactor(Abc_Ntk_t *, Abc_Obj_t *, int)i == Cudd_ReadPerm(ddOld, i)iFreeVar != iCof && iFreeVar < Abc_ObjFaninNum(pNode)Abc_ObjFaninNum(pNode) > nLutSizeAbc_Obj_t *Abc_NtkBddDecompose(Abc_Ntk_t *, Abc_Obj_t *, int, int)Decomposing %d-input node %d using MUX. Decomposing %d-input node %d using cofactoring with %d cofactors. Decomposing %d-input node %d using Curtis with %d unique columns. The LUT count (%d) should be at least 4. The LUT count (%d) should not exceed 6. *** Iteration %d: Decomposing network with %d nodes and %d max fanin count for K = %d. Abc_NtkLutmin: The network check has failed.zDsrc/base/abci/abcMap.cAbc_Ntk_t *Abc_NtkMap(Abc_Ntk_t *, double, double, double, float, float, float, int, int, int, int, int, int, int)The cell areas are multiplied by the factor: ^ (%.2f). The cell delays are multiplied by the factor: ^ (%.2f). Converting "%s" into supergate library "%s". .superAbc_Ntk_t *Abc_NtkSuperChoice(Abc_Ntk_t *)Abc_NtkHasMapping(pNode->pNtk)Abc_Obj_t *Abc_NtkFetchTwinNode(Abc_Obj_t *)Vec_Int_t *Abc_NtkWriteMiniMapping(Abc_Ntk_t *)Vec_StrSize(vGates) % 4 == 0Mapped network has %d CIs, %d COs, %d gates, and %d flops. The first %d object IDs (from 0 to %d) are reserved for the CIs. Node %d has fanins {CO %d is driven by node %d Node %d has gate "%s" Array has size %d ints. Map_Man_t *Abc_NtkToMap(Abc_Ntk_t *, double, int, float *, int)pNode->pCopy == NULLMap_ManReadBufNum(pMan) == pNtk->nBarBufsAbc_Ntk_t *Abc_NtkFromMap(Map_Man_t *, Abc_Ntk_t *, int)Error creating mapped network: Library does not have a constant %d gate. Map_NodeReadCutBest(pNodeMap, !fPhase) != NULL || Map_NodeIsConst(pNodeMap)Abc_Obj_t *Abc_NodeFromMap_rec(Abc_Ntk_t *, Map_Node_t *, int)Map_NodeReadCutBest(pNodeMap, fPhase) != NULL || Map_NodeIsConst(pNodeMap)Abc_Obj_t *Abc_NodeFromMapPhase_rec(Abc_Ntk_t *, Map_Node_t *, int)pNodePIs[i] != NULLvoid Abc_NodeFromMapCutPhase(Abc_Ntk_t *, Map_Cut_t *, int)Abc_NtkMap(): Genlib library has profile.Abc_NtkMap: The network check has failed.Performing mapping with choices.Abc_NtkFromMapSuperChoice(): Converting to SOPs has failed.Current network in ABC framework is not mapped.CI index is not valid.CO index is not valid.Current network in ABC framework is not defined.ABC framework is not initialized by calling Abc_Start()pPars->nMaxDistance > 0src/base/abci/abcMerge.cvoid Abc_NtkCollectNonOverlapCands(Abc_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *, Nwk_LMPars_t *)Node %6d : Fanins = %d. Fanouts = %3d. Cand1 = %3d. Cand2 = %3d. Mergable LUTs = %6d. Total cands = %6d. Deriving graphGRAPH: Nodes = %6d. Edges = %6d. Pairs = %6d. Solving@@ ``00 Vec_PtrSize(vNodes) == Abc_NtkNodeNum(pNtk)src/base/abci/abcMfs.cVec_Ptr_t *Abc_NtkAssignIDs2(Abc_Ntk_t *)nFirstFixed >= 0 && nFirstFixed < Abc_NtkNodeNum(pNtk)Sfm_Ntk_t *Abc_NtkExtractMfs(Abc_Ntk_t *, int)Abc_SopGetVarNum((char *)pNode->pData) == Vec_IntSize(vArray)void Abc_NtkInsertMfs(Abc_Ntk_t *, Sfm_Ntk_t *)int Abc_NtkPerformMfs(Abc_Ntk_t *, Sfm_Par_t *)Currently "mfs" cannot process the network containing nodes with more than 15 fanins. The network has %d nodes changed by "mfs". nFramesAdd >= 0Abc_Ntk_t *Abc_NtkUnrollAndDrop(Abc_Ntk_t *, int, int, Vec_Int_t *, int *)Vec_IntSize(vFlops) == Abc_NtkLatchNum(p)void Abc_NtkReinsertNodes(Abc_Ntk_t *, Abc_Ntk_t *, int)Abc_NtkCiNum(p) <= Abc_NtkCiNum(pNtk)Vec_PtrSize(vNodes) + Abc_NtkCiNum(p) + Abc_NtkPoNum(p) == iPivotpNodeNew->pCopy == pNodeint Abc_NtkMfsAfterICheck(Abc_Ntk_t *, int, int, Vec_Int_t *, Sfm_Par_t *)unroll_dump.blifConversion to SOP has failed due to low resource limit.src/base/abci/abcMini.cAbc_Ntk_t *Abc_NtkFromMiniAig(Mini_Aig_t *)Vec_IntSize(vCopies) == nNodesAbc_NtkFromMini(): Network check has failed. Mini_Aig_t *Abc_NtkToMiniAig(Abc_Ntk_t *)miniaig.datap->nSize < MINI_AIG_NULL/4void Mini_AigPush(Mini_Aig_t *, int, int)void Mini_AigGrow(Mini_Aig_t *, int)Lit0 >= 0 && Lit0 < Litint Mini_AigAnd(Mini_Aig_t *, int, int)Lit1 >= 0 && Lit1 < Litint Mini_AigCreatePo(Mini_Aig_t *, int)Cannot open file for writing "%s". PI = %d. PO = %d. Node = %d. Cannot open file for reading "%s". src/base/abci/abcMiter.cAbc_Ntk_t *Abc_NtkMiter(Abc_Ntk_t *, Abc_Ntk_t *, int, int, int, int)Abc_Ntk_t *Abc_NtkMiterAnd(Abc_Ntk_t *, Abc_Ntk_t *, int, int)1 == Abc_NtkCoNum(pNtk1)1 == Abc_NtkCoNum(pNtk2)0 == Abc_NtkLatchNum(pNtk1)0 == Abc_NtkLatchNum(pNtk2)Abc_Ntk_t *Abc_NtkMiterCofactor(Abc_Ntk_t *, Vec_Int_t *)1 == Abc_NtkCoNum(pNtk)Abc_Ntk_t *Abc_NtkMiterForCofactors(Abc_Ntk_t *, int, int, int)Out < Abc_NtkCoNum(pNtk)In1 < Abc_NtkCiNum(pNtk)In2 < Abc_NtkCiNum(pNtk)Abc_Ntk_t *Abc_NtkMiterQuantify(Abc_Ntk_t *, int, int)In < Abc_NtkCiNum(pNtk)Abc_Ntk_t *Abc_NtkMiterQuantifyPis(Abc_Ntk_t *)Abc_NtkIsStrash(pMiter)int Abc_NtkMiterIsConstant(Abc_Ntk_t *)Abc_ObjRegular(pChild) == Abc_AigConst1(pMiter)Output #%2d : Abc_Ntk_t *Abc_NtkFrames(Abc_Ntk_t *, int, int, int)%s_%d_framesWarning: %d uninitialized latches are replaced by free PI variables. int Abc_NtkDemiter(Abc_Ntk_t *)Abc_NtkPoNum(pNtk) == 1Abc_ObjRegular(pNodeA) == Abc_ObjRegular(pNodeB)addOut1addOut2First cone = %6d. Second cone = %6d. Common = %6d. int Abc_NtkCombinePos(Abc_Ntk_t *, int, int)Abc_NtkPoNum(pNtk) == 0Vec_Ptr_t *Abc_NtkTryNewMiter(char *, char *)status != l_UndefOutput %3d (out of %3d) is SAT. Cannot open node list "%s". Abc_Ntk_t *Abc_NtkSpecialMiter(Abc_Ntk_t *, Vec_Ptr_t *)pi_%s_%d_copymiter_outputAbc_Ntk_t *Abc_NtkMiterInt(Abc_Ntk_t *, Abc_Ntk_t *, int, int, int, int)nPartSize == 0 || fMulti == 0void Abc_NtkMiterFinalize(Abc_Ntk_t *, Abc_Ntk_t *, Abc_Ntk_t *, int, int, int, int)Vec_PtrSize(vPairs) == 2 * Abc_NtkCoNum(pNtk1)miter_void Abc_NtkMiterAddOne(Abc_Ntk_t *, Abc_Ntk_t *)int Abc_LatchIsInit0(Abc_Obj_t *)Satisfiable.Unsatisfiable.Abc_NtkMiterAnd: The network check has failed.Abc_NtkMiterCofactor: The network check has failed.Abc_NtkMiter: The network check has failed.Satisfiable. (Constant 1).Abc_NtkFrames: The network check has failed.The root of the miter is not an EXOR gate.Abc_NtkDemiter: The network check has failed.Abc_NtkOrPos: The network check has failed.src/base/abci/abcMulti.cAbc_Ntk_t *Abc_NtkMulti(Abc_Ntk_t *, int, int, int, int, int, int)nThresh >= 0nFaninMax > 1int Abc_NtkMultiLimit_rec(Abc_Obj_t *, Vec_Ptr_t *, int, int, int)vCone->nSize == 0nNodes0 <= nFaninMaxAbc_ObjFanin(pNode,0)->fMarkA == 0Abc_ObjFanin(pNode,1)->fMarkA == 0void Abc_NtkMultiCone_rec(Abc_Obj_t *, Vec_Ptr_t *)Abc_Obj_t *Abc_NtkMulti_rec(Abc_Ntk_t *, Abc_Obj_t *)!Abc_AigNodeIsConst(pNodeOld)pNodeOld->fMarkADdNode *Abc_NtkMultiDeriveBdd(DdManager *, Abc_Obj_t *, Vec_Ptr_t *)DdNode *Abc_NtkMultiDeriveBdd_rec(DdManager *, Abc_Obj_t *, Vec_Ptr_t *)pNode->fMarkA == 0void Abc_NtkMultiSetBounds(Abc_Ntk_t *, int, int)vCone->nSize <= nFaninMaxvoid Abc_NtkMultiSetBoundsCnf(Abc_Ntk_t *)void Abc_NtkMultiSetBoundsMulti(Abc_Ntk_t *, int)void Abc_NtkMultiSetBoundsSimple(Abc_Ntk_t *)void Abc_NtkMultiSetBoundsFactor(Abc_Ntk_t *)Abc_NtkMulti: The network check has failed.Warning: The choice nodes in the AIG are removed by renoding.Abc_NtkDeriveFromBdd(): Network check has failed. Abc_NtkGlobalBdd(pNtk) == NULLsrc/base/abci/abcNtbdd.cvoid *Abc_NtkBuildGlobalBdds(Abc_Ntk_t *, int, int, int, int, int)The BDD before = %d. The BDD after = %d. void Abc_NtkBddToMuxesPerform(Abc_Ntk_t *, Abc_Ntk_t *)Abc_Obj_t *Abc_NodeBddToMuxes_rec(DdManager *, DdNode *, Abc_Ntk_t *, st__table *)int Abc_NtkBddToMuxesPerformGlo(Abc_Ntk_t *, Abc_Ntk_t *, int)DdNode *Abc_NodeGlobalBdds_rec(DdManager *, Abc_Obj_t *, int, int, ProgressBar *, int *, int)The number of live nodes reached %d. Abc_ObjGlobalBdd(pNode) == NULLAbc_NtkBddToMuxes: The network check has failed.Constructing global BDDs is aborted.;sRvRtRvuRgtR9wRwRvR Y0,AVxp->pFuncs[0] != NULLsrc/base/abci/abcNpn.cint Abc_TruthNpnCountUnique(Abc_TtStore_t *)int Abc_TruthNpnCountUniqueSort(Abc_TtStore_t *)void Abc_TruthNpnPrint(char *, unsigned int, int) %c = ( %c%s ) uniqifying exact NPN counting 1s Jake's hybrid fast Jake's hybrid good new hybrid fast new phase flipping new hier. matching new adap. matching adjustable algorithm (heuristic) adjustable algorithm (exact) new cost-aware exact algorithm p->nVars <= 16void Abc_TruthNpnPerform(Abc_TtStore_t *, int, int)Applying %-20s to %8d func%s of %2d vars... Classes =%9d _out.tt_out.txtThe resulting functions are written into file "%s". Unknown canonical form value (%d). %03d: %s p->pBins != NULLsrc/base/abci/abcNpnSave.cvoid Npn_ManResize(Npn_Man_t *)Counter == p->nEntriesp->nEntries < p->nBufferSizeNpn_Obj_t *Npn_ManAdd(Npn_Man_t *, word)Cannot open NPN function file "%s". Skipping token %s that does not look like a 16-digit hex number. pEntry->Count == 1void Npn_ManRead(Npn_Man_t *, char *)Removing old table with %d entries. Created new table with %d entries from file "%s". There is no table with entries. Dumped table with %d entries from file "%s". void Npn_ManSaveOne(unsigned int *, int)Creating new table with 0 entries. i < p->nBufferSizeNpn_Obj_t *Npn_ManObj(Npn_Man_t *, int)p->pBuffer < pObjint Npn_ManObjNum(Npn_Man_t *, Npn_Obj_t *)nVarsMax > 4 && nVarsMax < 16src/base/abci/abcOdc.cOdc_Man_t *Abc_NtkDontCareAlloc(int, int, int, int)nLevels > 0 && nLevels < 10Wins = %5d. Empty = %5d. SimsEmpty = %5d. QuantOver = %5d. WinsFinish = %5d. Ave DCs per window = %6.2f %%. Ave DCs per finished window = %6.2f %%. Cleaning Windowing Miter Simulation Quantifying Truth table Aborted void Abc_NtkDontCareWinCollectRoots_rec(Abc_Obj_t *, Vec_Ptr_t *)Abc_NodeIsTravIdCurrent(pObj)!Abc_NodeIsTravIdCurrent(p->pNode)void Abc_NtkDontCareWinCollectRoots(Odc_Man_t *)void *Abc_NtkDontCareTransfer_rec(Odc_Man_t *, Abc_Obj_t *, Abc_Obj_t *)!Odc_IsComplement(Lit)unsigned int Abc_NtkDontCareCofactors_rec(Odc_Man_t *, Odc_Lit_t, unsigned int)p->iRoot < 0xffffint Abc_NtkDontCareQuantify(Odc_Man_t *)Vec_PtrSize(p->vBranches) <= 32p->nObjs <= p->nObjsAlloc!Odc_IsComplement( Lit )void Abc_NtkDontCareTruthOne(Odc_Man_t *, Odc_Lit_t)!Odc_IsTerm( p, Lit )void Abc_NtkDontCareSimulate_rec(Odc_Man_t *, Odc_Lit_t)int Abc_NtkDontCareCompute(Odc_Man_t *, Abc_Obj_t *, Vec_Ptr_t *, unsigned int *)Vec_PtrSize(vLeaves) <= p->nVarsMaxLeaf = %2d Root = %2d Bran = %2d AIG = %5d i >= 0 && i < p->nPisOdc_Lit_t Odc_Var(Odc_Man_t *, int)iFan0 < iFan1Odc_Lit_t *Odc_HashLookup(Odc_Man_t *, Odc_Lit_t, Odc_Lit_t)p->nObjs < p->nObjsAllocOdc_Obj_t *Odc_ObjNew(Odc_Man_t *)!(Lit & 1) && (int)(Lit>>1) < p->nObjsOdc_Obj_t *Odc_Lit2Obj(Odc_Man_t *, Odc_Lit_t)Runtime stats of the ODC manager:=== Overflow! ===Simulation cutoff.Name "%s" is not a PI name. Cannot use this order. The number of names in the order (%d) is not the same as the number of PIs (%d). Vec_PtrSize(vSupp) == Abc_NtkCiNum(pNtk)src/base/abci/abcOrder.cvoid Abc_NtkChangeCiOrder(Abc_Ntk_t *, Vec_Ptr_t *, int)src/base/abci/abcPart.cchar *Supp_ManFetch(Supp_Man_t *, int)p->nFreeSize >= nSizeRealp->nOuts <= p->nOutsAllocSupp_One_t *Supp_ManMergeEntry(Supp_Man_t *, Supp_One_t *, Supp_One_t *, int)p->nOuts >= p1->nOutsp->nOuts >= p2->nOutsVec_Ptr_t *Abc_NtkDfsNatural(Abc_Ntk_t *)pPart0->nRefs > 0Vec_Ptr_t *Abc_NtkComputeSupportsSmart(Abc_Ntk_t *)pPart1->nRefs > 0Entry < nPisunsigned int *Abc_NtkSuppCharStart(Vec_Int_t *, int)void Abc_NtkSuppCharAdd(unsigned int *, Vec_Int_t *, int)%d=(%d,%d) Total = %d. Outputs = %d. vPart == NULLvoid Abc_NtkPartitionCompact(Vec_Ptr_t *, Vec_Ptr_t *, int)vPartSupp != NULLCompsCreated %d partitions. !Abc_ObjIsComplement(pObj->pNext)Hop_Man_t *Abc_NtkPartStartHop(Abc_Ntk_t *)Abc_Ntk_t *Abc_NtkPartStitchChoices(Abc_Ntk_t *, Vec_Ptr_t *)Abc_NtkIsStrash(pNtkTemp)Cannot find CI node %s in the original network. !Abc_ObjIsComplement(pObj->pCopy)Cannot find CO node %s in the original network. Abc_Ntk_t *Abc_NtkFraigPartitioned(Vec_Ptr_t *, void *)unset progressbarFraiging part %4d (out of %4d) PI = %5d. PO = %5d. And = %6d. Lev = %4d. void Abc_NtkFraigPartitionedTime(Abc_Ntk_t *, void *)Finished part %5d (out of %5d) Partitioned fraiging timepEntry->nOuts <= pEntry->nOutsAllocvoid Supp_ManRecycleEntry(Supp_Man_t *, Supp_One_t *)pEntry->nOuts >= pEntry->nOutsAlloc/2Abc_NtkPartStartHop: HOP manager check has failed.Abc_NtkPartStitchChoices: The network check has failed.|@ @0@@r@$@YSSSSW SS|S|S|S|S|S|S}S|S }S|S~S@A>_best.blifsrc/base/abci/abcPrint.cfloat Abc_NtkGetArea(Abc_Ntk_t *)XMA stats: Xor =%7d (%6.2f %%) Mux =%7d (%6.2f %%) And =%7d (%6.2f %%) Total =%7d%s%-30s:%s i/o =%5d/%5d(c=%d) net =%5d nd =%5d wbox =%3d bbox =%3d and =%7d (choice = %d) edge =%7d cube =%6d lit(sop) =%6d lit(fac) =%6d aig =%6d bdd =%6dvoid Abc_NtkPrintStats(Abc_Ntk_t *, int, int, int, int, int, int, int, int, int, int) area =%5.2f delay =%5.2f lev =%3d lev = %d buf = %d power =%7.2f glitch =%7.2f %% Currently computes glitching only for K-LUT networks with K <= 6. mem =%5.2f MBabcstats.txtPrimary inputs (%d): %d=%sPrimary outputs (%d):Latches (%d): %s(%s=%s)void Abc_NtkPrintLatch(FILE *, Abc_Ntk_t *)Init < 4Total latches = %5d. Init0 = %d. Init1 = %d. InitDC = %d. Const data = %d. Input support computationOutput support computationInput cone computationOutput cone computationThe distribution of %s and %s in the network: Number %s with %s %s with %s Repr1 Repr2 %12s fUseFanio + fUsePio + fUseSupp + fUseCone == 1void Abc_NtkPrintFanio(FILE *, Abc_Ntk_t *, int, int, int, int)faninsfanoutsfaninfanoutI/Oinput supportsoutput supportsin-suppout-suppinput conesoutput conesin-coneout-coneThe distribution of fanins and fanouts in the network: Number Nodes with fanin Nodes with fanout %15d : %d - %d%15s : Fanins: Max = %d. Ave = %.2f. Fanouts: Max = %d. Ave = %.2f. Node %sFanins (%d): Fanouts (%d): void Abc_NtkPrintFactor(FILE *, Abc_Ntk_t *, int)Skipping the PI node. Skipping the latch. void Abc_NodePrintFactor(FILE *, Abc_Obj_t *, int)[%8.2f - %8.2f] : COs = %4d. %5.1f %% Level = %4d. COs = %4d. %5.1f %% void Abc_NtkPrintLevel(FILE *, Abc_Ntk_t *, int, int, int)CO %4d : %*s Primary input. Latch. Constant %d. Level = %3d. Mffc = %5d. Cone = %5d. %-*s Fanin = %2d Instance = %8d Area = %10.2f %6.2f %% %8d %8d %s %-*s Instance = %8d Area = %10.2f %6.2f %% AbsDiff = %d Const = %8d %6.2f %% Buffer = %8d %6.2f %% Inverter = %8d %6.2f %% And = %8d %6.2f %% Or = %8d %6.2f %% Other = %8d %6.2f %% TOTAL = %8d %6.2f %% (CO1,CO2)=NumShared : (%d,%d)=%d %5d %20s : Cone = %5d. Supp = %5d. (PIs = %5d. FFs = %5d.) Object %5d : NONE Const1 PI PO BI BO Net Node Latch WhiteboxBlackboxvoid Abc_ObjPrint(FILE *, Abc_Obj_t *) Fanins ( Miter: I =%6d N =%7d ? =%7d U =%6d S =%6d %7.2f sec The first satisfiable output is number %d (%s). %s = Const%d %s = %s%s float Abc_NtkMfsTotalGlitchingLut(Abc_Ntk_t *, int, int, int)Abc_NtkGetFaninMax(pNtk) <= 6(F0 & F1) == 0void Abc_Show6VarFunc(word, word) |Wrong length (%d) of 6-var truth table. int Abc_LatchIsInitDc(Abc_Obj_t *)Nodes by level:Abc_NtkPrintGates(): Converting to SOPs has failed.Statistics about sharing of logic nodes among the CO pairs.Structural support info:Actual support info:Abc_NtkMfsTotalGlitching() This procedure works only for mapped networks with LUTs size up to 6 inputs.src/base/abci/abcProve.cint Abc_NtkMiterProve(Abc_Ntk_t **, void *)RESOURCE LIMITS: Iterations = %d. Rewriting = %s. Fraiging = %s. Miter = %d (%3.1f). Rwr = %d (%3.1f). Fraig = %d (%3.1f). Last = %d. ITERATION %2d : Confs = %6d. FraigBTL = %3d. Rewriting FRAIGing BDD buildingAttempting SAT with conflict limit %d ... Nodes = %7d. Levels = %4d. Reached global limit on conflicts/inspects. Quitting.src/base/abci/abcQbf.cvoid Abc_NtkQbf(Abc_Ntk_t *, int, int, int, int)nPars > 0 && nPars < Abc_NtkPiNum(pNtk).qdimacsThe 2QBF formula was written into file "%s". Iter %2d : AIG = %6d SynParameters: Statistics: 0=%d 1=%d Solved after %d iterations. Quit after %d iterations. Implementation does not exist. Verification timed out.Synthesis timed out.src/base/abci/abcQuant.cint Abc_NtkQuantify(Abc_Ntk_t *, int, int, int)iVar < Abc_NtkCiNum(pNtk)Abc_Ntk_t *Abc_NtkTransRel(Abc_Ntk_t *, int, int)%s_TRAbc_NtkPiNum(pNtkNew) == Abc_NtkPiNum(pNtk) + 2*nLatchesAbc_Ntk_t *Abc_NtkInitialState(Abc_Ntk_t *)Abc_Ntk_t *Abc_NtkSwapVariables(Abc_Ntk_t *)Abc_NtkIsStrash(pNtkRel)Abc_Ntk_t *Abc_NtkReachability(Abc_Ntk_t *, int, int)Abc_NtkLatchNum(pNtkRel) == 0Abc_NtkPiNum(pNtkRel) % 2 == 0I = %3d : Reach = %6d Fr = %6d FrM = %6d %7.2f %% Reachability analysis stopped after %d iterations. Abc_NtkTransRel: The network check has failed.Abc_NtkReachability: The network check has failed.Fixed point is reached!Qsrc/base/abci/abcRec3.cVec_Wrd_t *Lms_GiaDelays(Gia_Man_t *)int Lms_ObjArea(Gia_Obj_t *)Vec_Str_t *Lms_GiaSuppSizes(Gia_Man_t *)Vec_StrSize(vSupps) == Gia_ManObjNum(p)A = %2d void Lms_GiaPrintSubgraph_rec(Gia_Man_t *, Gia_Obj_t *)void Lms_GiaPrintSubgraph(Gia_Man_t *, Gia_Obj_t *)nVars >= 6 && nVars <= LMS_VAR_MAXLms_Man_t *Lms_ManStart(Gia_Man_t *, int, int, int, int)recordIndex == Prev || Index == Prev + 1!p->fLibConstrvoid Lms_ManPrepare(Lms_Man_t *)p->vTruthPo == NULLVec_IntFindMin(p->vTruthIds) >= 0Vec_IntFindMax(p->vTruthIds) < Vec_MemEntryNum(p->vTtMem)p->vDelays == NULLp->vAreas == NULLp->vFreqs == NULLInputs = %2d. Funcs = %8d. Subgrs = %8d. Ratio = %6.2f. Cuts = %10d. Class = %10d (%6.2f %%). Status == -2void Lms_ManPrintFreqStats(Lms_Man_t *)NPN: Full = %6.2f %% Part = %6.2f %% None = %6.2f %% All: 1stp = %6.2f %% Comp = %6.2f %% Library with %d vars has %d classes and %d AIG subgraphs with %d AND nodes. Subgraphs tried = %10d. (%6.2f %%) Subgraphs filtered by support size = %10d. (%6.2f %%) Subgraphs filtered by structural redundancy = %10d. (%6.2f %%) Subgraphs filtered by volume = %10d. (%6.2f %%) Subgraphs filtered by TT redundancy = %10d. (%6.2f %%) Subgraphs filtered by error = %10d. (%6.2f %%) Subgraphs filtered by isomorphism = %10d. (%6.2f %%) Subgraphs added = %10d. (%6.2f %%) Functions added = %10d. (%6.2f %%) Cuts whose logic structure has a hole = %10d. (%6.2f %%) Runtime: Truth Runtime: Canon Runtime: Build Runtime: Check Runtime: InsertRuntime: Other Runtime: TOTAL The number of Library inputs (%d) differs from the number of Gia inputs (%d). void Abc_NtkRecLibMerge3(Gia_Man_t *)Vec_IntSize(pLib->vTtNodes) > 0Gia_ObjIsAnd(pTemp)Gia_ManCoNum(pGia) == Vec_IntSize(p->vTruthIds)p->nVars == (int)pCut->nLimitint Abc_NtkRecAddCut3(If_Man_t *, If_Obj_t *, If_Cut_t *)If_ObjIsAnd(pIfObj)int If_CutDelayRecCost3(If_Man_t *, If_Cut_t *, If_Obj_t *)pIfMan->pPars->fCutMin == 1Hop_Obj_t *Abc_RecToHop3(Hop_Man_t *, If_Man_t *, If_Cut_t *, If_Obj_t *)Abc_TtSuppOnlyOne(uSupport)Gia_WordCountOnes(uSupport) == nLeavesBestPo >= 0Gia_ObjIsAnd( Gia_ObjFanin0(pGiaPo) )Vec_IntSize(pGia->vTtNodes) > 0Gia_ObjIsAnd(pGiaTemp)int Abc_RecToGia3(Gia_Man_t *, If_Man_t *, If_Cut_t *, Vec_Int_t *, int)nLeaves == Vec_IntSize(vLeaves)Entry > 0Vec_Int_t *Lms_GiaCollectUsefulCos(Lms_Man_t *)*pPlace == -1D1 > 0Vec_Int_t *Lms_GiaFindNonRedundantCos(Lms_Man_t *)D2 > 0Gia_ObjIsAnd(Gia_ObjFanin0(pObj))void Lms_GiaNormalize(Lms_Man_t *)Prev <= NextpObj->fMark0 == 0Before normalizing: Library has %d classes and %d AIG subgraphs with %d AND nodes. After normalizing: Library has %d classes and %d AIG subgraphs with %d AND nodes. Normalization runtimes_pMan3 == NULLvoid Abc_NtkRecStart3(Gia_Man_t *, int, int, int, int)s_pMan3 != NULLvoid Abc_NtkRecStop3()v >= 0 && v < LMS_VAR_MAXint Lms_DelayGet(word, int)void Lms_DelaySet(word *, int, int)d >= 0 && d < LMS_VAR_MAXword Lms_DelayInit(int)char Vec_StrEntry(Vec_Str_t *, int)Delay profile = {p->nEntries == Vec_IntSize(p->vNexts)int Vec_MemHashInsert(Vec_Mem_t *, word *)*pSpot == -1void Vec_MemHashResize(Vec_Mem_t *)word *Vec_MemGetEntry(Vec_Mem_t *, int)nVarS < nVarBvoid Abc_TtStretch5(unsigned int *, int, int)step < nWordsGia_ObjId(p, pObjCo) > Abc_Lit2Var(iLit0)void Gia_ManPatchCoDriver(Gia_Man_t *, int, int)int If_CutFindBestStruct(If_Man_t *, If_Cut_t *, char *, unsigned int *, int *)int If_CutTruthIsCompl(If_Cut_t *)int Abc_TtSuppIsMinBase(int)QUUUUUUUU33333333Performing recoding structures with choices.The file cannot be opened.There is not truth tables.!Abc_ObjIsComplement(pRoot)src/base/abci/abcReconv.cVec_Ptr_t *Abc_NodeFindCut(Abc_ManCut_t *, Abc_Obj_t *, int)Vec_PtrSize(p->vNodeLeaves) <= p->nNodeSizeMaxp->nNodeSizeMax < p->nConeSizeMaxVec_PtrSize(p->vConeLeaves) <= p->nConeSizeMax!Abc_ObjIsPi(pNode)DdNode *Abc_NodeConeBdd(DdManager *, DdNode **, Abc_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *)bFuncVec_Ptr_t *Abc_NodeCollectTfoCands(Abc_ManCut_t *, Abc_Obj_t *, Vec_Ptr_t *, int)vVec->nSize == 0LevelMin >= 0CostBest < 3int Abc_NodeBuildCutLevelOne_int(Vec_Ptr_t *, Vec_Ptr_t *, int, int)Abc_ObjIsNode(pFaninBest)vLeaves->nSize <= nSizeLimitint Abc_NodeGetLeafCostOne(Abc_Obj_t *, int)void Abc_NodeConeMarkCollect_rec(Abc_Obj_t *, Vec_Ptr_t *)src/base/abci/abcReach.cDdNode **Abc_NtkCreatePartitions(DdManager *, Abc_Ntk_t *, int, int)BDD nodes in the partitions before reordering %d. BDD nodes in the partitions after reordering %d. nIterMax > 1DdNode *Abc_NtkComputeReachable(DdManager *, Abc_Ntk_t *, DdNode **, DdNode *, DdNode *, int, int, int, int, int)The miter is proved REACHABLE in %d iterations. Iteration = %3d. BDD = %5d. Reachability analysis is stopped after %d iterations. Reachability analysis completed in %d iterations. Verified ONLY FOR STATES REACHED in %d iterations. The miter is proved unreachable in %d iteration. void Abc_NtkVerifyUsingBdds(Abc_Ntk_t *, int, int, int, int, int)Abc_ObjFanoutNum(Abc_NtkPo(pNtk,0)) == 0The number of intermediate BDD nodes exceeded the limit (%d). Shared BDD size is %6d nodes. The miter is proved REACHABLE in the initial state. src/base/abci/abcRefactor.cword *Abc_NodeConeTruth(Vec_Ptr_t *, Vec_Ptr_t *, int, Abc_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *)Nodes considered = %8d. Nodes refactored = %8d. Gain = %8d. (%6.2f %%). Cuts Resynthesis BDD DCs SOP FF Eval AIG update TOTAL int Abc_NtkRefactor(Abc_Ntk_t *, int, int, int, int, int, int)Abc_AigNodeIsAnd(pNode)int Abc_NodeIsPersistant(Abc_Obj_t *)Refactoring statistics:Abc_NtkRefactor: The network check has failed.s_pReo == NULLsrc/base/abci/abcRenode.cAbc_Ntk_t *Abc_NtkRenode(Abc_Ntk_t *, int, int, int, int, int, int, int, int, int, int)s_vMemory == NULLint Abc_NtkRenodeEvalSop(If_Man_t *, If_Cut_t *)int Abc_NtkRenodeEvalCnf(If_Man_t *, If_Cut_t *)int Abc_NtkRenodeEvalMv(If_Man_t *, If_Cut_t *)Performing renoding with choices.%10s: Before = %5d BDD nodes. After = %5d BDD nodes. src/base/abci/abcRestruct.cint Abc_NtkRestructure(Abc_Ntk_t *, int, int, int, int)pNode->fMarkC == 0void Abc_RestructNodeDivisors(Abc_ManRst_t *, Abc_Obj_t *, int)void Abc_NodeEdgeDsdPermute(Dec_Graph_t *, Abc_ManRst_t *, Vec_Int_t *, int)Index < Dec_GraphLeaveNum(pGraph)Dec_Edge_t Abc_NodeEvaluateDsd_rec(Dec_Graph_t *, Abc_ManRst_t *, Dsd_Node_t *, int, int, int *)DecType == DSD_NODE_OR || DecType == DSD_NODE_EXOR || DecType == DSD_NODE_PRIMEVec_IntSize(vEdges) > 1Required == ABC_INFINITY || Level3 == (int)Abc_ObjRegular(pNode3)->LevelRequired == ABC_INFINITY || Level4 == (int)Abc_ObjRegular(pNode4)->LevelAbc_NodeIsTravIdPrevious(pRoot)int Abc_NodeResubMffc(Abc_ManRst_t *, Vec_Ptr_t *, int, Abc_Obj_t *)k == Vec_PtrSize(p->vDecs)pRoot == Vec_PtrEntryLast(p->vDecs)pGraphDec_Graph_t *Abc_NodeMffcConstants(Abc_ManRst_t *, Vec_Int_t *)nNodesSaved > 0Dec_Graph_t *Abc_NodeResubEval(Abc_ManRst_t *, Abc_Obj_t *, Cut_Cut_t *)Nodes considered = %8d. Cuts considered = %8d. Cuts explored = %8d. Nodes restructured = %8d. Calculated gain = %8d. DSD UUUOUȈU9UUUՋUfU%U|UUjU2Usrc/base/abci/abcResub.cint Abc_NtkResubstitute(Abc_Ntk_t *, int, int, int, int, int, int)Abc_ObjRegular(pObj0) != Abc_ObjRegular(pObj1)Dec_Graph_t *Abc_ManResubQuit1(Abc_Obj_t *, Abc_Obj_t *, Abc_Obj_t *, int)Dec_Graph_t *Abc_ManResubQuit21(Abc_Obj_t *, Abc_Obj_t *, Abc_Obj_t *, Abc_Obj_t *, int)Abc_ObjRegular(pObj0) != Abc_ObjRegular(pObj2)Abc_ObjRegular(pObj1) != Abc_ObjRegular(pObj2)Dec_Graph_t *Abc_ManResubQuit2(Abc_Obj_t *, Abc_Obj_t *, Abc_Obj_t *, Abc_Obj_t *, int)Dec_Graph_t *Abc_ManResubQuit3(Abc_Obj_t *, Abc_Obj_t *, Abc_Obj_t *, Abc_Obj_t *, Abc_Obj_t *, int)Abc_ObjRegular(pObj2) != Abc_ObjRegular(pObj3)!Abc_ObjIsCi(pNode)Vec_Ptr_t *Abc_CutFactor(Abc_Obj_t *)Used constants = %6d. Cuts Used replacements = %6d. Resub Used single ORs = %6d. Div Used single ANDs = %6d. Mffc Used double ORs = %6d. Sim Used double ANDs = %6d. 1 Used OR-AND = %6d. D Used AND-OR = %6d. 2 Used OR-2ANDs = %6d. Used AND-2ORs = %6d. AIG TOTAL = %6d. Total leaves = %8d. Total divisors = %8d. Gain = %8d. (%6.2f %%). nSteps >= 0Dec_Graph_t *Abc_ManResubEval(Abc_ManRes_t *, Abc_Obj_t *, Vec_Ptr_t *, int, int, int)nSteps <= 3p->nMffc > 0pRoot == Vec_PtrEntryLast(p->vDivs)int Abc_ManResubCollectDivs(Abc_ManRes_t *, Abc_Obj_t *, Vec_Ptr_t *, int)Vec_PtrSize(p->vDivs) - Vec_PtrSize(vLeaves) <= Vec_PtrSize(p->vSims) - p->nLeavesMaxVec_PtrSize(vDivs) - nLeaves <= Vec_PtrSize(vSims) - nLeavesMaxvoid Abc_ManResubSimulate(Vec_Ptr_t *, int, Vec_Ptr_t *, int, int)Dec_Graph_t *Abc_ManResubDivs12(Abc_ManRes_t *, int)LevelMax <= Required - 1pObjMin0pObjMin1Abc_CutVolumeCheck() ERROR: The set of nodes is not a cut!src/base/abci/abcRewrite.cint Abc_NtkRewrite(Abc_Ntk_t *, int, int, int, int, int)%6d : %c %6d : %2d = void Abc_RwrExpWithCut_rec(Abc_Obj_t *, Vec_Ptr_t *, int)(%d,%d:%d) Abc_NtkRewrite: The network check has failed.Solution : %s null %d of %d (%.2f %%) functions are RPO. Number of variables = %d src/base/abci/abcRpo.cRpo_TtStore_t *Abc_TtStoreLoad(char *, int)void Abc_TruthStoreRead(char *, Rpo_TtStore_t *)Edges tried = %6d. Edges removed = %6d. (%5.2f %%) Node gain = %6d. (%5.2f %%) Level gain = %6d. Windowing Miter Construct Prove Update TOTAL src/base/abci/abcRr.cint Abc_NtkRRUpdate(Abc_Ntk_t *, Abc_Obj_t *, Abc_Obj_t *, Abc_Obj_t *)LevelLimit >= 0int Abc_NtkRRTfi_int(Vec_Ptr_t *, int)Abc_Ntk_t *Abc_NtkWindow(Abc_Ntk_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *)tempWarning: Structural hashing during windowing reduced %d nodes (this is a bug). pObj->pData == NULLvoid Abc_NtkRRSimulateStart(Abc_Ntk_t *)Abc_NtkRR: The network check has failed.Redundancy removal statistics:Abc_NtkWindow: The network check has failed.חAsrc/base/abci/abcSat.cint Abc_NtkMiterSat(Abc_Ntk_t *, ABC_INT64_T, ABC_INT64_T, int, ABC_INT64_T *, ABC_INT64_T *)trace.cnfint Abc_NtkClauseAnd(sat_solver *, Abc_Obj_t *, Vec_Ptr_t *, Vec_Int_t *)int Abc_NtkClauseMux(sat_solver *, Abc_Obj_t *, Abc_Obj_t *, Abc_Obj_t *, Abc_Obj_t *, Vec_Int_t *)Abc_NodeIsMuxType( pNode )int Abc_NtkCollectSupergate_rec(Abc_Obj_t *, Vec_Ptr_t *, int, int)void Abc_NtkCollectSupergate(Abc_Obj_t *, int, Vec_Ptr_t *)(int)pObj->Level <= nLevelMaxint Abc_NtkNodeFactor(Abc_Obj_t *, int)int Abc_NtkMiterSatCreateInt(sat_solver *, Abc_Ntk_t *)Abc_NtkIsStrash(pNtk) || Abc_NtkIsBddLogic(pNtk)void *Abc_NtkMiterSatCreate(Abc_Ntk_t *, int)nFanins == Abc_SopGetVarNum( pSop0 )int Abc_NodeAddClauses(sat_solver *, char *, char *, Abc_Obj_t *, Vec_Int_t *)The number of queens (Q = %d) should belong to the interval: 0 < Q < %d. nQueens > 0 && nQueens < nVarsvoid Abc_NtkWriteSorterCnf(char *, int, int)gen -s -N %d sorter%d.blifCannot execute command "%s". read sorter%d.blif; strashc CNF for %d-bit sorter with %d bits set to 1 generated by ABC. %d %s%d %s%d 0 -%d %s%d 0 The CNF is trivially UNSAT.rq? _BInitial Refine by Dependency graph ... Initial Refine by Simulation ... This output is not dependent on any input Build functional dependency graph (dependency stats are below) ... group size = %fe%d Runtime %s=%dsrc/base/abci/abcSaucy.cint refineBySim1_init(struct saucy *, struct coloring *)int refineBySim2_init(struct saucy *, struct coloring *)int refineBySim1_left(struct saucy *, struct coloring *)int refineBySim2_left(struct saucy *, struct coloring *)name[0] == 'N' && name[2] == ':'int check_OPP_for_Boolean_matching(struct saucy *, struct coloring *)name[1] == '2'c == &s->rightint refineBySim1_other(struct saucy *, struct coloring *)int refineBySim2_other(struct saucy *, struct coloring *)in level %d: %s->%s Backtrack by SAT from level %d to %d (%sgenerators = %d total support = %d average support = %.2f nodes per generator = %.2f bad nodes = %d BAD NODEdone! -------------------- --------------------*** Networks are NOT equivalent ****** Networks are equivalent ***Networks are undecided (SAT solver timed out).Renoding for CNF has failed.Miter computation has failed.%s=%s%s %s_bmc%s%d pairs of sequentially equivalent nodes are written into file "%s". Input file "%s" cannot be opened. Output file "%s" cannot be opened. Reading input file "%s" has failed. Deriving logic network from input file %s has failed. .BENCH.initInit file "%s" cannot be opened. Initial state was derived from file "%s". Deriving strashed network from input file %s has failed. src/base/abci/abcSense.cAbc_Obj_t *Abc_NtkSensitivityMiter_rec(Abc_Ntk_t *, Abc_Obj_t *)Abc_Ntk_t *Abc_NtkSensitivityMiter(Abc_Ntk_t *, int)Vec_Int_t *Abc_NtkSensitivity(Abc_Ntk_t *, int, int)The outputs are sensitive to %d (out of %d) inputs: Abc_NtkSensitivityMiter: The network check has failed.ERROR in Abc_NtkMiterProve(): Generated counter-example is invalid.(knA_@MbP?333333???YAbc_ObjFaninNum(pNode) == 0 || pPinPerm[0] < Abc_ObjFaninNum(pNode)src/base/abci/abcSpeedup.cvoid Abc_NtkDelayTraceSortPins(Abc_Obj_t *, int *, float *)pPinPerm[i] < Abc_ObjFaninNum(pNode)pPinDelays[pPinPerm[i-1]] >= pPinDelays[pPinPerm[i]]float Abc_NtkDelayTraceLut(Abc_Ntk_t *, int)The max LUT size (%d) is less than the max fanin count (%d). tSlack + 0.001 > 0.0Num >=0 && Num <= nStepsvoid Abc_NtkDelayTracePrint(Abc_Ntk_t *, int, int)Max delay = %6.2f. Delay trace using %s model: LUT libraryunit-delay%3d %s : %5d (%6.2f %%) levint Abc_AigCheckTfi(Abc_Obj_t *, Abc_Obj_t *)int Abc_NtkSpeedupNode_rec(Abc_Obj_t *, Vec_Ptr_t *)Max delay = %.2f. Delta = %.2f. Using %s model. Percentage = %d. Edges: Total = %7d. 0-slack = %7d. Critical = %7d. Ratio = %4.2f %5d Node %5d : %d %2d %2d %d(%.2f)%s Nodes: Total = %7d. 0-slack = %7d. Workable = %7d. Ratio = %4.2f Vec_IntSize(vProbs) >= Abc_NtkObjNumMax(pNtk)void Abc_NtkPowerPrint(Abc_Ntk_t *, Vec_Int_t *)pProb[i] >= 0.0 && pProb[i] <= 1.0Node distribution: n%d%d = %6.2f%% Power distribution: p%d%d = %6.2f%% Total probs = %7.2f. Total edges = %d. Average = %7.2f. Nodes: Total = %7d. Power-critical = %7d. Workable = %7d. Ratio = %4.2f src/base/abci/abcStrash.cAbc_Ntk_t *Abc_NtkRestrash(Abc_Ntk_t *, int)Abc_Ntk_t *Abc_NtkRestrashRandom(Abc_Ntk_t *)Abc_Ntk_t *Abc_NtkRestrashZero(Abc_Ntk_t *, int)Converting %d flops from don't-care to zero initial value. Abc_NtkRestrash(): AIG cleanup removed %d nodes (this is a bug). Abc_Ntk_t *Abc_NtkStrash(Abc_Ntk_t *, int, int, int)int Abc_NtkAppend(Abc_Ntk_t *, Abc_Ntk_t *, int)Abc_NtkIsLogic(pNtk2) || Abc_NtkIsStrash(pNtk2)Warning: Procedure Abc_NtkAppend() added %d new CIs. iNodeId >= 0void Abc_NodeStrash_rec(Abc_Aig_t *, Hop_Obj_t *)Abc_Obj_t *Abc_NodeStrash(Abc_Ntk_t *, Abc_Obj_t *, int)Abc_NtkHasAig(pNodeOld->pNtk) && !Abc_NtkIsStrash(pNodeOld->pNtk)Abc_Obj_t *Abc_NtkTopmost_rec(Abc_Ntk_t *, Abc_Obj_t *, int)Abc_Ntk_t *Abc_NtkTopmost(Abc_Ntk_t *, int)Abc_NtkCoNum(pNtk) == 1Abc_ObjIsNode(pNode) && !Abc_ObjIsComplement(pNode)Vec_Ptr_t *Abc_NodeGetSuper(Abc_Obj_t *)Abc_Ntk_t *Abc_NtkTopAnd(Abc_Ntk_t *)Vec_PtrSize(vNodes) >= 2Abc_NtkTopAnd(): AIG cleanup removed %d nodes (this is a bug). void Abc_NtkWriteAig(Abc_Ntk_t *, char *) "%s", // pi=%d po=%d and=%d { "%s",NULL }, 0 }, Abc_Ntk_t *Abc_NtkPutOnTop(Abc_Ntk_t *, Abc_Ntk_t *)Abc_NtkIsLogic(pNtk2)Abc_NtkPoNum(pNtk) == Abc_NtkPiNum(pNtk2)Abc_NtkPutOnTop(): Network check has failed. Abc_NtkIsLogic(pNtkOld)void Abc_NtkStrashPerform(Abc_Ntk_t *, Abc_Ntk_t *, int, int)Warning: The choice nodes in the original AIG are removed by strashing.Abc_NtkAppend(): The union of the network PIs is computed (warning).Abc_NtkAppend: The network check has failed.Converting to AIGs has failed.Abc_NtkTopmost: The network check has failed.src/base/abci/abcSweep.cint Abc_NtkFraigSweep(Abc_Ntk_t *, int, int, int, int)int Abc_NtkCleanup(Abc_Ntk_t *, int)Cleanup removed %d dangling nodes. int Abc_NtkCleanupNodes(Abc_Ntk_t *, Vec_Ptr_t *, int)void Abc_NodeConstantInput(Abc_Obj_t *, Abc_Obj_t *, int)int Abc_NtkSweep(Abc_Ntk_t *, int)Abc_ObjFaninNum(pNode) == 1Sweep removed %d nodes. Abc_ObjFaninNum(pObj) == 1void Abc_NtkSetTravId_rec(Abc_Obj_t *)int Abc_NtkCheckConstant_rec(Abc_Obj_t *)!Abc_ObjIsLatch(pFanin)int Abc_NtkReplaceAutonomousLogic(Abc_Ntk_t *)int Abc_NtkCleanupSeq(Abc_Ntk_t *, int, int, int)Cleanup removed %4d dangling objects. Cleanup removed %4d redundant latches. Cleanup added %4d additional PIs. Cleanup removed %4d autonomous objects. int Abc_NtkSweepBufsInvs(Abc_Ntk_t *, int)Removed %d single input nodes. Class %2d : {(%c)Sweeping stats for network "%s": Internal nodes = %d. Different functions (up to compl) = %d. Non-trivial classes = %d. Nodes in non-trivial classes = %d. pChainvoid Abc_NtkFraigMergeClassMapped(Abc_Ntk_t *, Abc_Obj_t *, int, int)pChain->pNextvoid Abc_NtkFraigMergeClass(Abc_Ntk_t *, Abc_Obj_t *, int, int)int Abc_NtkReduceNodes(Abc_Ntk_t *, Vec_Ptr_t *)int Abc_LatchInit(Abc_Obj_t *)Abc_NtkFraigSweep: The network check has failed.Abc_NtkCleanup: The network check has failed.Abc_NtkCleanupSeq: The network check has failed.00]W]W]W^W ^W^WCNSJ/_9*(B0 ZAbc_TtCompareRev(pNpn, pFunT, nWords) != 1src/base/abci/abcSymm.cvoid Ntk_SymTryRandomFlips(word *, word *, int)!(nVars < 1 || nVars > 16)void Ntk_SymFunGenerate(int, int)Generating truth tables of all symmetric functions of %d variables. : NPN Class %3dThe number of different NPN classes is %d. The total number of symmetries is %d. Shared BDD size = %d nodes. Algorithm = %s. Reordering = %s. Garbage collection = %s. naivefastConstructing BDDsComputing symms TOTAL Output %6s (%d): Total number of vars in functional supports = %8d. Total number of two-variable symmetries = %8d. pVarTaken[k] == 0void Ntk_NetworkSymmsPrint(Abc_Ntk_t *, Extra_SymmInfo_t *) { %sStatistics of BDD-based symmetry detection:src/base/abci/abcTim.cvoid Abc_NtkTestTimNodeStrash_rec(Gia_Man_t *, Hop_Obj_t *)int Abc_NtkTestTimNodeStrash(Gia_Man_t *, Abc_Obj_t *)Abc_NtkIsAigLogic(pNode->pNtk)void Abc_NtkTestTimCollectCone_rec(Abc_Obj_t *, Vec_Ptr_t *)Vec_Ptr_t *Abc_NtkTestTimCollectCone(Abc_Ntk_t *, Abc_Obj_t *)!Abc_NodeIsTravIdCurrent( pObj )Abc_NtkIsTopo(pNtk)Gia_Man_t *Abc_NtkTestTimDeriveGia(Abc_Ntk_t *, int)Selecting node %6d as white boxes with %d inputs and %d output. curPi == Gia_ManPiNum(pGia)curPo == Gia_ManPoNum(pGia)pGia->pManTime == NULLholes00.aigp->pReprsvoid Gia_ManVerifyChoices(Gia_Man_t *)Gia_ObjIsHead(p, iRepr)Member %d of choice class %d is a representative. Node %d participates in more than one choice node. Fanin 0 of AND node %d has a repr. Fanin 1 of AND node %d has a repr. Fanin 0 of CO node %d has a repr. void Gia_ManReverseClasses(Gia_Man_t *, int)Gia_ObjRepr(p, iNode) == iRepr && iRepr > iNodeGia_ObjRepr(p, iNode) == iRepr && iRepr < iNodevoid Abc_NtkTestTim(Abc_Ntk_t *, int)Created GIA manager for network with %d white boxes. test1.aigtest2.aigNum == GIA_VOID || Num > Idvoid Gia_ObjSetReprRev(Gia_Man_t *, int, int)Num == GIA_VOID || Num < Idvoid Gia_ObjSetRepr(Gia_Man_t *, int, int)Verification suceessful.??(knNsrc/base/abci/abcTiming.cAbc_Time_t *Abc_NtkReadDefaultArrival(Abc_Ntk_t *)Abc_Time_t *Abc_NtkReadDefaultRequired(Abc_Ntk_t *)pNode->pNtk->pManTimeAbc_Time_t *Abc_NodeReadArrival(Abc_Obj_t *)Abc_Time_t *Abc_NodeReadRequired(Abc_Obj_t *)Abc_Time_t *Abc_NtkReadDefaultInputDrive(Abc_Ntk_t *)Abc_Time_t *Abc_NtkReadDefaultOutputLoad(Abc_Ntk_t *)Abc_Time_t *Abc_NodeReadInputDrive(Abc_Ntk_t *, int)Abc_Time_t *Abc_NodeReadOutputLoad(Abc_Ntk_t *, int)PiNum >= 0 && PiNum < Abc_NtkCiNum(pNtk)void Abc_NtkTimeSetInputDrive(Abc_Ntk_t *, int, float, float)PoNum >= 0 && PoNum < Abc_NtkCoNum(pNtk)void Abc_NtkTimeSetOutputLoad(Abc_Ntk_t *, int, float, float)pNtkOld == NULL || pNtkOld->pManTime != NULLvoid Abc_NtkTimeInitialize(Abc_Ntk_t *, Abc_Ntk_t *)pNtkOld == NULL || Abc_NtkCiNum(pNtk) == Abc_NtkCiNum(pNtkOld)pNtkOld == NULL || Abc_NtkCoNum(pNtk) == Abc_NtkCoNum(pNtkOld)Abc_NtkCiNum(pNtkOld) == Abc_NtkCiNum(pNtkNew)void Abc_ManTimeDup(Abc_Ntk_t *, Abc_Ntk_t *)Abc_NtkCoNum(pNtkOld) == Abc_NtkCoNum(pNtkNew)Default arrival = %8f Default required = %8f Inputs (%d): %20s arrival = %8f required = %8f Outputs (%d): int Abc_NtkDelayTraceCritPath_rec(Vec_Int_t *, Abc_Obj_t *, Abc_Obj_t *, Vec_Int_t *)Abc_ObjIsCi(pNode) || Abc_ObjIsNode(pNode)void Abc_NtkDelayTraceCritPathCollect_rec(Vec_Int_t *, Abc_Obj_t *, Vec_Int_t *, Vec_Ptr_t *)float Abc_NtkDelayTrace(Abc_Ntk_t *, Abc_Obj_t *, Abc_Obj_t *, int)pOut == NULL || Abc_ObjIsCo(pOut)pIn == NULL || Abc_ObjIsCi(pIn)pOut != NULLThe logic cone of PO "%s" has no primary inputs. There is no combinational path between PI "%s" and PO "%s". Critical path from PI "%s" to PO "%s": Level %3d : Primary input "%s". Arrival time =%6.1f. Primary output "%s". Arrival =%6.1f. %10s/%-4s (%s)Arrival =%6.1f. I/O times: (%s%.1f -> %.1f)Required time = %6.1f. Path slack = %6.1f. pNtk->vLevelsRint Abc_ObjRequiredLevel(Abc_Obj_t *)int Abc_ObjReverseLevel(Abc_Obj_t *)void Abc_ObjSetReverseLevel(Abc_Obj_t *, int)void Abc_NtkStopReverseLevels(Abc_Ntk_t *)Abc_ObjLevel(pTemp) == Levvoid Abc_NtkUpdateLevel(Abc_Obj_t *, Vec_Vec_t *)Abc_ObjLevel(pFanout) >= LevLevelOld == Levvoid Abc_NtkUpdateReverseLevel(Abc_Obj_t *, Vec_Vec_t *)LevFanin >= LevThere is no timing managerOut%4d : Ins/Outs = %4d/%4d. Total supp = %5d. Total unate = %5d. Glob BDDsUnatenessTotal BDD nodes in the unreachable states before reordering %d. BDD nodes in the unreachable states after reordering %d. src/base/abci/abcUnreach.cDdNode *Abc_NtkTransitionRelation(DdManager *, Abc_Ntk_t *, int)BDD nodes in the transition relation before reordering %d. BDD nodes in the transition relation after reordering %d. The number of minterms in the reachable state set = %d. (%6.2f %%) Abc_NtkExtractSequentialDcs: The network check has failed.Abc_NtkConstructExdc(): Converting to SOPs has failed.src/base/abci/abcVerify.cvoid Abc_NtkCecFraig(Abc_Ntk_t *, Abc_Ntk_t *, int, int)Abc_NtkPoNum(pMiter) == 1Abc_NtkPoNum(pExdc) == 1Networks are NOT EQUIVALENT after structural hashing. Networks are equivalent after structural hashing. Networks are undecided (resource limits is reached). nPartSize > 0void Abc_NtkCecFraigPart(Abc_Ntk_t *, Abc_Ntk_t *, int, int, int)Networks are undecided (resource limits is reached). Timed out after verifying %d outputs (out of %d). Verifying part %4d (out of %4d) PI = %5d. PO = %5d. And = %6d. Lev = %4d. int Abc_NtkSecFraig(Abc_Ntk_t *, Abc_Ntk_t *, int, int, int)Verification failed for at least %d output%s of frame %d: Output %s: Value in Network1 = %d. Value in Network2 = %d. The cone of influence of output %s in Network1: PIs: Latches: The cone of influence of output %s in Network2: Frame %d: PI(1):L(1):%s(1):PI(2):L(2):%s(2):11001101011101011111110100100010001strlen(vPiValues1) == (unsigned)Abc_NtkPiNum(pNtk)void Abc_NtkSimulteBuggyMiter(Abc_Ntk_t *)1 == Abc_NtkPoNum(pNtk)void Abc_NtkVerifyReportError(Abc_Ntk_t *, Abc_Ntk_t *, int *)Verification failed for at least %d outputs: Input pattern: First network has no EXDC. Comparing main networks under EXDC of the second network.Second network has no EXDC. Comparing main networks under EXDC of the first network.Comparing EXDC of the two networks:Comparing networks under EXDC of the first network.Networks are equivalent. Networks are NOT EQUIVALENT. Networks are NOT EQUIVALENT after partitioning.Networks are equivalent after SAT.Networks are NOT EQUIVALENT after SAT.Networks are NOT EQUIVALENT after fraiging.Networks are equivalent after fraiging.Networks are undecided (SAT solver timed out on the final miter).Networks are equivalent after framing.Networks are NOT EQUIVALENT after framing.Frames computation has failed.Networks are equivalent after structural hashing.Networks are NOT EQUIVALENT after structural hashing.No output mismatches detected.src/base/abci/abcXsim.cvoid Abc_NtkXValueSimulate(Abc_Ntk_t *, int, int, int, int)Frame : Inputs : Latches : Outputs void Abc_NtkCycleInitState(Abc_Ntk_t *, int, int, int)Value0 == XVS1 && Value1 == XVS1int Abc_XsimAnd(int, int)Value == XVSXint Abc_XsimInv(int)void Abc_XsimPrint(FILE *, int)Basicechoquitabcrchistoryunaliashelpsourceunsetrecallmvsiscapostarterautotunerload_pluginwgnuplot.exegnuplotCannot open the plot file "%s". gnuplotwingnuplotunixCannot find "%s" or "%s" in the current directory. %s %s usage: time [-ch] print the runtime since the last call -c clears the elapsed time without printing it -h print the command usage usage: echo [-h] string -n suppress newline at the end usage: quit [-sh] -h print the command usage -s frees all the memory before quitting usage: abcrc [-h] -h sources "abc.rc" from the current/parent/grandparent directory usage: history [-h] lists the last commands entered on the command line : the maximum number of entries to show [default = %d] usage: alias [-h] [command [string]] usage: unalias [-h] alias_names adhusage: help [-a] [-d] [-h] prints the list of available commands by group -a toggle printing hidden commands [default = %s] -d print usage details to all commands [default = %s] -h print the command usage ipsxhprompt Use "quit" to leave ABC. abc - > %s** cmd error: aborting 'source %s' usage: source [-psxh] -p supply prompt before reading each line [default = %s] -s silently ignore nonexistant file [default = %s] -x echo each line as it is executed [default = %s] -h print the command usage abcoutabcerrusage: set [-h] sets the value of parameter usage: unset [-h] removes the value of parameter usage: undo sets the current network to be the previously saved network savestepsCan only recall step %d. Can only recall steps %d-%d. Cannot recall step %d. usage: recall -h set the current network to be one of the previous networks : level to return to [default = previous] -h : print the command usage usage: empty [-h] removes all the currently stored networks Wrong command: "%s". Cannot produce the intermediate network. %s -x -c read_blif _sis_in.blifwrite_blif _sis_out.blifThe following command has returned non-zero exit status: Cannot open SIS output file "%s". Usage: sis [-h] invokes SIS command for the current ABC network (the executable of SIS should be in the same directory) -h : print the command usage : a SIS command (or a semicolon-separated list of commands in quotes) Example 1: sis eliminate 0 Example 2: sis "ps; rd; fx; ps" Example 3: sis source script.rugged mvsis.exemvsiswinmvsisunixread_blif _mvsis_in.blifwrite_blif _mvsis_out.blifCannot open MVSIS output file "%s". Usage: mvsis [-h] invokes MVSIS command for the current ABC network (the executable of MVSIS should be in the same directory) : a MVSIS command (or a semicolon-separated list of commands in quotes) Example 1: mvsis fraig_sweep Example 2: mvsis "ps; fxu; ps" Example 3: mvsis source mvsis.rugged capo.execapowincapounix_capo_in.blif%s -f _capo_in.blif -log out.txt -plot%s.pltUsage: capo [-h] peforms placement of the current network using Capo a Capo binary should be present in the same directory (if plotting, the Gnuplot binary should also be present) : a Capo command Example 1: capo (performs placement with default options) Example 2: capo -AR -WS -save (specifies the aspect ratio [default = 1.0] and the whitespace percentage [0%%; 100%%) [default = 15%%]) Example 3: capo -plot (produces and visualize it using Gnuplot) Example 4: capo -help (prints the default usage message of the Capo binary) Please refer to the Capo webpage for additional information: http://vlsicad.eecs.umich.edu/BK/PDtools/ NCvhCommand line switch "-C" should be followed by a string (possibly in quotes). The file name should be given on the command line. open_path.s.scr.scriptusage: starter [-N num] [-C cmd] [-vh] runs command lines listed in concurrently on CPUs -N num : the number of concurrent jobs including the controler [default = %d] -C cmd : (optional) ABC command line to execute on benchmarks in : file name with ABC command lines (or benchmark names, if is given) NCFvhCommand line switch "-F" should be followed by a string (possibly in quotes). File containing configuration for autotuning is not given. File contining list of files for autotuning is not given. Cannot open configuration file "%s". Cannot open the file list "%s". usage: autotuner [-N num] [-C file] [-F file] [-vh] performs autotuning -C cmd : configuration file with settings for autotuning -F cmd : list of AIGER files to be used for autotuning usage: version [-h] print the version string The current network is unmapped before calling SIS.The current network is unmapped before calling MVSIS.The current network is unmapped before calling Capo.!fStatussrc/base/cmd/cmdAlias.cvoid CmdCommandAliasAdd(Abc_Frame_t *, char *, int, char **)%-15sCmd warning: redefining '%s' src/base/cmd/cmdApi.cvoid Cmd_CommandAdd(Abc_Frame_t *, const char *, const char *, Cmd_CommandFuncType, int)#PSpi=%d po=%d fn=%d ma=%.1f de=%d #CECproofStatus=%d #ASSERT_PI_==<=_PO__NODE__AREA__DEPTH_succeededMX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OXJXJXJXKX=KXlKXKXKXKX(LXWLXLXLXLX5MXdMXMX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OX OXPJX((PPxx-C %d -V %.3f -W %.3f src/base/cmd/cmdAuto.cnProcs >= 1 && nProcs <= CMD_THR_MAXint Cmd_RunAutoTunerEval(Vec_Ptr_t *, satoko_opts_t *, int)status == 0ThData[i].Result >= 0!ThData[i].fWorkingCPDEFGHIJKLMNOQRShvCommand line switch "-D" should be followed by an float. Command line switch "-E" should be followed by an float. Command line switch "-R" should be followed by an float. Command line switch "-S" should be followed by an float. Argc <= CMD_AUTO_ARG_MAXvoid Cmf_CreateOptions_rec(Vec_Wec_t *, int, char (*)[20], int, Vec_Ptr_t *)Adding settings %s Abc_Int2Float(Num) == -1.0-%cNumF >= 0Finished creating %d settings. File containing list of files "%s" cannot be opened. Upper-case character (%c) should be followed by a number without space in line "%s". Expecting a leading lower-case or upper-case digit in line "%s". Cannot read AIG from file "%s". Evaluating settings: %20s... Cost = %6d. The best settings are: %20s Best cost = %6d. Cannot parse command line options...Creating all possible settings to be used by the autotuner:hi hiabccmd_Cannot run the binary "%s". src/base/cmd/cmdPlugin.cchar *Abc_GetBinaryName(Abc_Frame_t *, int, char **) -abc Current AIG does not exist (try command &ps). __abctmp_Cannot create a temporary file. .outInput file "%s" and output file "%s" are not deleted. -abc -input= -output=There is no output file "%s". result:bug-free-depth:abstraction:counter-example:Adjusting counter-example by adding zeros for PIs without fanout. Counter example has a wrong length. Problem is satisfiable. Found counter-example in frame %d. Generated counter-example is INVALID. Returned counter-example successfully verified in ABC. aig:vphCannot run the binary "%s". File does not exist. %s -abc -list-commands > %sRunning command %s Command "%s" failed. Cannot open file with the list of commands. Creating command %s with binary %s usage: load_plugin [-pvh] loads external binary as a plugin -p : toggle searching the command in PATH [default = %s]. %u "%s" src/base/cmd/cmdStarter.cvoid *Abc_RunThread(void *)The number of cores (%d) should be more than 1. Starter cannot open file "%s". %s -c "%s; %s" > %sCalling: %s void Cmd_RunStarter(char *, char *, char *, int)i < nLinesFinished processing commands in file "%s". Total wall time/bin/shsrc/base/cmd/cmdUtils.cint CmdCommandDispatch(Abc_Frame_t *, int *, char ***)** cmd error: unknown command '%s' (this is likely caused by using an alias defined in "abc.rc" without having this file in the current or parent directory) autoexec** cmd warning: ignoring unbalanced quote ... ** cmd warning: alias loop stdinlib_path%s:%sLoading resource file "%s". CmdCommandPrintCompare( ppCommands, ppCommands + nCommands - 1 ) <= 0void CmdCommandPrint(Abc_Frame_t *, int, int) Welcome to ABC compiled on %s %s!Sep 14 202408:33:20 %-*s%s -h ----------------------------------------------------------------------%s commands: %-15s %-15s int CmdCommandPrintCompare(Abc_Command **, Abc_Command **)wXX}XXXXXXXXXXXXXXXXXXXXXXXXX-XXnBits == Abc_NtkCiNum(pNtk) * (pCex->iFrame + 1)src/base/io/io.cvoid Abc_NtkDumpOneCex(FILE *, Abc_Ntk_t *, Abc_Cex_t *, int, int, int, int, int, int, int, int, int, int)%s@%d=%c # FALSIFYING OUTPUTS:# COUNTEREXAMPLE LENGTH: %u IoCommandWriteCex(): Cannot find special PI required by switch "-z". iFlop == nXValuesmcbghstrlen(pFileName) < 900int IoCommandRead(Abc_Frame_t *, int, char **)read_genlib %sread_lib %sread_scl %sread_super %sread_constr %sso %sdsd_load %sAbc_CommandBlast(): Bit-blasting has failed. Cannot read mapped design when the library is not given. The new network has no primary inputs. It is recommended to add a dummy PI to make sure all commands work correctly. usage: read [-mcbgh] replaces the current network by the network read from by calling the parser that matches the extension of (to read a hierarchical design, use "read_hie") -m : toggle reading mapped Verilog [default = %s] -c : toggle network check after reading [default = %s] -b : toggle reading barrier buffers [default = %s] -g : toggle reading and flattening into &-space [default = %s] -h : prints the command summary file : the name of a file to read usage: read_aiger [-ch] reads the network in the AIGER format (http://fmv.jku.at/aiger) usage: read_baf [-ch] reads the network in Binary Aig Format (BAF) usage: read_bblif [-ch] reads the network in a binary BLIF format nmachusage: read_blif [-nmach] reads the network in binary BLIF format (if this command does not work, try "read") -n : toggle using old BLIF parser without hierarchy support [default = %s] -m : toggle saving original circuit names into a file [default = %s] -a : toggle creating AIG while reading the file [default = %s] usage: read_blif_mv [-ch] reads the network in BLIF-MV format usage: read_bench [-ch] reads the network in BENCH format usage: read_dsd [-h] parses a formula representing DSD of a function -h : prints the command summary formula : the formula representing disjoint-support decomposition (DSD) Example of a formula: !(a*(b+CA(!d,e*f,c))*79B3(g,h,i,k)) where '!' is an INV, '*' is an AND, '+' is an XOR, CA and 79B3 are hexadecimal representations of truth tables (in this case CA=11001010 is truth table of MUX(Data0,Data1,Ctrl)) The lower chars (a,b,c,etc) are reserved for elementary variables. The upper chars (A,B,C,etc) are reserved for hexadecimal digits. No spaces are allowed in formulas. In parentheses, LSB goes first. usage: read_eqn [-ch] reads the network in equation format usage: read_fins [-vh] usage: read_init [-h] reads initial state of the network in BENCH format zbdxchusage: read_pla [-zbdxch] reads the network in PLA -z : toggle reading on-set and off-set [default = %s] off-seton-set -b : toggle reading both on-set and off-set as on-set [default = %s] -d : toggle reading both on-set and dc-set as on-set [default = %s] -x : toggle reading Exclusive SOP rather than SOP [default = %s] usage: read_plamo [-mvh] reads the network in multi-output PLA -m : toggle dist-1 merge for cubes with identical outputs [default = %s] xfhReading truth table has failed. Deriving the network has failed. usage: read_truth [-xfh] creates network with node having given truth table -x : toggles between bin and hex representation [default = %s] hexbin -f : toggles reading truth table from file [default = %s] truth : truth table with most signficant bit first (e.g. 1000 for AND(a,b)) file : file name with the truth table mcbhusage: read_verilog [-mcbh] reads the network in Verilog (IWLS 2002/2005 subset) Cannot open input file "%s". usage: read_status [-ch] reads verification log file usage: &read_gig [-h] reads design in GIG format usage: read_json [-h] reads file in JSON format int IoCommandWrite(Abc_Frame_t *, int, char **)write_genlib %swrite_liberty %sdsd_save %susage: write [-h] writes the current network into by calling the writer that matches the extension of -h : print the help massage file : the name of the file to write usage: write_hie [-h] the hierarchical writer that matches the extension of -m : toggle reading mapped Verilog for [default = %s] orig : the name of the original file with the hierarchical design scuvhWriting this format is only possible for structurally hashed AIGs. usage: write_aiger [-scuvh] writes the network in the AIGER format (http://fmv.jku.at/aiger) -s : toggle saving I/O names [default = %s] -c : toggle writing more compactly [default = %s] file : the name of the file to write (extension .aig) There is no current CEX. usage: write_aiger_cex [-h] writes the current CEX in the AIGER format (http://fmv.jku.at/aiger) usage: write_baf [-h] writes the network into a BLIF file file : the name of the file to write (extension .baf) usage: write_bblif [-h] writes the network into a binary BLIF file file : the name of the file to write (extension .bblif) Sjahusage: write_blif [-S str] [-jah] -S str : string representing the LUT structure [default = %s] -j : enables special BLIF writing [default = %s] -a : enables hierarchical BLIF writing for LUT structures [default = %s] file : the name of the file to write (extension .blif) usage: write_blif_mv [-h] writes the network into a BLIF-MV file file : the name of the file to write (extension .mv) usage: write_bench [-lh] writes the network in BENCH format -l : toggle using LUTs in the output [default = %s] file : the name of the file to write (extension .bench) usage: write_book [-h] [-options] -h : prints the help massage file : the name of the file to write (extension .aux, .nodes, .nets) This command is developed by Myungchul Kim (University of Michigan). The network should be a logic network (if it an AIG, use command "logic") usage: write_cellnet [-h] writes the network is the cellnet format nfpcvhusage: write_cnf [-nfpcvh] generates CNF for the miter (see also "&write_cnf") -f : toggle using fast algorithm [default = %s] -p : toggle using all primes to enhance implicativity [default = %s] -c : toggle adjasting polarity of internal variables [default = %s] KaiovhIoCommandWriteCnf2(): There is no AIG. IoCommandWriteCnf2(): Works only for combinational miters. IoCommandWriteCnf2(): Invalid LUT size (%d). IoCommandWriteCnf2(): Cannot input precomputed DSD information. usage: &write_cnf [-Kaiovh] writes CNF produced by a new generator -K : the LUT size (3 <= num <= 8) [default = %d] -a : toggle using new algorithm [default = %s] -i : toggle using AIG object IDs as CNF variables [default = %s] -o : toggle adding OR clause for the outputs [default = %s] -h : print the help massage file : the name of the file to write CNF variable mapping rules: Assume CNF has N variables, with variable IDs running from 0 to N-1. Variable number 0 is not used in the CNF. Variables 1, 2, 3,... represent POs in their natural order. Variables N-, N-+1, N-+2, ... N-1, represent PIs in their natural order. The internal variables are ordered in a reverse topological order from outputs to inputs. That is, smaller variable IDs tend to be closer to the outputs, while larger variable IDs tend to be closer to the inputs. It was found that this ordering leads to faster SAT solving for hard UNSAT CEC problems. usage: write_dot [-h] writes the current network into a DOT file snmueocafzvhIoCommandWriteCex(): Cannot open the output file "%s". # # # CEX for output %d # # DONE @0%s%s=%c usage: write_cex [-snmueocfzvh] saves counter-example (CEX) derived by "sat", "iprove", "dprove", etc the output file contains values for each PI in natural order -s : always report a sequential CEX (cycle 0 for comb) [default = %s] -n : write input names into the file [default = %s] -m : minimize CEX by dropping don't-care values [default = %s] -u : use fast SAT-based CEX minimization [default = %s] -e : use high-effort SAT-based CEX minimization [default = %s] -o : use old CEX minimization algorithm [default = %s] -c : check generated CEX using ternary simulation [default = %s] -a : print cex in AIGER 1.9 format [default = %s] -f : enable printing flop values in each timeframe [default = %s] -z : toggle using saved flop names [default = %s] -v : enable verbose output [default = %s] : the name of the file to write usage: write_eqn [-h] writes the current network in the equation format usage: write_gml [-h] writes network using graph representation formal GML Mmhusage: write_pla [-M ] [-mh] writes the collapsed network into a PLA file -M : the number of on-set minterms to write [default = %d] -m : toggle writing multi-output PLA [default = %s] usage: write_verilog [-ah] writes the current network in Verilog format -a : toggle writing expressions with only ANDs (without XORs and MUXes) [default = %s] NQhusage: write_sorter_cnf [-N ] [-Q ] writes CNF for the sorter -N num : the number of sorter bits [default = %d] -Q num : the number of bits to be asserted to 1 [default = %d] xrhusage: write_truth [-xrh] writes truth table into a file -r : toggle reversing bits in the truth table [default = %s] rbhIoCommandWriteTruths(): There is no AIG. IoCommandWriteTruths(): Can write truth tables up to 16 inputs. IoCommandWriteTruths(): Can write truth tables for 3 inputs or more. usage: &write_truths [-rbh] writes truth tables of each PO of GIA manager into a file -b : toggle using binary format [default = %s] usage: write_status [-h] writes verification log file usage: write_smv [-h] write the network in SMV format -h : print the help message file : the name of the file to write (extension .smv) No JSON info is available. usage: write_json [-ch] write the network in JSON format -c : output extracted version file : the name of the file to write (extension .json) File name should be given on the command line.File name is missing on the command line.Warning: Selected option to write all primes has no effect when deriving CNF from AIG.Current network should not an AIG. Run "logic".Can only write logic function with no more than 16 inputs.Can only write logic function with 0 inputs.Current network should have exactly one node.Current network should have exactly one primary output.Current network is not available.Counter-example minimization has failed.nYMYYMYMYMYMYMYMYMYMYMYMYMYMYMYMYMYMYMYMYMYMYMYMYMYMYMYMYMYMYMYnYMYYInputLayerinput Conv2Dconvo BatchNormalizationbatch Activationrelu AddeltwiseMaxPooling2Dpool GlobalAveragePooling2DDensefullconZeroPadding2DpadVec_IntSize(vArray) % 2 != 0src/base/io/ioJson.cvoid Json_Extract_rec(FILE *, Abc_Nam_t *, Vec_Wec_t *, Vec_Int_t *, int, int *)class_name %3d : %-8s N=%s ???kernel_size K=stridesfilters C=%sinbound_nodeslayersconfig# Data extracted from JSON file: [][ "%s" ]%*s"%s"%s %*s]void Json_Write_rec(FILE *, Abc_Nam_t *, Vec_Wec_t *, Vec_Int_t *, int, int, int)%*s"%s"%*s}%s test.json!Json_EntryIsName(Fan)Vec_Int_t *Json_EntryNode(Vec_Wec_t *, int)8YI9Y+Y+Y8Y+Y+Y8Y8Y+Y?9Y+Y+Y8Y.bz2.gzThe parameter line is in a wrong format. The number of objects does not match. Reading AIGER files with liveness properties is currently not supported. Warning: The last output is interpreted as a constraint. Warning: The last %d outputs are interpreted as constraints. Vec_PtrSize(vNodes) == i + 1 + nInputs + nLatchessrc/base/io/ioReadAiger.cAbc_Ntk_t *Io_ReadAiger(char *, int)Init == Abc_Var2Lit(1+Abc_NtkPiNum(pNtkNew)+i, 0)The initial value of latch number %d is not recongnized. The number of terminal is out of bound. Ioa_ReadLoadFileBz2(): BZ2_bzReadOpen() failed with error %d. amtRead != -1char *Ioa_ReadLoadFileGzAig(char *, int *)Io_ReadAiger: The network check has failed.Ioa_ReadLoadFileBz2(): Unable to read the compressed BLIF.Ioa_ReadLoadFileBz2(): The file is empty.Ioa_ReadLoadFileBz2(): The file is unavailable (absent or open).Io_ReadBaf: The network check has failed.Warning: Internal reader error.src/base/io/ioReadBblif.cAbc_Ntk_t *Bbl_ManToAbc(Bbl_Man_t *)!Bbl_ObjIsMarked(pObj)void Bbl_ManDfs_rec(Bbl_Obj_t *, Vec_Ptr_t *)test.bblifABC to ManWriting Reading Man to ABCVerify Runtime stats:Bbl_ManToAbc(): Network check has failed. ,()=Io_ReadBenchInit(): Failed to open file "%s". Io_ReadBenchInit(): Cannot find register with output %s. Io_ReadBenchInit(): The signal is not a register output %s. Io_ReadBenchInit(): The signal %s has unknown initial value (%s). %s: Wrong input file format. OUTPUT%s: Currently cannot read truth tables with more than 8 inputs (%d). %s: The LUT signature (%s) does not look like a hexadecimal beginning with "0x". %s: Reading hexadecimal number (%s) has failed. nNames > 0src/base/io/ioReadBench.cAbc_Ntk_t *Io_ReadBenchNetwork(Extra_FileReader_t *)%s: Reading truth table (%s) of single-input node has failed. nxorgndvddIo_ReadBenchNetwork(): Cannot determine gate type "%s" in line %d. Io_ReadBench: The network check has failed.Io_ReadBenchNetwork(): Converting to BDD has failed.Io_ReadBenchNetwork(): Converting to SOP has failed.Io_ReadBenchNetwork(): Adding constant 1 fanin to non-driven net "2".Io_ReadBenchNetwork(): Adding constant 0 fanin to non-driven net "1".src/base/io/ioReadBlif.cint Io_ReadBlifReorderFormalNames(Vec_Ptr_t *, Mio_Gate_t *, Mio_Gate_t *)Cannot parse formal/actual name pair "%s".Cannot find formal input "%s" as an PI of model "%s".Formal input "%s" is used more than once.Formal input "%s" of model %s is not driven.Cannot find formal output "%s" as an PO of model "%s".Formal output "%s" is used more than once.Formal output "%s" of model %s is not driven.Wrong input file format..exdcp->vTokens != NULLAbc_Ntk_t *Io_ReadBlifNetworkOne(Io_ReadBlif_t *)The .model line does not have exactly two entries.%s: File parsing skipped after line %d ("%s"). .gate.latch.input_arrival.output_required.default_input_arrival.default_output_required.input_drive.output_load.default_input_drive.default_output_load.and_gate_delay.blackbox%s (line %d): Skipping directive "%s". The .names line has less than two tokens.The number of tokens in the constant cube is wrong.The number of tokens in the cube is wrong.The output character in the constant cube is wrong.The number of fanins (%d) of node %s is different from SOP size (%d).p->pNtkCur->ntkFunc == ABC_FUNC_SOPint Io_ReadBlifNetworkGate(Io_ReadBlif_t *, Vec_Ptr_t *)ppNames[nNames] != NULL || ppNames[nNames+1] != NULLThe .latch line does not have enough tokens.The .latch line has an unknown reset value (%s).strncmp( (char *)vTokens->pArray[0], ".input_arrival", 14 ) == 0int Io_ReadBlifNetworkInputArrival(Io_ReadBlif_t *, Vec_Ptr_t *)Wrong number of arguments on .input_arrival line.Cannot find object corresponding to %s on .input_arrival line.Bad value (%s %s) for rise or fall time on .input_arrival line.strncmp( (char *)vTokens->pArray[0], ".output_required", 16 ) == 0int Io_ReadBlifNetworkOutputRequired(Io_ReadBlif_t *, Vec_Ptr_t *)Wrong number of arguments on .output_required line.Cannot find object corresponding to %s on .output_required line.Bad value (%s %s) for rise or fall time on .output_required line.strncmp( (char *)vTokens->pArray[0], ".default_input_arrival", 23 ) == 0int Io_ReadBlifNetworkDefaultInputArrival(Io_ReadBlif_t *, Vec_Ptr_t *)Wrong number of arguments on .default_input_arrival line.Bad value (%s %s) for rise or fall time on .default_input_arrival line.strncmp( (char *)vTokens->pArray[0], ".default_output_required", 25 ) == 0int Io_ReadBlifNetworkDefaultOutputRequired(Io_ReadBlif_t *, Vec_Ptr_t *)Wrong number of arguments on .default_output_required line.Bad value (%s %s) for rise or fall time on .default_output_required line.strncmp( (char *)vTokens->pArray[0], ".input_drive", 12 ) == 0int Io_ReadBlifNetworkInputDrive(Io_ReadBlif_t *, Vec_Ptr_t *)Wrong number of arguments on .input_drive line.Cannot find object corresponding to %s on .input_drive line.Bad value (%s %s) for rise or fall time on .input_drive line.strncmp( (char *)vTokens->pArray[0], ".output_load", 12 ) == 0int Io_ReadBlifNetworkOutputLoad(Io_ReadBlif_t *, Vec_Ptr_t *)Wrong number of arguments on .output_load line.Cannot find object corresponding to %s on .output_load line.Bad value (%s %s) for rise or fall time on .output_load line.strncmp( (char *)vTokens->pArray[0], ".default_input_drive", 21 ) == 0int Io_ReadBlifNetworkDefaultInputDrive(Io_ReadBlif_t *, Vec_Ptr_t *)Wrong number of arguments on .default_input_drive line.Bad value (%s %s) for rise or fall time on .default_input_drive line.strncmp( (char *)vTokens->pArray[0], ".default_output_load", 21 ) == 0int Io_ReadBlifNetworkDefaultOutputLoad(Io_ReadBlif_t *, Vec_Ptr_t *)Wrong number of arguments on .default_output_load line.Bad value (%s %s) for rise or fall time on .default_output_load line.strncmp( (char *)vTokens->pArray[0], ".and_gate_delay", 25 ) == 0int Io_ReadBlifNetworkAndGateDelay(Io_ReadBlif_t *, Vec_Ptr_t *)Wrong number of arguments (%d) on .and_gate_delay line (should be 1).Bad value (%s) for AND gate delay in on .and_gate_delay line line.%s: %s %s (line %d): %s Io_ReadBlif: The network check has failed. .end Line %d: Skipping line "%s". !strcmp(pToken, "model")src/base/io/ioReadBlifAig.cint Io_BlifParseModel(Io_BlifMan_t *, char *)Line %d: Model line has %d entries while it should have 2.!strcmp(pToken, "inputs")int Io_BlifParseInputs(Io_BlifMan_t *, char *)Line %d: Primary input (%s) is defined more than once.p->iObjNext < p->nObjectsIo_BlifObj_t *Io_BlifHashFindOrAdd(Io_BlifMan_t *, char *)!strcmp(pToken, "outputs")int Io_BlifParseOutputs(Io_BlifMan_t *, char *)Line %d: Primary output (%s) is defined more than once (warning only). !strcmp(pToken, "latch")int Io_BlifParseLatch(Io_BlifMan_t *, char *)Line %d: Latch does not have input name and output name.Line %d: Initial state of the latch is incorrect (%s).Line %d: Primary input (%s) is also defined latch output.Line %d: Latch output (%s) is defined as the output of another latch.!strcmp((char *)Vec_PtrEntry(p->vTokens,0), "names")int Io_BlifParseNames(Io_BlifMan_t *, char *)Line %d: Primary input (%s) has a table.Line %d: Latch output (%s) has a table.Line %d: Signal (%s) is defined more than once.The number of dangling tables = %d. AND nodes = %6d. Estimate = %6d. Line %d: Signal (%s) is not defined as a table.Line %d: Signal (%s) appears twice on a combinational path.Line %d: Constant table has wrong output value (%s).Line %d: Table has odd number of tokens (%d).Line %d: Cube (%s) has size different from the fanin count (%d).Line %d: Output value (%s) is incorrect.Line %d: Output value (%s) differs from the value in the first line of the table (%d).Line %d: Product term (%s) contains character (%c). 5 QIo_Blif: The network check has failed.Io_Blif(): The file is unavailable (absent or open).Io_BlifLoadFile(): The file is empty.Io_BlifLoadFile(): The file is unavailable (absent or open).%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%Z%ZIo_ReadBlifMv: The network check has failed for model %s. EXDCpNtk->pExdc == NULLsrc/base/io/ioReadBlifMv.cAbc_Ntk_t *Io_ReadBlifMv(char *, int, int)Warning: The design has %d root-level modules. The first one (%s) will be used. Vec_PtrSize(pDesign->vModules) > 0Io_MvLoadFileBz2(): The file is unavailable (absent or open). Io_MvLoadFileBz2(): BZ2_bzReadOpen() failed with error %d. Io_MvLoadFileBz2(): The file is empty. Io_MvLoadFileBz2(): Unable to read the compressed BLIF. char *Io_MvLoadFileGz(char *, int *)def ltlformulareset constraintWarning: The design contains EXDC network. attribinput_output_no_mergeLine %d: Model %s is defined twice.int Io_MvParseLineModel(Io_MvMod_t *, char *)int Io_MvParseLineInputs(Io_MvMod_t *, char *)int Io_MvParseLineOutputs(Io_MvMod_t *, char *)!strcmp(pToken, "constraint")int Io_MvParseLineConstrs(Io_MvMod_t *, char *)strcmp( "ltlformula", keyWordLtlFormula ) == 0int Io_MvParseLineLtlProperty(Io_MvMod_t *, char *)Line %d: Model %s has different number of latches (%d) and reset nodes (%d).Parsed %d groups of 1-hot registers: { The total number of 1-hot registers = %d. (%.2f %%) _1h.blifOne-hotness condition is written into file "%s". Warning: The parser converted %d .flop lines into .latch lines Warning: The parser added %d constant 0 nodes to replace non-deterministic nodes. !strcmp(pName, "mv")int Io_MvParseLineMv(Io_MvMod_t *, char *)Line %d: The number of values in not specified in .mv line.Line %d: The number of values (%d) is incorrect (should be >= 2 and <= %d).Line %d: Wrong number (%d) of symbolic value names (should be %d).Line %d: Symbolic value name "%s" is repeated in .mv line.!p->pMan->fBlifMvint Io_MvParseLineFlop(Io_MvMod_t *, char *)!strcmp(pToken, "flop")Line %d: Cannot find flop output.Line %d: Cannot find flop input.init=Line %d: Cannot read flop init value %s.int Io_MvParseLineLatch(Io_MvMod_t *, char *)Warning: Line %d has .latch directive with unrecognized entries (the total of %d entries). Line %d: Initial state of the latch is incorrect "%s".int Io_MvParseLineNamesMv(Io_MvMod_t *, char *, int)Line %d: Multi-output node symbol (->) in binary BLIF file.!strcmp((char *)Vec_PtrEntry(vTokens,0), "r") || !strcmp((char *)Vec_PtrEntry(vTokens,0), "reset")!strcmp((char *)Vec_PtrEntry(vTokens,0), "names") || !strcmp((char *)Vec_PtrEntry(vTokens,0), "table")pFirst[1] == 'd'Line %d: Wrong number of literals in the table of node "%s". (Spaces inside literals are not allowed.)p->pResetLatch != NULLAbc_Obj_t *Io_MvParseAddResetCircuit(Io_MvMod_t *, char *)_reset1 - - =1 0 - - =2 pFlex != NULLIo_MvVar_t *Abc_NtkMvVarDup(Abc_Ntk_t *, Io_MvVar_t *)Line %d: Latch with output signal "%s" does not exist.nInputs == Vec_PtrSize(vTokens) - 2int Io_MvParseLineNamesMvOne(Io_MvMod_t *, Vec_Ptr_t *, Vec_Ptr_t *, int, int, int, int)Line %d: Signal "%s" is defined more than once.Line %d: Node name in the table "%s" cannot be found on .names line.iLit < Abc_ObjFaninNum(pNode)int Io_MvParseLiteralMv(Io_MvMod_t *, Abc_Obj_t *, char *, Vec_Str_t *, int)Line %d: Cannot find value name "%s" among the value names of variable "%s".int Io_MvParseLineNamesBlif(Io_MvMod_t *, char *)!strcmp((char *)Vec_PtrEntry(vTokens,0), "names")Line %d: The current library is not available.Line %d: The .gate line has less than two tokens.Line %d: Cannot find gate "%s" in the library.int Io_MvParseLineGateBlif(Io_MvMod_t *, Vec_Ptr_t *)pModel->ntkFunc == ABC_FUNC_SOPLine %d: Mismatch in the fanins of gate "%s".Line %d: Invalid gate input assignment.Line %d: Constant table has wrong output value "%s".Line %d: Cube "%s" has size different from the fanin count (%d).Line %d: Output value "%s" is incorrect.Line %d: Output value "%s" differs from the value in the first line of the table (%d).int Io_MvParseLineShortBlif(Io_MvMod_t *, char *)Line %d: Expecting three entries in the .short line.!strcmp((char *)Vec_PtrEntry(vTokens,0), "short")Line %d: Cannot find buffer gate in the library.!strcmp(pToken, "subckt")int Io_MvParseLineSubckt(Io_MvMod_t *, char *)Line %d: Cannot find the model for subcircuit %s.!strcmp(pToken, "onehot")Vec_Int_t *Io_MvParseLineOnehot(Io_MvMod_t *, char *)Line %d: Signal with name "%s" does not exist in the model "%s".Line %d: Signal with name "%s" is not a register in the model "%s".Io_ReadBlifMv(): The file is unavailable (absent or open).Io_MvLoadFile(): The file is empty.Io_MvLoadFile(): The file is unavailable (absent or open).(information about set, reset, enable of the flops may be lost).*pCur == '('src/base/io/ioReadDsd.cchar *Io_ReadDsdFindEnd(char *)*pCurint Io_ReadDsdStrSplit(char *, char **, int *)pCur[strlen(pCur)-1] == ')'Abc_Obj_t *Io_ReadDsd_rec(Abc_Ntk_t *, char *, char *)*(pCur+1) == 0Io_ReadDsd(): Network check has failed. Wrong separating symbol.Different types of separating symbol ennPartsed.Cannot find the closing parenthesis.Cannot find the opening parenthesis.Cannot find the end of hexidecimal truth table.Currently this parser does not work!INORDEROUTORDER!*+()Io_ReadEqn: The network check has failed.iVar >= 0 && iVar < nWords*32src/base/io/ioReadPla.cint Io_ReadPlaSelfSubsumption(word **, int, int, Vec_Bit_t *)c == nCubesword **Io_ReadPlaCubeSetup(Vec_Str_t *)Cover %5d : V =%5d C%d =%5d |./src/misc/vec/vecBit.hvoid Vec_BitGrow(Vec_Bit_t *, int)int Vec_BitEntry(Vec_Bit_t *, int)void Vec_BitWriteEntry(Vec_Bit_t *, int, int).type%s (line %d): Wrong number of token. .i.o.p.ilbWarning: Mismatch between the number of PIs on the .i line (%d) and the number of PIs on the .ilb line (%d). .obWarning: Mismatch between the number of POs on the .o line (%d) and the number of POs on the .ob line (%d). %s: The number of inputs is not specified. %s: The number of outputs is not specified. z%0*d%s (line %d): Input and output cubes are not specified. %s (line %d): Input cube length (%d) differs from the number of inputs (%d). %s (line %d): Output cube length (%d) differs from the number of outputs (%d). Warning: Mismatch between the number of cubes (%d) and the number on .p line (%d). -01Io_ReadPla: The network check has failed.Mop_ManLoadFile(): The file is unavailable (absent or open). Mop_ManLoadFile(): The file is empty. .i Cannot read cube %d (%s). iCube < nCubessrc/base/io/ioReadPlaMo.cMop_Man_t *Mop_ManRead(char *).%d Mop_ManCheckDist1(pCube1, pCube2, p->nWordsIn)int Mop_ManMergeDist1Pairs(Mop_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, int)!memcmp(pCube1, pCube2, sizeof(word)*p->nWordsOut)memcmp(pCube1Out, pCube2Out, sizeof(word)*p->nWordsOut)int Mop_ManMergeDist1Pairs2(Mop_Man_t *, Vec_Int_t *, Vec_Int_t *)Removed == Count1 + Count2 + Count3void Mop_ManReduce2(Mop_Man_t *)Cubes: %d -> %d. C = %d. M = %d. C = %d. M = %d. C = %d. Output lits: %d -> %d. Total = %d. Reduced %d equal and %d contained cubes. Output lits: %d -> %d. int Mop_ManFindDiffVar(word *, word *, int)-01?Detected constant-1 cover.Warning: The design has %d root-level modules: src/base/io/ioReadVerilog.cAbc_Ntk_t *Io_ReadVerilog(char *, int)ZZZZZZZZZZZZZZZZZZHZ^ZZZrZZZZZiZZZZZZZZedifGeneric file reader requires a known file extension to open "%s". .bafReading AIG from file has failed. Unknown file format. Vec_PtrSize( tempStore ) == Vec_PtrSize( pNtk->vLtlProperties )src/base/io/ioUtil.cVec_Ptr_t *temporaryLtlStore(Abc_Ntk_t *)tempLtlStore != NULLvoid updateLtlStoreOfNtk(Abc_Ntk_t *, Vec_Ptr_t *)Abc_Ntk_t *Io_Read(char *, Io_FileType_t, int, int)Flattening logic hierarchy has failed. Hierarchy reader converted %d instances of blackboxes. Converting blackboxes has failed. Converting BLIF-MV to AIG has failed. Converting netlist to logic network after reading has failed. The generic file writer requires a known file extension. Writing Binary BLIF is only possible for logic networks. PLA writing is available for collapsed networks. Latches are writen into the PLA file at PI/PO pairs. Writing traditional BENCH is available for AIGs only (use "write_bench"). Writing traditional SMV is available for AIGs only. Converting to netlist has failed. void Io_WriteHie(Abc_Ntk_t *, char *, char *)Unknown input file format. Hierarchy writer replaced %d barbufs by hierarchy boundaries. Hierarchy writer reintroduced %d instances of blackboxes. Unknown output file format. Warning: PI "%s" appears twice in the list. Warning: PO "%s" appears twice in the list. pNetAbc_Obj_t *Io_ReadCreateConst(Abc_Ntk_t *, char *, int)Abc_Obj_t *Io_ReadCreateInv(Abc_Ntk_t *, char *, char *)Abc_Obj_t *Io_ReadCreateBuf(Abc_Ntk_t *, char *, char *)%s/%sUsing file %s Warning: The output network does not contain blackboxes.Hierarchy writer does not support BLIF-MV with blackboxes.$ZEZLZ$ZTZuZ|ZTZTZuZ|ZTZsrc/base/io/ioWriteAiger.cvoid Io_WriteAiger_old(Abc_Ntk_t *, char *, int, int)Io_WriteAiger(): Cannot write AIGER format with non-0 latch init values. Run "zero". Io_WriteAiger(): Cannot open the output file "%s". aig%s %u %u %u %u %u%u 1 Abc_LatchIsInitNone(pLatch) || Abc_LatchIsInitDc(pLatch)uLit1 < uLitPos < nBufferSizei%d %s l%d %s o%d %s b%d %s c%d %s This file was produced by ABC on %s For information about AIGER format, refer to %s http://fmv.jku.at/aigervoid Io_WriteAigerGz(Abc_Ntk_t *, char *, int)Io_WriteAigerGz(): Cannot open the output file "%s". aig %u %u %u %u %uIoa_WriteBlif(): I/O error writing to compressed stream. void Io_WriteAiger(Abc_Ntk_t *, char *, int, int, int)Ioa_WriteBlif(): Cannot open the output file "%s". Ioa_WriteBlif(): Cannot start compressed stream. Io_WriteAiger(): I/O error writing to compressed stream. %s%c This file was written by ABC on %s Io_WriteAiger(): I/O error closing compressed stream. pCex != NULLvoid Io_WriteAigerCex(Abc_Cex_t *, Abc_Ntk_t *, void *, char *)b == pCex->nBitsIo_WriteAiger(): AIGER generation has failed because the allocated buffer is too small.AIG parameters do not match those of the CEX.src/base/io/ioWriteBaf.cvoid Io_WriteBaf(Abc_Ntk_t *, char *)Io_WriteBaf(): Cannot open the output file "%s". # BAF (Binary Aig Format) for "%s" written by ABC on %s %d%cnBufferSize == nAndssrc/base/io/ioWriteBblif.cBbl_Man_t *Bbl_ManFromAbc(Abc_Ntk_t *)Abc_NtkIsSopNetlist(pNtk)src/base/io/ioWriteBench.cint Io_WriteBench(Abc_Ntk_t *, const char *)Io_WriteBench(): Signal names in this benchmark contain parentheses making them impossible to reproduce in the BENCH format. Use "short_names". Io_WriteBench(): Cannot open the output file. # Benchmark "%s" written by ABC on %s Abc_NtkIsAigNetlist(pNtk)int Io_WriteBenchLut(Abc_Ntk_t *, char *)Io_WriteBenchLut(): Signal names in this benchmark contain parentheses making them impossible to reproduce in the BENCH format. Use "short_names". INPUT(%s) OUTPUT(%s) %-11s = DFF(%s) int Io_WriteBenchOneNode(FILE *, Abc_Obj_t *)Abc_NodeIsConst1(pNode)%-11s%-11s = BUFF(%-11s = NOT( = AND(%s, %-11s = DFFRSE( %s, gnd, gnd, gnd, gnd ) int Io_WriteBenchLutOneNode(FILE *, Abc_Obj_t *, Vec_Int_t *)nFanins <= 8%-11s = gnd %-11s = vdd %-11s = LUT 0x%d ( %s ) %-11s = LUT 0xIo_WriteBench: EXDC is not written (warning).src/base/io/ioWriteBlif.cvoid Io_WriteBlif(Abc_Ntk_t *, char *, int, int, int)Io_WriteBlif(): Cannot open the output file. .attrib white box seq .attrib white box comb .delay 1 %s_in .latch %s_in %s 1 m%d \ %c=%s%s=%s i == Abc_ObjFaninNum(pNode)int Io_NtkWriteNodeGate(FILE *, Abc_Obj_t *, int)Warning: Missing second output of gate(s) "%s". %s=%s.and_gate_delay %g .default_input_arrival %g %g .default_output_required %g %g .input_arrival %s %g %g .output_required %s %g %g .default_input_drive %g %g .input_drive %s %g %g .default_output_load %g %g .output_load %s %g %g char *Io_NtkDeriveSop(Mem_Flex_t *, word, int, Vec_Int_t *)Node "%s" has more than 7 inputs. Writing BLIF has failed. nVarsMin[0] < 5void Io_NtkWriteNodeInt(FILE *, Abc_Obj_t *, Vec_Int_t *)nVarsMin[1] < 5 %s_cascade0 %s_cascade11-1 1 01- 1 %s_cascade%d nVars == 6 || nVars == 7Node "%s" is not decomposable. Writing BLIF has failed. %s_cascadeWrong LUT struct (%s) The LUT size (%d) should belong to {3,4,5,6}. The node size (%d) is too large for the LUT structure %s. .names %s %d %s_lut1 %s_lut1 %s_lut2 %s_lut2.model m%d %c lut1 lut1 lut2 lut2void Io_WriteBlifInt(Abc_Ntk_t *, char *, char *, int)Io_WriteBlifInt(): Cannot open the output file. void Io_WriteBlifSpecial(Abc_Ntk_t *, char *, char *, int)void Io_NtkWrite(FILE *, Abc_Ntk_t *, int, int, int).exdc .blackbox .subckt %s.barbuf %10ssrc/base/io/ioWriteBlifMv.cvoid Io_WriteBlifMv(Abc_Ntk_t *, char *)Io_WriteBlifMv(): Cannot open the output file. void Io_NtkWriteBlifMv(FILE *, Abc_Ntk_t *).end .mv %s %d .reset %s .subckt %s %s.table.default Io_NtkWriteBlifMv(): EXDC is not written.Writing BOOK has failed. src/base/io/ioWriteBook.cvoid Io_WriteBook(Abc_Ntk_t *, char *).nodes.nets.auxIo_WriteBook(): Cannot open the output files. RowBasedPlacement : %s.nodes %s.nets %s.scl %s.pl %s.wts.sclunsigned int Io_NtkWriteNodes(FILE *, Abc_Ntk_t *)NumNodes : %d NumTerminals : %d UCLA nodes 1.0 NumNodes : %d i%s_input terminal o%s_output %s_%s_latch name Abc_NtkHasSop(pNode->pNtk)unsigned int Io_NtkWriteIntNode(FILE *, Abc_Obj_t *, int)isize > 2unsigned int Io_NtkWriteNodeGate(FILE *, Abc_Obj_t *)%s_%s int Abc_NodeIsNand2(Abc_Obj_t *)-0 1 0- 1 0- 1 -0 1 int Abc_NodeIsNor2(Abc_Obj_t *)int Abc_NodeIsOr2(Abc_Obj_t *)01 0 10 0 int Abc_NodeIsXor2(Abc_Obj_t *)10 1 01 1 void Io_NtkWriteNets(FILE *, Abc_Ntk_t *)NumNets : %d NumPins : %d UCLA nets 1.0 NumNets : %d NumPins : %d NetDegree : %d %s i%s_input I %s_%s_latch I : name I : %.2f %.2f o%s_output O %s_%s_latch O : name O : Core cell height(==site height) is %d Total core cell width is %d giving an ave width of %f Area : %f WS%% : %f AR : %f Width : %f Height: %f (%d rows) AR : %f UCLA scl 1.0 Numrows : %d CoreRow Horizontal Coordinate : %d Height : %d Sitewidth : %d Sitespacing : %d Siteorient : %s Sitesymmetry : %c SubrowOrigin : %d Numsites : %d End termsOnTop+termsOnBottom+termsOnLeft+termsOnRight == (unsigned)Vec_PtrSize(vOrderedTerms)void Io_NtkWritePl(FILE *, Abc_Ntk_t *, unsigned int, double, double)Terminals: %d Top: %d Bottom: %d Left: %d Right: %d UCLA pl 1.0 i%s_input o%s_output %d %d : %s /FIXED FW %d %d : %s termCount==numTermsVec_Ptr_t *Io_NtkOrderingPads(Abc_Ntk_t *, Vec_Ptr_t *)Abc_ObjIsPi(pTerm) || Abc_ObjIsPo(pTerm)Abc_Obj_t *Io_NtkBfsPads(Abc_Ntk_t *, Abc_Obj_t *, unsigned int, int *)Abc_ObjIsNode(pNeighbor) || Abc_ObjIsTerm(pNeighbor)<Target Dimensions:Actual Dimensions:Done constructing layout regionIo_WriteCnf(): Currently can only process the miter (the network with one PO). Io_WriteCnf(): Currently can only process the miter for combinational circuits. The network has no logic nodes. No CNF file is generaled. The problem is trivially UNSAT. No CNF file is generated. c PI variable numbers: c %s %d Io_WriteCnf() warning: Generating CNF by convering logic nodes into CNF clauses.Io_WriteCnf() warning: Generating CNF by applying heuristic AIG to CNF conversion.src/base/io/ioWriteDot.cvoid Io_WriteDotNtk(Abc_Ntk_t *, Vec_Ptr_t *, Vec_Ptr_t *, char *, int, int)The set has more than %d nodes. DOT file is not written. LevelMax == LevelMin# %s Network structure generated by ABCdigraph network { edge [dir = back]; node [shape = plaintext]; edge [style = invis]; LevelTitle1 [label=""]; LevelTitle2 [label=""]; Level%d [label = LevelTitle1 -> LevelTitle2 -> rank = same; LevelTitle1; title1 [shape=plaintext, fontsize=20, fontname = "Times-Roman", label="Network structure visualized by ABCBenchmark \"%s\". Time was %s. ]; LevelTitle2; title2 [shape=plaintext, fontsize=18, The network contains %d logic nodes and %d latches.The set contains %d logic nodes and spans %d levels. Level%d; Node%d [label = "%s%s", shape = %sinvtriangle, style = filled, color = coral, fillcolor = coral Node%d [label = "%d\n%s", shape = ellipse Node%d [label = "Const%d" Node%d [label = "%s"title1 -> title2 [style = invis]; title2 -> Node%d [style = invis]; Node%d -> Node%d [style = invis]; Node%d [style = %sdottedsolidvoid Io_WriteDotSeq(Abc_Ntk_t *, Vec_Ptr_t *, Vec_Ptr_t *, char *, int, int) Node%d [label = "Const1", shape = boxIo_WriteDotNtk(): Converting to SOPs has failed.The set has no nodes. DOT file is not written.src/base/io/ioWriteEqn.cvoid Io_WriteEqn(Abc_Ntk_t *, char *)Io_WriteEqn(): Cannot open the output file "%s". # Equations for "%s" written by ABC on %s INORDER =OUTORDER =The network cannot be written in the EQN format because object %d has name "%s". Warning: only combinational portion is being written.Consider renaming the objects using command "short_names" and trying again.src/base/io/ioWriteGml.cvoid Io_WriteGml(Abc_Ntk_t *, char *)Io_WriteGml(): Cannot open the output file "%s". # GML for "%s" written by ABC on %s graph [ node [ id %5d label "%s" graphics [ type "triangle" fill "#00FFFF" ] ] graphics [ type "triangle" fill "#00FF00" ] graphics [ type "rectangle" fill "#FF0000" ] graphics [ type "ellipse" fill "#CCCCFF" ] edge [ source %5d target %5d graphics [ type "line" arrow "first" ] Io_WriteList(): Cannot open the output file "%s". # Adjacency list for sequential AIG "%s" # written by ABC on %s src/base/io/ioWriteList.cvoid Io_WriteCellNet(Abc_Ntk_t *, char *)Io_WriteCellNet(): Cannot open the output file "%s". # CellNet file for network "%s" written by ABC on %s cell %d is 0 cell %d is 1 cell %d is 2 cell %d is %d net %d %d 0 %d %d%-10s > ([%s_to_ %s ([%s_to_%s] = %d)HOSTAbc_ObjIsCi(pDriver)src/base/io/ioWritePla.cint Io_WritePlaOne(FILE *, Abc_Ntk_t *)!Abc_SopIsComplement( (char *)pDriver->pData )(int)(ABC_PTRUINT_T)pFanin->pCopy < nInputsAbc_ObjIsCi(pFanin).e int Io_WritePla(Abc_Ntk_t *, char *)Abc_NtkLevel(pNtk) == 1Io_WritePla(): Cannot open the output file. Vec_PtrSize(vFuncs) == Abc_NtkCoNum(pNtk)int Io_WriteMoPlaOneInt(FILE *, Abc_Ntk_t *, DdManager *, Vec_Ptr_t *)dd->size <= 1000nOutputs > 1dd->size == nInputs + nOutputsTrying %d output. Onset = %d nodes. Offset = %d nodes. Cover = %d nodes. ISOP = %d int Io_WriteMoPlaOneIntMinterms(FILE *, Abc_Ntk_t *, DdManager *, Vec_Ptr_t *)int Io_WriteMoPlaOne(FILE *, Abc_Ntk_t *)int Io_WriteMoPla(Abc_Ntk_t *, char *)int Io_WriteMoPlaOneIntMintermsM(FILE *, Abc_Ntk_t *, DdManager *, DdNode *, int)int Io_WriteMoPlaM(Abc_Ntk_t *, char *, int)Io_WriteMoPlaM(): Cannot open the output file. Io_WritePla: EXDC is not written (warning).Cannot write multi-output PLA for more than 16 inputs.Cannot write minterms because the size of the manager for local BDDs is not equal tothe number of primary inputs. (It is likely that the current network is not collapsed.)First primary output has constant 0 function.First primary output has constant 1 function.Io_WriteVerilog(): Cannot open the output file "%s". // Benchmark "%s" written by ABC on %s Abc_NtkIsNetlist(pNetlist)src/base/io/ioWriteVerilog.cvoid Io_WriteVerilog(Abc_Ntk_t *, char *, int)module %s ( clock, , input clock; output reg wirepSkipvoid Io_WriteVerilogPos(FILE *, Abc_Ntk_t *, int)Io_WriteVerilogPos(): Omitted %d feedthrough nets from output list of module (e.g. %s). Counter == nNodesvoid Io_WriteVerilogWires(FILE *, Abc_Ntk_t *, int) %s box%0*d_const0__const1_ %-*s %s = 1'b%d; assigni == Abc_ObjFaninNum(pObj)void Io_WriteVerilogObjects(FILE *, Abc_Ntk_t *, int) %-*s g%0*d assign %s = always @ (posedge clock) begin %s <= %s; end initial begin %s <= 1'b0; %s <= 1'b1; Io_WriteVerilog(): Can produce Verilog for mapped or AIG netlists only.src/base/io/ioWriteSmv.cint Io_WriteSmv(Abc_Ntk_t *, char *)Io_WriteSmv(): Signal names in this benchmark contain parentheses making them impossible to reproduce in the SMV format. Use "short_names". Io_WriteSmv(): Cannot open the output file. -- benchmark "%s" written by ABC on %s MODULE main VAR -- inputs %s : boolean; VAR -- state variables DEFINE ASSIGN Reset >= 1int Io_WriteSmvOne(FILE *, Abc_Ntk_t *)Reset <= 3 init(%s) := %d; next(%s) := assume_fair_FAIRNESS %s; Assert_assert_safety_INVARSPEC %s; assert_fair_LTLSPEC G F %s; strlen(s) < 1024char *cleanUNSAFE(const char *)int Io_WriteSmvOneNode(FILE *, Abc_Obj_t *) := 1; %s := %s := ! := %s & Io_WriteSmv: EXDC is not written (warning).namemodeThe current network has no primary outputs. Some commands may not work correctly. set checkreadq\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\q\]\q\q\]\q\q\q\q\q\q\q\q\q\q\^\q\]^\^\q\q\q\q\q\q\q\q\q\q\q\q\q\._\<_\~_\q\_\q\q\q\q\q\_\`\q\^`\q\y`\q\p]\`\q\q\q\Wa\dm:l:c:q:C:Q:S:hf:F:o:st:T:xbLimiting memory use to %d MB Limiting time to %d seconds source %ssource -x %sread_%swrite_%sABC command line: "%s". unknown type %s ABC_LIB_PATHlibabc_.soWarning: maximum number of ABC libraries (%d) exceeded. Not loading %s. %s/Loaded ABC library: %s (Abc library extension #%d) Warning: failed to load ABC library %s: %s Warning: failed to close library %d abc_initWarning: Failed to initialize library %d. abc_endWarning: Failed to end library %d. %s (compiled %s %s)UC Berkeley, ABC 1.01abc %02d> usage: %s [-c cmd] [-q cmd] [-C cmd] [-Q cmd] [-f script] [-h] [-o file] [-s] [-t type] [-T type] [-x] [-b] [file] -c cmd execute commands `cmd' -q cmd execute commands `cmd' quietly -C cmd execute commands `cmd', then continue in interactive mode -Q cmd execute commands `cmd' quietly, then continue in interactive mode -F script execute commands from a script file and echo commands -f script execute commands from a script file -h print the command usage -o file specify output filename to store the result -s do not read any initialization file -t type specify input type (blif_mv (default), blif_mvs, blif, or none) -T type specify output type (blif_mv (default), blif_mvs, blif, or none) -x equivalent to '-t none -T none' -b running in bridge mode HOME.abc.rcsource -s %ssource -s abc.rc***EOF***\~\~\ \P\\6\=\\\\Ѐ\\\\\F\ۂ\\\\\\\\'\'\\\\\\\˄\҄\nVars >= nNegssrc/base/exor/exor.cint GetQCost(int, int) ITERATION #%d g_CoverInfo.nCubesInUse + g_CoverInfo.nCubesFree == g_CoverInfo.nCubesAllocint ReduceEsopCover()void AddCubesToStartingCover(Vec_Wec_t *)nIns > 0int Exorcism(Vec_Wec_t *, int, int, char *)Starting cover generation time is %.2f sec The number of cubes in the starting cover is %d The size of the starting cover is more than %d cubes. Quitting... Dynamically allocated memory is %dK Minimization time is %.2f sec The number of cubes after minimization is %d temp.esopMinimized cover has been written into file <%s> Incoming ESOP has %d inputs, %d outputs, and %d cubes. (int)(ABC_PTRUINT_T)pFanin->pCopy < nInsVec_Wec_t *Abc_ExorcismNtk2Esop(Abc_Ntk_t *)Performing minimization...Generating the starting cover...Unexpected memory allocation problem. Quitting...Something went wrong when minimizing the cover EXORCISM, Ver.4.7: Exclusive Sum-of-Product Minimizerby Alan Mishchenko, Portland State University, July-September 2000 @ADEPQTU@ADEPQT@ADEPQT@ADP@ADEPQT@ADP@ADP@@@@@@@@@@@A@D@E@P@Q@T@AAAAAAA@AAADAPADDDDDDD@DADDDPDEEEE@EPPPPPPP@PAPDPPPQQQQ@QTTTT@TUValue == VAR_NEG || Value == VAR_POS || Value == VAR_ABSsrc/base/exor/exorBits.cvarvalue GetVar(Cube *, int)BitGroupNumbers[Temp] != MARKNUMBERint FindDiffVars(int *, Cube *, Cube *)nVarsIn > 0 && nVarsIn <= g_CoverInfo.nVarsInvoid InsertVars(Cube *, int *, int, int *)pVars[i] >= 0 && pVars[i] < g_CoverInfo.nVarsInpVarValues[i] == VAR_NEG || pVarValues[i] == VAR_POS || pVarValues[i] == VAR_ABSvoid InsertVarsWithoutClearing(Cube *, int *, int, int *, int)src/base/exor/exorCubes.cint AllocateCover(int, int, int)void AddToFreeCubes(Cube *)p->Prev == NULLp->IDs_CubesFreeCube *GetFreeCube() Px @ @ @ @$AB$$AABB!"!"$$!$$"AA!AA"BB!BB"$!!$$""$AB!A!BAB"A"B              pC1 != NULLsrc/base/exor/exorLink.cint ExorLinkCubeIteratorStart(Cube **, Cube *, Cube *, cubedist)pC2 != NULL!fWorkingint ExorLinkCubeIteratorNext(Cube **)GroupCostBest != -1NewZ != 255int ExorLinkCubeIteratorPick(Cube **, int)g >= 0 && g < nGroupsVisitedGroups & s_BitMasks[g]ELCubes[CubeNum] != NULLvoid ExorLinkCubeIteratorCleanUp(int)-\A\\;\ExLink-%d: Que= %5d Att= %4d Resh= %4d NoResh= %4d Cubes= %3d (%d) Lits= %5d QCost = %6dp->Prev == NULL && p->Next == NULLsrc/base/exor/exorList.cvoid CubeInsert(Cube *)Cube *CubeExtract(Cube *)s_pCubeLast == NULLCube *IterCubeSetStart()s_pCubeLastCube *IterCubeSetNext()s_Iter.fStarted == 0int IteratorCubePairStart(cubedist, Cube **, Cube **)CubeDist >= 0 && CubeDist <= 2s_Iter.fStartedint IteratorCubePairNext()void NewRangeInsertCubePair(cubedist, Cube *, Cube *)src/base/exor/exorUtil.cint CountLiteralsCheck()Warning! The recorded number of literals (%d) differs from the actual number (%d) void WriteTableIntoFile(FILE *) Cannot open the output file # EXORCISM-4 output for command line arguments: "-Q %d -V %d" # Minimization performed %s# Initial statistics: Cubes = %d Literals = %d QCost = %d # Final statistics: # File reading and reordering time = %.2f sec # Starting cover generation time = %.2f sec # Pure ESOP minimization time = %.2f sec .type esop 1'bxpNtk->pManFunc == NULLsrc/base/ver/verCore.cint Ver_ParseConvertNetwork(Ver_Man_t *, Abc_Ntk_t *, int)The network %s appears to have both gates and assign statements. Currently such network are not allowed. One way to fix this problem might be to replace assigns by buffers from the library.nMsb >= 0 && nMsb < 128int Ver_ParseInsertsSuffix(Ver_Man_t *, char *, int, int)nLsb >= 0 && nLsb < 128pWord[0] == '['int Ver_ParseSignalPrefix(Ver_Man_t *, char **, int *, int *)Cannot find closing bracket in this line.nMsb >= 0 && nLsb >= 0pWord[Length-1] == ']'int Ver_ParseSignalSuffix(Ver_Man_t *, char *, int *, int *)Cannot find opening bracket in signal name %s.pWord[0] >= '1' && pWord[1] <= '9'int Ver_ParseConstant(Ver_Man_t *, char *)Cannot find symbol ' in the constant.Currently can only handle binary constants.Having problem parsing the binary constant.Warning: The design contains %d undefined object types interpreted as blackboxes: %s (%d) pBundleint Ver_ParseFormalNetsAreDriven(Abc_Ntk_t *, char *)Abc_NtkFindNet( pNtk, Buffer ) == NULLint Ver_ParseDriveFormal(Ver_Man_t *, Abc_Ntk_t *, Ver_Bundle_t *)Abc_NtkBoxNum(pNtk) <= 1Missing specification of the I/Os of undefined box "%s".The number of formal inputs (%d) is different from the expected one (%d) when instantiating network %s in box %s.int Ver_ParseDriveInputs(Ver_Man_t *, Vec_Ptr_t *)%s.logThe hierarhical design %s contains %d modules: %-50s : undefboxlogicbox instantiated %6d times pi = %4d po = %4d nd = %8d lat = %6d box = %6dThe number of modules with one output = %d (%.2f %%). The outputs of all box instances are connected. The outputs of %d box instances are not connected: In module "%s" instance "%s" of box "%s" has different numbers of actual/formal nets (%d/%d). Hierarchy statistics can be found in log file "%s". Cannot read "module" directive.The network check has failed for network %s.Cannot find "(" after "module" in network %s.Symbol == ')'int Ver_ParseModule(Ver_Man_t *)Expected closing parenthesis after "module".inoutdffalwaysinitialendmodulenMsb == -1 && nLsb == -1int Ver_ParseSignal(Ver_Man_t *, Abc_Ntk_t *, Ver_SignalType_t)Cannot parse signal line (expected , or ;).Cannot parse a standard gate (expected opening parenthesis).Net is missing in gate %s.Cannot parse a standard gate %s (expected closing parenthesis).Buffer or interver with multiple fanouts %s (currently not supported).Cannot read standard gate %s (expected closing semicolumn).Cannot parse the flop.#11'h01'h1Cannot read the assign statement for %s (expected equality sign).Currently can only assign vector-signal "%s" to be a constant.The constant size (%d) is different from the signal"%s" size (%d).pNet != NULLint Ver_ParseAssign(Ver_Man_t *, Abc_Ntk_t *)Cannot read the assign statement for %s (output wire is not defined).pWord[0] != '\\'Cannot read the equation for %s.Cannot read Verilog with non-trivial assignments in the mapped netlist.Reading assign statement for node %s has failed because the genlib library has no buffer.Cannot read the assign statement for %s (input wire %s is not defined).Cannot read the always statement for %s (output wire is not defined).Cannot read the assign statement for %s (expected <= or =).Cannot read the always statement for %s (input wire is not defined).Symbol == ';'int Ver_ParseAlways(Ver_Man_t *, Abc_Ntk_t *)Cannot read the initial statement for %s (output wire is not defined).Cannot find the latch to assign the initial value.Abc_ObjIsLatch(pNode)int Ver_ParseInitial(Ver_Man_t *, Abc_Ntk_t *)Incorrect initial value of the latch %s.The network appears to be mapped. Use "r -m" to read mapped Verilog.Cannot parse gate %s (expected opening parenthesis).Cannot parse gate %s (expected .).Formal input name %s cannot be found in the gate %s.Cannot formal parameter %s of gate %s (expected opening parenthesis).pWord[0] != '~'int Ver_ParseGate(Ver_Man_t *, Abc_Ntk_t *, Mio_Gate_t *)Actual net %s is missing.Cannot formal parameter %s of gate %s (expected closing parenthesis).Parsing of gate %s has failed.Cannot read gate %s (expected closing semicolumn).Cannot parse box %s (expected opening parenthesis).Cannot parse box %s (expected .).Cannot formal parameter %s of box %s (expected opening parenthesis).Actual net "%s" is missing in gate "%s".Open_dct_unconnectedActual net "%s" is missing in box "%s".int Ver_ParseBox(Ver_Man_t *, Abc_Ntk_t *, Abc_Ntk_t *)Cannot parse formal parameter %s of gate %s (expected comma).Cannot parse formal parameter %s of box %s (expected closing parenthesis).Cannot parse formal parameter %s of box %s (expected comma).Cannot read box %s (expected closing semicolumn).Vec_PtrSize( vUndefs ) > 0int Ver_ParseAttachBoxes(Ver_Man_t *)pNtkBox->pNameint Ver_NtkIsDefined(Abc_Ntk_t *)!Ver_ObjIsConnected(pBox)int Ver_ParseConnectBox(Ver_Man_t *, Abc_Obj_t *)Ver_NtkIsDefined(pNtkBox)!Abc_NtkHasBlackbox(pNtkBox) || Abc_NtkBoxNum(pNtkBox) == 1The number of actual IOs (%d) is bigger than the number of formal IOs (%d) when instantiating network %s in box %s.Warning: The instance %s of network %s will be connected without using formal names. The number of actual IOs (%d) is different from the number of formal IOs (%d) when instantiating network %s in box %s.pBundle != NULLCannot find an actual net for the formal net %s when instantiating network %s in box %s._temp_net%dIt looks like formal output %s is driving a constant net (%s) when instantiating network %s in box %s.int Ver_ObjIsConnected(Abc_Obj_t *)Abc_ObjIsBlackbox(pObj)void Abc_ObjBlackboxToWhitebox(Abc_Obj_t *)N]N]M]M]N]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]N]L]M]M]M]M]L]M]sM]-M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]L]M]M]M]M]L]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]L]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]M]L]M]L]=R]xR]kR]R]^R]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]S]Parse_FormulaParser(): Different number of opening and closing parentheses ().Parse_FormulaParser(): Variable before negation.Parse_FormulaParser(): There is no variable before AND, EXOR, or OR.Parse_FormulaParser(): Variable before a parenthesis.Parse_FormulaParser(): There is no opening parenthesis Parse_FormulaParser(): Unknown operation Parse_FormulaParser(): Incorrect state.Parse_FormulaParser(): Something is left in the operation stack Parse_FormulaParser(): Something is left in the function stack Parse_FormulaParser(): The input string is empty Ver_FormulaReduction(): Unknown operation (%c) Cannot parse after symbol "/". (),;Ver_StreamAlloc(): Cannot open input file "%s". !p->fStopsrc/base/ver/verStream.cchar Ver_StreamScanChar(Ver_Stream_t *)char Ver_StreamPopChar(Ver_Stream_t *)void Ver_StreamSkipChars(Ver_Stream_t *, char *)pCharsToSkip != NULLVer_StreamSkipSymbol() failed to parse the file "%s". void Ver_StreamSkipToChars(Ver_Stream_t *, char *)pCharsToStop != NULLVer_StreamSkipToSymbol() failed to parse the file "%s". char *Ver_StreamGetWord(Ver_Stream_t *, char *)Ver_StreamGetWord() failed to parse the file "%s". z_g_co_gvoid Ver_StreamReload(Ver_Stream_t *)p->pBufferCur > p->pBufferStopp->pBufferCur < p->pBufferEndVer_StreamGetWord(): The buffer size is exceeded.PIs:POs:FO(Fi)s: %s(%s)Objs: vSuppRefs || vSuppListsrc/base/wlc/wlcAbs.cvoid Wlc_NtkAbsGetSupp(Wlc_Ntk_t *, Wlc_Obj_t *, Vec_Bit_t *, Vec_Int_t *, Vec_Int_t *)Vec_IntSize( vDeltaB )void Wlc_NtkAbsAnalyzeRefine(Wlc_Ntk_t *, Vec_Int_t *, Vec_Bit_t *, int *, int *)Vec_IntSize(vMapFfNew2Bit1) == Vec_IntSize(vFfNew)Vec_Int_t *Wlc_NtkFlopsRemap(Wlc_Ntk_t *, Vec_Int_t *, Vec_Int_t *)iFfNew >= 0pWla->vSignalsVec_Int_t *Wla_ManCollectNodes(Wla_Man_t *, int)Derived abstraction with %d objects and %d PPIs. Bit-blasted AIG stats are: pAigScorrint Wla_ManCheckCombUnsat(Wla_Man_t *, Aig_Man_t *)SCORR proved UNSAT. TimeSCORR failed with %d ANDs. ABS becomes combinationally UNSAT. TimeCheck comb. unsat failed. TimeVec_VecSize( pWla->vClauses) >= 2int Wla_ManSolveInt(Wla_Man_t *, Aig_Man_t *)Refinement of CEX in frame %d came up with %d un-abstacted PPIs, whose MFFCs include %d objects. Refinement of CEX in frame %d came up with %d un-abstacted PPIs. Iteration %d: Abstraction resulted in a real CEXis successfully provedtimed outPDRA reused %d clauses. PDR CEX Refine Proof Refine Misc. Total int Wlc_NtkAbsCore(Wlc_Ntk_t *, Wlc_Par_t *)pObj->Type == WLC_OBJ_FOWlc_Obj_t *Wlc_ObjFo2Fi(Wlc_Ntk_t *, Wlc_Obj_t *)Wlc_ObjIsCi(p)int Wlc_ObjCiId(Wlc_Obj_t *)Id > 0 && Id < p->nObjsAllocWlc_Obj_t *Wlc_NtkObj(Wlc_Ntk_t *, int)vWhites && Vec_IntSize(vWhites)Vec_Bit_t *Wlc_NtkProofReduce(Wlc_Ntk_t *, Wlc_Par_t *, int, Vec_Int_t *, Vec_Int_t *, int)ProofReduce: remove %d out of %d white boxes.Vec_Int_t *Wlc_NtkGetCoreSels(Gia_Man_t *, int, int, int, Vec_Bit_t *, int, Wlc_Par_t *, int, int)pCnf->pVarNums[pObj->Id] >= 0UNSAT after adding PO clauses. var >= 0UNKNOWN. int Vec_BitCount(Vec_Bit_t *)Abstraction engine marked %d adds/subs, %d muls/divs, %d muxes, and %d flops to be abstracted away (out of %d signals). %%PDRA: %d-th ADD has width = %d %%PDRA: %d-th MUL has width = %d %%PDRA: %d-th MUX has width = %d %%PDRA: %d-th FF has width = %d *pvBlacksint Wlc_NtkUpdateBlacks(Wlc_Ntk_t *, Wlc_Par_t *, Vec_Int_t **, Vec_Bit_t *, Vec_Int_t *)Abstraction engine marked %d adds/subs, %d muls/divs, %d muxes, and %d flops to be abstracted away. CEX is real on the original model. pCexCare->nPis == pCex->nPisVec_Int_t *Wlc_NtkAbsRefinement(Wlc_Ntk_t *, Gia_Man_t *, Abc_Cex_t *, Vec_Int_t *)Vec_IntSize( vCoreSels )int Wlc_NtkProofRefine(Wlc_Ntk_t *, Wlc_Par_t *, Abc_Cex_t *, Vec_Int_t *, Vec_Int_t **)Proof-based refinement reduces %d (out of %d) white boxes #orig_pis = %d, #ppis = %d, #sel_pis = %d, #undc_pis = %d Gia_ManPiNum(pGiaChoice)==nbits_old_pis+num_ppis+num_sel_pis+num_undc_pisGia_Man_t *Wlc_NtkUnrollWithCex(Wlc_Ntk_t *, Abc_Cex_t *, int, int, int *, int, int)Gia_ManPiNum(pGiaChoice)==pCex->nPis+num_sel_pisint Wlc_NtkMarkMffc(Wlc_Ntk_t *, Wlc_Obj_t *, Vec_Bit_t *)!Wlc_ObjIsPi(pObj)void Wlc_NtkAbsMarkNodes_rec(Wlc_Ntk_t *, Wlc_Obj_t *, Vec_Bit_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)src/base/wlc/wlcAbs2.cint Wlc_NtkAbsCore2(Wlc_Ntk_t *, Wlc_Par_t *)abc_blast_input.info%s[%d] : %c %s[%d] : o %s[%d:%d] : [%d] -> %dsrc/base/wlc/wlcAbc.cvoid Wlc_NtkPrintInvStats(Wlc_Ntk_t *, Vec_Int_t *, int)pi%dpNtk == NULL || Vec_IntSize(vCounts) == nBitsAbc_Ntk_t *Wlc_NtkGetInv(Wlc_Ntk_t *, Vec_Int_t *)Value == i+1Vec_Int_t *Wlc_NtkGetPut(Abc_Ntk_t *, Gia_Man_t *)Cannot read input name "%s" of fanin %d. Cannot read names for %d inputs of the invariant. Vec_IntSize(vFanins) == Abc_ObjFaninNum(pNode)Mismatch between number of inputs and the number of literals in the invariant.The number of internal nodes is other than 1.The number of outputs is other than 1.RunId <= g_nRunIdssrc/base/wlc/wlcPth.cint Wla_CallBackToStop(int)void Wla_ManJoinThread(Wla_Man_t *, int)pAbcNtk->pSeqModelvoid *Wla_Bmc3Thread(void *)Bmc3 found CEX. RunId=%d. Bmc3 was cancelled. RunId=%d. pWla->pThread == NULLvoid Wla_ManConcurrentBmc3(Wla_Man_t *, Aig_Man_t *, Abc_Cex_t **)qR^xR^R^R^R^R^S^S^S^S^S^ T^^^^[^^^^^^F^K^^_^տ^^_^տ^|^^^|^s^E^+^^T^^/^^^^^^^^^^^^^^0^0^0^^^^0^E^4G_4G_^^^^nFanins <= nTotalsrc/base/wlc/wlcBlast.cint *Wlc_VecLoadFanins(Vec_Int_t *, int *, int, int, int)int Wlc_NtkMuxTree2_nb(Gia_Man_t *, int *, int, Vec_Int_t *, Vec_Int_t *)!nCtrl || Vec_IntSize(vData) == (1 << nCtrl)int Wlc_NtkMuxTree2(Gia_Man_t *, int *, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)!nCtrl || Vec_IntSize(vAnds) == (1 << nCtrl)nShift <= 32void Wlc_BlastShiftRightInt(Gia_Man_t *, int *, int, int *, int, int, Vec_Int_t *)void Wlc_BlastShiftLeftInt(Gia_Man_t *, int *, int, int *, int, int, Vec_Int_t *)void Wlc_BlastRotateRight(Gia_Man_t *, int *, int, int *, int, Vec_Int_t *)void Wlc_BlastRotateLeft(Gia_Man_t *, int *, int, int *, int, Vec_Int_t *)int Wlc_BlastReduction(Gia_Man_t *, int *, int, int)nBits == 1void Wlc_BlastLess_rec(Gia_Man_t *, int *, int *, int, int *, int *)nBits % 2 == 0void Wlc_BlastAdderCLA_rec(Gia_Man_t *, int *, int *, int *, int, int *, int *)nBits >= 2void Wlc_BlastAdderCLA_int(Gia_Man_t *, int *, int *, int, int)void Wlc_BlastAdderFast_int(Gia_Man_t *, int *, int *, int, int)Vec_IntSize(vTemp) == nBitsvoid Wlc_BlastMultiplier2(Gia_Man_t *, int *, int *, int, Vec_Int_t *, Vec_Int_t *)nArgA > 0 && nArgB > 0void Wlc_BlastMultiplier(Gia_Man_t *, int *, int *, int, int, Vec_Int_t *, Vec_Int_t *, int)fSigned == 0 || fSigned == 1nNum == nDivvoid Wlc_BlastDivider(Gia_Man_t *, int *, int, int *, int, int, Vec_Int_t *)nNum > 0 && nDiv > 0void Wlc_BlastDivider2(Gia_Man_t *, int *, int, int *, int, int, Vec_Int_t *)Vec_IntSize(vRes) < nNum + nDivVec_IntSize(vRes) == nNumvoid Wlc_BlastDividerSigned(Gia_Man_t *, int *, int, int *, int, int, Vec_Int_t *)nOuts == 1void Wlc_BlastLut(Gia_Man_t *, word, int *, int, int, Vec_Int_t *)nNum % 2 == 0void Wlc_BlastSqrt(Gia_Man_t *, int *, int, Vec_Int_t *, Vec_Int_t *)void Wlc_BlastSqrtNR(Gia_Man_t *, int *, int, Vec_Int_t *, Vec_Int_t *)pIn1[0] == 0k == 2*i+2Booth partial products: %d pps, %d unique, %d nodes. Obj = %4d : Compl = %d Rank = %2d nSize == Vec_WecSize(vLevels)void Wlc_BlastReduceMatrix(Gia_Man_t *, Vec_Wec_t *, Vec_Wec_t *, Vec_Int_t *, int, int)Vec_IntSize(vProd) == 2Gia_ObjLevelId(pNew, Abc_Lit2Var(Node3)) >= Gia_ObjLevelId(pNew, Abc_Lit2Var(Node2))void Wlc_BlastReduceMatrix2(Gia_Man_t *, Vec_Wec_t *, Vec_Int_t *, int, int)Gia_ObjLevelId(pNew, Abc_Lit2Var(Node2)) >= Gia_ObjLevelId(pNew, Abc_Lit2Var(Node1))Vec_IntSize(vArgB) % 2 == 1void Wlc_BlastBooth(Gia_Man_t *, int *, int *, int, int, Vec_Int_t *, int, int)Vec_IntSize(&p->vFfs2) == 0Gia_Man_t *Wlc_NtkBitBlast(Wlc_Ntk_t *, Wlc_BstPar_t *)Vec_IntSize(pPar->vBoxIds) > 0pObj->Type == WLC_OBJ_ARI_MULTI || pObj->Type == WLC_OBJ_ARI_ADD!pPar->fGiaSimplepPar->vBoxIds == 0pObj->Type == WLC_OBJ_FFWlc_ObjRange(pObj) == Wlc_ObjRange(Wlc_ObjFanin0(p, pObj))Vec_IntSize(vRegClasses) == nFf2RegsnRange > 0pObj->Type == WLC_OBJ_ARI_MULTI || pObj->Type == WLC_OBJ_ARI_ADD || pObj->Type == WLC_OBJ_ARI_SUBnRange2 == 1Vec_IntSize(vRes) == nRange%s%03dnRange0 >= 1 && Wlc_ObjFaninNum(pObj) >= 31 + (1 << nRange0) == Wlc_ObjFaninNum(pObj)nRange0 == Wlc_ObjFaninNum(pObj)-1nRange == Wlc_ObjRange(pFanin)nRange0 == nRangenRange == End - Beg + 1pFanin->Beg <= Beg && End <= pFanin->EndnRange == Beg - End + 1pFanin->End <= End && Beg <= pFanin->BegnRange == nTotalnRange0 <= nRangeVec_IntSize(vBits) == Wlc_ObjCopy(p, i)nBits == Vec_IntSize(vBits)ff_combWlc_NtkPoNum(p) % 2 == 0nRange1 == nRange2Derived an ordinary miter with %d bit-level outputs, one for each pair of word-level outputs. Derived a dual-output miter with %d pairs of bits belonging to %d pairs of word-level outputs. Created %d additional POs for %d interesting internal word-level variables. nFFins == 0 && nFFouts == 0nFFins == nFFoutsThe number of init values (%d) does not match the number of flops (%d). curPi == Tim_ManCiNum(pManTime)curPo == Tim_ManCoNum(pManTime)Gia_ManPoNum(pExtra) == Gia_ManCiNum(pNew) - nBitCis - nFf2Regs_%s_abc_%d_%s_fo[%d]Vec_PtrEntry(pNew->vNamesIn, SepStart) == NULLVec_PtrEntry(pNew->vNamesIn, NullStart+i) == NULLabc_reset_flopnRange > 1Vec_PtrSize(pNew->vNamesIn) == Gia_ManCiNum(pNew)%s_in[%d]nRange >= 1%s_xor_%snRange == nRange1abc_reset_flop_in%s_fi[%d]Vec_PtrSize(pNew->vNamesOut) == Gia_ManCoNum(pNew)iHere >= 0 && iHere <= p->nSizevoid Vec_IntInsert(Vec_Int_t *, int, int)It is assumed that the AIG has constant 0 initial state.NV_TV_ZV_`V_V_V_V_V_V_V_V_V_fV_V_mV_V_V_V_V_tV_V_#V_X_Z_Z_Y_Z_Z_Z_Z_Z_Z_Z_Z_Z_Z_Z_Z_Z_Z_Z_Z_Z_Z_Z_Z_Z_Z_RY_Z_Z_Z_Z_Z_Z_Z_Z_Z_ZY_[_]_]_]_]_ \_]_]_2\_]_]_W\_|\_]_]_]_]_]_]_]_]_]_]_\_]_]_]_]_]_]_]_]_]_]_]_\_]_]_]_]_]_]_]_]_]_]_]_]_]_]_]_]_]_\_[_\_`_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_8a_"__8a_8a_8a_8a_J__8a_8a_r__8a_8a_____8a_8a_8a_8a_8a_8a_8a_8a_8a_8a___8a_8a_8a_8a_8a_8a_8a_8a_$`_.`_8`_B`_8a_8a_8a_8a_L`_8a_8a_V`_``_8a_8a_j`_t`_~`_`_`_`_`_^_`_Rd_e_e_e_e_zd_e_e_d_e_e_e_d_e_e_e_e_e_e_e_e_e_e_d_e_e_e_e_e_e_e_e_e_e_e_e_e_e_e_e_e_e_e_e_e_e_e_e_e_e_e_e_e_$e_'d_.e_Qm_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_n_sk_n_n_n_n_n_n_n_n_n_n_n_k_n_k_n_n_$l_n_n_n_n_n_n_n_n_n_n_n_n_n_n__l_sl_l_l_l_n_n_n_l_n_n_n_l_l_l_n_l_n_m_'m_n_9k_n_n_n_:m_Word level%read%write%ps%cone%abs%pdra%abs2%memabs%memabs2%blast%blastmem%graft%retime%profile%short_names%show%testinv_psinv_printinv_checkinv_getinv_putinv_minopvh.smt.smt2usage: %%read [-opvh] reads word-level design from Verilog file -o : toggle using old SMT-LIB parser [default = %s] -p : toggle printing parse SMT-LIB tree [default = %s] anfvhAbc_CommandWriteWlc(): There is no current design. _out.vusage: %%write [-anfvh] writes the design into a file -a : toggle adding a CO for each node [default = %s] -n : toggle splitting into individual nodes [default = %s] -f : toggle skipping flops when writing file [default = %s] cbamdtovhAbc_CommandPs(): There is no current design. usage: %%ps [-cbamdtovh] prints statistics -c : toggle printing cones [default = %s] -b : toggle printing multipliers [default = %s] -a : toggle printing adders [default = %s] -m : toggle printing memories [default = %s] -d : toggle printing distrubition [default = %s] -t : toggle printing stats for LHS and RHS [default = %s] -o : toggle printing all objects [default = %s] ORisvhAbc_CommandCone(): There is no current design. Abc_CommandCone(): Illegal output index (%d) (should be 0 <= num < %d). Extracting output %d as a %s word-level network. sequentialcombinationalusage: %%cone [-OR num] [-isvh] extracts logic cone of one or more word-level outputs -O num : zero-based index of the first word-level output to extract [default = %d] -R num : total number of word-level outputs to extract [default = %d] -i : toggle using support composed of all primary inputs [default = %s] -s : toggle performing extracting sequential cones [default = %s] AMXFILabrcdilpqmstuxvwhusage: %%pdra [-AMXFIL num] [-abrcdilpqmxstuvwh] abstraction for word-level networks -A num : minimum bit-width of an adder/subtractor to abstract [default = %d] -M num : minimum bit-width of a multiplier to abstract [default = %d] -X num : minimum bit-width of a MUX operator to abstract [default = %d] -F num : minimum bit-width of a flip-flop to abstract [default = %d] -I num : maximum number of CEGAR iterations [default = %d] -L num : maximum number of each type of signals [default = %d] -x : toggle XORing outputs of word-level miter [default = %s] -a : toggle running pdr with -nct [default = %s] -b : toggle using proof-based refinement [default = %s] -r : toggle using both cex-based and proof-based refinement [default = %s] -c : toggle checking clauses in the reloaded trace [default = %s] -d : toggle using another way of creating abstractions [default = %s] -i : toggle using PPI values in proof-based refinement [default = %s] -l : toggle loading previous PDR traces [default = %s] -s : toggle shrinking abstractions with BMC [default = %s] -t : toggle restarting pdr from scratch after shrinking abstractions with BMC [default = %s] -u : toggle checking combinationally unsat [default = %s] -p : toggle pushing clauses in the reloaded trace [default = %s] -q : toggle running bmc3 in parallel for CEX [default = %s] -m : toggle refining the whole MFFC of a PPI [default = %s] -w : toggle printing verbose PDR output [default = %s] AMXFILdxvwhusage: %%abs [-AMXFIL num] [-dxvwh] AMXFIxvwhusage: %%abs2 [-AMXFI num] [-xvwh] IdwvhAbc_CommandMemAbs(): There is no current design. usage: %%memabs [-I num] [-dwvh] memory abstraction for word-level networks -d : toggle dumping abstraction as an AIG [default = %s] Abc_CommandMemAbs2(): There is no current design. usage: %%memabs2 [-F num] [-vh] ORAMcombqadestnizvhAbc_CommandBlast(): There is no current design. Abc_CommandBlast(): Trying to bit-blast network with asynchronous reset. Warning: There is no multipliers in the design. Warning: There is no adders and multipliers that will not be blasted. Warning: %d adders and %d multipliers will not be blasted. Abc_CommandBlast(): The output range [%d:%d] is incorrect. Bit-blasting created a traditional multi-output miter by XORing POs pair-wise. pio_name_map.txtFinished dumping file "pio_name_map.txt" containing PI/PO name mapping. usage: %%blast [-ORAM num] [-combqadestnizvh] performs bit-blasting of the word-level design -O num : zero-based index of the first word-level PO to bit-blast [default = %d] -R num : the total number of word-level POs to bit-blast [default = %d] -A num : blast adders smaller than this (0 = unused) [default = %d] -M num : blast multipliers smaller than this (0 = unused) [default = %d] -c : toggle using AIG w/o const propagation and strashing [default = %s] -o : toggle using additional POs on the word-level boundaries [default = %s] -m : toggle creating boxes for all multipliers in the design [default = %s] -b : toggle generating radix-4 Booth multipliers [default = %s] -q : toggle generating non-restoring square root [default = %s] -a : toggle generating carry-look-ahead adder [default = %s] -d : toggle creating dual-output multi-output miter [default = %s] -e : toggle creating miter with output word bits combined [default = %s] -s : toggle creating decoded MUXes [default = %s] -t : toggle creating regular multi-output miter [default = %s] -n : toggle dumping signal names into a text file [default = %s] -i : toggle to print input names after blasting [default = %s] -z : toggle saving flop names after blasting [default = %s] Abc_CommandBlastMem(): There is no current design. usage: %%blastmem [-vh] performs blasting of memory read/write ports Abc_CommandGraft(): There is no current design. usage: %%graft [-vh] detects multipliers in LHS of the miter and moves them to RHS usage: %%retime [-sdvh] performs retiming for the NDR design -s : toggle printing simple nodes [default = %s] -d : toggle dumping the network in Verilog [default = %s] Abc_CommandProfile(): There is no current design. usage: %%profile [-vh] profiles arithmetic components in the word-level networks usage: %%short_names [-vh] derives short names for all objects of the network usage: %%show [-mh] visualizes the network structure using DOT and GSVIEW -m : toggle showing memory subsystem [default = %s] -h : print the command usage Abc_CommandInvPs(): There is no current design. Abc_CommandInvPs(): Invariant is not available. usage: inv_ps [-vh] prints statistics for inductive invariant (in the case of 'sat' or 'undecided', inifity clauses are used) usage: inv_print [-vh] prints the current inductive invariant Abc_CommandInvMin(): There is no current design. Abc_CommandInvMin(): There is no saved invariant. Abc_CommandInvMin(): The number of flops in the invariant and in GIA should be the same. Invariant verification failed for %d clauses (out of %d). Invariant verification succeeded. usage: inv_check [-vh] checks that the invariant is indeed an inductive invariant (AIG representing the design should be in the &-space) Abc_CommandInvGet(): Invariant is not available. usage: inv_get [-vh] places invariant found by PDR as the current network in the main-space Abc_CommandInvPut(): There is no current design. Abc_CommandInvPut(): There is no current AIG. usage: inv_put [-vh] inputs the current network in the main-space as an invariant Abc_CommandInvMin(): Invariant is not available. usage: inv_min [-lvh] performs minimization of the current invariant -l : toggle minimizing literals rather than clauses [default = %s] usage: %%test [-vh] experiments with word-level networks Abc_CommandReadWlc(): Unknown file extension.Abc_CommandReadWlc(): Input file name should be given on the command line.Output file name should be given on the command line.Abc_CommandRetime(): Input file name should be given on the command line.Transforming NDR into internal represnetation has failed.%2d(%d) Obj %4d. Range = %2d. Bit %2d. Entry %d(%d). %s nMultiLHS > 0src/base/wlc/wlcGraft.cWlc_Ntk_t *Wlc_NtkGraftMulti(Wlc_Ntk_t *, int)nMultiRHS == 0Vec_MemEntryNum(vTtMem) == 2*nInsVec_Int_t *Sbc_ManDetectMult(Gia_Man_t *, Vec_Int_t *)Vec_IntSize(vIns) % 2 == 0Temp == *pInfoObjMatched out %d in phase %d with object %d (%s) bit %d (out of %d). Considering object %d (%s): Matching bit %d with output %d / %d. Matched node %5d (%10s) bit %3d (out of %3d) with output %3d(%d). Found object %d with all bits matched. Gia_ObjId(p, pObj) < p->nTravIdsAllocvoid Gia_ObjSetTravIdCurrent(Gia_Man_t *, Gia_Obj_t *)int Gia_ObjIsTravIdCurrent(Gia_Man_t *, Gia_Obj_t *)Multipliers are present in both sides of the miter.No multipliers are present.Input identification did not work out.nRegs * DataW == Wlc_ObjRange(pMem)src/base/wlc/wlcMem.cvoid Wlc_NtkMemBlast_rec(Wlc_Ntk_t *, Wlc_Ntk_t *, int, Vec_Int_t *)Wlc_ObjRange(pObj) == Wlc_ObjRange(pMem)Vec_Int_t *Wlc_NtkAbsCreateFlopOutputs(Wlc_Ntk_t *, Wlc_Ntk_t *, Vec_Int_t *, Vec_Int_t *)Vec_IntSize(vNewObjs) == 2 * Vec_IntSize(vNodeFrames)void Wlc_NtkAbsCreateFlopInputs(Wlc_Ntk_t *, Wlc_Ntk_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Wlc_Obj_t *, int)Wlc_ObjRange(pFlop) == Wlc_ObjRange(pFanin)void Wlc_NtkAbsCreateLogic(Wlc_Ntk_t *, Wlc_Ntk_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Wec_t *, Wlc_Obj_t *)Vec_IntSize(vTrace) >= 2Index[0] >= 0 && Index[1] >= 0Index[0] >= 0Wlc_ObjType(Wlc_NtkObj(p, Entry >> 11)) == WLC_OBJ_MUXWlc_ObjRange(pAddrs[0]) == Wlc_ObjRange(pAddrs[1])Memory abstraction created %d miter outputs. Wlc_ObjRange(pFanin) == 1Vec_Int_t *Wlc_NtkDeriveFirstTotal(Wlc_Ntk_t *, Vec_Int_t *, Vec_Int_t *, int, int, int)nMemFanins == Vec_IntSize(vMemFanins)Obj %5d Fanin %5d : %16s : %d(%d) First < Gia_ManCiNum(pAbs)int Wlc_NtkCexResim(Gia_Man_t *, Abc_Cex_t *, Vec_Int_t *, int, Vec_Wrd_t *, int)Frame %d: iObj == Vec_IntEntry(vMemObjs, iNum)void Wlc_NtkTrace_rec(Wlc_Ntk_t *, Wlc_Obj_t *, int, Vec_Int_t *, Vec_Wrd_t *, word, Vec_Int_t *)iFrame >= 0Value == 0 && Value == 1Wlc_ObjType(pObj) == WLC_OBJ_READVec_Int_t *Wlc_NtkTrace(Wlc_Ntk_t *, Wlc_Obj_t *, int, Vec_Int_t *, Vec_Wrd_t *)int Wlc_NtkTraceCheckConfict(Wlc_Ntk_t *, Vec_Int_t *, Vec_Int_t *, Vec_Wrd_t *)iObjLast == Vec_IntEntry(vMemObjs, iNumLast)iObjFirst == Vec_IntEntry(vMemObjs, iNumFirst)Wlc_ObjType(pObjLast) == WLC_OBJ_READWlc_ObjType(pObjFirst) == WLC_OBJ_WRITE || Wlc_ObjIsPi(pObjFirst)Vec_WrdEntry(vValues, iIndLast + 1) == Vec_WrdEntry(vValues, iIndFirst + 1)3 * nFrames * Vec_IntSize(vMemObjs) == Vec_WrdSize(vValues)Vec_Int_t *Wlc_NtkFindConflict(Wlc_Ntk_t *, Vec_Int_t *, Vec_Wrd_t *, int)iObj1 == Vec_IntEntry(vMemObjs, iNum1)iObj2 == Vec_IntEntry(vMemObjs, iNum2)%3d: entry %9d : obj %5d with name %16s in frame %d Frame%02d PI%d:FF:iFirstMemPi = %d iFirstCi = %d iFirstMemCi = %d nDcBits = %d Gia_ManPiNum(pAbsFull) == iFirstCi + nDcBitsint Wlc_NtkMemAbstract(Wlc_Ntk_t *, int, int, int, int) ITERATIONS %d: mem_abs.aigIteration %3d: Dumped abstraction in file "%s" after finding CEX in frame %d. resulted in a real CEX in frame %dObj %6d : Visit = %6d Pair = %6d Read port %6d : Inputs = %6d %d(%s) pObj->Mark2 == 0Vec_Int_t *Wlc_NtkFindReachablePiFo(Wlc_Ntk_t *, Vec_Int_t *, int)Wlc_ObjRange(pObjR) == Wlc_ObjRange(Wlc_NtkObj(pNew, iFanin0New))void Wlc_NtkCreateMemoryConstr(Wlc_Ntk_t *, Wlc_Ntk_t *, Vec_Int_t *, Vec_Int_t *)Wlc_ObjRange(pObjR) == Wlc_ObjRange(Wlc_NtkObj(pNew, iFanin1New))iObjNew != -1Wlc_NtkObj(pNew, iObjNew)->Type == WLC_OBJ_BUFnFrames == 0Wlc_Ntk_t *Wlc_NtkAbstractMem(Wlc_Ntk_t *, int, int)Vec_IntSize(vReachReadCi) % 3 == 0Wlc_ObjIsRead(pObj)Memory subsystem is composed of the following objects:Memory semantics failure trace:The CEX is NULL.q`T` ` ` ` ` ` ``$`5`0`6`<`B`H`N`J`J`J`J`T`Z```f``l`r`x`J`J`~``J`J`J`J`J`J`J`````````J``J``J`J`J`J`J`J`J`J`````````` `J`J```Ʈ`̮````Ү```خ`ޮ`J`>`J`D`J`J`J`J`J`J`J`J`J`J`J` `J`$`&`,`*`2``8`J`5`r``````````````\``g```````%(&)'*9:+,--.0/123!#$"  ;6748YYa EGDFIH [\]^$_%')BC>A?@ "!#2346879:;`PQb,0KnBits + 10 < 10000src/base/wlc/wlcNdr.cchar *Ndr_ObjWriteConstant(unsigned int *, int)Vec_IntSize(vFanins) == 0void *Wlc_NtkToNdr(Wlc_Ntk_t *)Dumped the current design into file "%s". test.ndrWrongn symbol (%c) in binary Verilog constant "%s". %5d = Name Id %d pi po Internal object %d of type %s has no output name. Output name %d is used more than once (obj %d and obj %d). Input name %d appearing as fanin %d of obj %d is not used as output name in any object. Wlc_ObjType(pObj) == WLC_OBJ_FOWlc_Ntk_t *Wlc_NtkFromNdr(void *)Vec_IntSize(vFanins) == 1Wlc_ObjFaninNum(pObj) == 2nArray == 1 && NameId == -1(Vec_IntSize(&pNtk->vFfs) & 1) == 0Vec_IntSize(&pNtk->vFfs) == 2 * Vec_IntSize(pNtk->vInits)!fFound && i == NameIdtop.ndrtop.v./src/aig/miniaig/ndr.hNdr_DataType(p, i) <= NDR_OBJECTvoid Ndr_DataAddTo(Ndr_Data_t *, int, int)(int)p->pBody[0] == p->nSizeObjType != 0void Ndr_AddObject(void *, int, int, int, int, int, int, int, int *, int, int *, char *)nArray > 0void Ndr_DataPushArray(Ndr_Data_t *, int, int, int *) module %s ( ); output %s%s ABC_DFF.q(%s), .d(%s), .init(%s) ABC_DFFRSE.clk(%s), .reset(%s), .set(%s), .enable(%s), .async(%s), .sre(%s), ABC_READ.data(%s), .mem_in(%s), .addr(%s) ABC_WRITE.mem_out(%s), .addr(%s), .data(%s) %s %s %s; %s + %s + %s; %s ? %s : %s; ; endmodule signed p->pHead[i]int Ndr_DataType(Ndr_Data_t *, int)fonmaj~&~|~^=>&&||^^sqrtsquar!=<<<>>>rotLrotR[:]{}zPadsExt./src/aig/miniaig/abcOper.hconst char *Abc_OperName(int)void *Ndr_Read(char *)p->nSize == (int)p->pBody[0]Constants should be represented in binary Verilog notation 'b as char strings (for example, "4'b1010").Node IDs and their fanins:ʚ;ʚ;ʚ;ʚ;ʚ;1`````B````O```9````````h``]``e`{``d```1`,`G``z`8`N```v`!`````|~fS P O \ W H? , / 2 a h m 45 8 ; > aL w,d? , / 2 :!k)bY:A F />lviCout_of_boundno_objsrc/base/wlc/wlcNtk.cvoid Wlc_ObjSetCi(Wlc_Ntk_t *, Wlc_Obj_t *)Wlc_ObjFaninNum(pObj) == 0Type != WLC_OBJ_PO && Type != WLC_OBJ_FIint Wlc_ObjAlloc(Wlc_Ntk_t *, int, int, int, int)pObj->Type == WLC_OBJ_NONEvoid Wlc_ObjUpdateType(Wlc_Ntk_t *, Wlc_Obj_t *, int)pObj->nFanins == 0void Wlc_ObjAddFanins(Wlc_Ntk_t *, Wlc_Obj_t *, Vec_Int_t *)Object %6d has range %d, which is reduced to %d in the statistics. Object %d with name "%s" has type 0. Looks like it was declared by not defined... Wlc_ObjFaninNum(pObj) >= 2void Wlc_NtkPrintDistrib(Wlc_Ntk_t *, int, int)Warning: %d objects of the design have non-zero-based ranges. In particular, object %6d with name "%s" has range %d=[%d:%d] ID : name occurrence%s and2 (occurrence)=. ... Left Share Right%2d : %-8s %6d =%s%d.%s%d%8d : Lev = %2d %6d%s = PI : %-12s FO : %-12s = %-12s Unknown object without fanins : %-12s %6d%s %5s %6d%s %-12s = %-12s %5s %-12s Operation %s %8d :%-20s : PI = %4d PO = %4d FF = %4d Obj = %6d Mem = %.3f MB%2d : %-8s %6d %7.2f %% %2d : %-8s %6d !Wlc_NtkHasCopy(pNew) && Wlc_NtkHasCopy(p)void Wlc_NtkTransferNames(Wlc_Ntk_t *, Wlc_Ntk_t *)!Wlc_NtkHasNameId(pNew) && Wlc_NtkHasNameId(p)pNew->pManName == NULL && p->pManName != NULL%s_o%d_%sVec_IntSize(vInit) == Wlc_NtkCiNum(p) - Wlc_NtkPiNum(p)Vec_Int_t *Wlc_ReduceMarkedInitVec(Wlc_Ntk_t *, Vec_Int_t *)nBits == (int)strlen(pInit)char *Wlc_ReduceMarkedInitStr(Wlc_Ntk_t *, char *)void Wlc_ObjCollectCopyFanins(Wlc_Ntk_t *, int, Vec_Int_t *)pObj->Type != WLC_OBJ_FFvoid Wlc_NtkDupDfs_rec(Wlc_Ntk_t *, Wlc_Ntk_t *, int, Vec_Int_t *)Wlc_Ntk_t *Wlc_NtkDupDfsAbs(Wlc_Ntk_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)!Wlc_ObjIsPi(pObj) && Wlc_ObjIsCi(pObj)Cone %5d : FO = %4d Node = %6d Add/Sub = %4d Mult = %4d fibi{,}addsubword Vec_WrdAddToEntry(Vec_Wrd_t *, int, word)p->Type == WLC_OBJ_CONSTint *Wlc_ObjConstValue(Wlc_Obj_t *)Node type statistics: 0123456789abcdefsrc/base/wlc/wlcReadSmt.cint Smt_PrsBuildNode(Wlc_Ntk_t *, Smt_Prs_t *, int, int, char *)Vec_IntSize(vFans) == 3Smt_EntryIsName(iNode)#b1Type != WLC_OBJ_BIT_SIGNEXT && Type != WLC_OBJ_BIT_ZEROPADValue1 >= 0 && Value2 >= 0 && Value1 >= Value2Value1 >= 0Vec_IntSize(vFanins) == 3!Smt_EntryIsName(Fan)Wlc_Ntk_t *Smt_PrsBuild(Smt_Prs_t *)Ignoring directive "%s". Vec_IntSize(vFans) == 4Bool!strcmp("Bool", Smt_VecEntryName(p, vFans, 3))Vec_IntSize(vFans2) == 3!strcmp("_", Smt_VecEntryName(p, vFans2, 0))BitVec!strcmp("BitVec", Smt_VecEntryName(p, vFans2, 1))iObj == NameIdVec_IntSize(vFans) == 5#b0true!Smt_EntryIsName(Fan3)Vec_IntSize(vFans) == 2_%0*X__as%dAbc_NamStrFind( pNtk->pManName, pStr_loc )int Smt_PrsBuild2_rec(Wlc_Ntk_t *, Smt_Prs_t *, int, int, char *)Vec_IntSize(vRoots) == 3Smt_VecEntryIsType(vRoots, 0, SMT_PRS_LET)!Smt_EntryIsName(iRoot1)Vec_IntSize(vFans3) == 2iObjPrev != -1Num1 >= Num2Type0 != WLC_OBJ_BIT_SIGNEXT && Type0 != WLC_OBJ_BIT_ZEROPAD && Type0 != WLC_OBJ_BIT_SELECT && Type0 != WLC_OBJ_ROTATE_R && Type0 != WLC_OBJ_ROTATE_L!Smt_EntryIsName(Root)Wlc_Ntk_t *Smt_PrsBuild2(Smt_Prs_t *)Vec_IntSize(&p->vStack) == 0void Smt_PrsReadLines(Smt_Prs_t *)Vec_WecSize(&p->vObjs) == 0Vec_IntSize(&p->vStack) == 1Vec_WecSize(&p->vObjs) == Vec_WecCap(&p->vObjs)%*s( %*s) int Smt_PrsBuildConstant(Wlc_Ntk_t *, char *, int, char *)char *Smt_GetHexFromDecimalString(char *)int Abc_TtReadHexNumber(word *, char *)int Smt_PrsCreateNode(Wlc_Ntk_t *, int, int, int, Vec_Int_t *, char *)Range >= 0fSigned >= 0_n%d_new_size=2iObj1 == NameIdiObj2 == NameIdiObj3 == NameIdVec_IntSize(vFans) >= 3int Smt_PrsReadType(Smt_Prs_t *, int, int *, int *, int *)!strcmp(pStr, "_")pStr[0] != 'b' || pStr[1] != 'v'bvlshrbvashrbvshlrotate_rightrotate_leftbvnotbvandbvorbvxorbvnandbvnorbvxnorconcatzero_extendsign_extendbvcompdistinctbvultbvugtbvulebvugebvsltbvsgtbvslebvsgebvredandbvredorbvredxorbvaddbvsubbvmulbvudivbvurembvsdivbvsrembvsmodbvnegThe following operations is currently not supported (%s) The input SMTLIB file has different number of opening and closing parentheses (%d and %d). Abc_NamObjNumMax(p) == SMT_PRS_ENDvoid Smt_AddTypes(Abc_Nam_t *)set-optionset-logicset-infodefine-fundeclare-funassertletcheck-satget-valueexitLine %d: %s The input SMTLIB file has no opening or closing parentheses.Cannot open input file.aaaaaoaaaaaaaoaaaaaaaaaaaaaaaaaaayaeaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaeaaDaamamamamamamamamamamamamamamamamamamamamamamamamamamamamamamamamaLamamamaaamamamaaamaKamaYamamamamamamamamamamamamaaa8aamamamamamamamamamamamamamamamamamamamamamamamamamamamagamamaamamamamamamamamamamamamamamamamamamamamamamamamamamamamamagamaap->nFileSize > 0src/base/wlc/wlcReadVer.cWlc_Prs_t *Wlc_PrsStart(char *, char *)strlen(pMessage) < WLV_PRS_MAX_LINE - 100int Wlc_PrsWriteErrorMessage(Wlc_Prs_t *, char *, const char *, ...)p->sError[0] == 0Pair:Cannot find end-of-line after symbols "//".Cannot find end-of-line after symbols "`".Cannot find symbols "*/" after symbols "/*".endspecifyIgnoring specify/endspecify directives. Vec_IntSize(p->vLines) == 0int Wlc_PrsPrepare(Wlc_Prs_t *)Vec_IntSize(p->vStarts) == 0Non-standard range.Cannot read name in declaration.Name %s is declared more than once.int Wlc_PrsReadDeclaration(Wlc_Prs_t *, char *)Cannot read model name.CPL_endcaseCannot read module "%s".Width1 == nBitsint Wlc_PrsDerive(Wlc_Prs_t *)Network is already defined.(Vec_IntSize(&p->pNtk->vFfs) & 1) == 0Vec_IntSize(&p->pNtk->vFfs) == 2 * Vec_IntSize(p->pNtk->vInits)Detected async reset "%s". Vec_StrEntryLast(p->vPoPairs) == 0i < Wlc_NtkPoNum(p->pNtk)Vec_IntSize(&p->pNtk->vPoPairs) % 2 == 0Finished parsing %d output pairs to be checked for equivalence. Cannot read name after assign.Name %s is not declared.Cannot read table.Cannot read case statement.Cannot read name after case.Cannot find the object in case statement.Cannot find colon in the case statement.Cannot find equality in the case statement.Cannot read name inside case statement.defaultThe number of values in the case statement is wrong.arstCannot read opening parenthesis in the flop description.Cannot read name inside flop description.arstvalName of flop input or flop output is missing.Initial value of flop "%s" is not specified. Zero is assumed. Warning! Flop init signal "%s" bit-width (%d) is different from the flop declaration (%d) Warning! Flop input "%s" bit-width (%d) is different from that of flop output (%d) Warning! Flop init signal "%s" bit-width (%d) is different from that of flop output (%d) CPL_MEM_mem_data_indata_outaddr_inCannot read name of the input/output port.Name of one of signals of read port is missing.Name of one of signals of write port is missing.mem_inmem_outCPL_RROTCPL_LROTCannot read opening parenthesis in the rotation description.Cannot read name inside rotation description.Some fields of CPL_ROT are missing.Cannot read line %d beginning with %s."?"Warning: Input file contains %d objects with non-zero-based ranges. For example, signal with range [%d:%d] is declared in line %d. Warning: Input file contains %d objects with negative ranges. Warning: Input file contains %d objects with reversed ranges. (pFileName == NULL) != (pStr == NULL)Wlc_Ntk_t *Wlc_ReadVer(char *, char *)test.aigchar Vec_StrEntryLast(Vec_Str_t *)Expecting closing parenthesis.int Wlc_PrsFindDefinition(Wlc_Prs_t *, char *, Vec_Int_t *, int *)Cannot read name after !.Cannot read name after a unary operator.Expecting one comma in this line.Cannot read name in sign-extension.There is no closing brace (}).Cannot read name in concatenation.Expected comma (,) in this place.Cannot read name in MUX.MUX lacks the colon symbol (:).Unsupported operation (%c).Warning: Trailing symbols "%s" in line %d. Name %s is left at the end of the line._c%d_Name %s is already used.char *Wlc_PrsReadName(Wlc_Prs_t *, char *, Vec_Int_t *)Cannot read name in assign-statement.Name %s is used but not declared.*pRange < 32char *Wlc_PrsReadConstant(Wlc_Prs_t *, char *, Vec_Int_t *, int *, int *, int *)Wrong digit in binary constant "%c".Expecting hexadecimal constant and not "%c".Detected async reset.Warning: Case-statement with 1-bit control is treated as a 2:1 MUX (correct for unsigned signals only).Warning: The number of values in the case statement is wrong.Replaced %d dangling internal bits with constant 0. Cannot visualize WLC with more than %d nodes. WLC structure generated by ABCdigraph WLC { Benchmark \"%s\" from file \"%s\". The word-level network contains %d nodes and spans %d levels. NodePo%d [label = "%s%s %d" Node%d [label = "%d:%d'h Node%d [label = "%d: %d" Node%d [label = "%d:%s" Node%d [label = "%d:%s %d", shape = doublecircle, shape = diamond, shape = triangle, shape = trapeziumtitle2 -> NodePo%d [style = invis]; NodePo%d -> NodePo%d [style = invis]; NodePo%d, style = %sbold%s_%s.dot WWWWWWWWWWWWWWWW0000000000000000Sum >= 0 && Sum < Radixsrc/base/wlc/wlcStdin.cvoid Wlc_ComputeSum(char *, char *, int, int)Carry == 0Radix >= 2 && Radix < 36Vec_Str_t *Wlc_ConvertToRadix(unsigned int *, int, int, int)pCex->nRegs == 0void Wlc_NtkReport(Wlc_Ntk_t *, Abc_Cex_t *, char *, int)Cannot find "%s" among nodes of the network. Cannot find "%s" among primary inputs of the network. Radix == 2 || Radix == 10 || Radix == 16((%s %s%s)) #x#b(check-sat)Something did not work out with the command "%s". int Wlc_StdinProcessSmt(Abc_Frame_t *, char *) ()ABC is expecting "get-value" in a follow-up input of the satisfiable problem. ABC received a follow-up input for a problem that is not known to be satisfiable. () ABC does not have a counter-example available to process a "get-value" request. Vec_IntSize(vPairs) > 0 && Vec_IntSize(vPairs) % 2 == 0src/base/wlc/wlcUif.cWlc_Ntk_t *Wlc_NtkUifNodePairs(Wlc_Ntk_t *, Vec_Int_t *)Wlc_NtkPairIsUifable(p, pObj, pObj2)Vec_IntSize(vUifConstrs) > 0Vec_IntEntry(&p->vPos, i) == iObjVec_IntEntry(&p->vCos, i) == iObjpObj->fIsPo!Wlc_ObjHasArithm_rec(p, pObj)src/base/wlc/wlcWin.cint Wlc_ObjHasArithmFanins(Wlc_Ntk_t *, Wlc_Obj_t *)void Wlc_WinCompute(Wlc_Ntk_t *, Wlc_Obj_t *, Vec_Int_t *, Vec_Int_t *)Arithmetic cone of node %d (%s): pObj->Mark == 0void Wlc_WinProfileArith(Wlc_Ntk_t *)Finished printing %d arithmetic cones. bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbybbcbbObHbEbEbEbEbEbEbbEbEbEbEbEbEbƷb!bҶbobbEbEbEbEbEbEbEbEbEbEbbbb b)b&bEbEbEbEbEbEbEb bObYbhbrbbbbb˽bսb߽bbbbbbbbbbb bbbb%b,b3bbbbbbb:bAbHbObbbVbbobvbmFtz FFnOuts > 0 && nOuts <= 64 && (64 % nOuts) == 0src/base/wlc/wlcWriteVer.cvoid Wlc_WriteTableOne(FILE *, int, int, word *, int)module table%d(ind, val); input [%d:0] ind; output [%d:0] val; reg [%d:0] val; always @(ind) begin case (ind) %d'h%x: val = %d'h%x; endcase endmodule pObj->Type == WLC_OBJ_TABLEvoid Wlc_WriteTables(FILE *, Wlc_Ntk_t *)%s[%d:%d]%*swire %s %s ; assign reg %s wire %s %s ; table%d s%d_Index(%s, %s ; LUT lut%d (%s, ; // TT = %-16s = %d'%shvoid Wlc_WriteVerInt(FILE *, Wlc_Ntk_t *, int)Num0 > 0 && Num0 < Wlc_ObjRange(pObj)%-16s = (%s >> %d) | (%s << %d)(%s << %d) | (%s >> %d)always @( or case ( %s ) %d : %s = (1 << nRange) == Wlc_ObjRange(pObj)%s%s%s[%d]assign %s = { %s%s_ } ; %s = %s ? %s + %s + %s : %s - %s - %s ; .%s(%s), .%s(%s) ) ; nBitsMem % nBitsDat == 0%s_%d (CPL_MEM_READCPL_MEM_WRITE%s ? ~%s!%s~&%s~|%s~^%s{ {%d{%s[%d]}}, %s }{ {%d{1'b0}}, %s }Failed to write node "%s" with unknown operator type (%d). + %s ;%s // signed SMT-LIB operator!p->vInits || Wlc_NtkFfNum(p) == Vec_IntSize(p->vInits)i == Wlc_ObjCiId(pObj) [%d:%d]%*s%s_init%*s = reg%d ( .q(%s), .d(%s), .init(%s_init)#%d%*s .qbar(), .clk(%s), .arst(%s), .arstval(%s_init) .arstval(%s)!p->vInits || iFanin == (int)strlen(p->pInits)clkasyncsreWlc_WriteVer(): Cannot open the output file "%s". // Benchmark "%s" from file "%s" written by ABC on %s p->Type == WLC_OBJ_TABLEint Wlc_ObjTableId(Wlc_Obj_t *)p->Type == WLC_OBJ_BIT_SELECTint Wlc_ObjRangeEnd(Wlc_Obj_t *)Ic$cccccccccccccccc c c c ccc c&cc,c2c8c c c>cDc c c c c c c cJcPcVc\cbchcnctc cc cc c c c c c c c ccccczcccccc c ccccccccccccc cc cc c c c c c c c c c c cc cccccccc ccType != ABC_OPER_DFFsrc/base/wln/wlnNdr.cWln_Ntk_t *Wln_NtkFromNdr(void *, int)Wln_ObjFaninNum(pNtk, iObj) == 2nArray == 1 && NameId == -1 && InstId == -1i == Vec_PtrSize(vConstStrings)temp_ndr.vDumped design "%s" into file "temp_ndr.v". D:\temp\brijesh\for_alan_dff_warning\work_fir_filter_fir_filter_proc_out.ndrtest__test.v*pPlace == 0./src/misc/vec/vecHash.hint Hash_Int2ManInsert(Hash_IntMan_t *, int, int, int)int *Hash_Int2ManLookup(Hash_IntMan_t *, int, int)Retiming network is not available.FcFcFcFcFcFcFcGcGcGcGcFcFcFcFczGcFcGcGcGcGcGcGcGcGcGcGcGcGcGcGc Gc&Gc,Gc2Gc8Gc>GcDGcGcGcGcGcGcGcGcGcGcGcGcGcGcGcFcFcJGcPGcFcFcFcFcGcGcGcGcVGc\GcGcFcFcbGcGcFchGcnGcGcGcGcGcGcGcGcGcGcGcGcGcGcGcGcGcGcFcGcGcFcGctGcGcGcFcHash_IntManEntryNum(p->pRanges) == 128src/base/wln/wlnNtk.cWln_Ntk_t *Wln_NtkAlloc(char *, int)Printing %d objects of network "%s": Network contains combinational loop! Node %16s is encountered twice on the following path: Node %16s (ID %6d) of type %5s (type ID %2d) -> Primary output %16s (ID %6d) Flip-flop %16s (ID %6d) The network has %d objects and %d (%6.2f %%) of them are not connected to the outputs. These unconnected objects feed into %d sink objects without fanout: Node %16s (ID %6d) of type %5s (type ID %2d) Unconnected object %s void Wln_NtkTransferNames(Wln_Ntk_t *, Wln_Ntk_t *)!Wln_NtkHasCopy(pNew) && Wln_NtkHasCopy(p)!Wln_NtkHasNameId(pNew) && Wln_NtkHasNameId(p)!Wln_NtkHasInstId(pNew) && Wln_NtkHasInstId(p)!Wln_ObjIsFf(p, iObj)int Wln_NtkDupDfs_rec(Wln_Ntk_t *, Wln_Ntk_t *, int)iOffset == Vec_IntSize(vFaninMap)void Wln_NtkStartFaninMap(Wln_Ntk_t *, Vec_Int_t *, int)iOffset == Vec_IntSize(vFanoutMap)void Wln_NtkStartFanoutMap(Wln_Ntk_t *, Vec_Int_t *, Vec_Int_t *, int)Wln_ObjRefs(p, iObj) == Vec_IntEntry(vRefsCopy, iObj)void Wln_NtkStaticFanoutStart(Wln_Ntk_t *)Printing fanouts of %d objects of network "%s": Fanouts : rcqcqcqcqcqcqcZscZscZscZscqcqcpc,qc6qcqcqc@qcZscZscLrcqcZscZscZscZscZscZscZscpc,qc6qcqcqc@qcqcqcZscSrcZscZrcZscZscZscZscZscZscZscZscarcqc"qc"qcqcrcJqcTqcqc^qcZscZschrcorcrcrcvrchqc&rc0rc}rcrqc7rc>rcZscrcZscrcZscZscZscZscZscZscZscZscZscZscZscrcZsc|qcrcrcqcrcErcrcZscrcWln_ObjIsConst(p, iObj)src/base/wln/wlnObj.cchar *Wln_ObjConstString(Wln_Ntk_t *, int)Wln_ObjIsNone(p, iObj)void Wln_ObjUpdateType(Wln_Ntk_t *, int, int)void Wln_ObjSetConst(Wln_Ntk_t *, int, int)Wln_ObjIsSlice(p, iObj)void Wln_ObjSetSlice(Wln_Ntk_t *, int, int)pVec->nSize < pVec->nCapvoid Wln_ObjAddFanin(Wln_Ntk_t *, int, int)iObj == Vec_StrSize(&p->vSigns)int Wln_ObjAlloc(Wln_Ntk_t *, int, int, int, int)iObj == Vec_IntSize(&p->vRanges)Obj %6d : Type = %6s Fanins = %d : ucucucucucucucvcvcvcvcucucucucJvcucucucvcvcucucvcvcvcvcvcvcvcucucucucvcvcvcvcvcPvcvcVvcvcvcvcvcvcvcvcvc\vcbvcTucTucvc vcZuc`ucfuclucvcvchvcnvc&vc,vctvcrucxuc2vczvc~uc8vc>vcvcvcvcvcvcvcvcvcvcvcvcvcvcvcvcvcvcucvcvcucvcDvcvcvcucQObj %6d : Type = %6s NameId = %5d InstId = %5d Fanins = %d : (%d : %d %d) Total number of objects = %d. Objects with non-trivial delay = %d. The following %d objects have non-trivial delays: Detected %d flops and %d flop classes. Wln_ObjRefs(pNtk, iObj) == Vec_IntEntry(vRefsCopy, iObj)src/base/wln/wlnRetime.cWln_Ret_t *Wln_RetAlloc(Wln_Ntk_t *)pHead[0]int *Wln_RetHeadToTail(Wln_Ret_t *, int *)pLink[0]int Wln_RetRemoveOneFanin(Wln_Ret_t *, int)Wln_ObjIsFf( p->pNtk, iFlop )int Wln_RetRemoveOneFanout(Wln_Ret_t *, int)void Wln_RetInsertOneFanin(Wln_Ret_t *, int, int)void Wln_RetInsertOneFanout(Wln_Ret_t *, int, int)Move %4d : Recording initial state (delay = %6d) Move %4d : Recording %s retiming (delay = %6d) :forward backward %d (NameID = %d) %3d retimed objectsWarning: Object %d of type %s has zero delay. Retiming will not work correctly. Sinks: Sources: Retiming instruction contains %d moves and %d total retimed objects. Initial delay = %d. The best delay achieved = %d. Improvement = %d. (%6.2f %%) int Wln_RetCheckForwardOne(Wln_Ret_t *, int)int Wln_RetCheckBackwardOne(Wln_Ret_t *, int)Objects without fanout:The design has no delay information.Assuming default delays: 10 units for most nodes and 1 unit for bit-slice, concat, and buffers driving COs.Using delays given by the user in the input file. The resulting moves recorded in terms of name IDs of the NDR nodes:Cannot retime forward and backward.Cannot reduce delay by retiming.0000src/base/wln/wlnWlc.cWln_Ntk_t *Wln_NtkFromWlc(Wlc_Ntk_t *)Flop %3d init state: %d'b (range %d)ff_init_%dp->pInits == NULL || iBit == (int)strlen(p->pInits)Vec_IntSize(vInits) == Wlc_NtkCoNum(p) - Wlc_NtkPoNum(p)test_wlc2wln.v./src/base/wlc/wlc.hccccccccccccccccccccccccccccchchcc$cc2cccccccccccccccccccccCcKccScScScScScScScSccScScScScScScScScc8cccKclccScScScScScScScScScScScScScScScScScScScScScqcScScScScScScScScScScScScScScScScScScScScScScScScScScScScScScScScc cccccccccccccccccccccccccccOccYccccccccccccmcwccccccccccccccccccccccccccccccccccccccccccccc cmFtz FFsrc/base/wln/wlnWriteVer.cvoid Wln_WriteTableOne(FILE *, int, int, word *, int)%-16s = %s ; %-16s = %sNum0 > 0 && Num0 < Wln_ObjRange(p, iObj)void Wln_WriteVerInt(FILE *, Wln_Ntk_t *)(1 << nRange) == Wln_ObjRange(p, iObj)Wln_WriteVer(): Cannot open the output file "%s". Abc_NtkIsSopLogic(p)src/base/acb/acbAbc.cAcb_Ntk_t *Acb_NtkFromAbc2(Abc_Ntk_t *)Acb_Ntk_t *Acb_NtkFromAbc(Abc_Ntk_t *)pObj == NULL || pObj->iTemp == (int)Abc_ObjId(pObj)Abc_SopGetVarNum((char *)pObjNew->pData) == Abc_ObjFaninNum(pObjNew)Abc_Ntk_t *Acb_NtkToAbc(Abc_Ntk_t *, Acb_Ntk_t *)Cannot find fanin %d of node "%s". nArray == 1Acb_Ntk_t *Acb_NtkFromNdr(char *, void *, Abc_Nam_t *, Vec_Int_t *, int)Adding constant 0 driver to non-driven PO "%s". 1'bznCis >= 0 && nCos >= 0 && nObjs >= 0src/base/acb/acb.hAcb_Ntk_t *Acb_NtkAlloc(Acb_Man_t *, int, int, int, int)int Acb_ObjAlloc(Acb_Ntk_t *, Acb_ObjType_t, int, int)!Acb_ObjIsBox(p, iObj) || nFons > 0p->pCostsFlt == NULLvoid Vec_QueSetPriority(Vec_Que_t *, float **)iFanin > 0void Acb_ObjAddFanin(Acb_Ntk_t *, int, int)pFanins[ 1 + pFanins[0] ] == -1i>0int Acb_ObjFanOffset(Acb_Ntk_t *, int)Acb_ObjTruth(p, i) == 0void Acb_ObjSetTruth(Acb_Ntk_t *, int, word)word Acb_ObjTruth(Acb_Ntk_t *, int)Acb_NtkHasObjTruths(p)Network with name "%s" already exists. NtkId == pNtk->Idvoid Acb_NtkAdd(Acb_Man_t *, Acb_Ntk_t *)Acb_ObjCopy(p, i) == -1void Acb_ObjSetCopy(Acb_Ntk_t *, int, int)Acb_ObjType_t Acb_ObjType(Acb_Ntk_t *, int)word *Acb_ObjTruthP(Acb_Ntk_t *, int)int Acb_ObjCopy(Acb_Ntk_t *, int)Acb_NtkHasObjCopies(p)Acb_ObjName(p, i) == 0void Acb_ObjSetName(Acb_Ntk_t *, int, int)int Acb_ObjName(Acb_Ntk_t *, int)Acb_NtkHasObjNames(p)Acb_ObjWeight(p, i)== 0void Acb_ObjSetWeight(Acb_Ntk_t *, int, int)int Acb_ObjWeight(Acb_Ntk_t *, int)Acb_NtkHasObjWeights(p)Acb_NtkToAbc: The network check has failed.c=d:d;d9;dndldldldldld2/wJJ~|fuYufu+2++~|fuYufuGATE buf 1 O=a; PIN * INV 1 999 1.0 0.0 1.0 0.0 GATE inv 1 O=!a; PIN * INV 1 999 1.0 0.0 1.0 0.0 GATE and2 1 O=a*b; PIN * INV 1 999 1.0 0.0 1.0 0.0 GATE and3 1 O=a*b*c; PIN * INV 1 999 1.0 0.0 1.0 0.0 GATE and4 1 O=a*b*c*d; PIN * INV 1 999 1.0 0.0 1.0 0.0 GATE or2 1 O=a+b; PIN * INV 1 999 1.0 0.0 1.0 0.0 GATE or3 1 O=a+b+c; PIN * INV 1 999 1.0 0.0 1.0 0.0 GATE or4 1 O=a+b+c+d; PIN * INV 1 999 1.0 0.0 1.0 0.0 GATE nand2 1 O=!(a*b); PIN * INV 1 999 1.0 0.0 1.0 0.0 GATE nand3 1 O=!(a*b*c); PIN * INV 1 999 1.0 0.0 1.0 0.0 GATE nand4 1 O=!(a*b*c*d); PIN * INV 1 999 1.0 0.0 1.0 0.0 GATE nor2 1 O=!(a+b); PIN * INV 1 999 1.0 0.0 1.0 0.0 GATE nor3 1 O=!(a+b+c); PIN * INV 1 999 1.0 0.0 1.0 0.0 GATE nor4 1 O=!(a+b+c+d); PIN * INV 1 999 1.0 0.0 1.0 0.0 GATE xor 1 O=!a*b+a*!b; PIN * INV 1 999 1.0 0.0 1.0 0.0 GATE xnor 1 O=a*b+!a*!b; PIN * INV 1 999 1.0 0.0 1.0 0.0 GATE zero 0 O=CONST0; GATE one 0 O=CONST1; iccad17.genlibi == NameId && !fFoundsrc/base/acb/acbFunc.cAbc_Nam_t *Acb_VerilogStartNames() (),;=Vec_IntEntry(vBuffer, 0) == ACB_MODULEvoid *Acb_VerilogSimpleParse(Vec_Int_t *, Abc_Nam_t *) (),Cannot find name "%s" among node names of this network. (),;Cannot read input file "%s". Cannot read weight file "%s". input %s; output %s; wire %s; %s (, %s %*s // weight = %dAcb_ObjType(p, iObj) == ABC_OPER_CONST_F || Acb_ObjType(p, iObj) == ABC_OPER_CONST_Tvoid Acb_VerilogSimpleWrite(Acb_Ntk_t *, char *) 1'b%d!Acb_ObjIsCi(p, iObj)int Acb_NtkFindRoots_rec(Acb_Ntk_t *, int, Vec_Bit_t *)Vec_IntSize(vTargets) > 0Vec_Int_t *Acb_NtkFindRoots(Acb_Ntk_t *, Vec_Int_t *, Vec_Bit_t **)Acb_ObjWeight(p, iObj) > 0Vec_Int_t *Acb_NtkFindDivsCis(Acb_Ntk_t *, Vec_Int_t *)Divisors are %d support variables (CIs in the TFO of the targets). Reducing divisor set from %d to !Acb_ObjIsCo(p, iObj)void Acb_NtkFindNodes_rec(Acb_Ntk_t *, int, Vec_Int_t *)!Acb_ObjIsCio(p, iObj)int Acb_ObjToGia(Gia_Man_t *, Acb_Ntk_t *, int, Vec_Int_t *)Acb_ObjCopy(p, iFanin) >= 0status == l_TrueVec_Int_t *Acb_FindSupportStart(sat_solver *, int, Vec_Int_t *, Vec_Wrd_t **, int *)Vec_Int_t *Acb_FindSupportNext(sat_solver *, int, Vec_Int_t *, Vec_Wrd_t *, int *)Exceeded %d words. *pnPats < NWORDS*64Vec_Int_t *Acb_FindSupportMinOne(sat_solver *, int, Vec_Wrd_t *, int *, Vec_Int_t *, int)nWords <= NWORDSvoid Acb_FindReplace(sat_solver *, int, Vec_Int_t *, Vec_Wrd_t *, int, Vec_Int_t *)Vec_IntEntry(vWeights, k) < Vec_IntEntry(vWeights, iDiv)Starting cost = %d. Timeout after %d sec. Iter %4d: Next cost = %5d. Support computation timed out after %d sec. status == l_FalseVec_Int_t *Acb_DerivePatchSupport(Cnf_Dat_t *, int, int, int, Vec_Int_t *, Acb_Ntk_t *, Vec_Int_t *, int)Proved that the problem has a solution. Found one feasible set of %d divisors. Support minimization did not succeed. Minimized support to %d supp vars. Demonstrated that the problem has NO solution. Solved the problem with %d supp vars. FreeVar < sat_solver_nvars(pSat)char *Acb_EnumerateSatAssigns(sat_solver *, int, int, Vec_Int_t *, Vec_Int_t *, Vec_Str_t *)Finished enumerating %d cubes. status == 1iVar >= 0void Acb_CollectIntNodes_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)Gia_ManCoNum(pOne) == 1Gia_Man_t *Acb_UpdateMiter(Gia_Man_t *, Gia_Man_t *, int, int, Vec_Int_t *, int)Gia_ManCiNum(pRes) == Gia_ManCiNum(pM)Gia_ManCoNum(pRes) == Gia_ManCoNum(pM) patch p0 (%s .%s(%s), .%s(%s)Vec_WecSize(vGates) == Vec_IntSize(vUsed) + nNodes + Vec_IntSize(vTars)Vec_Ptr_t *Acb_GenerateSignalNames(Acb_Ntk_t *, Vec_Int_t *, Vec_Int_t *, int, Vec_Int_t *, Vec_Wec_t *)Vec_IntEntry(vGate, 0) == ABC_OPER_BIT_BUFww%d// Patch statistics: in = %d out = %d gate = %d (const = %d buf = %d inv = %d other = %d) module patch (Vec_IntSize(vTars) == nOutsVec_Str_t *Acb_GeneratePatch(Acb_Ntk_t *, Vec_Int_t *, Vec_Int_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Int_t *)wwVec_IntEntry(vGate, 0) == ABC_OPER_CONST_F || Vec_IntEntry(vGate, 0) == ABC_OPER_CONST_TSynthesized patch with %d inputs, %d outputs and %d gates (const = %d buf = %d inv = %d other = %d). %s .%s(t%d_%s)Vec_Ptr_t *Acb_GenerateSignalNames2(Vec_Wec_t *, Vec_Ptr_t *, Vec_Ptr_t *)Vec_Str_t *Acb_GeneratePatch2(Gia_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *)Synthesized patch with %d inputs, %d outputs and %d gates. patch.vFinished dumping patch file "%s". temp.vFinished dumping intermediate file "%s". Finished dumping the resulting file "%s". Patch has %d inputs: %d=%s(w=%d) Total weight = %d M_quo: Quantifying target %3d Gia_ManCiNum(pCof) == Gia_ManCiNum(p)Cnf_Dat_t *Acb_NtkDeriveMiterCnf(Gia_Man_t *, int, int, int)M_syn: %*sCof%d%d : %*sInter%d : Gia_Man_t *Acb_NtkDeriveMiterCnfInter2(Gia_Man_t *, int, int)Cof0 : Cof1 : Gia_Man_t *Acb_NtkDeriveMiterCnfInter(Gia_Man_t *, int, int)iVar >= 0 && iVar < nVarschar *Acb_RemapOneFunction(char *, Vec_Int_t *, Vec_Int_t *, int)The number of used variables %d (out of %d). The number of targets = %d. NtkF: NtkG: Miter: The ECO problem has %s solution. NO Considering target %d (out of %d)... Target %d has support with %d variables. Tar%02d: Function %d %sThe ECO solution was verified successfully. The ECO solution verification FAILED. Finished dumping resulting file "%s". _w.vPermuting targets as follows: Acb_NtkCiNum(pNtkF) == Acb_NtkCiNum(pNtkG)void Acb_NtkRunEco(char **, int, int, int, int)Acb_NtkCoNum(pNtkF) == Acb_NtkCoNum(pNtkG)read %s; strash; write temp1.aig; read %s; strash; write temp2.aig; &cec temp1.aig temp2.aigvoid *Ndr_Create(int)int Acb_Type2Oper(int)char *Acb_ObjNameStr(Acb_Ntk_t *, int)char *Acb_Oper2Name(int)int sat_solver_add_xor(sat_solver *, int, int, int, int)Cidint satoko_add_xor(satoko_t *, int, int, int, int)int sat_solver_var_literal(sat_solver *, int)Updating best solution.ECO does not exist.Unsat is detected earlier.Assuming constant 0 function.Computation did not succeed.src/base/acb/acbMfs.cint Acb_DeriveCnfFromTruth(word, int, Vec_Int_t *, Vec_Str_t *)Vec_StrSize(vCnfBase) == 0void Acb_DeriveCnfForWindowOne(Acb_Ntk_t *, int)Vec_WecSize(vCnfs) == Acb_NtkObjNumMax(p)Vec_Wec_t *Acb_DeriveCnfForWindow(Acb_Ntk_t *, Vec_Int_t *, int)Acb_ObjFunc(p, iFanin) >= 0void Acb_DeriveCnfForNode(Acb_Ntk_t *, int, sat_solver *, int)Cnf_Dat_t *Acb_NtkWindow2Cnf(Acb_Ntk_t *, Vec_Int_t *, int)nRoots == Vec_IntSize(vFaninVars)nVars == nVarsAllVec_IntEntry(&p->vObjFunc, Abc_Lit2Var(iObj)) != -1void Acb_NtkWindowUndo(Acb_Ntk_t *, Vec_Int_t *)sat_solver_nvars(pSat) == 0int Acb_NtkWindow2Solver(sat_solver *, Cnf_Dat_t *, Vec_Int_t *, int, int, int)nTimes == 1 || nTimes == 2 || nTimes == 6Test == pCnf->pClauses[0][0]word Acb_ComputeFunction(sat_solver *, int, int, Vec_Int_t *, int)%s: %s: Vec_IntEntryLast(vDivs) == PivotVec_Int_t *Acb_NtkDivisors(Acb_Ntk_t *, int, int, int)Acb_ObjTravIdDiff(p, Root) > 2int Acb_ObjLabelTfo(Acb_Ntk_t *, int, int, int, int)Diff == 1void Acb_ObjDeriveTfo_rec(Acb_Ntk_t *, int, Vec_Int_t *, Vec_Int_t *, int)Vec_IntEntryLast(vTfo) == Pivotvoid Acb_ObjDeriveTfo(Acb_Ntk_t *, int, int, int, Vec_Int_t **, Vec_Int_t **, int)Vec_IntEntryLast(vRoots) != PivotVec_IntEntryLast(vTfiNew) == PivotVec_Int_t *Acb_NtkCollectNewTfi(Acb_Ntk_t *, int, Vec_Int_t *, Vec_Int_t *, int *)Vec_IntEntryLast(vTfi) == PivotVec_Int_t *Acb_NtkCollectWindow(Acb_Ntk_t *, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Failed internal check at node %d. int Acb_NtkFindSupp1(Acb_Ntk_t *, int, sat_solver *, int, int, Vec_Int_t *, Vec_Int_t *)Acb_ObjFunc(p, iFanin) >= 0 && Acb_ObjFunc(p, iFanin) < nDivsint Acb_NtkFindSupp2(Acb_Ntk_t *, int, sat_solver *, int, int, Vec_Int_t *, Vec_Int_t *, int, int)Acb_ObjLevelD( p, Pivot ) > 1nNonCrits < Vec_IntSize(vSupp)iFanin != iFanin2int Acb_NtkFindSupp3(Acb_Ntk_t *, int, sat_solver *, int, int, Vec_Int_t *, Vec_Int_t *, int, int)Acb_ObjFunc(p, iFanin3) >= 0Vec_IntCheckUniqueSmall(vSupp)NodeMark > 0nValues % nScope == 0void Acb_NtkOptNodeAnalyze(Acb_Mfs_t *, int, int, int, int *, Vec_Int_t *)nFrames <= 16%2d:Divisors = %d. Frames = %d. Patterns = %d. Acb_ObjFanoutNum(p->pNtk, Pivot) > 0int Acb_NtkOptNode(Acb_Mfs_t *, int)Node %d: Window contains %d objects and %d divisors. PivotVar == Acb_ObjFunc(p->pNtk, Pivot)Found constant %d. Vec_IntSize(p->vSupp) < p->pPars->nLutSizeFound %d inputs: Vec_IntSize(p->vSupp) <= p->pPars->nLutSizeResult < p->pPars->nLutSizeVec_IntSize(p->vSupp)-Result <= p->pPars->nLutSizeObj %5d: Found %d Hvars and %d Gvars: Var >= 0 && Var < nDivsVar + 2*pCnf->nVars < sat_solver_nvars(p->pSat[1])Error: SAT solver became UNSAT at a wrong place (place 2). Found C-var in object %d. Error: SAT solver became UNSAT at a wrong place (place 1). %s-optimization parameters: TfiLev(I) = %d TfoLev(O) = %d WinMax(W) = %d LutSize = %d AreaNode = %d Win = %d (Ave = %d) DivAve = %d Change = %d C = %d N1 = %d N2 = %d N3 = %d Over = %d Str = %d 2Node = %d. Windowing CNF computeMake solverVec_Str_t *Acb_ObjCnfs(Acb_Ntk_t *, int)int Acb_ObjFunc(Acb_Ntk_t *, int)Acb_NtkHasObjFuncs(p)Acb_ObjFunc(p, i) == -1void Acb_ObjSetFunc(Acb_Ntk_t *, int, int)iVarA >= 0 && iVarB >= 0 && iVarEn >= 0int sat_solver_add_buffer_enable(sat_solver *, int, int, int, int)int Acb_ObjLevelD(Acb_Ntk_t *, int)void Acb_NtkRemapIntoSatVariables(Acb_Ntk_t *, Vec_Int_t *)int Vec_QuePop(Vec_Que_t *) Quitting.Error: SAT solver became UNSAT at a wrong place (while adding new CNF).Error: SAT solver became UNSAT at a wrong place.Too many divisors.e+e eeeteeeeeUUUUUUUU33333333""""""""DDDDDDDD 00000000src/base/acb/acbPush.cvoid Acb_ObjPushToFanout(Acb_Ntk_t *, int, int, int)!Acb_ObjIsCio(p, iFanout)iFanoutFaninIndex >= 0iFaninIndex < Acb_ObjFaninNum(p, iObj)Acb_ObjFanoutNum(p, iObj) == 1void Acb_ObjPushToFanin(Acb_Ntk_t *, int, int, int)!Acb_ObjIsCio(p, iFanin)iFaninIndex2 < Acb_ObjFaninNum(p, iObj)iFaninIndex != iFaninIndex2Acb_ObjFanoutNum(p, iFanin) == 1void Acb_ObjRemoveDup(Acb_Ntk_t *, int, int, int)Acb_ObjFanin(p, iObj, i) == Acb_ObjFanin(p, iObj, j)void Acb_ObjRemoveDupFanins(Acb_Ntk_t *, int)void Acb_ObjRemoveConst(Acb_Ntk_t *, int)Acb_ObjFaninNum(p, iObj) == 0uTruth == 0 || ~uTruth == 0void Acb_ObjRemoveBufInv(Acb_Ntk_t *, int)Acb_ObjFaninNum(p, iObj) == 1uTruth == s_Truths6[0] || ~uTruth == s_Truths6[0]Acb_ObjIsCo(p, iFanout)Saved %d nodes after %d pushes. c0 != c1int Abc_Tt6CheckOutDec(word, int, word *)iVar >= 0 && iVar < 6word Abc_Tt6Cofactor0(word, int)word Abc_Tt6Cofactor1(word, int)!Abc_Tt6HasVar(t, iVar)word Abc_Tt6RemoveVar(word, int)void Acb_ObjRemoveFaninFanoutOne(Acb_Ntk_t *, int, int)pFanins[ 1 + iFaninIndex ] == iFaninvoid Acb_ObjDeleteFanin(Acb_Ntk_t *, int, int)iFanin != iFaninNewvoid Acb_ObjPatchFanin(Acb_Ntk_t *, int, int, int)void Acb_ObjRemoveFaninFanout(Acb_Ntk_t *, int)pFanins[i] > 0void Acb_ObjRemoveFanins(Acb_Ntk_t *, int)!Acb_ObjIsCio(p, iObj) + p->LevelMax >= LevelSumsrc/base/acb/acbUtil.cint Acb_ObjSlack(Acb_Ntk_t *, int)int Acb_ObjComputePathD(Acb_Ntk_t *, int)int Acb_ObjComputePathR(Acb_Ntk_t *, int)Obj = %5d : LevelD = %5d LevelR = %5d PathD = %5d PathR = %5d Paths = %5d LevelD == LevelRint Acb_NtkComputePaths(Acb_Ntk_t *)Computed %d paths. Vec_IntEntryLast(vTfi) == iObjvoid Acb_NtkUpdateTiming(Acb_Ntk_t *, int)Vec_IntEntryLast(vTfo) == iObjnPaths1 == nPaths2Node %5d : LevelD = %d. LevelR = %d. !Acb_ObjIsCio(p, Pivot)void Acb_NtkResetNode(Acb_Ntk_t *, int, word, Vec_Int_t *)Acb_ObjFanoutNum(p, Pivot) > 0void Acb_NtkFindNodes2_rec(Acb_Ntk_t *, int, Vec_Int_t *)int Acb_ObjToGia2(Gia_Man_t *, int, Acb_Ntk_t *, int, Vec_Int_t *, int)iLit > 0Vec_Int_t *Acb_NtkCollectUser(Acb_Ntk_t *, Vec_Ptr_t *)Vec_IntSize(vRes) == Vec_PtrSize(vUser)int Acb_NtkExtract(char *, char *, int, int, Gia_Man_t **, Gia_Man_t **, int, Vec_Int_t **, Vec_Ptr_t **, Vec_Bit_t **)int Abc_ObjToGia2(Gia_Man_t *, Abc_Ntk_t *, Abc_Obj_t *, Vec_Int_t *, int)pFanin->iTemp >= 0Abc_NtkCiNum(pNtkF) == Abc_NtkCiNum(pNtkG)int Abc_NtkExtract(char *, char *, int, int, Gia_Man_t **, Gia_Man_t **, Vec_Int_t **, Vec_Ptr_t **, Vec_Bit_t **)Abc_NtkCoNum(pNtkF) == Abc_NtkCoNum(pNtkG) ,pTemp < pLimitVec_Int_t *Acb_NtkPlaces(char *, Vec_Ptr_t *)Vec_IntSize(vPlaces) == 2*Vec_PtrSize(vNames)Cannot open output file "%s". // [t_%d = %s] // t_%d%s t%d_%s%s buf( %s, t_%d ); buf( %s, t%d_%s ); Canont open input file "%s". weights.txtint Acb_ObjLevelR(Acb_Ntk_t *, int)int Acb_ObjPathD(Acb_Ntk_t *, int)int Acb_ObjPathR(Acb_Ntk_t *, int)void Vec_FltWriteEntry(Vec_Flt_t *, int, float)p->pHeap[0] == -1void Vec_QueClear(Vec_Que_t *)p->pHeap[i] >= 0 && p->pOrder[p->pHeap[i]] == iint Gia_ManAppendXorReal(Gia_Man_t *, int, int)fNf f(fffffrffffp->ppGraphs == NULLsrc/base/bac/bacBlast.cvoid Bac_ManPrepareGates(Bac_Man_t *)iRes > 0int Bac_ManAddBarbuf(Gia_Man_t *, int, Bac_Man_t *, int, int, int, int, Vec_Int_t *)Bac_ManNtkIsOk(p, iLNtk) && Bac_ManNtkIsOk(p, iRNtk)Bac_ObjIsBoxPrim(p, iBox)int Bac_ManExtract_rec(Gia_Man_t *, Bac_Ntk_t *, int, int, Vec_Int_t *)nLits <= 16pGraph != NULLBac_BoxBoNum(p, iBox) == 2Vec_IntSize(&p->vBuf2LeafNtk) == pNew->nBufsGia_Man_t *Bac_ManExtract(Bac_Man_t *, int, int)Vec_IntSize(&p->vBuf2LeafNtk) == Gia_ManBufNum(pGia)void Bac_ManMarkNodesGia(Bac_Man_t *, Gia_Man_t *)pObj->Value == Gia_ObjFanin1(pObj)->ValueCount == Gia_ManBufNum(pGia)Gia_ObjFanin0(pObj)->Value == 1!Vec_IntSize(&pNew->vBuf2RootNtk)void Bac_ManRemapBarbufs(Bac_Man_t *, Bac_Man_t *)Bac_ObjIsCo(pNtk, iTerm)void Bac_NtkInsertGia(Bac_Man_t *, Gia_Man_t *)Vec_IntSize(&p->vBuf2LeafNtk) == pNtk->nBarBufs2void Bac_ManMarkNodesAbc(Bac_Man_t *, Abc_Ntk_t *)pObj->iTemp == pFanin->iTempAbc_ObjFanin0(pObj)->iTemp == 1Count == pNtk->nBarBufs2!pFanin || Abc_NodeIsConst0(pFanin) || Abc_NodeIsConst1(pFanin)void Bac_NtkCreateOrConnectFanin(Abc_Obj_t *, Bac_Ntk_t *, int)Abc_NamObjNumMax(p->pMods) > 1void Bac_NtkPrepareLibrary(Bac_Man_t *, Mio_Library_t *)void Bac_NtkInsertNtk(Bac_Man_t *, Abc_Ntk_t *)Bac_ObjIsCo(pCbaNtk, iTerm)src/base/bac/bac.hint Bac_ObjFanin(Bac_Ntk_t *, int)Bac_ObjIsBox(p, b)int Bac_BoxBi(Bac_Ntk_t *, int, int)Bac_ObjIsCio(p, i)int Bac_ObjIndex(Bac_Ntk_t *, int)Bac_ManNtkIsOk(p->pDesign, i)int Bac_NtkId(Bac_Ntk_t *)int Bac_BoxNtkId(Bac_Ntk_t *, int)int Bac_BoxBoNum(Bac_Ntk_t *, int)Bac_ObjCopy(p, i) == -1void Bac_ObjSetCopy(Bac_Ntk_t *, int, int)Bac_ObjIndex(p, i) == -1void Bac_ObjSetIndex(Bac_Ntk_t *, int, int)Bac_NtkObjNumAlloc(p)void Bac_NtkStartCopies(Bac_Ntk_t *)iObj == Vec_IntSize(&p->vFanin)int Bac_ObjAlloc(Bac_Ntk_t *, Bac_ObjType_t, int)Bac_ObjFanin(p, i) == -1 && Bac_ObjIsCo(p, i)void Bac_ObjSetFanin(Bac_Ntk_t *, int, int)p->iCopy == -1void Bac_NtkSetCopy(Bac_Ntk_t *, int)pNew != pvoid Bac_NtkDupUserBoxes(Bac_Ntk_t *, Bac_Ntk_t *)pNew->pDesign != NULLvoid Bac_NtkAlloc(Bac_Ntk_t *, int, int, int, int)Bac_NtkPiNum(pNew) == 0Bac_NtkPoNum(pNew) == 0Network with name %s already exists. NtkId == Bac_NtkId(pNew)Bac_ObjName(p, i) == 0 && !Bac_ObjIsCo(p, i)void Bac_ObjSetName(Bac_Ntk_t *, int, int)int Bac_ObjNameInt(Bac_Ntk_t *, int)int Bac_BoxBiNum(Bac_Ntk_t *, int)Bac_ObjIsBox(p, i)&&Bac_ManNtkIsOk(p->pDesign, x)void Bac_BoxSetNtkId(Bac_Ntk_t *, int, int)p->iBoxNtk == -1void Bac_NtkSetHost(Bac_Ntk_t *, int, int)Bac_NtkHasNames(p)void Bac_NtkMoveNames(Bac_Ntk_t *, Bac_Ntk_t *)!Bac_NtkHasNames(pNew)void Bac_NtkStartNames(Bac_Ntk_t *)The library does not have one of the elementary gates.The standard cell library is not available.*pBuffer == ' 'src/base/bac/bacBac.cint BacManReadBacNameAndNums(char *, int *, int *, int *, int *)Vec_StrSize(p) == Vec_StrCap(p)void Bac_ManReadBacVecStr(Vec_Str_t *, int *, Vec_Str_t *, int)Vec_IntSize(p) == Vec_IntCap(p)void Bac_ManReadBacVecInt(Vec_Str_t *, int *, Vec_Int_t *, int)Bac_NtkPiNum(pNtk) == Bac_NtkPiNumAlloc(pNtk)void Bac_ManReadBacNtk(Vec_Str_t *, int *, Bac_Ntk_t *)Bac_NtkPoNum(pNtk) == Bac_NtkPoNumAlloc(pNtk)Bac_NtkObjNum(pNtk) == Bac_NtkObjNumAlloc(pNtk)Bac_NtkInfoNum(pNtk) == Bac_NtkInfoNumAlloc(pNtk)nNtks > 0Bac_Man_t *Bac_ManReadBacInt(Vec_Str_t *)Num1 >= 0 && Num2 >= 0 && Num3 >= 0Bac_ManNtkNum(p) == nNtksPos == Vec_StrSize(vOut)nFileSize == Vec_StrSize(vOut)Bac_Man_t *Bac_ManReadBac(char *)# Design "%s" written by ABC on %s %s %d %s %d %d %d %d p->pMioLib == NULLvoid Bac_ManWriteBac(char *, Bac_Man_t *)New word level@_read@_write@_ps@_put@_get@_clp@_cec@_testapvh.bacusage: @_read [-apvh] reads hierarchical design in BLIF or Verilog -a : toggle using old ABC parser [default = %s] -p : toggle using Ptr construction [default = %s] Bac_CommandWrite(): There is no current design. usage: @_write [-apvh] writes the design into a file in BLIF or Verilog -a : toggle using assign-statement for primitives [default = %s] -p : toggle using Ptr construction (mapped Verilog only) [default = %s] Bac_CommandPs(): There is no current design. usage: @_ps [-M num] [-vh] -M num : the number of first modules to report [default = %d] %-12s : pi =%5d po =%5d pri =%4d mod =%6d box =%7d obj =%7d mem =%6.3f MBModule %5d : box =%6d clp =%7d -> %sBac_CommandPut(): There is no current design. Bac_CommandPut(): Conversion to AIG has failed. usage: @_put [-bvh] extracts AIG from the hierarchical design -b : toggle using barrier buffers [default = %s] Bac_CommandGet(): There is no current design. Bac_CommandGet(): There is no current mapped design. Bac_CommandGet(): There is no current AIG. usage: @_get [-mvh] inserts AIG or mapped network into the hierarchical design -m : toggle using mapped network from main-space [default = %s] usage: @_clp [-vh] collapses the current hierarchical design Bac_CommandCec(): There is no current design. Extracting AIG from the current design has failed. src/base/bac/bacCom.cint Bac_CommandCec(Abc_Frame_t *, int, char **)Extracting AIG from the original design has failed. usage: @_cec [-vh] combinational equivalence checking usage: @_test [-vh] Converting from Ptr failed.There is no CBA design present.ABC framework is not started.Unrecognized input file extension.Bac_CommandRead(): Input file name should be given on the command line.Converting to Ptr has failed.Unrecognized output file extension.K r (2@W̿ !"#$%&'()s *+,-./ 0$1f2(3.455<6C7B8G9L:Q;V<[=iC>`?Bs@gkAqvB{CDE`sFOsGHsVec_IntSize(vBits) == (int)strlen(pSymb)src/base/bac/bacNtk.cchar *Bac_NtkGenerateName(Bac_Ntk_t *, Bac_ObjType_t, Vec_Int_t *)!strncmp(pName, s_Pref, strlen(s_Pref))Vec_Int_t *Bac_NameToRanges(char *)Bac_CharIsDigit(*pTemp)Vec_IntSize(vBits) <= 10Bac_ObjIsCi(p, iOld)void Bac_NtkUpdateFanout(Bac_Ntk_t *, int, int)Bac_ObjIsCi(p, iNew)Bac_ObjFanin(p, iCo) == iOld!Bac_NtkHasFanouts(p)void Bac_NtkDeriveFanout(Bac_Ntk_t *)!Bac_ObjNextFanout(p, iCo)%s%0*d_%diBit > 0void Bac_ManAssignInternWordNamesNtk(Bac_Ntk_t *, Vec_Int_t *)!Bac_ObjBit(p, iObj)Bac_ObjNameType(p, iObj) <= BAC_NAME_WORDnPis == Bac_NtkPiNum(p)nPos == Bac_NtkPoNum(p)Vec_IntCountEntry(vMap, 0) == Vec_IntSize(vMap)void Bac_ManAssignInternWordNames(Bac_Man_t *)Bac_ObjIsPi(p, iObj) || Bac_ObjIsBox(p, iObj)void Bac_NtkDfs_rec(Bac_Ntk_t *, int, Vec_Int_t *)Bac_ObjIsBoxUser(p, iObj)int Bac_NtkDfsUserBoxes_rec(Bac_Ntk_t *, int, Vec_Int_t *)Vec_IntSize(vSigs) == Bac_NtkPiNum(p)void Bac_NtkCollapse_rec(Bac_Ntk_t *, Bac_Ntk_t *, Vec_Int_t *)Vec_IntSize(vSigs) == Bac_BoxBoNum(p, iObj)Vec_IntSize(vSigs) == Bac_NtkPoNum(pRoot)Bac_Man_t *Bac_ManCollapse(Bac_Man_t *)Bac_NtkObjNum(pRootNew) == Bac_NtkObjNumAlloc(pRootNew)BIBOCFCXCZaocaboMAJabcoRANDRNANDRNORRXORRXNORLANDLNANDLORLNORLXORLXNORNMUXPSELiaboPENCEDECiabsoMULDIVMODREMPOWMINLTHANLETHANMETHANMTHANNEQUSHILSHIRROTLROTRGATEASSIGNRAMeadroRAMReamoRAMWRAMWCceadoRAMBOXdvsgqdsrgqdvscqdsrcqABC_Bac_ObjIsCi(p, i)int Bac_ObjFanout(Bac_Ntk_t *, int)int Bac_ObjNextFanout(Bac_Ntk_t *, int)void Bac_ObjSetFanout(Bac_Ntk_t *, int, int)void Bac_NtkStartFanouts(Bac_Ntk_t *)void Bac_ObjSetNextFanout(Bac_Ntk_t *, int, int)!Bac_ObjIsBox(p, i)int Bac_ObjBit(Bac_Ntk_t *, int)int Abc_Lit2Var2(int)Bac_ObjIsBo(p, i) && !Bac_ObjBit(p, i)int Bac_BoxBoRange(Bac_Ntk_t *, int)int Abc_Lit2Att2(int)Bac_NameType_t Bac_NameType(int)Cyclic dependency of user boxes is detected.Vec_IntEntry(vMap, NameId) == -1src/base/bac/bacPrsBuild.cvoid Psr_ManRemapOne(Vec_Int_t *, Psr_Ntk_t *, Vec_Int_t *)Vec_IntSize(vSigs) % 2 == 0Vec_IntEntry(vMap, NameId) != -1NtkIdNew > 0void Psr_ManRemapBoxes(Bac_Man_t *, Vec_Ptr_t *, Psr_Ntk_t *, Vec_Int_t *)Psr_NtkPioNum(pNtk) == 0void Psr_ManBuildNtk(Bac_Ntk_t *, Vec_Ptr_t *, Psr_Ntk_t *, Vec_Int_t *, Vec_Int_t *)Primary inputs %d and %d have the same name. Box output name %d is already driven. Index - Psr_NtkPiNum(pNtkBox) < Psr_NtkPoNum(pNtkBox)Node output name %d is already driven. Module %s has %d non-driven nets (for example, %s). Vec_IntCountEntry(vMap, -1) == Vec_IntSize(vMap)Bac_Man_t *Psr_ManBuildCba(char *, Vec_Ptr_t *)Abc_Lit2Att2(i) == BAC_PRS_NAMEsrc/base/bac/bacPrs.hint Psr_NtkSigName(Psr_Ntk_t *, int)int Bac_BoxBo(Bac_Ntk_t *, int, int)Vec_IntSize(vSlices) > 0src/base/bac/bacPrsTrans.cint Psr_ManRangeSizeArray(Psr_Ntk_t *, Vec_Int_t *, int, int)pStr[0] == '['int Psr_ManRangeSizeRange(Psr_Ntk_t *, int)Vec_PtrSize((Vec_Ptr_t *)Vec_PtrEntry(vNtk, 3)) == 0src/base/bac/bacPtr.cvoid Bac_PtrDumpModuleBlif(FILE *, Vec_Ptr_t *)// Design "%s" written via Ptr in ABC on %s .%s(%s)%smodule %s ( ); void Bac_PtrDumpModuleVerilog(FILE *, Vec_Ptr_t *)Const0TConst1TBufTInvTAndTNandTOrTNorTXorTXnorT2 * i == Vec_PtrSize(vBox)void Bac_PtrUpdateBox(Vec_Ptr_t *, Vec_Ptr_t *)test1.bliftest2.blifc/hie/dump/1/netlist_1.vnCap >= 0Vec_Ptr_t *Vec_PtrAllocExact(int)Standard cell library is not entered.src/base/bac/bacPtrAbc.cchar *Ptr_HopToType(Abc_Obj_t *)char *Ptr_AbcObjName(Abc_Obj_t *)Vec_Ptr_t *Ptr_AbcDeriveNode(Abc_Obj_t *)Abc_ObjFaninNum(pObj) <= 2Vec_Ptr_t *Ptr_AbcDeriveBox(Abc_Obj_t *)Converting to Ptr: Memory = %6.3f MB Finished writing output file "%s". Vec_PtrSize(vNodes) == 0int Ptr_ManCountNtk(Vec_Ptr_t *)Bac_NtkNameId(pNtk) == NameIdint Bac_NtkDeriveFromPtr(Bac_Ntk_t *, Vec_Ptr_t *, Vec_Int_t *, Vec_Int_t *)PI with name "%s" is not unique module "%s". Vec_PtrSize(vBox) % 2 == 0nOutputs > 0 && 2*(nOutputs + 1) <= Vec_PtrSize(vBox)Signal "%s" has multiple drivers in module "%s". Vec_IntSize(vBox2Id) == Vec_PtrSize(vBoxes)Signal "%s" in not driven in module "%s". PO with name "%s" in not driven in module "%s". iObj == -1Bac_NtkObjNum(pNtk) == Vec_StrCap(&pNtk->vType)BAC_BOX_C0BAC_BOX_C1BAC_BOX_INVBAC_BOX_ANDBAC_BOX_NORBAC_BOX_OR-1 1 1- 1 1- 1 -1 1 BAC_BOX_XORBAC_BOX_XNORBAC_BOX_SHARPBAC_BOX_SHARPLchar *Ptr_SopToTypeName(char *)Vec_PtrSize(vArray) == Vec_PtrCap(vArray)int Ptr_CheckArray(Vec_Ptr_t *)Bac_ObjNameType(p, i) <= BAC_NAME_WORDchar *Bac_ObjNameStr(Bac_Ntk_t *, int)Cannot transform CBA network into Ptr because it is not mapped.MhxShZhZhMhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhMhZhZhuOhZhZhZhZhZhZhZhZhZhNNhOhZhNNhNNhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhZhNhOh-PhThThOhThThThThThThThThThThThThThThThThThThOhThThPhThThThThThThThThTh?OhThTh?Oh?OhThThThThThThThThThThThThThThThThThThThThThThThThThThThThThThThThThThThThThThThThThTh OhRhtShShShRhShShShShShShShShShShShShShShShShShShRhShShShDhThDhDhDhDhDhDhDhDhDhDhDhDhDhDhDhDhDhDhDhDhDhDhDhDhThEh?Fh}EhEhoEhFhFh3XhpXhFhFhtSh*Wh*WhFh*Wh*Wh*Wh*Wh*Wh*Wh*Wh*Wh*Wh*Wh*Wh*Wh*Wh*Wh*Wh*Wh*Wh*WhFh*Wh*WhKhXhIZhYhYhXhYhYhYhYhYhYhYhYhYhYhYhYhYhYhYhYhYhYhXhYhYh8ZhSXhZhXhXhSXhXhXhXhXhXhXhXhXhXhXhXhXhXhXhXhXhXhXhSXhXhXhYhYGhGhGhGhYGhGhGhGhGhGhGhGhGhGhGhGhGhGhGhGhGhGhGhYGhGhGhGhFhLhIhIhFhIhIhIhIhIhIhIhIhIhIhIhIhIhIhIhIhIhIhFhIhIhKhIhLhIhIhIhIhIhIhIhIhIhIhIhIhIhIhIhIhIhIhIhIhIhIhIhIhLhEhQLhHhHhEhHhHhHhHhHhHhHhHhHhHhHhHhHhHhHhHhHhHhEhHhHhKhHhQLhHhHhHhHhHhHhHhHhHhHhHhHhHhHhHhHhHhHhHhHhHhHhHhHh@LhrFhLhJhJhrFhJhJhJhJhJhJhJhJhJhJhJhJhJhJhJhJhJhJhrFhJhJhKhJhLhJhJhJhJhJhJhJhJhJhJhJhJhJhJhJhJhJhJhJhJhJhJhJhJhLhAEhiWhKhKhAEhKhKhKhKhKhKhKhKhKhKhKhKhKhKhKhKhKhKhAEhKhKhXWhMhtShWhWhMhWhWhWhWhWhWhWhWhWhWhWhWhWhWhWhWhWhWhMhWhWhMh*bh chObhObh*bhObhObhObhObhObhObhObhObhObhObhObhObhObhObhObhObhObhObh*bhObhObhbh`ch&fhchch`chchchchchchchchchchchchchchchchchchch`chchchfh*dhqdhqdhqdh*dhqdhqdhqdhqdhqdhqdhqdhqdhqdhqdhqdhqdhqdhqdhqdhqdhqdhqdh*dhqdhqdhOdhdhehdhdhdhdhdhdhdhdhdhdhdhdhdhdhdhdhdhdhdhdhdhdhdhdhehZehehhchhchZehhchhchhchhchhchhchhchhchhchhchhchhchhchhchhchhchhchhchZehhchhchehl@c/hie/dump/1/netlist_1_out8.blifFinished reading %d networks. NameIDs = %d. Memory = %.2f MB. c/hie/dump/1/netlist_1_out8_out.blifAbc_NamObjNumMax(p->pStrs) == isrc/base/bac/bacReadBlif.cvoid Psr_NtkAddBlifDirectives(Psr_Man_t *).inouts.shortPsr_ManIsChar(p, '\n')int Psr_ManReadLines(Psr_Man_t *)Cannot read directive "%s". Psr_ManIsLit(p)int Psr_ManReadCube(Psr_Man_t *)Cannot read cube.Cannot read output literal.Cannot read end of cube.!p->ErrorStr[0]int Psr_ManErrorSet(Psr_Man_t *, char *, int)void Psr_ManSaveCover(Psr_Man_t *)Vec_StrSize(&p->vCover) > 0Psr_BoxNtk(p->pNtk, Psr_NtkBoxNum(p->pNtk)-1) == 1Bac_ObjType_t Ptr_SopToType(char *)Parsing previous model is unfinished.Trailing symbols on .model line.p->pNtk == NULLvoid Psr_ManInitializeNtk(Psr_Man_t *, int, int)Signal list is empty.Vec_IntSize(vTemp) % 2 == 0void Psr_NtkAddBox(Psr_Ntk_t *, int, int, Vec_Int_t *)Value & 1Cannot read formal name.Cannot find symbol "=".Cannot read actual name.Cannot read a list of formal/actual names.The number of formal/actual names is not even.Cannot read latch input.Cannot read .short input.Directive .end without .model.Trailing symbols on .end line.hԥhQhԥh'hԥhԥhԥhsh&/4:?DIUbo}$).?;KFP]gtCannot read signal in the list.Expecting comma in the list.Succeeded parsing %d models: Skipped %d known models: Skipped %d failed models: c/hie/dump/1/netlist_1_out_new.vError number 9.Cannot read nested concatenations.Error number 11.Error number 13.Error number 15.Unexpectedly reached end-of-file.src/base/bac/bacReadVer.cCannot read constant.Cannot read radix of constant.!(Att >> 2)int Abc_Var2Lit2(int, int)Psr_ManIsChar(p, '{')int Psr_ManReadConcat(Psr_Man_t *, Vec_Int_t *)Error number 7.Psr_ManIsChar(p, '}')Vec_IntSize(vTemp2) > 0int Psr_NtkAddConcat(Psr_Ntk_t *, Vec_Int_t *)Psr_ManIsChar(p, '[')int Psr_ManReadRange(Psr_Man_t *)Cannot read digit in range specification.Cannot read closing brace in range specification.void Psr_NtkAddVerilogDirectives(Psr_Man_t *)defparamint Psr_ManReadDesign(Psr_Man_t *)Parsing previous module is unfinished.Cannot read "module" keyword.Cannot read module name.Cannot find "endmodule" keyword.Cannot find "(" in the argument declaration.Cannot find ";" in the module definition.VERIFIC_add_mult_div_mod_rem_shift_left_shift_right_rotate_left_rotate_right_reduce_and_reduce_or_reduce_xor_reduce_nand_reduce_nor_reduce_xnor_LessThan_Mux_EnabledDecoder_PrioSelect_DualPortRam_ReadPort_ClockedWritePort_buf_inv_tri_sub_unary_minus_not_equal_wide_mux_wide_select_wide_dff_wide_dlatch_wide_dffrs_wide_dlatchrs_wide_prio_select_pow_PrioEncoder_Error number 31.Error number 33.Error number 35.Expecting comma in the instance.Psr_ManIsChar(p, ')')p->pNtk != NULLvoid Psr_ManFinalizeNtk(Psr_Man_t *)Error number 21.Cannot read name in the list.Cannot read output in assign-statement.Expecting "=" in assign-statement.Cannot read first input name in the assign-statement.Unrecognized operator in the assign-statement.Cannot read second input name in the assign-statement.int Psr_ManReadAssign(Psr_Man_t *)Expected colon in the MUX assignment.Cannot read third input name in the assign-statement.Expected semicolon at the end of the assign-statement.!fCompl && !fCompl2Expecting "(" in module instantiation.Cannot find elementary gate.Error number 28.int Psr_ManReadInstance(Psr_Man_t *, int)Expecting semicolon in the instance.Psr_ManIsChar(p, '.')int Psr_ManReadSignalList2(Psr_Man_t *, Vec_Int_t *)Cannot read formal name of the instance.Cannot read "(" in the instance.Cannot read actual name of the instance.Cannot read ")" in the instance.Vec_IntSize(vTemp) > 0constXconstZsharp# Design "%s" written by ABC on %s .gate %sVec_IntSize(&p->vFanin) == Bac_NtkObjNum(p)src/base/bac/bacWriteBlif.cvoid Bac_ManWriteBlifNtk(FILE *, Bac_Ntk_t *)# Design "%s" written via CBA package in ABC on %s Psr_BoxIONum(p, i) > 0void Psr_ManWriteBlifLines(FILE *, Psr_Ntk_t *)Vec_IntSize(vBox) % 2 == 011- 1 1-1 1 -11 1 char *Ptr_TypeToSop(Bac_ObjType_t)Genlib library used in the mapped design is not longer a current library. e j+ll& 2Hiiii9i9iiHihhyhhdaiaiaiaiwwJJmE\D+2~|fuYufu+( Vec_IntSize(vSigs) > 0src/base/bac/bacWriteVer.cvoid Psr_ManWriteVerilogArray(FILE *, Psr_Ntk_t *, Vec_Int_t *, int, int, int)// Design "%s" written by ABC on %s Bac_NtkInfoNum(pModel)void Bac_ManWriteVerilogBoxes(Bac_Ntk_t *, int)i == Bac_BoxBiNum(p, iObj)o == Bac_BoxBoNum(p, iObj)iSig == Vec_IntSize(vBits)inout void Bac_ManWriteVerilogNtk(Bac_Ntk_t *, int)module ; wire // Design "" written via CBA package in ABC on void Psr_ManWriteVerilogSignal(FILE *, Psr_Ntk_t *, int) %s %s%s; %s %s (Vec_IntSize(vSigs) == 8void Psr_ManWriteVerilogMux(FILE *, Psr_Ntk_t *, Vec_Int_t *) assign sharplchar *Ptr_TypeToName(Bac_ObjType_t)void Psr_ManWriteVerilogArray2(FILE *, Psr_Ntk_t *, Vec_Int_t *), .Bac_ObjIsCi(p, iObj)void Bac_ManWriteSig(Bac_Ntk_t *, int)int Bac_ObjGetConst(Bac_Ntk_t *, int)void Bac_ManWriteConstBit(Bac_Ntk_t *, int, int)nOutputs == 1void Bac_ManWriteAssign(Bac_Ntk_t *, int)Type == BAC_BOX_BUF & ~ | ~nObjs >= 1void Bac_ManWriteConcat(Bac_Ntk_t *, int, int)nBits == 4Digit == 0Bac_ObjNameType(p, f) != BAC_NAME_BINVec_Int_t *Bac_BoxCollectRanges(Bac_Ntk_t *, int)Vec_IntSize(vBits) < 10int Bac_ManFindRealIndex(Bac_Ntk_t *, int)Bac_NameType(NameId) != BAC_NAME_BINa[1]>=0int Bac_NtkInfoIndex(Bac_Ntk_t *, int, int)int Bac_ObjGetRange(Bac_Ntk_t *, int)Bac_NameType(NameId) == BAC_NAME_WORD || Bac_NameType(NameId) == BAC_NAME_INFOint Bac_ManFindRealNameId(Bac_Ntk_t *, int)Bac_NameType(NameId) == BAC_NAME_BIN || Bac_NameType(NameId) == BAC_NAME_WORDvi}iiiiiiGiֽiiֽi޹iֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽi.i|iֽi!iֽiƼiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiֽiiiiikiiYi'iYi'iYi'i'i'i'i'i'i'i'i'i'i'i'i'i'i'iiii.ii iiiiiiiiiiiiiiiiiiisrc/base/cba/cbaBlast.cint Cba_ReadHexDigit(char)nBits <= nTotalvoid Cba_BlastConst(Cba_Ntk_t *, Vec_Int_t *, int, int, int)*pConst == '\''int *Cba_VecLoadFanins(Cba_Ntk_t *, Vec_Int_t *, int, int *, int, int, int)Vec_IntSize(vOut) == nTotalvoid Cba_BlastShiftRight(Gia_Man_t *, int *, int, int *, int, int, Vec_Int_t *)void Cba_BlastShiftLeft(Gia_Man_t *, int *, int, int *, int, int, Vec_Int_t *)void Cba_BlastRotateRight(Gia_Man_t *, int *, int, int *, int, Vec_Int_t *)void Cba_BlastRotateLeft(Gia_Man_t *, int *, int, int *, int, Vec_Int_t *)int Cba_BlastReduction(Gia_Man_t *, int *, int, int)void Cba_BlastLess_rec(Gia_Man_t *, int *, int *, int, int *, int *)void Cba_BlastMultiplier2(Gia_Man_t *, int *, int *, int, Vec_Int_t *, Vec_Int_t *)void Cba_BlastMultiplier(Gia_Man_t *, int *, int *, int, int, Vec_Int_t *, Vec_Int_t *, int)void Cba_BlastDivider(Gia_Man_t *, int *, int, int *, int, int, Vec_Int_t *)void Cba_BlastDivider2(Gia_Man_t *, int *, int, int *, int, int, Vec_Int_t *)void Cba_BlastDividerSigned(Gia_Man_t *, int *, int, int *, int, int, Vec_Int_t *)void Cba_BlastSqrt(Gia_Man_t *, int *, int, Vec_Int_t *, Vec_Int_t *)Vec_IntSize(vBits) == Cba_FonCopy(p, Cba_ObjFon0(p, i))Gia_Man_t *Cba_NtkBlast(Cba_Ntk_t *, int)Type == CBA_BOX_DFFCPL || Cba_ObjFonNum(p, i) == 1Cba_ObjFinNum(p, i) > 0Left0 > Right0Left < Right && Left0 < Right0nRange0 >= 1 && Cba_ObjFinNum(p, i) >= 31 + (1 << nRange0) == Cba_ObjFinNum(p, i)nRange0 == 1Cba_ObjType(p, iObj) == CBA_BOX_DFFCPLnRange0 == nRange1Cba_FonIsReal(f)src/base/cba/cba.hvoid Cba_FonSetCopy(Cba_Ntk_t *, int, int)Cba_FonCopy(p, f) == 0Cba_FonIsConst(f)int Cba_FonRange(Cba_Ntk_t *, int)int Cba_FonRangeId(Cba_Ntk_t *, int)int Cba_FonConst(int)Cba_ObjType_t Cba_ObjType(Cba_Ntk_t *, int)int Cba_ObjFin0(Cba_Ntk_t *, int)f>0int Cba_FinFon(Cba_Ntk_t *, int) jljljljljljljljljljljljljljljljljljljlj:jljlj4jljljljljljljljlj@j:read:write:ps:put:get:clp:blast:cec:test.cbausage: :read [-tdvh] reads hierarchical design -t : toggle testing the parser [default = %s] -d : toggle computing DFS ordering [default = %s] Cba_NtkObjNum(pNew) == Cba_NtkObjNumAlloc(pNew)Cba_Ntk_t *Cba_NtkDup(Cba_Man_t *, Cba_Ntk_t *, Vec_Int_t *)nIns >= 0 && nOuts >= 0 && nObjs >= 0 && nFins >= 0 && nFons >= 0Cba_Ntk_t *Cba_NtkAlloc(Cba_Man_t *, int, int, int, int, int, int)Cba_ObjCopy(p, i) == -1void Cba_ObjSetCopy(Cba_Ntk_t *, int, int)int Cba_ObjFon(Cba_Ntk_t *, int, int)int Cba_ObjCopy(Cba_Ntk_t *, int)Cba_NtkHasObjCopies(p)void Cba_ObjSetFinFon(Cba_Ntk_t *, int, int, int)Cba_ObjFinFon(p, i, k)== 0p->iCopy == 0void Cba_NtkSetCopy(Cba_Ntk_t *, int)void Cba_NtkAdd(Cba_Man_t *, Cba_Ntk_t *)Vec_IntSize(&pNew->vOrder) == 0void Cba_NtkDupAttrs(Cba_Ntk_t *, Cba_Ntk_t *)Cba_CommandWrite(): There is no current design. Generated output file name "%s". usage: :write [-cvh] -c : toggle inlining input concatenations [default = %s] MmadvhCba_CommandPs(): There is no current design. usage: :ps [-M num] [-madvh] -m : toggle printing multipliers [default = %s] mod =%5d box =%5d prim =%5d user =%5d int Cba_ObjNtkId(Cba_Ntk_t *, int)seq =%5d bsvhCba_CommandPut(): There is no current design. Cba_CommandPut(): Conversion to AIG has failed. usage: :put [-bsvh] -s : toggle blasting sequential elements [default = %s] Cba_CommandGet(): There is no current design. Cba_CommandGet(): There is no current mapped design. Cba_CommandGet(): There is no current AIG. usage: :get [-mvh] extracts AIG or mapped network into the hierarchical design usage: :clp [-vh] Cba_CommandBlast(): There is no current design. Cba_CommandBlast(): Bit-blasting has failed. usage: :blast [-svh] Cba_CommandCec(): There is no current design. src/base/cba/cbaCom.cint Cba_CommandCec(Abc_Frame_t *, int, char **)usage: :cec [-vh] Cba_CommandTest(): There is no current design. usage: :test [-vh] Cba_CommandRead(): Input file name should be given on the command line.9jDjRj6EjRjGjRjRjRjEjRjRjRjRjRjRjRjRjGjRj KjRjKjRj8=jMjRj[>jRj!FjRjRjRjRjRjRjRjRj@j= 2src/base/cba/cbaNtk.cvoid Cba_NtkPrintDistrib(Cba_Ntk_t *, int)%2d : %-8s %6d%8d %3d%s = %3d%s %s %3d%s %-12s = %-12s %s Primitives (%d): %-20s = %5d User hierarchy (%d): Cba_CharIsDigit(p1[i])int Cba_StrCmpInt(char *, char *, int)Cba_CharIsDigit(p2[i])i == 0 || !Cba_CharIsDigit(p1[i-1])i == 0 || !Cba_CharIsDigit(p2[i-1])%s_%s_%dVec_IntSize(vObjs) <= Cba_NtkObjNum(p)Vec_Int_t *Cba_NtkCollectDfs(Cba_Ntk_t *)Warning: DSF ordering for module "%s" collected %d out of %d objects. For example, object %d with name "%s" is not reachable from outputs. Vec_IntSize(vSigs) == Cba_NtkPiNum(p)void Cba_NtkCollapse_rec(Cba_Ntk_t *, Cba_Ntk_t *, Vec_Int_t *)Vec_IntSize(vSigs) == Cba_ObjFinNum(p, iObj)Vec_IntSize(vSigs) == Cba_ObjFonNum(p, iObj)Vec_IntSize(vSigs) == Cba_NtkPiNum(pRoot)Cba_Man_t *Cba_ManCollapse(Cba_Man_t *)Vec_IntSize(vSigs) == Cba_NtkPoNum(pRoot)Cba_NtkObjNum(pRootNew) == Cba_NtkObjNumAlloc(pRootNew)Cba_NtkFinNum(pRootNew) == Cba_NtkFinNumAlloc(pRootNew)Cba_NtkFonNum(pRootNew) == Cba_NtkFonNumAlloc(pRootNew)void Cba_ManExtractGroupInt(Cba_Ntk_t *, Cba_Ntk_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Cba_NtkFinNum(pNew) == Cba_NtkFinNumAlloc(pNew)Cba_NtkFonNum(pNew) == Cba_NtkFonNumAlloc(pNew)Cba_NtkPiNum(pSyn) == Vec_IntSize(vFonIns)void Cba_NtkInsertGroup(Cba_Ntk_t *, Vec_Int_t *, Cba_Ntk_t *)Cba_NtkPoNum(pSyn) == Vec_IntSize(vFonOuts)Cba_FonIsReal(Cba_FonCopy(pSyn, iFon))int Cba_ObjFinFon(Cba_Ntk_t *, int, int)int Cba_ObjFinNum(Cba_Ntk_t *, int)Cba_NtkHasFonNames(p)char *Cba_FonNameStr(Cba_Ntk_t *, int)int Cba_ObjFon0(Cba_Ntk_t *, int)int Cba_ObjFonNum(Cba_Ntk_t *, int)int Cba_ObjIsSeq(Cba_Ntk_t *, int)i>=0int Cba_ObjAttr(Cba_Ntk_t *, int)Cba_ObjAttr(p, i) == 0void Cba_ObjSetAttrs(Cba_Ntk_t *, int, int *, int)Cba_ObjName(p, i) == 0void Cba_ObjSetName(Cba_Ntk_t *, int, int)int Cba_ObjName(Cba_Ntk_t *, int)Cba_NtkHasObjNames(p)void Cba_FonSetName(Cba_Ntk_t *, int, int)Cba_FonName(p, f) == 0int Cba_FonName(Cba_Ntk_t *, int)%s%d_%dVec_IntGetEntry(&p->vNameMap, i) == 0void Cba_ManSetMap(Cba_Man_t *, int, int)int Cba_NtkNewStrId(Cba_Ntk_t *, const char *, ...)int Cba_NtkInsertGiaObj(Cba_Ntk_t *, Gia_Man_t *, int, Vec_Int_t *, int)int Cba_NtkInsertGiaLit(Cba_Ntk_t *, int, Vec_Int_t *, int)Vec_IntEntry(vLit2Fon, Abc_LitNot(iLit)) >= 0void Cba_FonCleanName(Cba_Ntk_t *, int)Cba_FonName(p, f) != 0Primitives:User hierarchy:ID : name occurrence and2 (occurrence)=. ...kOkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk@kkk@k@kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk!k9k<kkk9kkkkkkkkkkkkkkkkkkk9kkk+kkkkkkkkkk^kkk^k^kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk@kkLk_k_kk_k_k_k_k_k_k_k_k_k_k_k_k_k_k_k_k_k_kk_k_kkkLkkkkkkkkkkkkkkkkkkkkkkkkk3kSkNkkkkkkkkkkLkkkkkkkkkkkkkkkkkkkkkkkkkkkkWkWkkWkWkWkWkWkWkWkWkWkWkWkWkWkWkWkWkWkWkkWkWk~kkJkkkkkkkkkkkkkkkkkkkkkkkkk:kIkknknkIknknknknknknknknknknknknknknknknknknkIknknk k)kak k k)k k k k k k k k k k k k k k k k k k k)k k kkL kakn kn kL kn kn kn kn kn kn kn kn kn kn kn kn kn kn kn kn kn kn kL kn kn kQkk`k>k>kk>k>k>k>k>k>k>k>k>k>k>k>k>k>k>k>k>k>kk>k>kk k`k. k. k k. k. k. k. k. k. k. k. k. k. k. k. k. k. k. k. k. k. k k. k. kPkykbk k kyk k k k k k k k k k k k k k k k k k kyk k kk kbk k k k k k k k k k k k k k k k k k k k k k k k kRk|kkkk|kkkkkkkkkkkkkkkkkkk|kkkkkLk k kk k k k k k k k k k k k k k k k k k kk k kkPkQkPkPkPkPkPkPkPkPkPkPkPkPkPkPkPkPkPkPkPkPkPkPkPkPkyQkQkUk#Rk#RkQk#Rk#Rk#Rk#Rk#Rk#Rk#Rk#Rk#Rk#Rk#Rk#Rk#Rk#Rk#Rk#Rk#Rk#RkQk#Rk#RkUk:SkSkSkSk:SkSkSkSkSkSkSkSkSkSkSkSkSkSkSkSkSkSkSk:SkSkSk_SkSk=UkSkSkSkSkSkSkSkSkSkSkSkSkSkSkSkSkSkSkSkSkSkSkSkSkUkTk}UkQkQkTkQkQkQkQkQkQkQkQkQkQkQkQkQkQkQkQkQkQkTkQkQkhUkn@Network "%s": Signal "%s" is not driven. Prs_BoxIONum(pNtk, i) > 0src/base/cba/cbaReadBlif.cint Prs_CreateBlifNtk(Cba_Ntk_t *, Prs_Ntk_t *)Cba_ObjType(p, iObj) == CBA_BOX_DFFRSCba_ObjType(p, iObj) == CBA_BOX_NODECba_NtkPiNum(pBox) == Cba_ObjFinNum(p, iObj)Cba_NtkPoNum(pBox) == Cba_ObjFonNum(p, iObj)Elaboration module "%s"... void Prs_NtkAddBlifDirectives(Prs_Man_t *)Prs_ManIsChar(p, '\n')int Prs_ManReadLines(Prs_Man_t *)Prs_ManIsLit(p)int Prs_ManReadCube(Prs_Man_t *)src/base/cba/cbaPrs.hint Prs_ManErrorSet(Prs_Man_t *, char *, int)void Prs_ManSaveCover(Prs_Man_t *)Prs_BoxNtk(p->pNtk, Prs_NtkBoxNum(p->pNtk)-1) == 1void Prs_ManInitializeNtk(Prs_Man_t *, int, int)void Prs_NtkAddBox(Prs_Ntk_t *, int, int, Vec_Int_t *)Cba_ObjFunc(p, i) == 0void Cba_ObjSetFunc(Cba_Ntk_t *, int, int)int Cba_ObjFunc(Cba_Ntk_t *, int)Cba_NtkHasObjFuncs(p)Vec_IntGetEntry(&p->vNameMap2, i) == 0void Cba_ManSetMap2(Cba_Man_t *, int, int)Cba_Ntk_t *Cba_ObjNtk(Cba_Ntk_t *, int)Cba_NtkBoxSeqNum(p) == 0void Cba_NtkPrepareSeq(Cba_Ntk_t *)kZkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk15ln lNllBlBlBlBlBlMBlBlBlBlBlBlBljBlBlBlBlBlBlBlBlBlBlBlBlBlBlBlBlBlBlBlqBlAOlQlQlQlwPlOlQlQlQl"PlPlHlPlQl\OlQlQlQlQlQlQlQlQlQlQlQlHlPlOl=PlOlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlclQlQlmOlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlQlPl&/4:?DIUbo}$).?;KFP]gtMnRn_nx~  |f u Y ufuKq~rrrr rr rjr rjr rjr rjrrjrsjrsrjs)sK:sTFsm\TDGSWsmfspsDGW{sm\TFDGUsmfspsFDGsmsmsmvsssss/ss(psmvstmtmtsss+tAt//s(p14(p3:(p4?(p5D(pAIs(KtBUs(KtEb(KtFo(Kt}((((( (;s(p(?)?-(.*s?LRt_tmtxttMtxtcjtNRt_tmtcjOFRt_tmtcjH (p (p(p (p (p(p K$0)(p7.??(p@;(pKvs6 (F?)P?U]mfspsDGWtmztDGTmztDGSgmfspsDG*?t6(p,9MnVxm/,+FDGtsrc/base/cba/cbaReadVer.cvoid Prs_NtkAddVerilogDirectives(Prs_Man_t *)Cba_FonIsReal(iFon)int Prs_CreateSlice(Cba_Ntk_t *, int, Prs_Ntk_t *, int)_icc%d_Type == CBA_PRS_CONCATRangeId > 0_occ%d_void Prs_CreateSignalOut(Cba_Ntk_t *, int, Prs_Ntk_t *, int)void Prs_CreateOutConcat(Cba_Ntk_t *, int *, int)NameId == pSlices[3*i+0] && iFon > 0BotId <= Bot && Top <= TopIdVec_IntEntry(vBits, k) == 0nBits == Cba_FonRangeSize(p, Prev)k == nParts*pConst == 'b'int Prs_CreateBitSignal(Prs_Ntk_t *, int)SigOne >= 0iSigSet >= 0 && iSigRst >= 0int Prs_CreateFlopSetReset(Cba_Ntk_t *, Prs_Ntk_t *, Vec_Int_t *, int *, int *, int *, int *)Num1 + Abc_Base2Log(Num2) < 32int Prs_CreateGetMemSize(char *)RampRamNameVec_Ptr_t *Prs_CreateDetectRams(Prs_Ntk_t *)Vec_IntSize(&pNtk->vInouts) == 0void Prs_CreateVerilogPio(Cba_Ntk_t *, Prs_Ntk_t *)%s_boxCba_FonLeft(p, iFon) <= MemSize-1int Prs_CreateVerilogNtk(Cba_Ntk_t *, Prs_Ntk_t *)Cba_FonRight(p, iFon) == 0%s_wp%dFatal error: Cannot find module "%s". wide_Cba_ObjType(p, iObj) == CBA_BOX_CONCATnInputs >= 0iFonType == Cba_ObjType(p, iObj)Index < nBitsCba_ObjFinNum(p, iObj) >= 2Slice * nParts == nBits_buf_const_%dNameId == Cba_ObjName(p, iObj)Cba_NtkRangeLeft(p, Abc_Lit2Var(RangeId)) == Cba_FonLeft(p, iFon)Cba_NtkRangeRight(p, Abc_Lit2Var(RangeId)) == Cba_FonRight(p, iFon)Building module "%s"... Prs_ManIsChar(p, '{')int Prs_ManReadSignal(Prs_Man_t *)Prs_ManIsChar(p, '}')p->fUsingTemp2int Prs_ManReadConcat(Prs_Man_t *, Vec_Int_t *)int Prs_NtkAddConcat(Prs_Ntk_t *, Vec_Int_t *)int Prs_ManReadRange(Prs_Man_t *)int Prs_ManReadDesign(Prs_Man_t *)*p->pCur == ')'int Prs_ManReadModule(Prs_Man_t *)Prs_ManIsChar(p, ',')abs_CPL_NMACROFFCPL_MACROFFPrs_ManIsChar(p, ')')void Prs_ManFinalizeNtk(Prs_Man_t *)Type >= PRS_VER_INPUT && Type <= PRS_VER_WIREint Prs_ManReadDeclaration(Prs_Man_t *, int)Input cannot be definedError number 24.Expecting closing parenthesis 1.int Prs_ManReadExpression(Prs_Man_t *, int)Expecting closing parenthesis 2.Cannot read name after a binary operator.Cannot determine word-level operator.!Prs_ManIsChar(p, '[')Vec_IntSize(&p->vTemp) == 8Unsupported operation.Trailing symbols on this line.Cannot parse always statement.Cannot read "begin" keyword.Cannot read "case" keyword.Cannot read "endcase" keyword.Cannot read "end" keyword.Cannot find "_func_" keyword.Error number 30a.Cannot find "input" keyword.endfunctionCannot find "endfunction" keyword.int Prs_ManReadInstance(Prs_Man_t *, int)Prs_ManIsChar(p, '.')int Prs_ManReadSignalList2(Prs_Man_t *, Vec_Int_t *)Cannot read actual name of an instance.bufif1Cba_NtkHasFonRanges(p)void Cba_FonSetRange(Cba_Ntk_t *, int, int)void Cba_FonSetRangeSign(Cba_Ntk_t *, int, int)%d'b%0sVERIFIC_PWRVERIFIC_GNDVERIFIC_XVERIFIC_ZVERIFIC_INVVERIFIC_BUFVERIFIC_ANDa1VERIFIC_NANDVERIFIC_ORVERIFIC_NORVERIFIC_XORVERIFIC_XNORVERIFIC_MUXVERIFIC_PULLUPVERIFIC_PULLDOWNVERIFIC_TRIVERIFIC_DLATCHRSVERIFIC_DLATCHasync_valasync_condVERIFIC_DFFRSVERIFIC_DFFVERIFIC_NMOSVERIFIC_PMOSVERIFIC_CMOSpcVERIFIC_TRANinout1inout2controlVERIFIC_FADDcinVERIFIC_RCMOSVERIFIC_RNMOSVERIFIC_RPMOSVERIFIC_RTRANVERIFIC_HDL_ASSERTIONconditionamountwrite_enablewrite_addresswrite_dataread_addressread_dataread_enablecarry_inqbarVec_IntSize(p) % nMulti == 0void Vec_IntSortMulti(Vec_Int_t *, int, int)void Cba_ObjCleanFinFon(Cba_Ntk_t *, int, int)Cba_ObjFinFon(p, i, k)!= 0Prs_BoxIONum(p, i) > 0src/base/cba/cbaWriteBlif.cvoid Prs_ManWriteBlifLines(FILE *, Prs_Ntk_t *)char *Cba_ObjNameStr(Cba_Ntk_t *, int)sliicclogic nandlogic norlogic xnornmuxprio-selectprio-encenable-dec@triramRramWramWCramBoxlatlatrsdffrs\%s src/base/cba/cbaWriteVer.cvoid Prs_ManWriteVerilogArray(FILE *, Prs_Ntk_t *, Vec_Int_t *, int)%s[%d:%d]\%s [%d]\%s [%d:%d][%d:%d] Open_%dCba_ObjIsConcat(p, iObj)void Cba_ManWriteConcat(Cba_Ntk_t *, int) // %s(%d)line );;%*s%s.%s(RAM_WRITERAM_READRAM_BOXrdatawenwaddrwdatarenraddrin3 %s( ) ); function input %sd%d casez(s) // synopsys full_case parallel_case %d'b: _func_ = d%d; endfunction = _func_(1 << nBitsIn) == nBitsOutvoid Cba_ManWriteVerilogNtk(Cba_Ntk_t *, int) casez(i) = %d'b%0*d; Cba_FonRangeSize(p, iFonSet) == 1 && Cba_FonRangeSize(p, iFonRst) == 1 reg always @(posedge if ( <= else if ( else CPL_FF#%d ( .d(), .arstval(), .arst(), .clk(), .q(), .qbar( assign {} = << >> ) | (Cba_ManWriteVerilog(): In module "%s", cannot write object "%s" with output name "%s". // name=pName != NULL && *pName != '\0'int Prs_NameIsLegalInVerilog(char *, int) %s %s%s %s %s ( void Prs_ManWriteVerilogMux(FILE *, Prs_Ntk_t *, Vec_Int_t *)void Prs_ManWriteVerilogArray2(FILE *, Prs_Ntk_t *, Vec_Int_t *)int Cba_NameIsLegalInVerilog(char *, int)int Cba_ObjAttrSize(Cba_Ntk_t *, int) reads the SOP from a PLA file Abc_CommandWritePla(): There is no current design. usage: |write [-vh] writes the SOP into a PLA file usage: |ps [-madvh] %-16s : In =%4d Out =%4d Cube =%8d LitIn =%8d LitOut =%8d Div =%6d IOPSspvhusage: |gen [-IOPS num] [-spvh] generate random or specialized SOP -I num : the number of inputs [default = %d] -O num : the number of outputs [default = %d] -P num : the number of products [default = %d] -S num : ramdom seed (0 <= num <= 1000) [default = %d] -s : toggle generating sorter as a PLA file [default = %s] -p : toggle generating prime detector [default = %s] Abc_CommandMerge(): There is no current design. usage: |merge [-mvh] performs distance-1 merge using cube hashing usage: |test [-N num] [-vh] experiments with SOPs Abc_CommandReadPla(): Unknown file extension.Abc_CommandReadPla(): Input file name should be given on the command line.nBits <= 26src/base/pla/plaHash.cint Pla_ManHashDistance1(Pla_Man_t *)!(Count & 1)Found %d pairs among %d cubes using cube hashing. Vec_Int_t *Pla_ManComputeDistance1Int(Pla_Man_t *)%d %d LogSize >= 4 && LogSize <= 26Tab_Man_t *Tab_ManAlloc(int, Pla_Man_t *)i >= 0 && i < PLA_HASH_VALUE_NUMint Pla_HashValue(int)jKS"bGݾ#&*UY4З.67ks"f܋.{]|tUʊtkP/#>W4hN^ Q'*9>(|7pQ|z{}.^jI}[UKIUj5XH;8K.*廌i; Vb %Kk=2dv7?7DwK+.1^#[Ɣz!52WdO_ncN{T}"[EyCQU弔!/og:Iy%7dʯt|P>t WPeo<_º2!p`&(OeR V&rj)ľU/Len4O_3(&H}=RW(:qQtޙzMRDoZF{Əi49>42yLl(yۣ8KT 5U*B5QX  ~V>qS$!tBJyt K9z 2.%-i_HE7{UJ2Q#y*M8A(r"7K ,QWڄw>>G,E( d8FmG <$e5tyNJm[ ̄u[2)rnZ4f^1+Ǎ,Ȩ-P؜hf8.t^CM*Ŏ<ܮXA>zZ;ZHoY Z:k 0PD\i%^: t+O⁏rM.tG/݂OfižԢުGɤTpI@ ,uј,\],Y7[?8/Ebr\4֦,CwBPd(C)1!թ9ޥ;gJ; DUٙ#u(YYi&1\lc߻A=ƪL )^Lg",Lb/FwO"\ mXGsorter%02d.pla# This file was generated by ABC on %s. Primes up to 2^%d = %d primes%02dnVars > 0 && nVars <= 30src/base/pla/plaMan.cVec_Bit_t *Pla_GenRandom(int, int, int)nNums > 0 && nNums < (1 << (nVars - 1))%s_%d_%d_%drandCount == nCubesPla_Man_t *Pla_ManGenerate(int, int, int, int)Vec_IntSize(vCube) == Vec_IntCap(vCube)void Pla_ManConvertFromBits(Pla_Man_t *)Found %d pairs among %d cubes using cube pair enumeration. void Vec_BitShrink(Vec_Bit_t *, int)# PLA file written via PLA package in ABC on .e Written file "%s". # BLIF file written via PLA package in ABC on .outputs o i%d !Abc_LitIsCompl(pLits[0])src/base/pla/plaSimple.cvoid Pla_ManDumpBlif(Pla_Man_t *, char *)!Abc_LitIsCompl(pLits[1])%d-0 1 -11 1 Vec_Wrd_t *Pla_ManFxMinimize(word *, int)Truth = %d. Cover = %d. Count: Cubes: primesmin%02d.pladm m mmmdm.e .type frfdfdrsrc/base/pla/plaRead.cVec_Str_t *Pla_ReadPlaBody(char *, char *, Pla_File_t)Vec_StrSize(vLits) % (p->nIns + p->nOuts) == 0void Pla_ReadAddBody(Pla_Man_t *, Vec_Str_t *)Warning: Declared number of cubes (%d) differs from the actual (%d). nCubesReal > Pla_ManCubeNum(p)Count == Vec_StrSize(vLits)Literal count is incorrect (in = %d; out = %d; lit = %d). The number of outputs (.o) should be positive.The number of inputs (.i) should be positive.mmGmm.e -01?# SOP "" written via PLA package in ABC on .type f .type fr .type fdr .type ??? .o .p read_super.genGenlib library should be read in first.. Reading supergate library has failed. usage: read_super [-ovh] read the supergate library from the file -e file : file contains list of genlib gates to exclude -o : toggles the use of old file format [default = %s] -v : toggles enabling of verbose output [default = %s] nPhases > 0src/map/mapper/mapperCanon.cint Map_CanonComputeSlow(unsigned int (*)[2], int, int, unsigned int *, unsigned char *, unsigned int *)p->pCounters[uTruth0] > 0int Map_CanonComputeFast(Map_Man_t *, int, int, unsigned int *, unsigned char *, unsigned int *)nVarsMax == 5nVarsReal == 5p->pCounters[uTruth1] > 0uPhaseBest < 16Delay : %s = %8.2f Flow = %11.1f Area = %11.1f %4.1f %% AreaFlow : %s = %8.2f Flow = %11.1f Area = %11.1f %4.1f %% Area : %s = %8.2f Flow = %11.1f Area = %11.1f %4.1f %% Switching: %s = %8.2f Flow = %11.1f Area = %11.1f %4.1f %% }}}}c_`?!Map_IsComplement(p1)src/map/mapper/mapperCreate.cint Map_NodeComparePhase(Map_Node_t *, Map_Node_t *)!Map_IsComplement(p2)p->nVarsMax > 0Map_Man_t *Map_ManCreate(int, int, int)p->pNodeDelays == NULLvoid Map_ManCreateNodeDelays(Map_Man_t *, int)N-canonical = %d. Matchings = %d. Phases = %d. Choice nodes = %d. Choices = %d. ToMapCuts MatchArea SweepToNettime1time2time3map_stats.txtpMan->pBins == NULLvoid Map_TableCreate(Map_Man_t *)Counter == pMan->nNodes - pMan->nInputsvoid Map_TableResize(Map_Man_t *)The supergate library is not specified. Use "read_super".Map_NodeIsVar(pNode) || Map_NodeIsBuf(pNode)src/map/mapper/mapperCut.cvoid Map_MappingCutsInput(Map_Man_t *, Map_Node_t *)p->nVarsMax > 1 && p->nVarsMax < 7void Map_MappingCuts(Map_Man_t *)Cuts ...Nodes = %6d. Total %d-feasible cuts = %10d. Per node = %.1f. Map_Cut_t *Map_CutCompute(Map_Man_t *, Map_CutTable_t *, Map_Node_t *)pTemp->pCutsMap_Cut_t *Map_CutTableConsider(Map_Man_t *, Map_CutTable_t *, Map_Node_t **, int)p->pBins[Place] == NULLp->pBins[ p->pCuts[i] ]void Map_CutTableRestart(Map_CutTable_t *)nCuts <= MAP_CUTS_MAX_COMPUTEMap_Cut_t *Map_CutSortCuts(Map_Man_t *, Map_CutTable_t *, Map_Cut_t *)m-kwqCUT: Delay = (%4.2f, %4.2f). Area = %4.2f. Nodes = %d -> {pCut->M[fPhase].pSuperBestsrc/map/mapper/mapperCutUtils.cfloat Map_CutGetRootArea(Map_Cut_t *, int)int Map_CutGetLeafPhase(Map_Cut_t *, int, int)pNode->pCutBest[fPhase]->M[fPhase].pSuperBestint Map_NodeGetLeafPhase(Map_Node_t *, int, int) } Ksrc/map/mapper/mapperLib.cMap_SuperLib_t *Map_SuperLibCreate(Mio_Library_t *, Vec_Str_t *, char *, char *, int, int)Loaded %d unique %d-input supergates from "%s". Cannot execute command "read_super %s". Error: Exclude file support not present for old format. Stop.}@@src/map/mapper/mapperMatch.cint Map_MatchNodePhase(Map_Man_t *, Map_Node_t *, int)fUsePhase0 ^ fUsePhase1void Map_NodeTryDroppingOnePhase(Map_Man_t *, Map_Node_t *)void Map_NodeTransferArrivalTimes(Map_Man_t *, Map_Node_t *)p->fMappingMode >= 0 && p->fMappingMode <= 4int Map_MappingMatches(Map_Man_t *)pNode->p2 == NULL Error: Could not match both phases of AIG node %d. Matches ...Please make sure that the supergate library has equivalents of AND2 or NAND2.If such supergates exist in the library, report a bug. Error: A node in the mapping graph does not have feasible cuts.@?!Map_IsComplement(pNode)src/map/mapper/mapperRefs.cint Map_NodeReadRefPhaseAct(Map_Node_t *, int)pNode->pCutBest[0] || pNode->pCutBest[1]float Map_NodeReadRefPhaseEst(Map_Node_t *, int)int Map_NodeIncRefPhaseAct(Map_Node_t *, int)int Map_NodeDecRefPhaseAct(Map_Node_t *, int)pNodeChild->nRefAct[fPhaseChild] >= 0float Map_CutRefDeref(Map_Cut_t *, int, int, int)Map_NodeIsAnd(pNode)void Map_MappingSetRefs_rec(Map_Man_t *, Map_Node_t *)pNode->pCutBest[0] != NULL || pNode->pCutBest[1] != NULLfloat Map_MappingGetArea(Map_Man_t *)pNode->nRefAct[0] > 0 || pNode->nRefAct[1] > 0\n ]n ]n ]n ]n ]n ]n ]n ]n ]n\n ]n ]n\n ]n ]n ]n ]n ]n ]n ]n ]n ]n ]n ]n ]n ]n ]n ]n ]n ]n ]n\npLib->pGenlib == NULLsrc/map/mapper/mapperSuper.cint Map_LibraryRead(Map_SuperLib_t *, char *)*pNamechar *Map_LibraryReadFormulaStep(char *, char **, int *)CountPars == 0*pPar2 == ')'A = %5.2f D = %5.2f/%5.2f/%5.2f The input file "%s" looks like a genlib file and not a supergate library file. Cannot open the genlib file "%s". Cannot read genlib file "%s". Suspicious number of variables (%d). Suspicious number of gates (%d). pGate->Num == nCounter + 1int Map_LibraryReadFile(Map_SuperLib_t *, FILE *)Map_LibraryTruthVerify(pLib, pGate)The number of gates read (%d) is different what the file says (%d). The following trailing symbols found "%s". pGateName[0] - 'a' < pLib->nVarsMaxvoid Map_LibraryComputeTruth_rec(Map_SuperLib_t *, char *, unsigned int (*)[2], unsigned int *)A supergate contains gate "%s" that is not in "%s". A gate name is empty.src/map/mapper/mapperSwitch.cfloat Map_MappingGetSwitching(Map_Man_t *)float Map_SwitchCutRefDeref(Map_Node_t *, Map_Cut_t *, int, int)Map_SuperTableCompareSupergates( ppSupers, ppSupers + nSupers - 1 ) <= 0src/map/mapper/mapperTable.cvoid Map_SuperTableSortSupergates(Map_HashTable_t *, int)D = %5.2f Map_SuperTableCompareGatesInList( ppSupers, ppSupers + nSupers - 1 ) <= 0void Map_SuperTableSortSupergatesByDelay(Map_HashTable_t *, int)void Map_SuperTableResize(Map_HashTable_t *)src/map/mapper/mapperTime.cvoid Map_TimePropagateRequiredPhase(Map_Man_t *, Map_Node_t *, int)pCut->ppLeaves[i]->nRefAct[2] > 0void Map_TimePropagateRequired(Map_Man_t *)Cannot meet the target required times (%4.2f). Continue anyway. Relaxing the required times from (%4.2f) to the target (%4.2f). nمnمnمnمnمnمnمnمnمnnمnمnnمnمnمnمnمnمnمnمnمnمnمnمnمnمnمnمnمnمnn < Cannot read the root gate names %s. The number of a child supergate (%d) exceeded the number of lines (%d). nBufferSize > 1src/map/mapper/mapperTree.cint Vec_StrGets(char *, int, Vec_Str_t *, int *)pBeg < pEndSupergate library "%s" requires the use of genlib library "%s". Suspicious number of lines (%d). The number of lines read (%d) is different from what the file says (%d). int Map_LibraryReadTree(Map_SuperLib_t *, Mio_Library_t *, char *, char *)Read %d gates from exclude file nRealVars > 0 && nRealVars <= pLib->nVarsMaxint Map_LibraryDeriveGateInfo(Map_SuperLib_t *, st__table *)%6s %3d %6.2f (%4.2f, %4.2f) (----, ----) (%4.2f, ----) (----, %4.2f)The number of fanins of a root gate is wrong.The number of a child supergate is negative.There are too many entries on the line.There are more pins than gate inputs.There are less pins than gate inputs.pNode->pCutssrc/map/mapper/mapperTruth.cvoid Map_MappingTruths(Map_Man_t *)pNode->pCuts->nLeaves == 1Tables ...pCut->fMark == 0void Map_TruthsCutOne(Map_Man_t *, Map_Cut_t *, unsigned int *)p->vVisited->nSize > 0void Map_CutsCollect_rec(Map_Cut_t *, Map_NodeVec_t *)src/map/mapper/mapperUtils.cvoid Map_MappingDfs_rec(Map_Node_t *, Map_NodeVec_t *, int)pNode->fMark0 == 0void Map_MappingUnmark_rec(Map_Node_t *)void Map_MappingMark_rec(Map_Node_t *)Output %-*s : Delay = (%5.2f, %5.2f) POSPrimary input %d is a secondary node. Constant 1 %d is a secondary node. Internal node %d is a secondary node. Internal node %d has first fanin that is a secondary node. Internal node %d has second fanin that is a secondary node. st__table *Map_CreateTableGate2Super(Map_Man_t *)nVars < 7void Map_MappingExpandTruth(unsigned int *, int)Max arrival times with fanouts = %10.2f. int Map_MappingUpdateLevel_rec(Map_Man_t *, Map_Node_t *, int)Maximum level: Original = %d. Reduced due to choices = %d. Choice stats: Choice nodes = %d. Total choices = %d. int Map_MappingCountLevels_rec(Map_Node_t *)nVars < 6unsigned int Map_MappingExpandTruth_rec(unsigned int, int)src/map/mapper/mapperVec.cvoid Map_NodeVecShrink(Map_NodeVec_t *, int)void Map_NodeVecRemove(Map_NodeVec_t *, Map_Node_t *)void Map_NodeVecWriteEntry(Map_NodeVec_t *, int, Map_Node_t *)Map_Node_t *Map_NodeVecReadEntry(Map_NodeVec_t *, int)read_genlibwrite_genlibprint_genlibread_profilewrite_profileprint_profileread_librarywrite_libraryprint_libraryWEnvhCommand line switch "-E" should be followed by a file name. Reading genlib library has failed. Entered genlib library with %d gates from file "%s". Reading second genlib library has failed. usage: read_genlib [-W float] [-E filename] [-nvh] read the library from a genlib file (if the library contains more than one gate with the same Boolean function, only the gate with the smallest area will be used) -W float : wire delay (added to pin-to-pin gate delays) [default = %g] -E file : the file name with gates to be excluded [default = none] -n : toggle replacing gate/pin names by short strings [default = %s] -h : enable verbose output vahError! Cannot open file "%s" for writing the library. The current genlib library is written into file "%s". usage: write_genlib [-vah] writes the current genlib library into a file -a : toggles writing min-area gates [default = %s] : optional file name to write the library usage: print_genlib [-savh] print the current genlib library -s : toggles writing short form [default = %s] There is no Genlib library entered. .profileusage: read_profile [-h] read a gate profile from a profile file -h : enable verbose output : file name to read the profile The current profile is written into file "%s". usage: write_profile [-h] writes the current profile into a file : file name to write the profile usage: print_profile [-h] print the current gate profile The file name is not given.Library is not available.pLib->ppGates0[Id]->Cell == Idsrc/map/mio/mioApi.cMio_Gate_t *Mio_LibraryReadGateById(Mio_Library_t *, int)CONST0Cannot parse formula "%s" of gate "%s". Cannot read formula "%s" of gate "%s". Name "%s" appears in the formula "%s" of gate "%s" but there is no such pin. iRoot < 2 * nVarsvoid Exp_Truth8(int, Vec_Int_t *, word **, word *)Abc_Lit2Var(iRoot) - nVars == i - 1vnvnPnPnvnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnvnnPnPnPnPnnnn nnnPnPnPnPnn!nPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnPnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnPn*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*nnn*n*n*n*nnnnnnn*n*n*n*nnn*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*nn*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*n*nnMio_ParseFormula(): Different number of opening and closing parentheses (). Mio_ParseFormula(): No operation symbol before constant 0. Mio_ParseFormula(): No operation symbol before constant 1. Mio_ParseFormula(): No variable is specified before the negation suffix. Mio_ParseFormula(): There is no variable before AND, EXOR, or OR. Mio_ParseFormula(): There is no opening parenthesis Mio_ParseFormula(): Unknown operation Mio_ParseFormula(): The negation sign or an opening parenthesis inside the variable name. Mio_ParseFormula(): The parser cannot find var "%s" in the input var list. Mio_ParseFormula(): Something is left in the operation stack Mio_ParseFormula(): Something is left in the function stack Mio_ParseFormula(): The input string is empty Skipping gate "%s" because substring "%s" does not match with a pin name. iPin < 32src/map/mio/mioParse.cint Mio_ParseCheckFormula(Mio_Gate_t *, char *)(Len0 & 1) && (Len1 & 1)Vec_Int_t *Exp_And(int *, int, Vec_Int_t *, Vec_Int_t *, int, int)Vec_IntSize(r) == Len0 + Len1 + 1Vec_Int_t *Exp_Xor(int *, int, Vec_Int_t *, Vec_Int_t *)Vec_IntSize(r) == Len0 + Len1 + 5ooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooopFile != NULLsrc/map/mio/mioRead.cchar *Mio_ReadFile(char *, int)i == pLib->nGatesvoid Mio_LibrarySortGates(Mio_Library_t *)tExcludeGateint Mio_LibraryReadExclude(char *, st__table *)Error: Could not open exclude file %s. Stop. %127sSkipping latch "%s"... Actually excluded %d cells PINNONINVWarning: Read extended genlib format but ignoring extensionsMio_LibraryRead: Had problems parsing formulas.The library contains no gates.Gates with more than 2 outputs are not supported.Warnings: genlib library reader cannot detect the AND2, NAND2, OR2, and NOR2 gate.Warnings: genlib library reader cannot detect the invertor gate.Warnings: genlib library reader cannot detect the buffer gate.Some parts of the supergate-based technology mapper may not work correctly.Cannot read pin phase specificationi == ksrc/map/mio/mioSop.cvoid Mio_SopPushSCC(Vec_Int_t *, unsigned int)(Vec_IntEntry(vExpr,0) >> 1) < nVarschar *Mio_LibDeriveSop(int, Vec_Int_t *, Vec_Str_t *)aa?@@C@@7 7 <@@@@PIN * PIN %*s %7s %8.2fNameLen+FormLen+2 < 5000src/map/mio/mioUtils.cvoid Mio_WriteGate(FILE *, Mio_Gate_t *, int, int, int, int, int)%s=%s;GATE %-*s unspecified # The genlib library "%s" with %d gates written by ABC on %s int Mio_DelayCompare(Mio_Gate_t **, Mio_Gate_t **)int Mio_AreaCompare(Mio_Cell_t *, Mio_Cell_t *)int Mio_AreaCompare2(Mio_Cell2_t *, Mio_Cell2_t *)iGate < nGatesMio_Gate_t **Mio_CollectRoots(Mio_Library_t *, int, float, int, int *, int)Selected gate %3d: %-20s A = %7.2f D = %7.2f %3s = %-s Mio_DelayCompare( ppGates, ppGates + iGate - 1 ) <= 0pGate->nInputs == 0Mio_Cell_t *Mio_CollectRootsNew(Mio_Library_t *, int, int *, int)pGate->nInputs == 1Mio_AreaCompare( ppCells + 4, ppCells + iCell - 1 ) <= 0i < iCell%-20s In = %d N = %3d A = %12.6f D = %12.6f iCell0 <= nGatesMio_Cell2_t *Mio_CollectRootsNew2(Mio_Library_t *, int, int *, int)pCell->nFanins == 0pCell->nFanins == 1Mio_AreaCompare2( ppCells + 4, ppCells + iCell - 1 ) <= 0iGate == nGatesint Mio_CollectRootsNewDefault3(int, Vec_Ptr_t **, Vec_Wrd_t **)Vec_WrdEntry(*pvTruths, 0) == 0Vec_WrdEntry(*pvTruths, 4) == ~(word)0Vec_WrdEntry(*pvTruths, 8) == s_Truths6[0]Vec_WrdEntry(*pvTruths, 12) == ~s_Truths6[0]pGate->nInputs <= 6word Mio_DeriveTruthTable6(Mio_Gate_t *)pGate->nInputs == nSignsvoid Mio_DeriveTruthTable(Mio_Gate_t *, unsigned int (*)[2], int, int, unsigned int *)pGate->nInputs == nTruthsvoid Mio_DeriveTruthTable2(Mio_Gate_t *, unsigned int (*)[2], int, int, unsigned int *)nInputs < 7nFanins == nInputspGate->nInputs == nPinsvoid Mio_DeriveGateDelays(Mio_Gate_t *, float **, int, int, float, float *, float *)DEBUG: problem gate is %s k == nPinstTemp2 == tCurvoid Nf_ManPrepareGate(int, word, int *, int *, Vec_Wrd_t *)tTemp1 == tCurn == 2*nPerms*nMintsvoid Nf_ManPreparePrint(int, int *, int *, char (*)[8])%8d : %d %3d %2d : %s pSizes[i] > 1 && pSizes[i] <= 6void Nf_ManPrepareLibrary(Mio_Library_t *)%16s : %48s : Inputs = %2d Total = %6d Classes = %6d Configs = %8.2f Classes = %d. Cannot find cell ID of gate %s. Cannot find gate "%s" in library "%s". %-24s %6d Renaming library "%s" into "%s%d". lib%dVec_WecSize(pLib->vTt2Match) == Vec_MemEntryNum(pLib->vTtMem)void Mio_LibraryMatchesStart(Mio_Library_t *, int, int, int)int Mio_CompareTwoGates(Mio_Gate_t *, Mio_Gate_t *)int Mio_CompareTwo(Mio_Cell_t *, Mio_Gate_t *)int Mio_CompareTwo2(Mio_Cell2_t *, Mio_Cell2_t *)Vec_Mem_t *Vec_MemAllocForTT(int, int)None""""""""DDDDDDDD 00000000Mio_CollectRoots(): Using gate profile to select gates for mapping.Error: Cannot find inverter gate in the library.Error: Cannot find buffer gate in the library.Error: Cannot find constant 1 gate in the library.Error: Cannot find constant 0 gate in the library.Standard cell library is not available.Genlib library cannot be found.SC library cannot be found.Gates with multiple outputs are not supported.{o2}o2}o{o |o2}o2}o2}o.|o2}o2}o_|o2}o|o2}o2}o2}o2}o2}o|o2}o2}o2}o2}o2}o2}o2}o2}o2}o2}o2}o2}o2}o2}o2}o2}o2}o2}o2}o2}o2}o2}o2}o2}o2}o2}o{o2}o2}o2}o|o2}o2}op{osuper2ILvhusage: super2 [-IL num] [-vh] precomputes the supergates composed of AND2s and INVs -I num : the max number of inputs to the supergate [default = %d] -L num : the max number of logic levels of gates [default = %d] -v : enable verbose output ILNTDAEsovhThe genlib library file should be given on the command line. The max number of variables (%d) should be more than 1 and less than 7. Reading library has failed. usage: super [-ILNT num] [-DA float] [-E file] [-sovh] precomputes the supergates for the given genlib library -I num : the max number of supergate inputs [default = %d] -L num : the max number of levels of gates [default = %d] -N num : the limit on the number of considered supergates [default = %d] -T num : the approximate runtime limit in seconds [default = %d] -D float : the max delay of the supergates [default = %.2f] -A float : the max area of the supergates [default = %.2f] -E file : file contains list of genlib gates to exclude -s : toggle the use of inverters at the inputs [default = %s] -o : toggle dumping the supergate library in old format [default = %s] -v : enable verbose output [default = %s] -h : print the help message Here is a piece of advice on precomputing supergate libraries: Start with the number of inputs equal to 5 (-I 5), the number of levels equal to 2 (-L 2), the delay equal to 2-3 delays of inverter, the area equal to 2-3 areas of two input NAND, and runtime limit equal to 10 seconds (-T 10). Run precomputation and learn from the result. Determine what parameter is most constraining and try to increase the value of that parameter. The goal is to have a well-balanced set of constraints and the resulting supergate library containing approximately 5K-20K supergates. Typically, it is better to increase delay limit rather than area limit, because having large-area supergates may result in a considerable increase in area. Note that a good supergate library for experiments typically can be precomputed in 30 sec or less. Increasing runtime limit makes sense when other parameters are well-balanced and it is needed to enumerate more choices to have a good result. In the end, to compute the final library the runtime can be set to 300 sec to ensure the ultimate quality. In some cases, the runtime has to be reduced if the supergate library contains too many supergates (> 500K). When precomputing libraries of 6 inputs (-i 6), start with even more restricted parameters and gradually increase them until the goal is met. nInputs < 6src/map/super/superAnd.cvoid Super2_Precompute(int, int, int)Computing supergates for %d inputs and %d levels: Level %d: Tried = %7d. Computed = %7d. Super2_Lib_t *Super2_LibCompute(Super2_Man_t *, Super2_Lib_t *)Tried %5d first gates... Level >= 0char *Super2_LibWriteGate_rec(Super2_Gate_t *, int, int)%c%s%s%cCannot write file for %d levels. Super2_LibCompareGates( pLib->pGates, pLib->pGates + pLib->nGates - 1 ) < 0void Super2_LibWrite(Super2_Lib_t *)SortingsuperI%dL%d# AND2/INV supergates derived on %s. # Command line: "super2 -i %d -l %d". # The number of inputs = %6d. # The number of levels = %6d. # The number of supergates = %6d. # The total functions = %6d. The supergates are written into file "%s" (%0.2f MB). New gate:9!9!"9!@9!9!:!9!9!.9!`9!9!p:!Writing the output file...Gate in the table:Zd;<<<<ooUoRooյooThe supergates are written using new format "%s" (%0.3f MB). src/map/super/superGate.cVec_Str_t *Super_PrecomputeStr(Mio_Library_t *, int, int, int, float, float, int, int, int)Erro! The number of supergates requested (%d) in less than the number of variables (%d). The library cannot be computed. Warning! Genlib library contains more gates than can be computed. Only one-gate supergates are included in the supergate library. Error: No genlib gates satisfy the limits criteria. Stop. Limits: max delay = %.2f, max area = %.2f, time limit = %d sec. Computing supergates with %d inputs, %d levels, and %d max gates. Lev %d: Try =%12d. Add =%6d. Rem =%5d. Save =%6d. Lookups =%12d. Aliases =%12d. # Supergate library derived for "%s" on %s. # Command line: "super -I %d -L %d -N %d -T %d -D %.2f -A %.2f %s %s". -s# The number of inputs = %10d. # The number of levels = %10d. # The maximum delay = %10.2f. # The maximum area = %10.2f. # The maximum runtime (sec) = %10d. # The number of attempts = %10d. # The number of supergates = %10d. # The number of functions = %10d. # The total functions = %.0f (2^%d). # Generation time = %10.2f sec. %04d %5.2fSorting array of %d supergates... Super_DelayCompare( pMan->pGates, pMan->pGates + pMan->nGates - 1 ) <= 0Super_Man_t *Super_Compute(Super_Man_t *, Mio_Gate_t **, int, int, int)Trying %d choices for %d inputs Super_AreaCompare( ppGatesLimit, ppGatesLimit + nGatesLimit - 1 ) <= 0Super_WriteCompare( pMan->pGates, pMan->pGates + pMan->nGates - 1 ) <= 0Vec_Str_t *Super_Write(Super_Man_t *)Writing old formatWriting new format%s.super_oldCounter == pMan->nGatesvoid Super_WriteLibrary(Super_Man_t *)The supergates are written using old format "%s" Timeout!The generated library is empty. No output file written.lutlibread_lutprint_lutread_boxprint_boxReading LUT library has failed. usage: read_lut [-vh] read the LUT library from the file File format for a LUT library: (the default library is shown) # The area/delay of k-variable LUTs: # k area delay 1 1 1 2 2 2 3 4 3 4 8 4 5 16 5 6 32 6 usage: print_lut [-vh] print the current LUT library Reading box library has failed. usage: read_box [-evh] read the box library from the file -e : toggles reading extended format [default = %s] usage: print_box [-vh] print the current box library ????????nShared >= 0 && nShared <= p->pPars->nLutSizesrc/map/if/ifCache.cvoid If_ManCacheRecord(If_Man_t *, int, int, int, int)%2d-var entries = %8d. (%6.2f %%) Unique entries = %8d. (%6.2f %%) Total entries = %8d. (%6.2f %%) Unique entries = %8d. (%6.2f %%) Vec_IntSize(vData) % nSize == 0Vec_Int_t *Hsh_IntManHashArray(Vec_Int_t *, int)int *Hsh_IntManLookup(Hsh_IntMan_t *, unsigned int *)Delay-2ŝtsrc/map/if/ifCut.cint If_CutVerifyCuts(If_Set_t *, int)pCut0->uSign == If_ObjCutSignCompute(pCut0)pCut0->pLeaves[m-1] < pCut0->pLeaves[m]pCut0->pLeaves[m] != pCut0->pLeaves[n]pCut1->uSign == If_ObjCutSignCompute(pCut1)pCutSet->ppCuts[pCutSet->nCuts] == pCutint If_CutFilter(If_Set_t *, If_Cut_t *, int)int If_CutMergeOrdered_(If_Man_t *, If_Cut_t *, If_Cut_t *, If_Cut_t *)void If_CutSort(If_Man_t *, If_Set_t *, If_Cut_t *)pCutSet->nCuts <= pCutSet->nCutsMaxpCut->pLeaves[i] != pCut->pLeaves[i+1]void If_CutOrder(If_Cut_t *)pCut->nLeaves <= pCut->nLimitint If_CutCheck(If_Cut_t *)If_CutCheck(): Cut has wrong ordering of inputs. %s%d %d(%.2f/%.2f)(pCut->pLeaves[i] & 255) < 255void If_CutLift(If_Cut_t *)pLeaf->EstRefs > p->fEpsilonfloat If_CutAreaFlow(If_Man_t *, If_Cut_t *)float If_CutEdgeFlow(If_Man_t *, If_Cut_t *)float If_CutPowerFlow(If_Man_t *, If_Cut_t *, If_Obj_t *)pLeaf->nRefs > 0float If_CutAreaDeref(If_Man_t *, If_Cut_t *)pLeaf->nRefs >= 0float If_CutAreaRef(If_Man_t *, If_Cut_t *)aResult > aResult2 - 3*p->fEpsilonfloat If_CutAreaDerefed(If_Man_t *, If_Cut_t *)aResult < aResult2 + 3*p->fEpsilonaResult > aResult2 - p->fEpsilonfloat If_CutAreaRefed(If_Man_t *, If_Cut_t *)aResult < aResult2 + p->fEpsilonfloat If_CutEdgeDeref(If_Man_t *, If_Cut_t *)float If_CutEdgeRef(If_Man_t *, If_Cut_t *)float If_CutEdgeDerefed(If_Man_t *, If_Cut_t *)float If_CutEdgeRefed(If_Man_t *, If_Cut_t *)float If_CutPowerDeref(If_Man_t *, If_Cut_t *, If_Obj_t *)float If_CutPowerRef(If_Man_t *, If_Cut_t *, If_Obj_t *)float If_CutPowerDerefed(If_Man_t *, If_Cut_t *, If_Obj_t *)float If_CutPowerRefed(If_Man_t *, If_Cut_t *, If_Obj_t *)Cound not find boundary for %d nodes. ConesTotal cut inputs = %d. Total fanins incremental = %d. pDom->nLeaves <= pCut->nLeavesint If_CutCheckDominance(If_Cut_t *, If_Cut_t *)p->SortMode == 2int If_ManSortCompare(If_Man_t *, If_Cut_t *, If_Cut_t *)src/map/if/ifDec07.cword If_Dec6Truth(word)v != 7void If_Dec7Verify(word *, word)If_Dec6HasVar( t, i )word If_Dec6Perform(word, int)Count > 1i == 15nVarsAll <= 6word If_Dec6MinimumBase(word, int *, int, int *)nVarsAll <= 7void If_Dec7MinimumBase(word *, int *, int, int *)t == t1void If_Dec5PerformTest()word If_CutPerformDerive07(If_Man_t *, unsigned int *, int, int, char *)int If_CutPerformCheck07(If_Man_t *, unsigned int *, int, int, char *)Var2Pla[v] >= pword If_Dec6MoveTo(word, int, int, int *, int *)Pla2Var[p] == vv < 5word If_Dec6SwapAdjacent(word, int)word If_Dec6DeriveNonDisjoint(word, int, int *, int *)2 >= If_Dec6CofCount2(c0)2 >= If_Dec6CofCount2(c1)void If_Dec7MoveTo(word *, int, int, int *, int *)void If_Dec7SwapAdjacent(word *, int)iCof2int If_Dec7CofCount3(word *)word If_Dec6TruthShrink(word, int, int, unsigned int)v >= 0 && v < 7int If_Dec7HasVar(word *, int)void If_Dec7TruthShrink(word *, int, int, unsigned int)Pla2Var[Var2Pla[i]] == ivoid If_DecVerifyPerm(int *, int *)word If_Dec5CofCount2(word, int, int, int *, word, int)y >= 0 && y < 4zz1 != -1 && zz2 != -1t1 == t0int Abc_TtHasVar(word *, int, int)""""""""DDDDDDDD 00000000UUUUUUUU33333333UUUUUUUUVerification failed!""""""""DDDDDDDD 00000000src/map/if/ifDec08.cvoid If_Dec08Cofactors(word *, int, int, word *, word *)nVars >= 6 && nVars <= 8int If_Dec08Perform(word *, int, int)If_Dec08HasVar( pF, nVars, i )Count[v] > 1v <= 210void If_Dec08ComposeLut4(int, word **, word *, int)Var2Pla[v] <= pvoid If_Dec08MoveTo(word *, int, int, int, int *, int *)iVar < nVars - 1void If_Dec08SwapAdjacent(word *, word *, int, int)void If_DecVerifyPerm(int *, int *, int)int If_Dec08CofCount2(word *, int)Num16 < (1<<16)-1int If_Dec08Count16(int)""""""""DDDDDDDD 00000000src/map/if/ifDec10.cvoid If_Dec10Cofactors(word *, int, int, word *, word *)nVars >= 6 && nVars <= 10int If_Dec10Perform(word *, int, int)If_Dec10HasVar( pF, nVars, i )void If_Dec10ComposeLut4(int, word **, word *, int)void If_Dec10MoveTo(word *, int, int, int, int *, int *)void If_Dec10SwapAdjacent(word *, word *, int, int)nVars > 6 && nVars <= 10int If_Dec10CofCount2(word *, int)int If_Dec10Count16(int)@A?  @@@@@@@@@@@@@@@@PPPPPPPPPPPPPPPP````````````````pppppppppppppppp pp p*p4ppppp$pnVars == nVars - g->nVars + 1 + (g->nMyu > 2)void If_CluPrintConfig(int, If_Grp_t *, If_Grp_t *, word, word *)g->nVars <= 6 && r->nVars <= 6void If_CluVerify(word *, int, If_Grp_t *, If_Grp_t *, word, word *)g->nVars >= 2 && g2->nVars >= 2 && r->nVars >= 2void If_CluVerify3(word *, int, If_Grp_t *, If_Grp_t *, If_Grp_t *, word, word, word)g->nVars <= 6 && g2->nVars <= 6 && r->nVars <= 6v >= 0 && v < nVarsvoid If_CluMoveVar(word *, int, int *, int *, int, int)nBSsize >= 2 && nBSsize <= 7 && nBSsize < nVarsint If_CluCountCofs(word *, int, int, int, word (*)[256])nWords * nMints == If_CluWordNum(nVars)nCofs >= 1 && nCofs <= 5pCofsint If_CluCountCofs4(word *, int, int, word (*)[256])nBSsize >= 2 && nBSsize <= 6 && nBSsize < nVarsnCofs >= 3 && nCofs <= 4void If_CluCofactors(word *, int, int, word *, word *)int If_CluDetectSpecialCaseCofs(word *, int, int)State[5] != nWordsState[i] <= nWordsg->nVars <= 6 && nFSset <= 4void If_CluDeriveDisjoint4(word *, int, int *, int *, If_Grp_t *, If_Grp_t *, word *, word *)nVars > nBSsize && nVars >= nBSsize + iVarStart && nVars <= CLU_VAR_MAXIf_Grp_t If_CluFindGroup(word *, int, int, int, int *, int *, int, int)nBSsize >= 2 && nBSsize <= 6!iVarStart || !iVarStopnCofs == nCofsBest2r == nRoundsg->nVars >= 2 && g->nVars <= 6void If_CluCheckGroup(word *, int, If_Grp_t *)g->nMyu >= 2 && g->nMyu <= 4nVarsAll <= 16int If_CluMinimumBase(word *, int *, int, int *)If_Grp_t If_CluCheck(If_Man_t *, word *, int, int, int, int, int, If_Grp_t *, word *, word *, word *, int)nVars <= nLutLeaf + nLutRoot - 1R.pVars[iNewPos] == nVarsiNewPos >= iVarStartIf_Grp_t If_CluCheck3(If_Man_t *, word *, int, int, int, int, If_Grp_t *, If_Grp_t *, word *, word *, word *)G2.pVars[i] < R2.nVarsLeaf size (%d) should belong to {3,4,5,6}. Root size (%d) should belong to {3,4,5,6}. The cut size (%d) is too large for the LUT structure %d%d. nLeaves <= 6float If_CutDelayLutStruct(If_Man_t *, If_Cut_t *, char *, float)G1.nMyu >= 2 && G1.nMyu <= 4G1.nVars + G2.nVars + G3.nVars == nLeaves + (G1.nVars > 0) + (G2.nVars > 0) + (G1.nMyu > 2) + (G2.nMyu > 2)nVars >= 6int If_CutPerformCheck16(If_Man_t *, unsigned int *, int, int, char *)The cut size (%d) is too large for the LUT structure %s. void If_CluSwapAdjacent(word *, word *, int, int)word If_CluAdjust(word, int)void If_CluTruthShrink(word *, int, int, unsigned int)nVarsCur < nVarsMaxvoid If_CluAdjustBig(word *, int, int)void Abc_TtStretch6(word *, int, int)nVars <= nVarsAllint Abc_TtMinBase(word *, int *, int, int) Y0`Hash table problem!!!SemiCanonical verification FAILED!Verification FAILED!If_CluDeriveDisjoint4(): Error!!!Group check 2 has failed.Group check 1 has failed.Group check 0 has failed.Permutation FAILED.*q == **p + 1 + (**p != '(')src/map/if/ifDec75.cint Dau_DsdCheckDecExist_rec(char *, char **, int *, int *)*p == qSum > 0 && Sum <= 8int Dau_DsdCheckDecAndExist_rec(char *, char **, int *, int *)nLeaves <= 8int If_CutPerformCheck75__(If_Man_t *, unsigned int *, int, int, char *)44int If_CutPerformCheck75(If_Man_t *, unsigned int *, int, int, char *)void Abc_TtShrink(word *, int, int, unsigned int)UUUUUUUU33333333""""""""DDDDDDDD 00000000??@p= ף@@(\ @p= ף @{Gz@@Gz@HzG@ףp= @RQ@@= ףp=@p= ף@@\(\@Gz@@If_CutLeaveNum(pCut) >= 0 && If_CutLeaveNum(pCut) <= 16src/map/if/ifDelay.cint If_CutDelaySop(If_Man_t *, If_Cut_t *)int If_CutSopBalancePinDelaysInt(Vec_Int_t *, int *, word *, int, word *)nCounterAnd > 0nCounterOr > 0int If_CutSopBalanceEvalInt(Vec_Int_t *, int *, int *, Vec_Int_t *, int *, int, int *)vAig == NULL || Abc_Lit2Var(iRes) == nLeaves + Abc_Lit2Var(Vec_IntSize(vAig)) - 1int If_CutSopBalanceEvalIntInt(Vec_Int_t *, int, int *, Vec_Int_t *, int, int *)vAig == NULL || (Vec_IntSize(vAig) & 1)Abc_Lit2Var(If_CutTruthLit(pCut)) == 0int If_CutSopBalanceEval(If_Man_t *, If_Cut_t *, Vec_Int_t *)Abc_Lit2Var(If_CutTruthLit(pCut)) == 1(If_CutLeaveNum(pCut) > LutSize) == (pCut->uMaskFunc > 0)int If_CutLutBalancePinDelays(If_Man_t *, If_Cut_t *, char *)int If_CutLutBalanceEval(If_Man_t *, If_Cut_t *)i >= 0 && i < (int)pCut->nLeavesIf_Obj_t *If_CutLeaf(If_Man_t *, If_Cut_t *, int)int If_CutTruthLit(If_Cut_t *)nTimes > 0src/map/if/ifCount.hint If_LogCounterPinDelays(int *, int *, word *, int, word, int, int)v >= 0 && v < 16int If_CutPinDelayGet(word, int)void If_CutPinDelaySet(word *, int, int)d >= 0 && d < 16word If_CutPinDelayInit(int)Delay > 1void If_CutPinDelayTranslate(word, int, char *)int If_LogCounterAddAig(int *, int *, int *, int, int, Vec_Int_t *, int, int, int)int If_LogCreateAnd(Vec_Int_t *, int, int, int))C g ]  7mHrHrHrHr7HrXrXrXrXrXrornrnrnrnr4prnrnrnrnrnrnrnrnrnrnrnr4prnrnrnrnroror!or(or5orBorOorrrrrДrUrrrrr([<{)]>}UUUUUUUU33333333)C g ]  7m7Q5/Vec_IntSize(&p->vNexts) == Vec_PtrSize(&p->vObjs)src/map/if/ifDsd.cIf_DsdObj_t *If_DsdObjAlloc(If_DsdMan_t *, int, int)Vec_IntSize(&p->vTruths) == Vec_PtrSize(&p->vObjs)nVars <= DAU_MAX_VARIf_DsdMan_t *If_DsdManAlloc(int, int)%02d.dsdVec_WecSize(p->vIsops[v]) == Vec_MemEntryNum(p->vTtMem[v])void If_DsdManAllocIsops(If_DsdMan_t *, int)dumpdsd%02dtts_nondsd.txttts_all.txtnSupp == If_DsdVecObjSuppSize(&p->vObjs, iObjId)void If_DsdManPrintOne(FILE *, If_DsdMan_t *, int, unsigned char *, int)Vec_MemEntryNum(p->vTtMem[v]) == Vec_PtrSize(p->vTtDecs[v])void If_DsdManPrintDecs(FILE *, If_DsdMan_t *) N : Total More Ave Max%6.1fThe distribution of object occurrences: %12d Fanins: Max = %d. Ave = %.2f. Support Obj ObjNDSD NPNNDSD Str StrNDSD Marked All : %9d %6.2f %% ***** NOTATIONS USED BELOW ***** Support -- the support size Obj -- the number of nodes in the DSD manager for each support size (the constant node and the primary input node have no support) ObjNDSD -- the number of prime nodes (that is, nodes whose function has no DSD) (percentage is relative to the number of all nodes of that size) NPNNDSD -- the number of different NPN classes of prime nodes (Each NPN class may appear more than once. For example: F1 = 17(ab(cd)) and F2 = 17(ab[cd]) both have prime majority node (hex TT is 17), but in one case the majority node is fed by AND, and in another by XOR. These two majority nodes are different nodes in the DSD manager Str -- the number of structures for each support size (each structure is composed of one or more nodes) StrNDSD -- the number of DSD structures containing at least one prime node Marked -- the number of DSD structures matchable with the LUT structure (say, "44") Number of inputs = %d. LUT size = %d. Marks = %s. NewAsUseless = %s. Bookmark = %d. Symbolic cell description: %s Non-DSD AIG nodes = %8d Unique table misses = %8d Unique table hits = %8d Memory used for objects = %8.2f MB. Memory used for functions = %8.2f MB. Memory used for hash table = %8.2f MB. Memory used for bound sets = %8.2f MB. Memory used for array = %8.2f MB. Memory used for AIG = %8.2f MB. Time DSD Time canon Time check Time check2Time verifyiLit0 == iLit1int If_DsdObjCompare(If_DsdMan_t *, Vec_Ptr_t *, int, int)Type != DAU_DSD_MUX || nLits == 3int If_DsdObjCreate(If_DsdMan_t *, int, int *, int, int)Type != DAU_DSD_MUX || !Abc_LitIsCompl(pLits[1]) || !Abc_LitIsCompl(pLits[2])Type != DAU_DSD_AND || Abc_LitIsCompl(pLits[i]) || If_DsdObjType(pFanin) != DAU_DSD_ANDType != DAU_DSD_XOR || If_DsdObjType(pFanin) != DAU_DSD_XORiPrev == -1 || If_DsdObjCompare(p, &p->vObjs, iPrev, pLits[i]) <= 0pObj->nSupp == 0truthId == Vec_MemEntryNum(p->vTtMem[nLits])-1int If_DsdObjFindOrAdd(If_DsdMan_t *, int, int *, int, word *)Vec_WecSize(p->vIsops[nLits]) == Vec_MemEntryNum(p->vTtMem[nLits])Writing DSD manager file "%s" has failed. dsd1Reading DSD manager file "%s" has failed. Unrecognized format of file "%s". Num >= 2If_DsdMan_t *If_DsdManLoad(char *)*pSpot == 0p->nUniqueMisses == Vec_PtrSize(&p->vObjs) - 2Num == Vec_MemEntryNum(p->vTtMem[v])Num2 == Vec_PtrSize(p->vTtDecs[v])p->nTtBits == pNew->nTtBitsvoid If_DsdManMerge(If_DsdMan_t *, If_DsdMan_t *)p->nConfigWords == pNew->nConfigWordsWarning! Old manager has %smarks while new manager has %smarks. Vec_IntSize(vMap) == Vec_PtrSize(&pNew->vObjs)(*pnSupp) <= p->nVarsvoid If_DsdManComputeTruth_rec(If_DsdMan_t *, int, word *, unsigned char *, int *)i == 3nSupp == If_DsdVecLitSuppSize(&p->vObjs, iDsd)void If_DsdManComputeTruthPtr(If_DsdMan_t *, int, unsigned char *, word *)int If_DsdManCheckInv_rec(If_DsdMan_t *, int)If_DsdManCheckInv_rec(p, pObj->pFans[1]) && If_DsdManCheckInv_rec(p, pObj->pFans[2])int If_DsdManPushInv_rec(If_DsdMan_t *, int, unsigned char *)Type == IF_DSD_AND || !Abc_LitIsCompl(iFanin)int If_DsdManOperation(If_DsdMan_t *, int, int *, int, unsigned char *, word *)j == nSSizeint If_DsdManAddDsd_rec(char *, char **, int *, If_DsdMan_t *, word *, unsigned char *, int *)**p == '{' && *q == '}'i == nVarsFunsigned int If_DsdManCheckAndXor(If_DsdMan_t *, int, unsigned int, If_DsdObj_t *, int, int, int, int)If_DsdObjSuppSize(pObj) > LutSizeLimitOut < LutSizeIf_DsdObjFaninNum(pObj) == 3unsigned int If_DsdManCheckMux(If_DsdMan_t *, int, unsigned int, If_DsdObj_t *, int, int, int, int)If_DsdObjFaninNum(pObj) > 2unsigned int If_DsdManCheckPrime(If_DsdMan_t *, int, unsigned int, If_DsdObj_t *, int, int, int, int) Dec using node nLeaves <= DAU_MAX_VARint If_DsdManCompute(If_DsdMan_t *, word *, int, unsigned char *, char *)nSupp == nLeavesIf_DsdVecLitSuppSize(&p->vObjs, iDsd) == nLeavesint If_CutDsdBalancePinDelays_rec(If_DsdMan_t *, int, int *, word *, int *, int, char *)If_DsdObjType(pObj) == IF_DSD_AND || If_DsdObjType(pObj) == IF_DSD_XORnCounter > 0nSupp == If_CutLeaveNum(pCut)int If_CutDsdBalancePinDelays(If_Man_t *, If_Cut_t *, char *)int If_CutDsdPermLitMax(char *, int, int)int If_CutDsdBalanceEval_rec(If_DsdMan_t *, int, int *, int *, Vec_Int_t *, int *, int, int *, char *)nSupp == nSuppAllint If_CutDsdBalanceEvalInt(If_DsdMan_t *, int, int *, Vec_Int_t *, int *, char *)vAig == NULL || Abc_Lit2Var(iLit) == nSupp + Abc_Lit2Var(Vec_IntSize(vAig)) - 1Abc_Lit2Var(If_CutDsdLit(p, pCut)) == 0int If_CutDsdBalanceEval(If_Man_t *, If_Cut_t *, Vec_Int_t *)Abc_Lit2Var(If_CutDsdLit(p, pCut)) == 1The support of DSD manager (%d) exceeds the support of the structure (%d). Warning: The support of DSD manager (%d) is less than the support of the structure (%d). Considering programmable cell: Largest LUT size = %d. Starting the tuning process from object %d (out of %d). %6d : %2d Finished matching %d functions. pThData->Status == 1void *Ifn_WorkerThread(void *)The number of processes (%d) exceeds the precompiled limit (%d). p->nConfigWords <= 10void Id_DsdManTuneStr(If_DsdMan_t *, char *, int, int, int)ThData[i].Status == 0ThData[i].Result == 0 || ThData[i].Result == 1Main : Thread %d : fUnate + fThresh + fThreshHeuristic <= 1void Id_DsdManTuneThresh(If_DsdMan_t *, int, int, int, int)tt_%s_%02d.txtDumped %d %d-var truth tables into file "%s" (%.2f MB). Memory vector has %d entries: i < (int)pObj->nFansint If_DsdObjFaninLit(If_DsdObj_t *, int)pObj->Type == IF_DSD_PRIME && pObj->nFans > 2void If_DsdObjSetTruth(If_DsdMan_t *, If_DsdObj_t *, int)void If_DsdObjHashResize(If_DsdMan_t *)p->nUniqueMisses - Prev == Vec_PtrSize(&p->vObjs) - 2nNested < DAU_MAX_VARvoid If_DsdMergeMatches(char *, int *)nNested == 0If_DsdObj_t *If_DsdObjFanin(Vec_Ptr_t *, If_DsdObj_t *, int) UNDEC TrivialWarning: DSD manager is already started without ISOPs.cannot open output file***** DSD MANAGER STATISTICS *****LUT size should be the same.The number of variables should be the same or smaller. Using prime node Using multi-input MUX node Using multi-input AND/XOR nodeVec_PtrEntry( p->vBoxes, pBox->Id ) == NULLsrc/map/if/ifLibBox.cvoid If_LibBoxAdd(If_LibBox_t *, If_Box_t *).boxblackouterwhiteinner!strcmp(pToken, "comb") || !strcmp(pToken, "white") || !strcmp(pToken, "inner")If_LibBox_t *If_LibBoxRead2(char *)nPis > 0 && nPos > 0Cannot read library name from file "%s". # Box library written by ABC on %s. # %s %d %d %d %d - .cdlThe table does not have enough entries.Wrong box format. Please try "read_box -e".rrrrrrrr ???????????????????? ????????????????????????????????????????????????????????????????????????????????????Error in the LUT library string. LUT %d has too many pins (%d). Max allowed is %d. Skipping LUTs of size more than %d. Pin %d of LUT %d has delay %f. Pin delays should be non-negative numbers. Technology mapping may not work correctly. Pin %d of LUT %d has delay %f. Pin %d of LUT %d has delay %f. Pin delays should be in non-decreasing order. Technology mapping may not work correctly. Reading LUT library from string has failed. 1 1.00 1000 2 1.00 1000 1200 3 1.00 1000 1200 1400 4 1.00 1000 1200 1400 1600 5 1.00 1000 1200 1400 1600 1800 6 1.00 1000 1200 1400 1600 1800 2000 Cannot open LUT library file "%s". Error in the LUT library file "%s". # k area delay %d %7.2f %7.2f%d %7.2f %7.2f nLutSize >= 3 && nLutSize <= 10src/map/if/ifLibLut.cIf_LibLut_t *If_LibLutSetSimple(int)H@!pPars->fUseDsd || !pPars->fUseTtPermsrc/map/if/ifMan.cIf_Man_t *If_ManStart(If_Par_t *)K = %d. Memory (bytes): Truth = %4d. Cut = %4d. Obj = %4d. Set = %4d. CutMin = %s Unique truth tables = %d Memory = %.2f MB Cache hits = %d. Cache misses = %d (%.2f %%) Non-DSD DSD hits DSD missesTOTAL Canon Useless cuts %2d = %9d (out of %9d) (%6.2f %%) Useless cuts all = %9d (out of %9d) (%6.2f %%) NonDec0 = %d. NonDec1 = %d. pObj->fRepr == 0void If_ManCreateChoice(If_Man_t *, If_Obj_t *)pCut->pLeaves[0] < p->vObjs->nSizevoid If_ManSetupCutTriv(If_Man_t *, If_Cut_t *, int)p->pMemCi == NULLvoid If_ManSetupCiCutSets(If_Man_t *)If_ObjIsAnd(pObj)If_Set_t *If_ManSetupNodeCutSet(If_Man_t *, If_Obj_t *)pObj->pCutSet == NULLvoid If_ManDerefNodeCutSet(If_Man_t *, If_Obj_t *)pObj->nVisits >= 0pFanin->nVisits > 0void If_ManDerefChoiceCutSet(If_Man_t *, If_Obj_t *)pObj->fReprpObj->nVisits > 0void If_ManSetupSetAll(If_Man_t *, int)Node = %7d. Ch = %5d. Total mem = %7.2f MB. Peak cut mem = %7.2f MB. xxxxxxxxxxxxxxxxxws@xswsxs?????UUUUUUUU33333333src/map/if/ifMap.cint If_ManCutAigDelay_rec(If_Man_t *, If_Obj_t *, Vec_Ptr_t *)pLeaf->fVisit == 0int If_ManCutAigDelay(If_Man_t *, If_Obj_t *, If_Cut_t *)pCut->nLeaves <= 3float If_CutDelaySpecial(If_Man_t *, If_Cut_t *, int)!If_ObjIsAnd(pObj->pFanin0) || pObj->pFanin0->pCutSet->nCuts > 0void If_ObjPerformMappingAnd(If_Man_t *, If_Obj_t *, int, int, int)!If_ObjIsAnd(pObj->pFanin1) || pObj->pFanin1->pCutSet->nCuts > 0pCut->Delay != -1If_ObjPerformMappingAnd(): Warning! Node with ID %d has delay (%f) exceeding the required times (%f). If_DsdManSuppSize(p->pIfDsdMan, If_CutDsdLit(p, pCut)) == (int)pCut->nLeavesp->pPars->fUseTtPerm == 0pCut->nLimit >= 4 && pCut->nLimit <= 16pCut->nLeaves <= 4p->pPars->nLutSize <= 13iDecMask >= 0iCofVar >= 0 && iCofVar <= (int)pCut->nLeavesIf_ObjCutBest(pObj)->Cost < IF_COST_MAX && If_ObjCutBest(pObj)->Delay < ABC_INFINITYpCutSet->nCuts <= pCutSet->nCutsMax+1The best cut is useless. pObj->pEquiv != NULLvoid If_ObjPerformMappingChoice(If_Man_t *, If_Obj_t *, int, int)Mode >= 0 && Mode <= 2int If_ManPerformMappingRound(If_Man_t *, int, int, int, int, char *)pObj->nVisits == pObj->nVisitsCopypObj->nVisits == 0%c: Del = %7.2f. Ar = %9.1f. Edge = %8d. Switch = %7.2f. Cut = %8d. nSuppLim < nVars && nVars <= 2 * nSuppLim && nVars <= 12int Abc_TtProcessBiDecInt(word *, int, int)2 <= nSuppLim && nSuppLim <= 6v < nVars - 1void Abc_TtComputeGraph(word *, int, int, int *)nVars <= nVarsMaxint Abc_TtCheckCondDep(word *, int, int)E: Del = %7.2f. Ar = %9.1f. Edge = %8d. src/map/if/ifReduce.cvoid If_ManImproveMark_rec(If_Man_t *, If_Obj_t *, Vec_Ptr_t *)int If_ManImproveNodeWillGrow(If_Man_t *, If_Obj_t *)int If_ManImproveNodeFaninCost(If_Man_t *, If_Obj_t *)void If_ManImproveNodeFaninUpdate(If_Man_t *, If_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *)Vec_PtrSize(vFront) <= nLimitint If_ManImproveNodeFaninCompact_int(If_Man_t *, If_Obj_t *, int, Vec_Ptr_t *, Vec_Ptr_t *)pCut->Delay <= pObj->Required + p->fEpsilonvoid If_ManImproveNodeExpand(If_Man_t *, If_Obj_t *, int, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *)CostBef >= CostAftAreaAft == AreaBefs ss s-s:sCssssss+s4s s[ssssnBSet + nSSet + nFSet == nVarssrc/map/if/ifSat.cint If_ManSatCheckXY(void *, int, word *, int, unsigned int, word *, word *, Vec_Int_t *)nSSet + nBSet <= nLutSizenLutSize + nSSet + nFSet <= 2*nLutSize - 1iBSet == nBSet && iFSet == nFSetVec_IntEntry(vLits, mNew) == -1nSSet + nFSet + 1 <= nLutSizenLutSize >= 2 && nLutSize <= 6unsigned int If_ManSatCheckXYall_int(void *, int, word *, int, Vec_Int_t *)nLutSize < nVars && nVars <= nTotalnShared >= 0 && nShared < nLutSize - 1nShared == 00123456789ABCDEF{abcdef}void If_ManSatTest2()iVarC >= 0 && iVarT >= 0 && iVarE >= 0 && iVarZ >= 0int sat_solver_add_mux(sat_solver *, int, int, int, int, int, int, int, int)iVarC0 >= 0 && iVarC1 >= 0 && iVarD0 >= 0 && iVarD1 >= 0 && iVarD2 >= 0 && iVarD3 >= 0 && iVarZ >= 0int sat_solver_add_mux41(sat_solver *, int, int, int, int, int, int, int)k <= 4word If_ManSat6ComposeLut4(int, word *, int)%5d = %5d & %5d | %5d Cut src/map/if/ifSelect.cint If_ManNodeShapeMap(If_Man_t *, If_Obj_t *, Vec_Int_t *)If_CutDataInt( If_ObjCutBest(pLeaf) ) == 0If_ManNodeShapeMap(): Computing local AIG has failed. int If_ManNodeShapeMap2(If_Man_t *, If_Obj_t *, Vec_Int_t *)If_ManNodeShapeMap2(): Computing local AIG has failed. Vec_Ptr_t *If_ManConeCollect(If_Man_t *, If_Obj_t *, If_Cut_t *)sat_solver_var_value(pSat, If_ObjSatVar(pIfObj)) == 1void If_ManNodeShape2_rec(sat_solver *, If_Man_t *, If_Obj_t *, Vec_Int_t *)pTemp != NULLint If_ManNodeShapeSat(If_Man_t *, If_Obj_t *, Vec_Int_t *)If_ObjSatVar(pObj) == 0Vec_IntSize(vFanins) > 0If_ObjSatVar(pObj) > 0Status == l_TruepObj->fMark == 0pIfObj->fMark == 0pLeaf->fMark == 0int If_ManCheckShape(If_Man_t *, If_Obj_t *, Vec_Int_t *)int If_ManNodeShape(If_Man_t *, If_Obj_t *, Vec_Int_t *, int)Vec_IntSize(vVars) < Vec_IntCap(vVars)void sat_solver_add_choice(sat_solver *, int, Vec_Int_t *)Vec_PtrSize(vLatches) == p->pPars->nLatchesCisrc/map/if/ifSeq.cVec_Ptr_t *If_ManCollectLatches(If_Man_t *)int If_ManPerformMappingRoundSeq(If_Man_t *, int)Attempt = %2d. Iters = %3d. Area = %10.2f. Fi = %6.2f. FeasibleInfeasible (timeout)InfeasibleFiMin < FiMaxint If_ManBinarySearch_rec(If_Man_t *, int, int)void If_ManPerformMappingSeqPost(If_Man_t *)If_ManPerformMappingSeq(): The upper bound on the clock period cannot be computed. If_ManPerformMappingSeq(): The final clock period cannot be confirmed. The best clock period is %3d. src/map/if/ifTest.cvoid Gia_ParTestSimulateObj(Gia_Man_t *, int)Vec_IntSize(vCounts) == Gia_ManObjNum(p)Vec_Int_t *Gia_ManCreateFaninCounts(Gia_Man_t *)void *Gia_ParWorkerThread(void *)pThData->Id >= 0void Gia_ParTestSimulate2(Gia_Man_t *, int, int)Vec_IntEntry(vFanins, iFan) > 0nCountFanins > 0%d -> %d Trying with %d words and %d threads. Memory usage = %.2f MB Regular timeSpecial time!p->pDatavoid Gia_ParTestAlloc(Gia_Man_t *, int)RtjRtRtRtXt!Xt@Xt`Xt!p->pPars->fLiftLeavessrc/map/if/ifTime.cfloat If_CutDelay(If_Man_t *, If_Obj_t *, If_Cut_t *)void If_CutPropagateRequired(If_Man_t *, If_Obj_t *, If_Cut_t *, float)Delay == (int)pCut->DelayDelay optimization of latch path is not performed because there is no latches. p->pPars->nLatchesCi > 0float If_ManDelayMax(If_Man_t *, int)Required times are exceeded at %d output%s. The earliest arrival times are used. Cannot meet the target required times (%4.2f). Mapping continues anyway. If_ManCoNum(p) == Vec_IntSize(p->vCoAttrs)void If_ManComputeRequired(If_Man_t *)!p->pPars->fUseTtPermsrc/map/if/ifTruth.cvoid If_CutRotatePins(If_Man_t *, If_Cut_t *)(p->puTempW[0] & 1) == 0(pTruth[0] & 1) == 0int If_CutComputeTruth(If_Man_t *, If_Cut_t *, If_Cut_t *, If_Cut_t *, int, int)Vec_WecSize(p->vTtIsops[pCut->nLeaves]) == Vec_MemEntryNum(p->vTtMem[pCut->nLeaves])pCut0->uMaskFunc >= 0int If_CutComputeTruthPerm_int(If_Man_t *, If_Cut_t *, If_Cut_t *, If_Cut_t *, int, int)pCut1->uMaskFunc >= 0pCut->uSign == If_ObjCutSignCompute( pCut )Vec_IntSize(p->vTtOccurs[pCut->nLeaves]) == Vec_MemEntryNum(p->vTtMem[pCut->nLeaves])pCut0->nLeaves + pCut1->nLeaves == pCut->nLeavesint If_CutComputeTruthPerm(If_Man_t *, If_Cut_t *, If_Cut_t *, If_Cut_t *, int, int)Num == Vec_IntSize(p->vPairRes)Num * (int)pCut->nLimit == Vec_StrSize(p->vPairPerms)Vec_Mem_t *If_DeriveHashTable6(int, word)pCut[i] == pCut0[k]void Abc_TtExpand(word *, int, int *, int, int *, int)iVar < jVar && jVar < nVarsvoid Abc_TtSwapVars(word *, int, int, int)""""""""DDDDDDDD 00000000UUUUUUUU33333333""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333tt߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽ttt߽tt߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽tt߽tt߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽t߽tt߽tttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt t t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t t t t t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t t@t t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t@t t@t t\ttttt tt0tttttttttuuuuuu,u9ucucuu$uj u_"u9 ]9zAe UUUUUUUU33333333""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333nVars <= p->nInpssrc/map/if/ifTune.cint Ifn_Prepare(Ifn_Ntk_t *, word *, int)p->nPars <= IFN_PAR%c=String "%s" contains unrecognized symbol '%c'. String "%s" has no symbol '%c'. For symbol '%c' cannot find matching symbol '%c'. nFanins < IFN_INSint Ifn_NtkParseInt_rec(char *, Ifn_Ntk_t *, char **, int *)Substring "%s" contans unrecognized symbol '%c'. pStr == pLimMUX should have exactly three fanins. The number of variables (%d) exceeds predefined limit (%d). Recompile with different value of IFN_INS. p->nInps > 1 && p->nInps < p->nObjs && p->nInps <= IFN_INS && p->nObjs < 2*IFN_INSint Ifn_NtkParseInt(char *, Ifn_Ntk_t *)The first symbol should be one of the symbols: (, [, <, {. The last symbol should be ';'. Mismatch in the number of nodes. String "%s" has definition of input variable '%c'. String "%s" has no definition for internal variable '%c'. int Ifn_NtkParseInt2(char *, Ifn_Ntk_t *)Cannot find definition of signal '%c'. Cannot find openning operation symbol in the definition of signal '%c'. Cannot find closing operation symbol in the definition of signal '%c'. Cannot find matching operation symbol in the definition of signal '%c'. Fanin number %d is signal %d is out of range. p->nConstr < IFN_INS*IFN_INSvoid Ifn_NtkParseConstraints(char *, Ifn_Ntk_t *)Gia_Man_t *Ifn_ManStrFindModel(Ifn_Ntk_t *)nFans >= 0 && nFans <= 8Step == nMintsGia_ManPiNum(pNew) == p->nParsVIni - (p->nObjs - p->nInps)Gia_ManPoNum(pNew) == 1sat_solver *Ifn_ManStrFindSolver(Gia_Man_t *, Vec_Int_t **, Vec_Int_t **)(1 << nInps) == Vec_IntSize(vPoVars)int Ifn_ManSatCheckOne(sat_solver *, Vec_Int_t *, word *, int, int *, int, Vec_Int_t *)nVars <= nInpspPerm[v] < nVarsnInps <= IF_MAX_FUNC_LUTSIZEint If_ManSatFindCofigBits(void *, Vec_Int_t *, Vec_Int_t *, word *, int, word, int, Vec_Int_t *)pPerm[i] < nVarsVec_IntSize(vLeaves) <= p->nInps && p->nParsVIni < 1000int If_ManSatDeriveGiaFromBits(void *, Ifn_Ntk_t *, word *, Vec_Int_t *, Vec_Int_t *)Abc_Lit2Var(iLit) < Vec_IntSize(vLeaves)nFans <= 6iVar == nTtBitsp->vConfigs != NULLvoid *If_ManDeriveGiaFromCells(void *)p->pCellStr != NULLVec_IntEntry(p->vConfigs, 0) == CountVec_IntSize(p->vConfigs) == 2 + nConfigInts * Countword *Ifn_NtkDeriveTruth(Ifn_Ntk_t *, int *)nVars > 0 && nVars <= 4void Ifn_TtComparisonConstr(word *, int, int, int)void Ifn_NtkAddConstrOne(sat_solver *, Vec_Int_t *, int *, int)p->nParsVNum <= 4void Ifn_NtkAddConstraints(Ifn_Ntk_t *, sat_solver *)pValues[i] != -1int Ifn_NtkAddClauses(Ifn_Ntk_t *, int *, sat_solver *)pValues[i] == -1pValues[p->nObjs-1] != -1Iter = %5d Mint = %5d Value = %2d Var = %6d Cla = %6d Conf = %6d status = unsatstatus = sat status = undec %d=word Ifn_NtkMatchCollectPerm(Ifn_Ntk_t *, sat_solver *)void Ifn_NtkMatchCollectConfig(Ifn_Ntk_t *, sat_solver *, word *)nInps <= 16void Ifn_NtkMatchPrintPerm(word, int)*pConfig == 0int Ifn_NtkMatch(Ifn_Ntk_t *, word *, int, int, int, int, word *)i < nIterMax%s Iter =%4d. Confl = %6d. 1008{(1008{(ab)cde}f)ghi}{({(ab)cde}f)ghi};AB;CD;DE;GH;HI<>*pStr == Openchar *Ifn_NtkParseFindClosingParenthesis(char *, char, char)String is empty.If_ObjIsCi(pObj) || pObj->fVisit == 0src/map/if/ifUtil.cint If_ManCrossCut(If_Man_t *)pObj->Level >= 0 && pObj->Level <= (unsigned)p->nLevelMaxVec_Ptr_t *If_ManReverseOrder(If_Man_t *)float If_ManMarkMapping_rec(If_Man_t *, If_Obj_t *)void If_CutTraverse(If_Man_t *, If_Obj_t *, If_Cut_t *, Vec_Ptr_t *)Object is NULL.Obj %4d : constant 1PO( %4d%s )AND( %4d%s, %4d%s ) (refs = %3d)o:X@p->nLevelMax < 4094src/map/amap/amapGraph.cAmap_Obj_t *Amap_ManCreatePo(Amap_Man_t *, Amap_Obj_t *)Abc_Lit2Var(pObj->Fan[0]) != Abc_Lit2Var(pObj->Fan[1])Amap_Obj_t *Amap_ManCreateAnd(Amap_Man_t *, Amap_Obj_t *, Amap_Obj_t *)Amap_Obj_t *Amap_ManCreateXor(Amap_Man_t *, Amap_Obj_t *, Amap_Obj_t *)Amap_Obj_t *Amap_ManCreateMux(Amap_Man_t *, Amap_Obj_t *, Amap_Obj_t *, Amap_Obj_t *)void Amap_ManCreateChoice(Amap_Man_t *, Amap_Obj_t *)Warning: Mapper allocates %.3f GB for subject graph with %d objects. Performing mapping with %d given and %d created choices. pObj->Equiv==0src/map/amap/amapInt.hvoid Amap_ObjSetChoice(Amap_Obj_t *, Amap_Obj_t *)%9s %6.2f GATE %12s %10.2f %s=%s; # The genlib library "%s". %3d :%12s %d %9.2f %4s=%40s DSD: Read %d gates from file "%s". Selected %d functionally unique gates. Created %d rules and %d matches. Truth table is not available.((((::::`uŚuʚuʚu`uʚuʚuʚuʚuʚuʚuʚuʚuʚuʚuʚuʚuʚuʚuʚuʚuʚuʚu`usrc/map/amap/amapLiberty.cvoid Amap_LibertyPrintLibertyItem(FILE *, Amap_Tree_t *, Amap_Item_t *, int)strlen(TimeStamp) < 100char *Amap_LibertyTimeStamp()dont_usePair.End-Pair.Beg < ABC_MAX_LIB_STR_LENchar *Amap_LibertyGetString(Amap_Tree_t *, Amap_Pair_t)Pair.End-Pair.Beg-2 < ABC_MAX_LIB_STR_LENchar *Amap_LibertyGetStringFormula(Amap_Tree_t *, Amap_Pair_t)# This Genlib file was generated by ABC on %s # The standard cell library "%s" is from Liberty file "%s" # (To find out more about Genlib format, google for "sis_paper.ps") GATE %s=Amap_LibertyPrintGenlib() skipped sequential cell "%s". Amap_LibertyPrintGenlib() skipped cell "%s" due to dont_use attribute. Amap_LibertyPrintGenlib() skipped cell "%s" without logic function. Amap_LibertyPrintGenlib() skipped cell "%s" with unspecified area. Amap_LibertyPrintGenlib() skipped cell "%s" with constant formula "%s". PIN %13s UNKNOWN 1 999 1.00 0.00 1.00 0.00 GATE _const0_ 0.000000 z=CONST0; GATE _const1_ 0.000000 z=CONST1; File "%s". Line %6d. Failed to parse entry "%s". Memory = %7.2f MB. v < p->nItemsAmap_Item_t *Amap_LibertyItem(Amap_Tree_t *, int)char *Amap_LibertyFindMatch(char *, char *)*pPos == ')' || *pPos == '}'Parsing failed.Amap_LibertyPrintLiberty(): The output file is unavailable (absent or open).Amap_LibertyPrintGenlib(): The output file is unavailable (absent or open).Amap_LibertyFileSize(): The input file is unavailable (absent or open).Parsing finished successfully.pGate->nPins == pM->pCut->nFanssrc/map/amap/amapMatch.cfloat Amap_ManComputeMapping_rec(Amap_Man_t *, Amap_Obj_t *, int)Area =%9.2f. Gate =%9.2f. Inv =%9.2f. (%6d.) Delay =%6.2f. Time Amap_ObjRefsTotal(pFanin) > 0float Amap_CutAreaDeref(Amap_Man_t *, Amap_Mat_t *)void Amap_ManMatchGetFlows(Amap_Man_t *, Amap_Mat_t *)void Amap_ManMatchGetExacts(Amap_Man_t *, Amap_Obj_t *, Amap_Mat_t *)Amap_ObjRefsTotal(pFanin) >= 0float Amap_CutAreaRef2(Amap_Man_t *, Amap_Mat_t *, Vec_Ptr_t *, int)float Amap_CutAreaRef(Amap_Man_t *, Amap_Mat_t *)pCut0->iMat >= pCut1->iMatsrc/map/amap/amapMerge.cAmap_Cut_t *Amap_ManCutCreate(Amap_Man_t *, Amap_Cut_t *, Amap_Cut_t *, int)pNode->pData == NULLvoid Amap_ManCutSaveStored(Amap_Man_t *, Amap_Obj_t *)nCuts == nCuts2(int *)pNext - pBuffer == nWordsnCuts < (1<<20)pCut == NULL || pCut->iMat <= pNext->iMatNODE %5d : Type = Cuts = %d %3d : Mat= %3d Inv=%d %d%c void Amap_ManMergeNodeCutsMux(Amap_Man_t *, Amap_Obj_t *)pNode->Type == AMAP_OBJ_MUXpNode->fRepr == 0void Amap_ManMergeNodeCuts(Amap_Man_t *, Amap_Obj_t *)AIG object is %d bytes. Internal AIG = %5.2f MB. Cuts = %5.2f MB. CutsMax = %d. Node =%6d. Try =%9d. Try3 =%10d. Used =%7d. R =%6.2f. Amap_ManCutSaveStored(): Error!pObj->fPolar == 0src/map/amap/amapOutput.cVec_Ptr_t *Amap_ManProduceMapped(Amap_Man_t *)pGate->nPins == pObj->Best.pCut->nFansAmap_ObjRefsTotal(pFanin)uuuuuuuuuuuuuuuuuuuuuuuuuuuuuu`uuuuuuuuuu$uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu_u@u@u@u@u@u@u@u@u_u_u@u@u_u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u_uu@u@u@u@u_u_uu_u_u_u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u_u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u@u_uAmap_ParseFormula(): Different number of opening and closing parentheses (). Amap_ParseFormula(): No operation symbol before constant 0. Amap_ParseFormula(): No operation symbol before constant 1. Amap_ParseFormula(): No variable is specified before the negation suffix. Amap_ParseFormula(): There is no variable before AND, EXOR, or OR. Amap_ParseFormula(): There is no opening parenthesis Amap_ParseFormula(): Unknown operation Amap_ParseFormula(): The negation sign or an opening parenthesis inside the variable name. Amap_ParseFormula(): The parser cannot find var "%s" in the input var list of gate "%s". Amap_ParseFormula(): Something is left in the operation stack Amap_ParseFormula(): Something is left in the function stack Amap_ParseFormula(): The input string is empty Gates with more than %d inputs will be ignored. Cannot parse formula "%s" of gate "%s" with no pins. Skipping gate "%s" because its output "%s" does not depend on all input variables. pNod->Type != AMAP_OBJ_MUXsrc/map/amap/amapPerm.cunsigned int *Amap_LibVerifyPerm_rec(Amap_Lib_t *, Amap_Nod_t *, Vec_Ptr_t *, Vec_Int_t *, int, int *)pGate->nPins > 1void Amap_LibVerifyPerm(Amap_Lib_t *, Amap_Gat_t *, Kit_DsdNtk_t *, Amap_Nod_t *, int *)iInput == (int)pGate->nPinsVerification failed for gate %d (%s) and node %d. Vec_IntSize(vPerm) == (int)pNod->nSuppSizeint Amap_LibDeriveGatePerm(Amap_Lib_t *, Amap_Gat_t *, Kit_DsdNtk_t *, Amap_Nod_t *, char *)Entry < 2 * (int)pNod->nSuppSizeId >= 0 && Id < pNtk->nVars + pNtk->nNodes./src/bool/kit/kit.hKit_DsdObj_t *Kit_DsdNtkObj(Kit_DsdNtk_t *, int)unsigned int *Vec_IntFetch(Vec_Int_t *, int)src/map/amap/amapRead.c = p->nPins == 1 && !strcmp( p->Pins->pName, "*" )Amap_Gat_t *Amap_ParseGateWithSamePins(Amap_Gat_t *)The first line should begin with %s. Cannot parse gate %s. Cannot read phase of pin %s of gate %s Warning: Detected %d multi-output gates (for example, "%s"). Vec_PtrSize(vVecNods0) > 0src/map/amap/amapRule.cVec_Int_t *Amap_CreateRulesVector_rec(Amap_Lib_t *, Vec_Ptr_t *, int)Vec_PtrSize(vVecNods1) > 0Vec_PtrSize(vVecNods0) < Vec_PtrSize(vVecNods)Vec_PtrSize(vVecNods1) < Vec_PtrSize(vVecNods)Vec_Int_t *Amap_CreateRulesFromDsd_rec(Amap_Lib_t *, Kit_DsdNtk_t *, int)Kit_DsdObjTruth(pObj)[0] == 0xCACACACAp->nVars >= 2Vec_Int_t *Amap_CreateRulesFromDsd(Amap_Lib_t *, Kit_DsdNtk_t *)!Abc_LitIsCompl(iLit0)int Amap_CreateCheckEqual_rec(Kit_DsdNtk_t *, int, int)pObj0->Type == KIT_DSD_AND || pObj0->Type == KIT_DSD_XORvoid Amap_CreateCheckAsym_rec(Kit_DsdNtk_t *, int, Vec_Int_t **)pObj->Type == KIT_DSD_AND || pObj->Type == KIT_DSD_XOR Processing library gate %4d: %10s iNod > 1void Amap_CreateRulesForGate(Amap_Lib_t *, Amap_Gat_t *)Cound not prepare gate "%s": Amap_LibCreateRules(): Skipping gate %s (%s). Vec_PtrSize(pLib->vRules) == 2*pLib->nNodesvoid Amap_LibCreateRules(Amap_Lib_t *, int)Vec_PtrSize(pLib->vRulesX) == 2*pLib->nNodesp->pNodes == NULLsrc/map/amap/amapUniq.cint Amap_LibCreateVar(Amap_Lib_t *)Creating node %5d %c : iFan0 = %5d%c iFan1 = %5d%c Creating node %5d %c : iFan0 = %5d%c iFan1 = %5d%c iFan2 = %5d%c nTotal == nEntriesint **Amap_LibLookupTableAlloc(Vec_Ptr_t *, int)pCube->nLits == (unsigned)vLits->nSizesrc/map/cov/covBuild.cAbc_Obj_t *Abc_NtkCovDeriveCube(Abc_Ntk_t *, Abc_Obj_t *, Min_Cube_t *, Vec_Int_t *, int)Lit == 1 || Lit == 2pCube->nLits > 1Abc_Obj_t *Abc_NtkCovDeriveNode_rec(Cov_Man_t *, Abc_Ntk_t *, Abc_Obj_t *, int)vSuppAbc_Ntk_t *Abc_NtkCovDerive(Cov_Man_t *, Abc_Ntk_t *)pObj->pCopyAbc_Obj_t *Abc_NtkCovDeriveInv(Abc_Ntk_t *, Abc_Obj_t *, int)Abc_Obj_t *Abc_NtkCovDeriveCubeInv(Abc_Ntk_t *, Abc_Obj_t *, Min_Cube_t *, Vec_Int_t *)Abc_Obj_t *Abc_NtkCovDeriveNodeInv_rec(Cov_Man_t *, Abc_Ntk_t *, Abc_Obj_t *, int)Abc_Ntk_t *Abc_NtkCovDeriveClean(Cov_Man_t *, Abc_Ntk_t *)Abc_Obj_t *Abc_NtkCovDerive_rec(Cov_Man_t *, Abc_Ntk_t *, Abc_Obj_t *)Abc_Ntk_t *Abc_NtkCovDeriveRegular(Cov_Man_t *, Abc_Ntk_t *)Abc_NtkCovDeriveInv: The network check has failed.Abc_NtkCovDerive: The network check has failed.src/map/cov/covCore.cAbc_Ntk_t *Abc_NtkSopEsopCover(Abc_Ntk_t *, int, int, int, int, int, int)vSupp0 && vSupp1Vec_Int_t *Abc_NodeCovSupport(Cov_Man_t *, Vec_Int_t *, Vec_Int_t *)Iter %d : Outs = %4d (%4d) Node = %6d (%6d) Max = %6d Bound = %4d Abc_ObjGetSupp(pObj) == NULLint Abc_NodeCovPropagate(Cov_Man_t *, Abc_Obj_t *)pCover0 && pCover1Min_Cube_t *Abc_NodeCovProduct(Cov_Man_t *, Min_Cube_t *, Min_Cube_t *, int, int)Abc_NtkCov: The network check has failed.pNtk->pManCut == NULLsrc/map/cov/covMan.cCov_Man_t *Cov_ManAlloc(Abc_Ntk_t *, int, int)p->vFanCountsvoid Abc_NodeCovDropData(Cov_Man_t *, Abc_Obj_t *)pCube != p->pBubblesrc/map/cov/covMinEsop.cvoid Min_EsopAddCube(Min_Man_t *, Min_Cube_t *)(int)pCube->nLits == Min_CubeCountLits(pCube)pCube == p->pBubblevoid Min_EsopRewrite(Min_Man_t *)pThis == p->ppStore[pThis->nLits]pCube == p->ppStore[pCube->nLits]Error: Min_CubesDistOne() looks at two equal cubes!Error: Min_CubesDistTwo() looks at two equal cubes or dist1 cubes!Min_CubeCheck( pCube )src/map/cov/covMinSop.cvoid Min_SopAddCube(Min_Man_t *, Min_Cube_t *)pCube->nLits == pCube2->nLitsvoid Min_SopDist1Merge(Min_Man_t *)pCubeNew->nLits == pCube->nLits - 1void Min_SopRewrite(Min_Man_t *)pCube != p->pBubble && pThis != p->pBubblev00 != v10 && v01 != v11v00 != 3 || v01 != 3v10 != 3 || v11 != 3v00 == (v10 ^ 3)v01 == (v11 ^ 3)v10 == 3 || v11 == 3v01 == 3v01 != 3 && v10 != 3v01 != 3 && v10 != 3 && v11 != 3pCube0->nVars == pCube1->nVarssrc/map/cov/covInt.hMin_Cube_t *Min_CubesXor(Min_Man_t *, Min_Cube_t *, Min_Cube_t *)int Min_CubesDisjoint(Min_Cube_t *, Min_Cube_t *)src/map/cov/covMinUtil.cvoid Min_CubeCreate(Vec_Str_t *, Min_Cube_t *, char)pCover != NULLvoid Min_CoverCreate(Vec_Str_t *, Min_Cube_t *, char)void Min_CubeWrite(FILE *, Min_Cube_t *)%s.%s# %s cover for output %s generated by ABC on %s ESOPi == (int)pCube->nLitsvoid Min_CoverCheck(Min_Man_t *)Min_Cube_t *Min_CoverCollect(Min_Man_t *, int)pCube->uData[0]HC*vzvzvzvzvzv\vzvzvzvzvzvvzvzvzvzvzvzvzvzvzvzvzvzvzvzvzvzvvzvzvzvzvzvzvzvzvzvvzvzvzvzvzvzvzvvgvvvv|vvvvvvvvvvvvv#vvvvvvv]vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv)vvSvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvnvvnvvnvnv/vnvevvnvnvnvvnvnvnvvnvKvnvnv~vvnvnvnvnvnvnvnvnvnvnvvvnvnvnvnvnvnvnvnvnvnvnvnvnvnv(vnvnv reads Liberty library from file -d : toggle dumping the parsed library into file "*_temp.lib" [default = %s] -v : toggle writing verbose information [default = %s] -w : toggle writing information about skipped gates [default = %s] -h : prints the command summary : the name of a file to read There is no Liberty library available. Cannot open output file "%s". usage: write_lib [-h] write current Liberty library into file SGishusage: print_lib [-SG float] [-ish] prints statistics of Liberty library -i : toggle printing invs/bufs only [default = %s] -s : toggle printing in short format [default = %s] ABvhusage: leak2area [-AB float] [-v] converts leakage into area: Area = A * Area + B * Leakage -A float : the multiplicative coefficient to transform area [default = %.2f] -B float : the multiplicative coefficient to transform leakage [default = %.2f] usage: read_scl [-dh] reads extracted Liberty library from file -d : toggle dumping the parsed library into file "*_temp.lib" [default = %s] : the name of a file to read usage: write_scl [-h] write extracted Liberty library into file SGMvhusage: dump_genlib [-SG float] [-M num] [-vh] writes GENLIB file for SCL library : optional GENLIB file name The current network is not mapped. usage: print_gs [-h] prints gate sizes in the current mapping XcapdhCommand line switch "-X" should be followed by a positive integer. The current network is not in a topo order (run "topo"). usage: stime [-X num] [-capdth] performs STA using Liberty library -X : min Cout/Cave ratio for tree estimations [default = %d] -c : toggle using wire-loads if specified [default = %s] -a : display timing information for all nodes [default = %s] -p : display timing information for critical path [default = %s] -d : toggle dumping statistics into a file [default = %s] usage: topo [-vh] rearranges nodes to be in a topological order The current network is not a logic network. usage: unbuffer [-ivh] collapses buffer/inverter trees -i : toggle removing interters [default = %s] GSNsbpcvwhCommand line switch "-G" should be followed by a positive integer. Fanin phase information is not avaiable. Library delay info is not available. usage: buffer [-GSN num] [-sbpcvwh] performs buffering and sizing and mapped network -G : target gain percentage [default = %d] -S : target slew in pisoseconds [default = %d] -N : the maximum fanout count [default = %d] -s : toggle performing only sizing [default = %s] -b : toggle using buffers instead of inverters [default = %s] -p : toggle buffering primary inputs [default = %s] -c : toggle using wire-loads if specified [default = %s] usage: minsize [-vh] downsizes all gates to their minimum size usage: maxsize [-vh] upsizes all gates to their maximum size IJWRNDGTXBcsdvwhCommand line switch "-J" should be followed by a positive integer. Command line switch "-R" should be followed by a positive integer. Command line switch "-B" should be followed by a positive integer. usage: upsize [-IJWRNDGTXB num] [-csdvwh] selectively increases gate sizes on the critical path -I : the number of upsizing iterations to perform [default = %d] -J : the number of iterations without improvement to stop [default = %d] -W : delay window (in percent) of near-critical COs [default = %d] -R : ratio of critical nodes (in percent) to update [default = %d] -N : limit on discrete upsizing steps at a node [default = %d] -D : delay target set by the user, in picoseconds [default = %d] -G : delay gap during updating, in picoseconds [default = %d] -T : approximate timeout in seconds [default = %d] -X : ratio for buffer tree estimation [default = %d] -B : frequency of bypass transforms [default = %d] -s : toggle using slack based on departure times [default = %s] -d : toggle dumping statistics into a file [default = %s] IJNDGTXcsdvwhusage: dnsize [-IJNDGTX num] [-csdvwh] selectively decreases gate sizes while maintaining delay usage: print_buf [-vh] prints buffers trees of the current design usage: read_constr [-nvh] read file with timing constraints for standard-cell designs -n : toggle using new constraint file format [default = %s] Scl_CommandWriteConstr(): There is no constraint manager. _out.construsage: write_constr [-vh] writes current timing constraints into a file .default_%s %s input_cell.default_%s %.2f input_slewinput_load.%s %s %s .%s %s %.2f usage: print_constr [-vh] prints current timing constraints usage: reset_constr [-vh] removes current timing constraints Scl_CommandWriteConstr(): Unrecognized output file extension.6e6e6e6eNode %d has dup fanin %d. src/map/scl/sclBuffer.cint Abc_SclIsInv(Abc_Obj_t *)Abc_ObjFaninNum(pFaninNew) == 1Abc_Ntk_t *Abc_SclUnBufferPerform(Abc_Ntk_t *, int)Abc_Ntk_t *Abc_SclBufferPhase(Abc_Ntk_t *, int)Added %d inverters (%.2f %% fanins) (%.2f %% compl fanins). pNtk->vPhases == NULLAbc_Ntk_t *Abc_SclUnBufferPhase(Abc_Ntk_t *, int)Saved %d (%.2f %%) fanin phase bits. Max depth = %d. obj %d and its fanin %d are not in the topo order node %d has no fanout Abc_ObjFaninNum(pObj) == 0 || Abc_SclObjIsBufInv(pObj)void Abc_NodeInvUpdateFanPolarity(Abc_Obj_t *)Abc_ObjFaninNum(pFanout) > 0Abc_ObjFanoutNum(pObj) > DegreeAbc_Obj_t *Abc_SclPerformBufferingOne(Abc_Obj_t *, int, int, int)i < Vec_PtrSize(vFanouts)Degree <= Degree0%d%s void Abc_SclPerformBuffering_rec(Abc_Obj_t *, int, int, int, int)Abc_NtkHasMapping(p)Abc_Ntk_t *Abc_SclPerformBuffering(Abc_Ntk_t *, int, int, int, int)void Abc_BufCollectTfoCone_rec(Abc_Obj_t *, Vec_Int_t *)void Abc_BufCollectTfiCone_rec(Abc_Obj_t *, Vec_Int_t *)Sep = %d. Dup = %d. Br0 = %d. Br1 = %d. BrC = %d. Orig = %d. Add = %d. Rem = %d. Slack >= 0Vec_Int_t *Abc_BufSortByDelay(Buf_Man_t *, int)Node %5d Fi = %d Fo = %3d Lev = %3d : {pObj->pData == Mio_LibraryReadBuf((Mio_Library_t *)pNtk->pManFunc)void Abc_BufReplaceBufsByInvs(Abc_Ntk_t *)Replaced %d buffers by invertor pairs. Abc_NtkObjNumMax(p->pNtk) + 30 < p->nObjAllocvoid Abc_BufPerformOne(Buf_Man_t *, int, int, int)ObjId = %6d : %-10s FI = %d. FO =%4d. Crit =%4d. Abc_NodeIsInv(pObj)Adding %d inverters Adding %d buffers j >= 0 && j < nDegreep->pNtk->vPhasesint Abc_ObjFaninPhase(Abc_Obj_t *, int)i >= 0 && i < Abc_ObjFaninNum(p)void Abc_ObjFaninFlipPhase(Abc_Obj_t *, int)Doing nothingAdding bufferThe network is in topo order and no dangling nodes.Warning!!! Using inverters instead of buffers.The phases are not given. The result will not verify.Duplicating nodeCannot find the default PI driving cell (%s) in the library. p->pPiDrive != NULLsrc/map/scl/sclBufSize.cvoid Bus_ManReadInOutLoads(Bus_Man_t *)p->pPiDrive->n_inputs == 1Bus_SclObjDept(pObj) == 0float Abc_NtkComputeNodeDeparture(Abc_Obj_t *, float)Bus_SclObjLoad(pObj) == 0float Abc_NtkComputeNodeLoad(Bus_Man_t *, Abc_Obj_t *)Obj %6d fanouts (%d): %3d : time = %7.2f ps load = %7.2f ff Fanout profile (%d): Fanouts %d and %d are out of order. %s%7d : Inv%d/%2d (%2d/%2d) gain =%5d dept =%7.0f ps (int)Abc_ObjId(pInv) == Vec_FltSize(p->vCins)Abc_Obj_t *Abc_SclAddOneInv(Bus_Man_t *, Abc_Obj_t *, Vec_Ptr_t *, float)LoadNew - Load < 1 && Load - LoadNew < 1Buffering could not be completed because the gain value (%d) is too low. void Abc_SclBufSize(Bus_Man_t *, float)p->pPars->fSizeOnly || Abc_ObjFanoutNum(pObj) <= p->pPars->nDegreeWireLoads = %d Degree = %d Target slew =%4d ps Gain2 =%5d Buf = %6d Delay =%7.0f ps float *Vec_FltEntryP(Vec_Flt_t *, int)Edge > 0float Abc_NtkComputeEdgeDept(Abc_Obj_t *, int, float)Vec_PtrSize(&p->vData) == 1src/map/scl/sclLib.hfloat Scl_LibLookup(SC_Surface *, float, float)Vec_FltSize(vTemp) == 1iPin >= 0 && iPin < pCell->n_inputsSC_Timing *Scl_CellPinTime(SC_Cell *, int)Vec_PtrSize(&pPin->vRTimings) == pCell->n_inputsVec_PtrSize(&pRTime->vTimings) == 1pCell->n_inputs == 1void Scl_LibHandleInputDriver(SC_Cell *, SC_Pair *, SC_Pair *, SC_Pair *)src/map/scl/sclDnsize.cvoid Abc_SclFindWindow(Abc_Obj_t *, Vec_Int_t **, Vec_Int_t **)Vec_IntSize(vEvals) > 0Vec_QueSize(p->vNodeByGain) == 0void Abc_NtkCollectNodesByArea(SC_Man *, Abc_Ntk_t *)Total : Try =%6d Over =%6d Fail =%6d Win =%6d %.2f (%+5.1f %%) %.2f ps %8.2f sec Iters =%5d. UseDept =%2d. UseWL =%2d. Target =%5d ps. DelayGap =%3d ps. Timeout =%4d secp->vGatesBest == NULLvoid Abc_SclDnsizePerformInt(SC_Lib *, Abc_Ntk_t *, SC_SizePars *) Runtime: Critical pathRuntime: Sizing eval Runtime: Timing updateRuntime: Other Runtime: TOTAL stats2.txtGate sizing timed out at %d seconds. Vec_FltSize(p->vLoads2) == ksrc/map/scl/sclSize.hvoid Abc_SclLoadRestore(SC_Man *, Abc_Obj_t *)Vec_FltSize(p->vTimes3) == kfloat Abc_SclEvalPerformLegal(SC_Man *, Vec_Int_t *, float)Vec_FltSize(p->vTimes2) == kvoid Abc_SclConeRestore(SC_Man *, Vec_Int_t *)void Vec_QueCheck(Vec_Que_t *)p->nSize <= p->nCapp->pOrder[i] > 0p->pOrder[i] == -1p->pHeap[p->pOrder[i]] == ip->pHeap[i] == -1Vec_QuePrio(p, p->pHeap[i]) >= Vec_QuePrio(p, p->pHeap[child])wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwsrc/map/scl/sclLiberty.cvoid Scl_LibertyParseDumpItem(FILE *, Scl_Tree_t *, Scl_Item_t *, int)Buffer[Pair.End-Pair.Beg-1] == '\"'char *Scl_LibertyReadString(Scl_Tree_t *, Scl_Pair_t)Parsing failed. Parsing timeParsing finished successfully. cell_leakage_powerwhenthree_stateScl_LibertyReadGenlib() skipped sequential cell "%s". Scl_LibertyReadGenlib() skipped cell "%s" due to dont_use attribute. Scl_LibertyReadGenlib() skipped three-state cell "%s". Scl_LibertyReadGenlib() skipped cell "%s" without logic function. Scl_LibertyReadGenlib() skipped cell "%s" with constant formula "%s". default_wire_loaddefault_wire_load_selectiondefault_max_transitiontime_unit1ns100ps10ps1pscapacitive_load_unit \",pfslopefanout_lengthwire_load_from_areapThird[strlen(pThird)-1] == '\"'void Scl_LibertyReadWireLoadSelect(Scl_Tree_t *, Vec_Str_t *)drive_strengthdirectiontimingrelated_pintiming_sensepositive_unatenegative_unateVec_FltSize(vInd1) * Vec_FltSize(vInd2) == Vec_FltSize(vValues)void Scl_LibertyDumpTables(Vec_Str_t *, Vec_Flt_t *, Vec_Flt_t *, Vec_Flt_t *)index_1vIndex1 == NULLint Scl_LibertyScanTable(Scl_Tree_t *, Vec_Ptr_t *, Scl_Item_t *, char *, Vec_Ptr_t *)index_2vIndex2 == NULLvValues == NULLscalarVec_FltSize(vValues) == 1!vIndex1 || Vec_FltSize(vIndex1) == Vec_FltSize(vInd1)!vIndex2 || Vec_FltSize(vIndex2) == Vec_FltSize(vInd2)!vIndex2 || Vec_FltSize(vIndex2) == Vec_FltSize(vInd1)!vIndex1 || Vec_FltSize(vIndex1) == Vec_FltSize(vInd2)Vec_FltSize(vValues) == Vec_FltSize(vValues2)Vec_PtrSize(vTables) > 0 && Vec_PtrSize(vTables) % 3 == 0int Scl_LibertyComputeWorstCase(Vec_Ptr_t *, Vec_Flt_t **, Vec_Flt_t **, Vec_Flt_t **)int Scl_LibertyReadTable(Scl_Tree_t *, Vec_Str_t *, Scl_Item_t *, char *, Vec_Ptr_t *)Vec_PtrSize(vRes) % 4 == 0void Scl_LibertyPrintTemplates(Vec_Ptr_t *)There are %d slew/load templates lu_table_templateVec_Ptr_t *Scl_LibertyReadTemplates(Scl_Tree_t *)variable_1pVar1 == NULLvariable_2pVar2 == NULLinput_net_transitiontotal_output_net_capacitanceTemplates are not defined. Scl_LibertyReadPinDirection(p, pPin) == 0Vec_Str_t *Scl_LibertyReadSclStr(Scl_Tree_t *, int, int)rise_capacitancefall_capacitanceScl_LibertyReadPinDirection(p, pPin) == 1max_capacitancecell_risecell_fallrise_transitionfall_transitionVec_PtrSize(vTemples) % 4 == 0Library "%s" from "%s" has %d cells (%d skipped: %d seq; %d tri-state; %d no func; %d dont_use). bwrc.libtest_scl.libScl_Item_t *Scl_LibertyItem(Scl_Tree_t *, int)char *Scl_LibertyFindMatch(char *, char *) %fScl_LibertyParseDump(): The output file is unavailable (absent or open).Scl_LibertyFileSize(): The input file is unavailable (absent or open).Scl_LibertyStringDump(): The output file is unavailable.Libery parser cannot read "time_unit". Assuming time_unit : "1ns".Libery parser cannot read "capacitive_load_unit". Assuming capacitive_load_unit(1, pf).Cannot read "scalar" templateTemplate cannot be found in the template libraryIncomplete table specificationTable cannot be found ? Qxzxbxnxsrc/map/scl/sclLibScl.cSC_Lib *Abc_SclReadFromStr(Vec_Str_t *)SC_Lib *Abc_SclReadFromFile(char *)Cannot open text file "%s" for writing. Dumped internal library into Liberty file "%s". int Abc_SclReadLibraryGenlib(SC_Lib *, Mio_Library_t *)Wrong version of the SCL file. int Abc_SclReadLibrary(Vec_Str_t *, int *, SC_Lib *)k == pCell->n_inputspPin->func_text == NULLVec_WrdSize(&pPin->vFunc) == 0Vec_WrdSize(&pPin->vFunc) == Abc_Truth6WordNum(pCell->n_inputs)Value == Vec_WrdEntry(&pPin->vFunc, k)n <= 1Vec_PtrSize(&pRTime->vTimings) == 0p->unit_time >= 0void Abc_SclWriteLibrary(Vec_Str_t *, SC_Lib *)p->unit_cap_snd >= 0pPin->dir == sc_dir_InputpPin->dir == sc_dir_Output/* This Liberty file was generated by ABC on %s */ /* The original unabridged library came from file "%s".*/ library(%s) { default_wire_load : "%s"; default_wire_load_selection : "%s"; default_max_transition : %f; time_unit : "1ns"; time_unit : "100ps"; time_unit : "10ps"; time_unit : "1ps"; void Abc_SclWriteLibraryText(FILE *, SC_Lib *) capacitive_load_unit(%.1f,%s); wire_load("%s") { capacitance : %f; slope : %f; fanout_length( %d, %f ); } wire_load_selection("%s") { wire_load_from_area( %f, %f, %s ); cell(%s) { /* n_inputs = %d n_outputs = %d */ area : %f; cell_leakage_power : %f; drive_strength : %d; pin(%s) { direction : %s; fall_capacitance : %f; rise_capacitance : %f; max_capacitance : %f; max_transition : %f; function : "%s"; /* truth table = */ timing() { related_pin : "%s" timing_sense : positive_unate; timing_sense : negative_unate; timing_sense : non_unate; cell_rise() { } cell_fall() { rise_transition() { fall_transition() { index_1("%f%s"); index_2(" values ("");src/map/scl/sclLibUtil.cint *Abc_SclHashLookup(SC_Lib *, char *)p->nBins == 0void Abc_SclHashCells(SC_Lib *)i < pCell->n_inputsvoid Abc_SclShortFormula(SC_Cell *, char *, char *)g%0*d_%0*dVec_PtrSize(&p->vCellClasses) == 0void Abc_SclLinkCells(SC_Lib *)pWLoadUsed != NULLSC_WireLoad *Abc_SclFetchWireLoadModel(SC_Lib *, char *)Cannot find wire load model "%s". Cannot find wire load selection model "%s". %s.skip Cannot find cell "%s" in the library "%s". Marked %d cells for skipping in the library "%s". Vec_PtrSize(&p->vCellClasses) > 0void Abc_SclPrintCells(SC_Lib *, float, float, int, int)Library "%s" has %d cells in %d classes. Delay estimate is based on slew %.2f ps and gain %.2f.Class%4d : Cells =%3d Ins =%2d Outs =%2d %-30s %3d %-*s A =%8.2f L =%8.2f LD =%6.1f ps PD =%6.1f ps C =%5.1f ff Cm =%5.0f ff Sm =%5.1f ps GATE _const0_ 0.00 z=CONST0; GATE _const1_ 0.00 z=CONST1; strlen(pCell->pName) < 200Vec_Str_t *Abc_SclProduceGenlibStrSimple(SC_Lib *)%-16s PIN Derived GENLIB library "%s" with %d gates. strlen(pRepr->pName) < 200Vec_Str_t *Abc_SclProduceGenlibStr(SC_Lib *, float, float, int, int *) UNKNOWN 1 999 %7.2f 0.00 %7.2f 0.00 Vec_Str_t *Abc_SclProduceGenlibStrProfile(SC_Lib *, Mio_Library_t *, float, float, int, int *)%s_s%03d_g%03d_m%d.genlibWritten GENLIB library with %d gates into file "%s". Derived GENLIB library "%s" with %d gates using slew %.2f ps and gain %.2f. 5 QReading library has filed.pWL != NULLsrc/map/scl/sclLoad.cVec_Flt_t *Abc_SclFindWireCaps(SC_WireLoad *, int)Maximum input drive strength is exceeded at primary input %d. void Abc_SclUpdateLoadSplit(SC_Man *, Abc_Obj_t *, Abc_Obj_t *)Abc_ObjFaninNum(pBuffer) == 1=Abc_NtkPoNum(p->pNtk) > 0src/map/scl/sclSize.cAbc_Obj_t *Abc_SclFindCriticalCo(SC_Man *, int *)pPivot != NULLWireLoad = "%s" %sGates =%7d%s (%5.1f %%) %sCap =%5.1f ff%s %sArea =%12.2f%s %sDelay =%9.2f ps%s Path%3d --Start-point = pi%0*d. End-point = po%0*d. !fDeptvoid Abc_SclTimeNode(SC_Man *, Abc_Obj_t *, int)Level of node %d is out of date! void Abc_SclManReadSlewAndLoad(SC_Man *, Abc_Ntk_t *)Node %d and its fanin %d have common fanin %d. %-16s : %6d: %-16s (%2d:%3d:%3d) a =%5.2f d = (%6.0f ps; %6.0f ps) l =%5.0f ff s =%5.0f ps sl =%5.0f ps L =%5.0f ff Lx =%5.0f ff Dx =%5.0f ps Cx =%5.0f psAbc_ObjIsBuffer(pObj)void Abc_SclPrintBuffersInt(SC_Man *, Abc_Obj_t *, int)void Abc_SclPrintBuffers(SC_Lib *, Abc_Ntk_t *, int)A =%7.2f D%s =%7.1f ps S =%6.1f ps Cin =%5.1f ff Cout =%6.1f ff Cmax =%6.1f ff G =%5d void Abc_SclTimeIncAddNode(SC_Man *, Abc_Obj_t *)pObj->fMarkC == 1void Abc_SclTimeIncUpdateClean(SC_Man *)pLib->unit_time == 12SC_Man *Abc_SclManAlloc(SC_Lib *, Abc_Ntk_t *)pLib->unit_cap_snd == 15?o:src/map/scl/sclUpsize.cvoid Abc_SclFindTFO_rec(Abc_Obj_t *, Vec_Int_t *, Vec_Int_t *)Vec_IntSize(vPath) > 0Vec_Int_t *Abc_SclFindTFO(Abc_Ntk_t *, Vec_Int_t *)Vec_IntSize(vPivots) > 0Vec_Int_t *Abc_SclFindCriticalCoWindow(SC_Man *, int)void Abc_SclFindCriticalNodeWindow_rec(SC_Man *, Abc_Obj_t *, Vec_Int_t *, float, int)Abc_ObjIsNode(pNext)void Abc_SclFindNodesToUpdate(Abc_Obj_t *, Vec_Int_t **, Vec_Int_t **, Abc_Obj_t *)pPivot->fMarkApBuf->fMarkB == 0int Abc_SclFindBypasses(SC_Man *, Vec_Int_t *, int, int, int, int, int)dGainBest2 > 0.0Node %6d Redir fanout %6d to fanin %6d. Gain = %7.1f ps. Gate %12s (%2d/%2d) -> %12s (%2d/%2d) int Abc_SclFindUpsizes(SC_Man *, Vec_Int_t *, int, int, int, int, int)dGainBest > 0.0pCellNew != NULLGateId == GateId2void Abc_SclApplyUpdateToBest(Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Vec_IntSize(vTrans) % 3 == 0void Abc_SclUndoRecentChanges(Abc_Ntk_t *, Vec_Int_t *)%6d : load rise differs %12.6f %f %f %6d : load fall differs %12.6f %f %f %6d : slew rise differs %12.6f %f %f %6d : slew fall differs %12.6f %f %f %6d : time rise differs %12.6f %f %f %6d : time fall differs %12.6f %f %f Win:%3d. PO:%6d. Path:%7d. Gate:%5d. TFO:%7d. B: (%+5.1f %%)Time win =%3d %%. Update ratio =%3d %%. void Abc_SclUpsizePerformInt(SC_Lib *, Abc_Ntk_t *, SC_SizePars *)Current delay (%.2f ps) does not exceed the target delay (%.2f ps). Upsizing is not performed. float Abc_SclEvalPerform(SC_Man *, Vec_Int_t *)Vec_FltSize(p->vLoads3) == kvoid Abc_SclLoadRestore3(SC_Man *, Abc_Obj_t *)bufferId >= 0src/map/scl/sclUtil.cvoid Abc_SclMioGates2SclGates(SC_Lib *, Abc_Ntk_t *)p->vGates == NULLgateId >= 0p->vGates != NULLvoid Abc_SclSclGates2MioGates(SC_Lib *, Abc_Ntk_t *)pCell->n_inputs == Abc_ObjFaninNum(pObj)pObj->fMarkA == 0 && pObj->fMarkB == 0Could not find %d (out of %d) gates in the current library. pOld->nBarBufs2 > 0void Abc_SclTransferGates(Abc_Ntk_t *, Abc_Ntk_t *)pNew->nBarBufs2 == 0pCell->Order < ABC_SCL_MAX_SIZEvoid Abc_SclManPrintGateSizes(SC_Lib *, Abc_Ntk_t *, Vec_Int_t *)Total gates = %d. Total area = %.1f Cell size = %d. Count = %6d Area = %12.1f gateId >= 0 && gateId < Vec_PtrSize(&pLib->vCells)void Abc_SclMinsizePerform(SC_Lib *, Abc_Ntk_t *, int, int)set_driving_cellSetting driving cell to be "%s". set_loadSetting output load to be %f. Unrecognized token "%s". Cannot find buffer in the current library. Quitting.Mig_ManObjNum(pMig) == Gia_ManObjNum(p)src/map/mpm/mpmAbc.cvoid Mig_ManCreateChoices(Mig_Man_t *, Gia_Man_t *)Vec_IntSize(&pMig->vSibls) == 0Abc_Lit2Var(pObj->Value) == iMig_Man_t *Mig_ManCreate(void *)fHash == 0int Mpm_ManNodeIfToGia_rec(Gia_Man_t *, Mpm_Man_t *, Mig_Obj_t *, Vec_Ptr_t *, int)int Mpm_ManNodeIfToGia(Gia_Man_t *, Mpm_Man_t *, Mig_Obj_t *, Vec_Int_t *, int)Mpm_ManNodeIfToGia(): Computing local AIG has failed. Abc_Lit2Var(Entry) < Abc_Lit2Var(iLitNew)void *Mpm_ManFromIfLogic(Mpm_Man_t *)Vec_IntSize(vMapping) == Gia_ManObjNum(pNew)pNew->vPacking == NULL!Gia_ObjIsAnd(Gia_ObjFanin0(pObj)) || Gia_ObjIsLut(pNew, Gia_ObjFaninId0p(pNew, pObj))src/map/mpm/mpmMig.hMig_Obj_t *Mig_ManObj(Mig_Man_t *, int)s > 0 && Mig_ObjId(p) > svoid Mig_ObjSetSiblId(Mig_Obj_t *, int)iLit0 != iLit1 && iLit0 != iCtrl && iLit1 != iCtrlint Mig_ManAppendMux(Mig_Man_t *, int, int, int)!Abc_LitIsCompl(iLit0) || !Abc_LitIsCompl(iLit1)p->nObjs < MIG_NONEMig_Obj_t *Mig_ManAppendObj(Mig_Man_t *)p->nObjs == (Vec_PtrSize(&p->vPages) << MIG_BASE)Mig_ObjIsNone(pObj)v >= 0 && v < MIG_NONEint Mig_FanSetId(Mig_Obj_t *, int, int)l >= 0 && (l >> 1) < Mig_ObjId(p)void Mig_ObjSetFaninLit(Mig_Obj_t *, int, int)int Mig_ManAppendXor(Mig_Man_t *, int, int)!Abc_LitIsCompl(iLit0) && !Abc_LitIsCompl(iLit1)int Mig_ManAppendAnd(Mig_Man_t *, int, int)Mig_FanIsNone(p, 1)void Mig_ObjSetCioId(Mig_Obj_t *, int)!Mig_ObjIsCo(Mig_ManObj(p, Abc_Lit2Var(iLit0)))int Mig_ManAppendCo(Mig_Man_t *, int)Mpm_CutWordNum(pCut->nLeaves) == (h & p->pManCuts->uMask)src/map/mpm/mpmInt.hMpm_Cut_t *Mpm_CutFetch(Mpm_Man_t *, int)(h & p->uMask) > 0./src/misc/mem/mem2.hword *Mmr_StepEntry(Mmr_Step_t *, int)h > 0 && h < (Vec_PtrSize(&p->vPages) << p->nPageBase)word *Mmr_FixedEntry(Mmr_Fixed_t *, int)i < 3 && Mig_FanId(p, i) < Mig_ObjId(p)int Mig_ObjFaninId(Mig_Obj_t *, int)Vec_IntSize(&Mig_ObjMan(p)->vCopies) != 0void Mig_ObjSetCopy(Mig_Obj_t *, int)pPars->pLib->LutMax <= MPM_VAR_MAXsrc/map/mpm/mpmCore.cGia_Man_t *Mpm_ManLutMapping(Gia_Man_t *, Mpm_Par_t *)pPars->nNumCuts <= MPM_CUT_MAX@%5d : %-20s Unused classes = %d (%.2f %%). Non-DSD cuts = %d (%.2f %%). No-match cuts = %d (%.2f %%). dsdfuncs6.datp->pDsd6 == NULLsrc/map/mpm/mpmDsd.cvoid Mpm_ManPrecomputePerms(Mpm_Man_t *)OneCopy == Onex == Vec_IntSize(vVars)Vec_IntEntry( p->vMap2Perm, One ) != -1p->vPerm6 == NULLuTruth == s_DsdClass6[i].uTruthSetting up DSD informationpMan->pDsd6[iClass].nVars == (int)pCut->nLeavesword Mpm_CutTruthFromDsd(Mpm_Man_t *, Mpm_Cut_t *, int)int Mpm_CutComputeDsd6(Mpm_Man_t *, Mpm_Cut_t *, Mpm_Cut_t *, Mpm_Cut_t *, Mpm_Cut_t *, int, int, int, int)(Config >> 6) < 720pLeavesNew[i] != -1(ab)[ab](abc)(!(ab)c)[(ab)c]([ab]c)[abc](abcd)(!(abc)d)[(abc)d](!(ab)cd)(!(!(ab)c)d)[(!(ab)c)d]([(ab)c]d)[(ab)cd]([ab]cd)(!([ab]c)d)[([ab]c)d]([abc]d)[abcd](d)[d](!(ab)!(cd))[(ab)(cd)]([ab]!(cd))([ab][cd])<(ab)cd><[ab]cd>(abcde)(!(abcd)e)[(abcd)e](!(abc)de)(!(!(abc)d)e)[(!(abc)d)e]([(abc)d]e)[(abc)de](!(ab)cde)(!(!(ab)cd)e)[(!(ab)cd)e](!(!(ab)c)de)(!(!(!(ab)c)d)e)[(!(!(ab)c)d)e]([(!(ab)c)d]e)[(!(ab)c)de]([(ab)c]de)(!([(ab)c]d)e)[([(ab)c]d)e]([(ab)cd]e)[(ab)cde]([ab]cde)(!([ab]cd)e)[([ab]cd)e](!([ab]c)de)(!(!([ab]c)d)e)[(!([ab]c)d)e]([([ab]c)d]e)[([ab]c)de]([abc]de)(!([abc]d)e)[([abc]d)e]([abcd]e)[abcde](de)(!(d)e)[(d)e]([d]e)[de](!(ab)!(cd)e)(!(!(ab)!(cd))e)[(!(ab)!(cd))e]([(ab)(cd)]e)(![(ab)(cd)]e)[(ab)(cd)e]([ab]!(cd)e)(!([ab]!(cd))e)[([ab]!(cd))e]([ab][cd]e)(!([ab][cd])e)[([ab][cd])e](e)[e](e)[e](<(ab)cd>e)(!<(ab)cd>e)[<(ab)cd>e](<[ab]cd>e)[<[ab]cd>e](!(abc)!(de))[(abc)(de)](!(!(ab)c)!(de))[(!(ab)c)(de)]([(ab)c]!(de))(!([ab]c)!(de))[([ab]c)(de)]([abc]!(de))(!(de))[(de)](!(abc)[de])(!(!(ab)c)[de])([(ab)c][de])(!([ab]c)[de])([abc][de])([de])><(ab)c(de)><(ab)c[de]><[ab]c(de)><[ab]c[de]><(ab)(cd)e><[ab](cd)e><[ab][cd]e><(abc)de><(!(ab)c)de><[(ab)c]de><([ab]c)de><[abc]de><de>(abcdef)(!(abcde)f)[(abcde)f](!(abcd)ef)(!(!(abcd)e)f)[(!(abcd)e)f]([(abcd)e]f)[(abcd)ef](!(abc)def)(!(!(abc)de)f)[(!(abc)de)f](!(!(abc)d)ef)(!(!(!(abc)d)e)f)[(!(!(abc)d)e)f]([(!(abc)d)e]f)[(!(abc)d)ef]([(abc)d]ef)(!([(abc)d]e)f)[([(abc)d]e)f]([(abc)de]f)[(abc)def](!(ab)cdef)(!(!(ab)cde)f)[(!(ab)cde)f](!(!(ab)cd)ef)(!(!(!(ab)cd)e)f)[(!(!(ab)cd)e)f]([(!(ab)cd)e]f)[(!(ab)cd)ef](!(!(ab)c)def)(!(!(!(ab)c)de)f)[(!(!(ab)c)de)f](!(!(!(ab)c)d)ef)(!(!(!(!(ab)c)d)e)f)[(!(!(!(ab)c)d)e)f]([(!(!(ab)c)d)e]f)[(!(!(ab)c)d)ef]([(!(ab)c)d]ef)(!([(!(ab)c)d]e)f)[([(!(ab)c)d]e)f]([(!(ab)c)de]f)[(!(ab)c)def]([(ab)c]def)(!([(ab)c]de)f)[([(ab)c]de)f](!([(ab)c]d)ef)(!(!([(ab)c]d)e)f)[(!([(ab)c]d)e)f]([([(ab)c]d)e]f)[([(ab)c]d)ef]([(ab)cd]ef)(!([(ab)cd]e)f)[([(ab)cd]e)f]([(ab)cde]f)[(ab)cdef]([ab]cdef)(!([ab]cde)f)[([ab]cde)f](!([ab]cd)ef)(!(!([ab]cd)e)f)[(!([ab]cd)e)f]([([ab]cd)e]f)[([ab]cd)ef](!([ab]c)def)(!(!([ab]c)de)f)[(!([ab]c)de)f](!(!([ab]c)d)ef)(!(!(!([ab]c)d)e)f)[(!(!([ab]c)d)e)f]([(!([ab]c)d)e]f)[(!([ab]c)d)ef]([([ab]c)d]ef)(!([([ab]c)d]e)f)[([([ab]c)d]e)f]([([ab]c)de]f)[([ab]c)def]([abc]def)(!([abc]de)f)[([abc]de)f](!([abc]d)ef)(!(!([abc]d)e)f)[(!([abc]d)e)f]([([abc]d)e]f)[([abc]d)ef]([abcd]ef)(!([abcd]e)f)[([abcd]e)f]([abcde]f)[abcdef](def)(!(de)f)[(de)f](!(d)ef)(!(!(d)e)f)[(!(d)e)f]([(d)e]f)[(d)ef]([d]ef)(!([d]e)f)[([d]e)f]([de]f)[def](!(ab)!(cd)ef)(!(!(ab)!(cd)e)f)[(!(ab)!(cd)e)f](!(!(ab)!(cd))ef)(!(!(!(ab)!(cd))e)f)[(!(!(ab)!(cd))e)f]([(!(ab)!(cd))e]f)[(!(ab)!(cd))ef]([(ab)(cd)]ef)(!([(ab)(cd)]e)f)[([(ab)(cd)]e)f](![(ab)(cd)]ef)(!(![(ab)(cd)]e)f)[(![(ab)(cd)]e)f]([(ab)(cd)e]f)[(ab)(cd)ef]([ab]!(cd)ef)(!([ab]!(cd)e)f)[([ab]!(cd)e)f](!([ab]!(cd))ef)(!(!([ab]!(cd))e)f)[(!([ab]!(cd))e)f]([([ab]!(cd))e]f)[([ab]!(cd))ef]([ab][cd]ef)(!([ab][cd]e)f)[([ab][cd]e)f](!([ab][cd])ef)(!(!([ab][cd])e)f)[(!([ab][cd])e)f]([([ab][cd])e]f)[([ab][cd])ef](ef)(!(e)f)[(e)f]([e]f)[ef](ef)(!(e)f)[(e)f]([e]f)[ef](<(ab)cd>ef)(!(<(ab)cd>e)f)[(<(ab)cd>e)f](!<(ab)cd>ef)(!(!<(ab)cd>e)f)[(!<(ab)cd>e)f]([<(ab)cd>e]f)[<(ab)cd>ef](<[ab]cd>ef)(!(<[ab]cd>e)f)[(<[ab]cd>e)f]([<[ab]cd>e]f)[<[ab]cd>ef](!(abc)!(de)f)(!(!(abc)!(de))f)[(!(abc)!(de))f]([(abc)(de)]f)(![(abc)(de)]f)[(abc)(de)f](!(!(ab)c)!(de)f)(!(!(!(ab)c)!(de))f)[(!(!(ab)c)!(de))f]([(!(ab)c)(de)]f)(![(!(ab)c)(de)]f)[(!(ab)c)(de)f]([(ab)c]!(de)f)(!([(ab)c]!(de))f)[([(ab)c]!(de))f](!([ab]c)!(de)f)(!(!([ab]c)!(de))f)[(!([ab]c)!(de))f]([([ab]c)(de)]f)(![([ab]c)(de)]f)[([ab]c)(de)f]([abc]!(de)f)(!([abc]!(de))f)[([abc]!(de))f](!(de)f)(!(!(de))f)[(!(de))f]([(de)]f)[(de)f](!(abc)[de]f)(!(!(abc)[de])f)[(!(abc)[de])f](!(!(ab)c)[de]f)(!(!(!(ab)c)[de])f)[(!(!(ab)c)[de])f]([(ab)c][de]f)(!([(ab)c][de])f)[([(ab)c][de])f](!([ab]c)[de]f)(!(!([ab]c)[de])f)[(!([ab]c)[de])f]([abc][de]f)(!([abc][de])f)[([abc][de])f]([de]f)(!([de])f)[([de])f](f)[f](f)[f](f)[f](f)[f](f)[f](>f)[>f](f)(!f)[f](f)[f](<(ab)c(de)>f)(!<(ab)c(de)>f)[<(ab)c(de)>f](<(ab)c[de]>f)(!<(ab)c[de]>f)[<(ab)c[de]>f](<[ab]c(de)>f)[<[ab]c(de)>f](<[ab]c[de]>f)[<[ab]c[de]>f](<(ab)(cd)e>f)(!<(ab)(cd)e>f)[<(ab)(cd)e>f](f)[f](<[ab](cd)e>f)(!<[ab](cd)e>f)[<[ab](cd)e>f](<[ab][cd]e>f)[<[ab][cd]e>f](<(abc)de>f)(!<(abc)de>f)[<(abc)de>f](<(!(ab)c)de>f)(!<(!(ab)c)de>f)[<(!(ab)c)de>f](<[(ab)c]de>f)[<[(ab)c]de>f](<([ab]c)de>f)(!<([ab]c)de>f)[<([ab]c)de>f](<[abc]de>f)[<[abc]de>f](<de>f)[<de>f](!(abcd)!(ef))[(abcd)(ef)](!(!(abc)d)!(ef))[(!(abc)d)(ef)]([(abc)d]!(ef))(!(!(ab)cd)!(ef))[(!(ab)cd)(ef)](!(!(!(ab)c)d)!(ef))[(!(!(ab)c)d)(ef)]([(!(ab)c)d]!(ef))(!([(ab)c]d)!(ef))[([(ab)c]d)(ef)]([(ab)cd]!(ef))(!([ab]cd)!(ef))[([ab]cd)(ef)](!(!([ab]c)d)!(ef))[(!([ab]c)d)(ef)]([([ab]c)d]!(ef))(!([abc]d)!(ef))[([abc]d)(ef)]([abcd]!(ef))(!(d)!(ef))[(d)(ef)]([d]!(ef))(!(ab)!(cd)!(ef))(!(!(ab)!(cd))!(ef))[(!(ab)!(cd))(ef)]([(ab)(cd)]!(ef))(![(ab)(cd)]!(ef))[(ab)(cd)(ef)]([ab]!(cd)!(ef))(!([ab]!(cd))!(ef))[([ab]!(cd))(ef)]([ab][cd]!(ef))(!([ab][cd])!(ef))[([ab][cd])(ef)](!(ef))[(ef)](!(ef))[(ef)](<(ab)cd>!(ef))(!<(ab)cd>!(ef))[<(ab)cd>(ef)](<[ab]cd>!(ef))[<[ab]cd>(ef)](!(abcd)[ef])(!(!(abc)d)[ef])([(abc)d][ef])(!(!(ab)cd)[ef])(!(!(!(ab)c)d)[ef])([(!(ab)c)d][ef])(!([(ab)c]d)[ef])([(ab)cd][ef])(!([ab]cd)[ef])(!(!([ab]c)d)[ef])([([ab]c)d][ef])(!([abc]d)[ef])([abcd][ef])(!(d)[ef])([d][ef])(!(!(ab)!(cd))[ef])([(ab)(cd)][ef])(![(ab)(cd)][ef])(!([ab]!(cd))[ef])([ab][cd][ef])(!([ab][cd])[ef])([ef])([ef])(<(ab)cd>[ef])(!<(ab)cd>[ef])(<[ab]cd>[ef])(!(abc)!(def))[(abc)(def)](!(!(ab)c)!(def))[(!(ab)c)(def)]([(ab)c]!(def))(!([ab]c)!(def))[([ab]c)(def)]([abc]!(def))(!(def))[(def)](!(!(ab)c)!(!(de)f))[(!(ab)c)(!(de)f)]([(ab)c]!(!(de)f))(!([ab]c)!(!(de)f))[([ab]c)(!(de)f)]([abc]!(!(de)f))(!(!(de)f))[(!(de)f)]([(ab)c][(de)f])(!([ab]c)[(de)f])([abc][(de)f])([(de)f])(!([ab]c)!([de]f))[([ab]c)([de]f)]([abc]!([de]f))(!([de]f))[([de]f)]([abc][def])([def])()[]f)>f]>>>>>(ef)><(ab)c(def)><(ab)c(!(de)f)><(ab)c[(de)f]><(ab)c([de]f)><(ab)c[def]><(ab)c><[ab]c(def)><[ab]c(!(de)f)><[ab]c[(de)f]><[ab]c([de]f)><[ab]c[def]><[ab]c><(ab)(cd)(ef)><(ab)(cd)[ef]><(ab)[cd](ef)><[ab](cd)(ef)><[ab](cd)[ef]><[ab][cd](ef)><[ab][cd][ef]><(abc)d(ef)><(abc)d[ef]><(!(ab)c)d(ef)><(!(ab)c)d[ef]><[(ab)c]d(ef)><[(ab)c]d[ef]><([ab]c)d(ef)><([ab]c)d[ef]><[abc]d(ef)><[abc]d[ef]><d(ef)><d[ef]><(abc)(de)f><(abc)[de]f><(!(ab)c)(de)f><(!(ab)c)[de]f><[(ab)c](de)f><[(ab)c][de]f><([ab]c)(de)f><([ab]c)[de]f><[abc](de)f><[abc][de]f><(de)f><[de]f><(abcd)ef><(!(abc)d)ef><[(abc)d]ef><(!(ab)cd)ef><(!(!(ab)c)d)ef><[(!(ab)c)d]ef><([(ab)c]d)ef><[(ab)cd]ef><([ab]cd)ef><(!([ab]c)d)ef><[([ab]c)d]ef><([abc]d)ef><[abcd]ef><(d)ef><[d]ef><(!(ab)!(cd))ef><[(ab)(cd)]ef><([ab]!(cd))ef><([ab][cd])ef><ef><ef><<(ab)cd>ef><<[ab]cd>ef>Hsh_IntMan_t *Hsh_WrdManHashArrayStart(Vec_Wrd_t *, int)Vec_WrdSize(p->vObjs) == nEntries""""""""DDDDDDDD 00000000Skipping cell %s with %d inputs and %d outputs Skipping cell %s with non-DSD function Gate %5d %-30s : Class %3d Area %10.3f src/map/mpm/mpmGates.ciObjId >= 0Abc_Obj_t *Mpm_ManGetAbcNode(Abc_Ntk_t *, Vec_Int_t *, int)pObj->pData != NULLAbc_Ntk_t *Mpm_ManDeriveMappedAbcNtk(Mpm_Man_t *, Mio_Library_t *)pPars->fMap4GatesAbc_Ntk_t *Mpm_ManPerformCellMapping(Mig_Man_t *, Mpm_Par_t *, Mio_Library_t *)pMio != NULLAbc_Ntk_t *Mpm_ManCellMapping(Gia_Man_t *, Mpm_Par_t *, void *)Genlib library does not match SCL library.nLutSize <= MPM_VAR_MAXsrc/map/mpm/mpmLib.cMpm_LibLut_t *Mpm_LibLutSetSimple(int)>src/map/mpm/mpmMan.cMpm_Man_t *Mpm_ManStart(Mig_Man_t *, Mpm_Par_t *)!pPars->fUseTruth || pPars->pLib->LutMax <= 16!pPars->fUseDsd || pPars->pLib->LutMax <= 6!p->pPars->fUseTruth || !p->pPars->fUseDsdtruths.txtK = %d. C = %d. Cand = %d. XOR = %d. MUX = %d. Choice = %d. CutMin = %d. Truth = %d. DSD = %d. Memory usage: Mig = %.2f MB Map = %.2f MB Cut = %.2f MB Total = %.2f MB. Runtime breakdown: Complete cut computation - Merging cuts - Evaluting cut parameters - Checking cut containment - Adding cuts to storage Other TOTAL nEntryWords > 0 && nEntryWords < (1 << nPageBase)void Mmr_FixedCreate(Mmr_Fixed_t *, int, int)%d : { src/map/mpm/mpmMap.cint Mpm_ObjAddCutToStore(Mpm_Man_t *, Mpm_Cut_t *, int)pUnitNew == (Mpm_Uni_t *)Vec_PtrEntryLast(&p->vFreeUnits)p->nCutStore < p->nNumCutsp->nCutStore > 0 && p->nCutStore <= p->nNumCutsvoid Mpm_ObjTranslateCutsFromStore(Mpm_Man_t *, Mig_Obj_t *)*pList == 0Vec_PtrSize(&p->vFreeUnits) == p->nNumCuts + 1Vec_PtrSize( &p->vFreeUnits ) == p->nNumCuts + 1int Mpm_ManDeriveCuts(Mpm_Man_t *, Mig_Obj_t *)Mpm_ObjCutList(p, pObj) == 0pCut->hNext == 0Arrival time (%d) exceeds required time (%d) at object %d. p->nCutStore > 0!p->fMainRunhCutBest > 0Vec_IntSize(&p->vMigRefs) == Vec_IntSize(&p->pMig->vRefs)void Mpm_ManPerformRound(Mpm_Man_t *)Mig_ManCandNum(p->pMig) == p->pManCuts->nEntriesDel =%5d. Ar =%8d. Edge =%8d. Cut =%10d. Max =%8d. Tru =%8d. Small =%6d. &pUnit->pCut == pCutMpm_Uni_t *Mpm_CutSetupInfo(Mpm_Man_t *, Mpm_Cut_t *, int)pEstRefs[iLeaf] > 0pUnit->mTime <= 0x3FFFFFFFpUnit->mArea <= 0x3FFFFFFFpUnit->mEdge <= 0x3FFFFFFFnWords > 0 && nWords <= p->uMaskint Mmr_StepFetch(Mmr_Step_t *, int)Required > 0void Mpm_ManFinalizeRound(Mpm_Man_t *)void Mpm_ManComputeEstRefs(Mpm_Man_t *)Mig_ObjIsNode(pObj)src/map/mpm/mpmMig.cint Mig_ManSuppSize_rec(Mig_Obj_t *)int Mig_ManSuppSize2_rec(Mig_Man_t *, int)?([%d(%d:%d) %2d, ABC_CONST(), "" }, // %4d src/map/mpm/mpmPre.cword Ifd_ObjTruth_rec(Ifd_Man_t *, int, int *)Vec_WrdSize(p->vTruths) == 0void Ifd_ManTruthAll(Ifd_Man_t *)int Mpm_ComputeCnfSizeOne(word, int, Vec_Int_t *, Vec_Str_t *)Vec_IntSize(p->vClauses) == 0void Mpm_ComputeCnfSizeAll(Ifd_Man_t *)iDsdC != -1 || iDsd0 >= iDsd1int Ifd_ManHashLookup(Ifd_Man_t *, int, int, int, int)iDsdC == -1 || !Abc_LitIsCompl(iDsd1)void Ifd_ManHashInsert(Ifd_Man_t *, int, int, int, int, int)iObj == Vec_IntSize(p->vRes)4 * Vec_IntSize(p->vRes) == Vec_IntSize(p->vArgs)int Ifd_ManHashFindOrAdd(Ifd_Man_t *, int, int, int, int)(int)pObj->Type == Type(int)pObj->nSupp == Ifd_LitSuppSize(p, iDsd0) + Ifd_LitSuppSize(p, iDsd1) + Ifd_LitSuppSize(p, iDsdC)The number of nodes is more than %d iDsd0 > 1 && iDsd1 > 1 && Type >= 1 && Type <= 3int Ifd_ManOper(Ifd_Man_t *, int, int, int, int)iDsdC == -1int Ifd_ManFindDsd_rec(Ifd_Man_t *, char *, char **, int *)**p == '(' && *q == ')'**p == '[' && *q == ']'**p == '<' && *q == '>'pTemp == Temp + 3v < IFM_MAX_STRint *Ifd_ManComputeMatches(char *)nNested < IFM_MAX_VAR*++p == 0int Ifd_ManFindDsd(Ifd_Man_t *, char *)(int)pLeaf0->nSupp == iVec_Wrd_t *Ifd_ManDsdTruths(int)(int)pLeaf1->nSupp == j(int)pLeaf2->nSupp == kVec_Wrd_t *Extra_Truth6AllConfigs2(word, int *, int *, int)Vec_Wrd_t *Extra_Truth6AllConfigs(word, int *, int *, int)%2d %2d %2d int Ifd_ManDsdTest()Vec_WrdSize(vTruths) < (1<<10)(Variant & 1) == 0Runner == Vec_IntSize(vUniques)Vec_WrdSize(vTruthRes) == Counterdsdfuncs%d.datFile "%s" with %d 6-input functions has been written out. int Abc_LitRegular(int)Ifd_Obj_t *Ifd_ManObj(Ifd_Man_t *, int)word Extra_Truth6ChangePhase(word, int)word Extra_Truth6SwapAdjacent(word, int)""""""""DDDDDDDD 00000000UUUUUUUU33333333p->nLutSize <= 6src/map/mpm/mpmTruth.cint Mpm_CutComputeTruth6(Mpm_Man_t *, Mpm_Cut_t *, Mpm_Cut_t *, Mpm_Cut_t *, Mpm_Cut_t *, int, int, int, int)pCut0->pLeaves[k] == pCut->pLeaves[i]void Mpm_TruthStretch(word *, Mpm_Cut_t *, Mpm_Cut_t *, int)k == nSuppSizeint Mpm_CutTruthMinimize6(Mpm_Man_t *, Mpm_Cut_t *)nSuppSize == Abc_TtSupportSize(&t, 6)int Abc_Tt6SupportAndSize(word, int, int *)int Mpm_CutComputeTruth7(Mpm_Man_t *, Mpm_Cut_t *, Mpm_Cut_t *, Mpm_Cut_t *, Mpm_Cut_t *, int, int, int, int)int Mpm_CutTruthMinimize7(Mpm_Man_t *, Mpm_Cut_t *)nSuppSize == Abc_TtSupportSize(p->Truth, Mpm_CutLeafNum(pCut))""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333UUUUUUUU33333333p1->nSize == p2->nSizesrc/misc/extra/extraUtilBitMatrix.cint Extra_BitMatrixIsDisjoint(Extra_BitMat_t *, Extra_BitMat_t *)nVarsMax <= 6src/misc/extra/extraUtilCanon.cint Extra_TruthCanonFastN(int, int, unsigned int *, unsigned int **, char **)nVarsReal <= nVarsMax%3d */ { %2d, nf0 == nf1int Extra_TruthCanonN_rec(int, unsigned char *, unsigned int **, char **, int)RetValue == Countersrc/misc/extra/extraUtilCube.cvoid Abc_EnumerateCubeStates2()Iter %2d -> %8d Did not converge.          Enumerating states of 2x2x2 cube.src/misc/extra/extraUtilDsd.cvoid Sdm_ManPrecomputePerms(Sdm_Man_t *)uMask > 1int Sdm_ManComputeFunc(Sdm_Man_t *, int, int, int *, int, int)iDsdLit0 < DSD_CLASS_NUM * 2iDsdLit1 < DSD_CLASS_NUM * 2pCut[0] <= 6iClass < DSD_CLASS_NUMnCosts == DSD_CLASS_NUMvoid Sdm_ManReadCnfCosts(Sdm_Man_t *, int *, int) (""""""""DDDDDDDD 00000000Decomposition exits.UU1-1-1-1-1-1--11-1-1-1--11-1--1-1-11-1-1--11--11--11-1--1-11--1-11--11-1-1--1-11-1--11--11--1-1-1-1-11-1--1-1-11--1-11--1-1-1-1-11-1---1---1-1----1--1-1-----1-1-1------11--1--1---1--1---1--1--1----1-1--1-----11---1-1---1---1--1--1---1---1-1---1----11----11---1----1-1--1----1--1-1----1---1-11---1----11----1---11-----1--11------1-1-1--1----1-1---1---1-1----1--1-1-----1-1--1-1----1--1--1---1--1---1--1--1----1-1---11----1---1-1---1---1--1--1---1---12*i < Vec_IntSize(vGates)src/misc/extra/extraUtilEnum.cvoid Abc_EnumPrint(Vec_Int_t *, int, int)nMints == 16 || nMints == 32void Abc_EnumerateFunctions(int)Vec_IntSize(vTruths) == nVarsTrying %d + %d + 1 = %d Found function %d with %d gates: Finished %d gates. Truths = %10d. p->nTops == 1void Abc_EnumerateFuncs_rec(Abc_EnuMan_t *, int, int)p->nTops > 0 && p->nTops <= p->nNodeMax - n + 1nRefedFans >= 0Level == Abc_MaxInt(p->pLevel[i], p->pLevel[k])n == p->nNodesThe gate count %d is not enough to have functions with %d inputs. nVars >= 2 && nVars <= 6void Abc_EnumerateFuncs(int, int, int)nGates > 0 && nVars + nGates < ABC_ENUM_MAXp->nNodes == nVarsp->nTops == nVarsVars = %d. Gates = %d. Tries = %u. Builds = %u. Finished = %d. %c=%c+%c %c=%s%c%s%cint Abc_EnumerateFilter(Abc_EnuMan_t *)i < p->nNodesvoid Abc_EnumRefNode(Abc_EnuMan_t *, int)p->pRefs[i] >= 0void Abc_EnumRef(Abc_EnuMan_t *, int)void Abc_EnumDerefNode(Abc_EnuMan_t *, int)void Abc_EnumDeref(Abc_EnuMan_t *, int)`ir{'2=HS^it$/:E)4?JU`kvstrlen(pBase) + strlen(pSuffix) < 500src/misc/extra/extraUtilFile.cchar *Extra_FileNameAppend(char *, char *)strlen(pBase) + strlen(pSuffix) < 1000char *Extra_FileNameGenericAppend(char *, char *)Extra_FileCheck(): File "%s" does not exist. Extra_FileCheck(): File "%s" is empty. unsigned int Extra_ReadBinary(char *)int Extra_ReadHex(unsigned int *, char *, int)Extra_FileSort(): Cannot open file "%s". Extra_FileSort(): Cannot read contents of file "%s". The file after sorting is "%s". Extra_FileLineNumAdd(): Cannot open file "%s". %03d %cThe resulting file is "%s". Extra_FileSize(): The file is unavailable (absent or open).-Bound <= n && n < Boundsrc/misc/extra/extraUtilMacc.cvoid Macc_ConstMultSpecOne2(FILE *, int, int, int)// %d-bit multiplier-accumulator with constant %d generated by ABC on %s module mulacc%03d%s ( _neg_pos input [%d:0] i, input [%d:0] s, output [%d:0] o wire [%d:0] c = %d'h%x; wire [%d:0] m = i * c; assign o = s %c m; void Macc_ConstMultSpecOne(FILE *, int, int, int)// %d-bit multiplier by %d-bit constant %d generated by ABC module mul%03d%s ( wire [%d:0] I = {{%d{i[%d]}}, i}; wire [%d:0] m = I * c; wire [%d:0] t = %cm; assign o = t[%d:%d]; const_mul//macc_spec_%03d.vGenerating numbers using %d adders: %d = %d << %d %d = %d + %d %d = %d - %d -%d = ~%d + 1 wire [%d:0] N1 = -n1; wire [%d:0] %c%d = %c%d << %d; wire [%d:0] %c%d = n%d %c n%d; wire [%d:0] N%d = -n%d; void Macc_ConstMultGenMult(FILE *, unsigned int *, int, int, int) assign o = %d'h0; wire [%d:0] n1 = {{%d{i[%d]}}, i}; assign o = %c%d[%d:%d]; void Macc_ConstMultGenMacc(FILE *, unsigned int *, int, int, int)// %d-bit multiplier-accumulator by %d-bit constant %d generated by ABC module macc%03d%s ( input [%d:0] c, assign o = c; wire [%d:0] s = %c%d[%d:%d]; assign o = s + c; void Macc_ConstMultGenMacc2(FILE *, unsigned int *, int, int, int)// %d-bit multiplier-accumulator by constant %d generated by ABC on %s assign o = s; wire [%d:0] n1 = i; assign o = s + %c%d; const_mul//macc%03d.vAdding one incrementor:Node %6d : %s Pred = %6d Vars = %d Nodes = %d History = %d%d Profile: src/misc/extra/extraUtilMaj.cGem_Man_t *Gem_ManAlloc(int, int)Originalp->nObjs == p->nObjsAllocvoid Gem_ManRealloc(Gem_Man_t *)Extending object storage: %d -> %d. int Gem_GroupVarRemove(int, int)i+1 >= 0int Gem_GroupVarsInsert1(int, int, int)!fGroup || i == -1 || ((Groups >> i) & 1)fGroup == 0 || fGroup == 1int Gem_GroupVarsInsert3(int, int)i == -1 || (Groups >> i) & 1nGroups >= 0int Gem_FuncFindPlace(word *, int, int, word *, int)i < (int)pObj->nVarsvoid Gem_FuncExpand(Gem_Man_t *, int, int)(int)pObj->nVars + 2 <= p->nVarsv == (int)pObj->nVars-1iFunc == p->nObjsExpand Found symmetric %d-variable function: This is majority-%d. i < j && j < 16int Gem_FuncReduce(Gem_Man_t *, int, int, int)v == (int)pObj->nVars-2CrossbarExpanding var %2d (functions = %10d) Connecting var %2d (functions = %10d) Finished (functions = %10d) i < nVars && j < nVarsint Abc_TtVarsAreSymmetric(word *, int, int, int, word *, word *)""""""""DDDDDDDD 00000000UUUUUUUU33333333Hard limit on the number of nodes (0x7FFFFFFF) is reached. Quitting...Fixed memory manager: Entry = %5d. Chunk = %5d. Chunks used = %5d. Entries used = %8d. Entries peak = %8d. Memory used = %8d. Memory alloc = %8d. p->pEntriesFree == NULLsrc/misc/extra/extraUtilMemory.cchar *Extra_MmFixedEntryFetch(Extra_MmFixed_t *)Flexible memory manager: Chunk size = %d. Chunks used = %d. Entries used = %d. Memory used = %d. Memory alloc = %d. p->pCurrent + nBytes <= p->pEndchar *Extra_MmFlexEntryFetch(Extra_MmFlex_t *, int)9B.?  @ @ @ @    @@@@@@@@     Degree >= 0src/misc/extra/extraUtilMisc.cdouble Extra_Power2(int)nDigits < 100int *Extra_DeriveRadixCode(int, int, int)Number == 0unsigned int Extra_TruthPermute(unsigned int, char *, int, int)unsigned int Extra_TruthPolarize(unsigned int, int, int)uTruth > uCanons[uTruth]void Extra_Truth4VarNPN(unsigned short **, char **, char **, unsigned char **)uCanons[uPerm] == uTruthnClasses == 222uTruth32 > uCanons[uTruth]void Extra_Truth3VarN(unsigned int **, char ***, char **)uCanons[uPhase] == uTruth32void Extra_Truth4VarN(unsigned short **, char ***, char **, int)uCanons[uPhase] == uTruthnCols > 0 && nRows > 0 && Size > 0void **Extra_ArrayAlloc(int, int, int)Phase >= 0 && Phase < 16unsigned short Extra_TruthPerm4One(unsigned int, int)Phase >= 0 && Phase < 32unsigned int Extra_TruthPerm5One(unsigned int, int)Phase >= 0 && Phase < 64void Extra_TruthPerm6One(unsigned int *, int, unsigned int *)uPhase > 0 && uPhase < (unsigned)(1 << nVars)void Extra_TruthExpand(int, int, unsigned int *, unsigned int, unsigned int *)nSize < 1000void Extra_BubbleSort(int *, int *, int, int) %d%s %d, -%d, {%s %diOne + iZero == 8void Extra_TruthExpandGeneratePermTable() }%s // b == (1<nObjs == nVars + 1src/misc/extra/extraUtilMult.cAbc_BddMan *Abc_BddManAlloc(int, int)BDD stats: Var = %d Obj = %d Alloc = %d Hit = %d Miss = %d BDD %d = int Abc_BddUniqueCreate(Abc_BddMan *, int, int, int)Var < Abc_BddVar(p, Then)Var < Abc_BddVar(p, Else)Aborting because the number of nodes exceeded %d. int Abc_BddUniqueCreateInt(Abc_BddMan *, int, int, int)!Abc_LitIsCompl(Else)Res >= 0int Abc_BddCacheInsert(Abc_BddMan *, int, int, int)testpath.aigsrc/misc/extra/extraUtilPath.cvoid Abc_GraphPathPrint4(int *, Vec_Int_t *)void Abc_GraphPathPrint5(int *, Vec_Int_t *)pathsgrid_%dx%d_e%03d.aigFinished dumping AIG into file "%s". pNodes[0] < pNodes[1]int Abc_GraphBuildState(Vec_Int_t *, int, int, Vec_Int_t *, Vec_Int_t *, Vec_Wec_t *, int *, Vec_Int_t *, int)Edge = %d. Arc = %d. Current state: Node != pNodes[n]Next state: Processing edge %d = {%d %d} Frontier: Return value = %d States = %8d Paths = %24.0f void Abc_GraphSolve(Gia_Man_t *)Vars = %d Iters = %d Ave = %.0f Total = %.0f Estimate = %.0f Q ================================= p->nObjs == nVars + 2src/misc/extra/extraUtilPerm.cAbc_ZddMan *Abc_ZddManAlloc(int, int)2 * p->nVars == nPermSize * (nPermSize - 1)void Abc_ZddManCreatePerms(Abc_ZddMan *, int)p->nPermSize == 0v == p->nVarsZDD stats: Var = %d Obj = %d Alloc = %d Hit = %d Miss = %d int Abc_ZddPerm(Abc_ZddMan *, int, int)Ai < Aj && Bi < Bj && Ai <= Bip->pV2TI[VarPerm] > p->pV2TI[VarTop]Abc_ZddObjVar(p, r1) > VarTop %2dEmpty set(%d %d)i == pPerm[i]int Abc_ZddPerm2Comb(int *, int, int *)p->nPermSize <= 24void Abc_ZddPrint_rec(Abc_ZddMan *, int, int *, int)Nodes = %d. Path = %d. Paths = %d. Shared nodes = %d. Perm %d: Iter %2d -> %8d Nodes = %7d Used = %10d nSize == 9void Abc_EnumerateCubeStatesZdd()int Abc_ZddUniqueCreate(Abc_ZddMan *, int, int, int)Var < Abc_ZddObjVar(p, True)Var < Abc_ZddObjVar(p, False)int Abc_ZddCacheInsert(Abc_ZddMan *, int, int, int, int)int Abc_ZddVarIJ(Abc_ZddMan *, int, int)Resulting set:              Resulting set of permutations:S@@}б}`}}Extra_FileReaderAlloc(): Cannot open input file "%s". iToken >= 0 && iToken < p->vTokens->nSizesrc/misc/extra/extraUtilReader.cint Extra_FileReaderGetLineNumber(Extra_FileReader_t *, int)Extra_FileReader failed to parse the file "%s". void *Extra_FileReaderGetTokens_int(Extra_FileReader_t *)void Extra_FileReaderReload(Extra_FileReader_t *)The total of %d pairs fail verification. %2d : %6d %6.2f %% nVars < 100src/misc/extra/extraUtilSupp.cvoid Abc_SuppTest(int, int, int, int, int)M = %2d N = %2d : K = %6d Total = %12.0f Distinct = %8d Solution with %d variables found. Covering timeINPUT F-COVERCannot find beginning of cube cover (%s). ,The number of inputs (%d) is too high. The number of inputs (%d) does not match declaration (%d). Strange literal representation (%s) of cube %d. The number of cubes (%d) does not match declaration (%d). Successfully parsed function with %d inputs and %d cubes. pStore == Vec_WrdLimit(vPairs)Vec_Wrd_t *Abc_SuppDiffMatrix(Vec_Wrd_t *)Successfully generated diff matrix with %10d rows (%6.2f %%). Vec_WecLevelSize(pS, iVar) == 0void Abc_SuppRemove(Vec_Wrd_t *, int *, Vec_Wec_t *, Vec_Wec_t *, int, int)%2d : S = %3d D = %3d int Vec_WecLevelSize(Vec_Wec_t *, int)Verification successful.The number of cubes in not in the range [1; 1000000]. DDDDDDDDDDDDDDDD""""""""""""""""k}L}}l}H}~~~~C~ ~' ~ ~ ~ ~~~~~~C~~}~~`~$~'%~$~ %~$~L,~,~,~,~n,~3A~A~mA~A~PA~3333UUUU""""DDDD 0000 %)+/5;=CGIOSYaegkmq %379=KQ[]agou{  #-39;AKQWY_eikw)+57;=GUY[_mqsw %'-?CEIOU]ci  ')/QW]ew #+/=AGIMSU[ey '7EKOQUWamsy!#')3?AQSY]_iq   # % + / 5 C I M O U Y _ k q w   ! 1 9 = I W a c g o u {      # ) - ? G Q W ] e o {   % / 1 A [ _ a m s w      ! + - = ? O U i y !'/5;KWY]kqu}  %)1CGMOSY[gk!%+9=?Qisy{ '-9EGY_cio #)+17AGS_qsy} '-7CEIOW]gim{!/3;EMYkoqu %)+7=ACI_egk} %39=EOUimou #'3A]cw{57;CIMUgqw}13EIQ[y!#-/5?MQik{}#%/17;AGOUYeks '+-3=EKOUs !#59?AKS]ciqu{} %+/=IMOmq 9IKQgu{src/misc/extra/extraUtilTruth.cvoid Extra_TruthSwapAdjacentVars(unsigned int *, unsigned int *, int, int)Start < nVars - 1void Extra_TruthSwapAdjacentVars2(unsigned int *, unsigned int *, int, int)Var == -1void Extra_TruthStretch(unsigned int *, unsigned int *, int, int, unsigned int)void Extra_TruthShrink(unsigned int *, unsigned int *, int, int, unsigned int)int Extra_TruthVarInSupport(unsigned int *, int, int)void Extra_TruthCofactor1(unsigned int *, int, int)void Extra_TruthCofactor0(unsigned int *, int, int)void Extra_TruthExist(unsigned int *, int, int)void Extra_TruthForall(unsigned int *, int, int)void Extra_TruthMux(unsigned int *, unsigned int *, unsigned int *, int, int)nVars <= 9int Extra_TruthVarsSymm(unsigned int *, int, int, int)int Extra_TruthVarsAntiSymm(unsigned int *, int, int, int)void Extra_TruthChangePhase(unsigned int *, int, int)int Extra_TruthMinCofSuppOverlap(unsigned int *, int, int *)nWords <= 1024unsigned int Extra_TruthHash(unsigned int *, int)%s: unknown option %c %s: %c requires an argument %ld.%02ld sec out of memory allocating %u bytes src/misc/extra/extraUtilUtil.cvoid Extra_UtilMMout_Of_Memory(long)src/misc/mvc/mvcCompare.cint Mvc_CubeCompareIntOutsideAndUnderMask(Mvc_Cube_t *, Mvc_Cube_t *, Mvc_Cube_t *)pCube->pNext == NULLsrc/misc/mvc/mvcContain.cvoid Mvc_CoverRemoveDuplicates(Mvc_Cover_t *)void Mvc_CoverRemoveContained(Mvc_Cover_t *)pCover->nWords >= 0src/misc/mvc/mvcCube.cMvc_Cube_t *Mvc_CubeAlloc(Mvc_Cover_t *)pCube->iLast == 0 || ((int)pCube->iLast) == pCover->nWords - 1void Mvc_CubeFree(Mvc_Cover_t *, Mvc_Cube_t *)((int)pCube->nUnused) == pCover->nUnusediCubeD < nCubesDsrc/misc/mvc/mvcDivide.cvoid Mvc_CoverDivideInternal(Mvc_Cover_t *, Mvc_Cover_t *, Mvc_Cover_t **, Mvc_Cover_t **)pGroups[g]+iCubeC < nCubesCnCubes == nCubesCMvc_CoverReadCubeNum(pDiv) == 1void Mvc_CoverDivideByCube(Mvc_Cover_t *, Mvc_Cover_t *, Mvc_Cover_t **, Mvc_Cover_t **)void Mvc_CoverDivideByLiteral(Mvc_Cover_t *, Mvc_Cover_t *, Mvc_Cover_t **, Mvc_Cover_t **)void Mvc_CoverDivideByLiteralQuo(Mvc_Cover_t *, int)Mvc_CoverReadCubeNum(pKernel)src/misc/mvc/mvcDivisor.cMvc_Cover_t *Mvc_CoverDivisor(Mvc_Cover_t *)Mvc_CubeReadNext(pCube) == NULLsrc/misc/mvc/mvcList.cvoid Mvc_ListDeleteCube_(Mvc_List_t *, Mvc_Cube_t *, Mvc_Cube_t *)void Mvc_CoverDeleteCube_(Mvc_Cover_t *, Mvc_Cube_t *, Mvc_Cube_t *)Counter == Mvc_CoverReadCubeNum(pCover)void Mvc_CoverList2Array(Mvc_Cover_t *)pCover->pCubesvoid Mvc_CoverArray2List(Mvc_Cover_t *)Mvc_CoverReadCubeNum(pSimple) == 1src/misc/mvc/mvcLits.cMvc_Cover_t *Mvc_CoverBestLiteralCover(Mvc_Cover_t *, Mvc_Cover_t *)pCover1->nBits == pCover2->nBitssrc/misc/mvc/mvcOpAlg.cMvc_Cover_t *Mvc_CoverAlgebraicMultiply(Mvc_Cover_t *, Mvc_Cover_t *)Mvc_Cover_t *Mvc_CoverAlgebraicSubtract(Mvc_Cover_t *, Mvc_Cover_t *)int Mvc_CoverAlgebraicEqual(Mvc_Cover_t *, Mvc_Cover_t *)Mvc_CoverMultiply(): Cover supports are not disjoint!src/misc/mvc/mvcOpBool.cMvc_Cover_t *Mvc_CoverBooleanOr(Mvc_Cover_t *, Mvc_Cover_t *)The cover contains %d cubes (%d bits and %d words) End of cover printoutpCompareFunc( Mvc_CoverReadCubeHead(pCover), Mvc_CoverReadCubeTail(pCover), pMask ) <= 0src/misc/mvc/mvcSort.cvoid Mvc_CoverSort(Mvc_Cover_t *, Mvc_Cube_t *, int (*)(Mvc_Cube_t *, Mvc_Cube_t *, Mvc_Cube_t *))src/misc/mvc/mvcUtils.cint Mvc_CoverCheckSuppContainment(Mvc_Cover_t *, Mvc_Cover_t *)pVarsRem[i] >= 0 && pVarsRem[i] < p->nBitsMvc_Cover_t *Mvc_CoverRemap(Mvc_Cover_t *, int *, int)iValue0 + 1 == iValue1Mvc_Cover_t *Mvc_CoverFlipVar(Mvc_Cover_t *, int, int)Value0 || Value1ValueA0 || ValueA1Mvc_Cover_t *Mvc_CoverUnivQuantify(Mvc_Cover_t *, int, int, int, int)ValueB0 || ValueB1Cube %2d out of %2d contains dirty bits. Mvc_CoverReadCubeNum(pCoverOld) == Mvc_CoverReadCubeNum(pCoverNew)void Mvc_CoverCopyColumn(Mvc_Cover_t *, Mvc_Cover_t *, int, int) modulus > 0src/misc/st/st.cint st__strhash(const char *, int)Gia_ManPoNum(p) > 0src/misc/util/utilBridge.cVec_Str_t *Gia_ManToBridgeVec(Gia_Man_t *)uLit0 != uLit1%.6d%.16dBridgeMode: failed to send package; aborting iBit == pCex->nBitsvoid Gia_ManFromBridgeCex(FILE *, Abc_Cex_t *)int Gia_ManToBridgeResult(FILE *, int, Abc_Cex_t *, int)!(iFan0 & 1)Gia_Man_t *Gia_ManFromBridgeReadBody(int, unsigned char *, Vec_Int_t **)verFairness == 1nFairness == 0nConstraints == 0pBufferEnd == pBuffer(iFan0 & 3) == BRIDGE_VALUE_0temp.aigpar_.dumpGia_ManFromBridgeReadPackage(); Error 2: Something is wrong!Gia_ManFromBridgeReadPackage(); Error 1: Something is wrong!src/misc/util/utilCex.cAbc_Cex_t *Abc_CexMakeTriv(int, int, int, int)Starting frame is more than the last frame of CEX (%d). Stopping frame is more than the last frame of CEX (%d). Starting frame (%d) should be less than stopping frame (%d). Abc_Cex_t *Abc_CexMerge(Abc_Cex_t *, Abc_Cex_t *, int, int)pCex->nPis == pPart->nPisiFrEnd - iFrBeg + pPart->iPo >= pPart->iFrameiBit == pNew->nBitsCEX: Po =%4d Frame =%4d FF = %d PI = %d Bit =%8d 1s =%8d (%5.2f %%) nRealPis <= p->nPisvoid Abc_CexPrintStatsInputs(Abc_Cex_t *, int)CEX: Po =%4d Fr =%4d FF = %d PI = %d Bit =%7d 1 =%8d (%5.2f %%) 1pi =%8d (%5.2f %%) 1ppi =%8d (%5.2f %%)State : Frame %3d : k == p->nBitsvoid Abc_CexPrint(Abc_Cex_t *)p->nPis % nPisOld == 0Abc_Cex_t *Abc_CexTransformPhase(Abc_Cex_t *, int, int, int)p->iPo < nPosNewp->iFrame > 0Abc_Cex_t *Abc_CexTransformTempor(Abc_Cex_t *, int, int, int)iAddPi == nAddPisAbc_Cex_t *Abc_CexTransformUndc(Abc_Cex_t *, char *)Vec_IntSize(vMapOld2New) == p->nPisAbc_Cex_t *Abc_CexPermute(Abc_Cex_t *, Vec_Int_t *)Vec_IntSize(vPermOld) == p->nPisAbc_Cex_t *Abc_CexPermuteTwo(Abc_Cex_t *, Vec_Int_t *, Vec_Int_t *)Vec_IntSize(vPermNew) == p->nPisStopping frame is less than 0.Starting frame is less than 0.The counter example is present but not available (pointer has value "1").The counter example is NULL.Background [1;4%dmForeground [%dm [%d;3%dm[%dm Hi Foreground [%d;3%dm [%d;3%dm[1;4%dm Hi UnderlinedBlinking Inverted Concealed *out_name != NULLsrc/misc/util/utilFile.cint tmpFile(const char *, const char *, char **)%sXXXXXX/dev/nullret[n] == 0char *vnsprintf(const char *, struct __va_list_tag *) @@@@ @@@@ @@@@\mcmjmwmmmmUUUUUUUU33333333puPy`}0Psrc/misc/util/utilIsop.cword Abc_Isop6Cover(word, word, word *, int, word, int *)(uOn & ~uOnDc) == 0(uOn & ~*pRes) == 0 && (*pRes & ~uOnDc) == 0nVars <= ABC_ISOP_MAX_VARvoid Abc_IsopBuildTruth(Vec_Int_t *, int, word *, int, int)int Abc_Isop(word *, int, int, Vec_Int_t *, int)vCover->nSize <= vCover->nCapint Abc_IsopCnf(word *, int, int, int *)Abc_TtHasVar( pFunc, nVars, nVars - 1 )int Abc_IsopCountLits(Vec_Int_t *, int)Constant %d void Abc_IsopPrintCover(Vec_Int_t *, int, int)word Abc_Esop6Cover(word, int, word, int *)nVars > 6word Abc_EsopCover(word *, int, word, int *)Abc_TtHasVar( pOn, nVars, nVars - 1 )word Abc_IsopNew(word *, word *, word *, int, word, int *)!Abc_TtIntersect2(pCube, pOffset, nWords)void Abc_IsopTestNew()Cubes = %d. Lits = %d. int Abc_IsopTest(word *, int, Vec_Int_t *)(pOn[0] & ~pOnDc[0]) == 0word Abc_Isop7Cover(word *, word *, word *, word, int *)(pOn[1] & ~pOnDc[1]) == 0(pOn[0] & ~pRes[0]) == 0 && (pRes[0] & ~pOnDc[0]) == 0(pOn[1] & ~pRes[1]) == 0 && (pRes[1] & ~pOnDc[1]) == 0(pOn[0] & ~pRes[0]) == 0 && (pOn[1] & ~pRes[1]) == 0 && (pOn[2] & ~pRes[2]) == 0 && (pOn[3] & ~pRes[3]) == 0word Abc_Isop8Cover(word *, word *, word *, word, int *)(pRes[0] & ~pOnDc[0])==0 && (pRes[1] & ~pOnDc[1])==0 && (pRes[2] & ~pOnDc[2])==0 && (pRes[3] & ~pOnDc[3])==0(pOn[c] & ~pRes[c] ) == 0 && (pRes[c] & ~pOnDc[c]) == 0word Abc_Isop9Cover(word *, word *, word *, word, int *)word Abc_Isop10Cover(word *, word *, word *, word, int *)word Abc_Isop11Cover(word *, word *, word *, word, int *)word Abc_Isop12Cover(word *, word *, word *, word, int *)word Abc_Isop13Cover(word *, word *, word *, word, int *)word Abc_Isop14Cover(word *, word *, word *, word, int *)word Abc_Isop15Cover(word *, word *, word *, word, int *)word Abc_Isop16Cover(word *, word *, word *, word, int *)Count node open file %s %8d = %s src/misc/util/utilNam.cvoid Abc_NamStrHashResize(Abc_Nam_t *)*piPlace == 0Vec_IntSize( &p->vInt2Handle ) == ii < (int)strlen(pStr)int Abc_NamStrFindOrAdd(Abc_Nam_t *, char *, int *)pStr < pLimint Abc_NamStrFindOrAddLim(Abc_Nam_t *, char *, char *, int *)int Abc_NamStrFindOrAddF(Abc_Nam_t *, const char *, ...)Entry > 0 && Entry < Abc_NamObjNumMax(p1)int Abc_NamReportCommon(Vec_Int_t *, Abc_Nam_t *, Abc_Nam_t *)char *Abc_NamReportUnique(Vec_Int_t *, Abc_Nam_t *, Abc_Nam_t *)*pStrint *Abc_NamStrHashFind(Abc_Nam_t *, const char *, const char *)EQGyU)] C k 1 g # ]  a  = WCg!i Y 7yEm!k)_=u#{7qQ!QAsE5c/Kg{pOut - pOutBeg == nEntriessrc/misc/util/utilSort.cvoid Abc_SortMerge(int *, int *, int *, int *, int *)void Abc_Sort_rec(int *, int *, int *)void Abc_MergeSortCostMerge(int *, int *, int *, int *, int *)void Abc_MergeSortCost_rec(int *, int *, int *)void Abc_SortTest()pArray[i-1] <= pArray[i]Old sort(unsigned)pData[i-1] >= (unsigned)pData[i](unsigned)pData[i-1] <= (unsigned)pData[i]void Abc_QuickSort3(word *, int, int)Prepare Sort newSort oldsrc/misc/nm/nmApi.cchar *Nm_ManStoreIdName(Nm_Man_t *, int, int, char *, char *)n%d_%dNm_ManStoreIdName(): Entry with the same ID already exists.Nm_ManDeleteIdName(): This entry is not in the table.Nm_ManTableLookupId(p, pEntry->ObjId) == NULLsrc/misc/nm/nmTable.cint Nm_ManTableAdd(Nm_Man_t *, Nm_Entry_t *)Nm_ManTableLookupId(p, ObjId) != NULLint Nm_ManTableDelete(Nm_Man_t *, int)*ppSpot == pEntryfRemovedpEntry->pNameSake != pEntry!strcmp(pPrev->Name, pEntry->Name)pPrev->pNextN2I == NULLI2N table: N2I table: void Nm_ManResize(Nm_Man_t *) 5 QfirstIn+i < p->nCossrc/misc/tim/timBox.cvoid Tim_ManCreateBox(Tim_Man_t *, int, int, int, int, int, int)firstOut+i < p->nCis(int)pTable[1] == pBox->nInputsfloat *Tim_ManBoxDelayTable(Tim_Man_t *, int)(int)pTable[2] == pBox->nOutputsiCiNum >= 0 && iCiNum < Tim_ManCiNum(p)int Tim_ManBoxFindFromCiNum(Tim_Man_t *, int)(int)pDelayTable[0] == isrc/misc/tim/timDump.cVec_Str_t *Tim_ManSave(Tim_Man_t *, int)VerNum == TIM_DUMP_VER_NUMTim_Man_t *Tim_ManLoad(Vec_Str_t *, int)pMan->vBoxes == NULLcurPi == nCiscurPo == nCospMan->vDelayTables == NULLTableId == iVec_PtrSize(pMan->vDelayTables) == TableIdTim_ManDelayTableNum(pMan) == nTablesVec_StrSize(p) == iStri == (int)pDelayTable[0]src/misc/tim/timMan.cTim_Man_t *Tim_ManDup(Tim_Man_t *, int)Vec_PtrEntry(pNew->vDelayTables, i) == NULLVec_IntSize(vBoxPres) == Tim_ManBoxNum(p)Tim_Man_t *Tim_ManTrim(Tim_Man_t *, Vec_Int_t *)nNewCis < Tim_ManCiNum(p)nNewCos < Tim_ManCoNum(p)curPi == Tim_ManCiNum(pNew)curPo == Tim_ManCoNum(pNew)Vec_IntSize(vBoxesLeft) <= Tim_ManBoxNum(p)Tim_Man_t *Tim_ManReduce(Tim_Man_t *, Vec_Int_t *, int)nNewCis <= Tim_ManCiNum(p) - nTermsDiffnNewCos <= Tim_ManCoNum(p) - nTermsDiffTim_ManBoxNum(pSpec) > Tim_ManBoxNum(pImpl)Vec_Int_t *Tim_ManAlignTwo(Tim_Man_t *, Tim_Man_t *)!Vec_IntEntry(vBoxPres, pBox->iCopy)p->vDelayTables == NULLvoid Tim_ManCreate(Tim_Man_t *, void *, Vec_Flt_t *, Vec_Flt_t *)pBox->iDelayTable >= 0 && pBox->iDelayTable < Vec_PtrSize(pLibBox->vBoxes)pIfBox != NULLpIfBox->nPis == pBox->nInputspIfBox->nPos == pBox->nOutputsVec_FltSize(vInArrs) == Tim_ManPiNum(p)Vec_FltSize(vOutReqs) == Tim_ManPoNum(p)k == Tim_ManPoNum(p)float *Tim_ManGetReqTimes(Tim_Man_t *)PI = %d. CI = %d. PO = %d. CO = %d. Box = %d. All PIs : arrival = %5.3f required = %5.3f PI%5d : arrival = %5.3f required = %5.3f All POs : arrival = %5.3f required = %5.3f PO%5d : arrival = %5.3f required = %5.3f *** Box %5d : I =%4d. O =%4d. I1 =%6d. O1 =%6d. Table =%4d Box inputs : arrival = %5.3f required = %5.3f box-in%4d : arrival = %5.3f required = %5.3f Box outputs : arrival = %5.3f required = %5.3f box-out%3d : arrival = %5.3f required = %5.3f Delay table %d: i == (int)pTable[0]void Tim_ManPrint(Tim_Man_t *)%5.0fHierarchy : PI/CI = %d/%d PO/CO = %d/%d Box = %d delay(AND2) = %d Box %4d Num = %4d Ins = %4d Outs = %4dvoid Tim_ManSetDelayTables(Tim_Man_t *, Vec_Ptr_t *)i < pBox->nInputssrc/misc/tim/timInt.hTim_Obj_t *Tim_ManBoxInput(Tim_Man_t *, Tim_Box_t *, int)i < pBox->nOutputsTim_Obj_t *Tim_ManBoxOutput(Tim_Man_t *, Tim_Box_t *, int)TIMING MANAGER:Warning: Mismatch in delay-table number between the manager and the box.iPi < p->nCissrc/misc/tim/timTime.cvoid Tim_ManInitPiArrival(Tim_Man_t *, int, float)iPo < p->nCosvoid Tim_ManInitPoRequired(Tim_Man_t *, int, float)iCo < p->nCosvoid Tim_ManSetCoArrival(Tim_Man_t *, int, float)!p->fUseTravId || p->pCos[iCo].TravId != p->nTravIdsiCi < p->nCisvoid Tim_ManSetCiRequired(Tim_Man_t *, int, float)!p->fUseTravId || p->pCis[iCi].TravId != p->nTravIdsvoid Tim_ManSetCoRequired(Tim_Man_t *, int, float)!p->fUseTravId || !p->nTravIds || p->pCos[iCo].TravId != p->nTravIdsTim_ManGetCoRequired(): Output required times of output %d the box %d are not up to date! Tim_Obj_t *Tim_ManCi(Tim_Man_t *, int)Tim_Obj_t *Tim_ManCo(Tim_Man_t *, int)Tim_ManGetCiArrival(): Input arrival times of the box are not up to date!src/misc/tim/timTrav.cint Tim_ManIsCiTravIdCurrent(Tim_Man_t *, int)p->fUseTravIdint Tim_ManIsCoTravIdCurrent(Tim_Man_t *, int) %d work, %d block, ratio %5.2f too repetitive; using fallback sorting algorithm bucket sorting ... depth %6d has %6d unresolved strings reconstructing block ... main sort initialise ... qsort [0x%x, 0x%x] done %d this %d %d pointers, %d sorted, %d scanned  (ylE q&TsY ) }$ bzip2/libbzip2: internal error number %d. This is a bug in bzip2/libbzip2, %s. Please report it to me at: jseward@bzip.org. If this happened when you were using some program which uses libbzip2 as a component, you should also report this bug to the author(s) of that program. Please make an effort to report this bug; timely and accurate bug reports eventually lead to higher quality software. Thanks. Julian Seward, 10 December 2007. *** A special note about internal error number 1007 *** Experience suggests that a common cause of i.e. 1007 is unreliable memory or other hardware. The 1007 assertion just happens to cross-check the results of huge numbers of memory reads/writes, and so acts (unintendedly) as a stress test of your memory system. I suggest the following: try compressing the file again, possibly monitoring progress in detail with the -vv flag. * If the error cannot be reproduced, and/or happens at different points in compression, you may have a flaky memory system. Try a memory-test program. I have used Memtest86 (www.memtest86.com). At the time of writing it is free (GPLd). Memtest86 tests memory much more thorougly than your BIOSs power-on test, and may find failures that the BIOS doesn't. * If the error can be repeatably reproduced, this is a bug in bzip2, and I would very much like to hear about it. Please let me know, and, ideally, save a copy of the file causing the problem -- without which I will be unable to investigate it. {0x%08x, 0x%08x} combined CRCs: stored = 0x%08x, computed = 0x%08x1.0.5, 10-Dec-2007SEQUENCE_ERRORPARAM_ERRORMEM_ERRORDATA_ERRORDATA_ERROR_MAGICIO_ERRORUNEXPECTED_EOFOUTBUFF_FULLCONFIG_ERRORſп block %d: crc = 0x%08x, combined CRC = 0x%08x, size = %d final combined CRC = 0x%08x %d in block, %d after MTF & 1-2 coding, %d+2 syms in use initial group %d, [%d .. %d], has %d syms (%4.1f%%) pass %d: size is %d, grp uses are bytes: mapping %d, selectors %d, code lengths %d, codes %d nL2NXft &%(7(!/Jax [%d: huff+mtf rt+rld1.2.5  @ @ @ @0w,aQ mjp5cd2yҗ+L |~-d jHqA}mQDžӃVlkdzbeO\lcc=  n;^iLA`rqg<GK k 5lBɻ@l2u\E Y=ѫ0&:QQaп!#ijV(_ $ |o/LhXa=-fAvq Ҙ*q俟3Ըx4  j-=mld\cQkkbal0eNbl{WٰeP긾|bI-|ӌeLXaMQ:t0AJו=mѤjiCn4Fgи`s-D3_L | jm Zjz  ' }Dңhi]Wbgeq6lknv+ӉZzJgo߹ﾎCՎ`~ѡ8ROggW?K6H+ L J6`zA`Ugn1yiFafo%6hRw G "/&U;( Z+j\1е,[d&cju m ?6grWJz+{8 Ғ |! ӆBhn[&wowGZpj;f\ eibkaElx TN³9a&g`MGiIwn>JjѮZf @;7SŞϲG0º0S$6к)WTg#.zfJah]+o*7 Z-A1b62S-+ldEw}ZVǖAOI OM~-QJ#SpxAaU׮.7׵Y-6]]wll?AZ$ Faw$e]]FD(koipvk19Z* ,  m86F]qTp0ek*1u4yީ%8<ysHj}A<*XOyD~b-OT@#8 Š8L! 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N `Qq1  a! A Y ;y9 i)  I U+u5  e% E ] S}= m-  M S#s3  c# C [ C{; k+  K W@3w7 g' G  _ c? o/ O `Psp0  ` @ X ;x8 h( H T+t4  d$ D \ S|< l,  L R#r2  b" B Z Cz: j*  J V@3v6 f& F  ^ c~> n. N `Qq1  a! A Y ;y9 i)  I U+u5  e% E ] S}= m-  M S#s3  c# C [ C{; k+  K W@3w7 g' G  _ c? o/ O A@!  @a`10  @invalid block typeinvalid stored block lengthstoo many length or distance symbolsinvalid code lengths setinvalid bit length repeatinvalid code -- missing end-of-blockinvalid literal/lengths setinvalid distances setinvalid literal/length codeinvalid distance codeinvalid distance too far backׁׁׁׁP"؁܁݁݁؁ہہففځ #ځY8ځIځyځ}     `Psp0  ` @ X ;x8 h( H T+t4  d$ D \ S|< l,  L R#r2  b" B Z Cz: j*  J V@3v6 f& F  ^ c~> n. N `Qq1  a! A Y ;y9 i)  I U+u5  e% E ] S}= m-  M S#s3  c# C [ C{; k+  K W@3w7 g' G  _ c? o/ O `Psp0  ` @ X ;x8 h( H T+t4  d$ D \ S|< l,  L R#r2  b" B Z Cz: j*  J V@3v6 f& F  ^ c~> n. N `Qq1  a! A Y ;y9 i)  I U+u5  e% E ] S}= m-  M S#s3  c# C [ C{; k+  K W@3w7 g' G  _ c? o/ O A@!  @a`10  @incorrect header checkinvalid window sizeheader crc mismatch inflate 1.2.5 Copyright 1995-2010 Mark Adler  #+3;CScsI !1Aa  0@`@@   L,l\<|B"bR2r J*jZ:zF&fV6vN.n^>~A!aQ1q I)iY9yE%eU5u M-m]=}   S S  3 3  s s    K K  + +  k k     [ [  ; ;  { {     G G  ' '  g g     W W  7 7  w w     O O  / /  o o     _ _  ? ?     @ `P0pH(hX8xD$dT4tC#c             (08@P`p  0@`  0@`need dictionarystream endfile errorstream errorinsufficient memorybuffer errorincompatible versionX)h)~s)~))))~src/misc/mem/mem.cchar *Mem_FixedEntryFetch(Mem_Fixed_t *)char *Mem_FlexEntryFetch(Mem_Flex_t *, int)pBuffer - p->pFileData == p->nFileSizesrc/misc/bbl/bblif.cBbl_Man_t *Bbl_ManReadBinaryBlif(char *)Total objects = %7d. Total nodes = %7d. Unique functions = %7d. Name manager = %5.2f MB Objs manager = %5.2f MB Fncs manager = %5.2f MB Length % (nVars + 3) == 0char *Bbl_ManSortSop(char *, int)nVars == 16 || nCubes == 16 || pFnc->nWords == nWordsint Bbl_ManSopCheckUnique(Bbl_Man_t *, char *, int, int, int)iFunc == (char *)pFnc - p->pFncs->pArrayint Bbl_ManSaveSop(Bbl_Man_t *, char *, int)Attempting to create a combinational input with %d fanins (should be 0). Attempting to create a combinational output with %d fanins (should be 1). Bbl_ManAddFanin(): Cannot add fanin of the combinational input (Id = %d). Bbl_ManAddFanin(): Cannot add fanout of the combinational output (Id = %d). Bbl_ManAddFanin(): Trying to add more fanins to object (Id = %d) than declared (%d). Bbl_ManCheck(): Node %d does not have function specified. Bbl_ManCheck(): CI with %d has function specified. Bbl_ManCheck(): CO with %d has function specified. Bbl_ManCheck(): Object %d has less fanins (%d) than declared (%d). int Bbl_ObjIdOriginal(Bbl_Man_t *, Bbl_Obj_t *)# Test file written by Bbl_ManDumpBlif() in ABC. .inputs %d .outputs %d char *Bbl_ManTruthToSop(unsigned int *, int)pTemp - pResult == nVars + 4pTemp - pResult == nOnes * (nVars + 3) + 1Old SOP: %s New SOP: %s hadder100 1 010 1 001 1 111 1 -11 1 1-1 1 11- 1 hadder.blifhadder.bblifBbl_ManFileSize(): The file is unavailable (absent or open).Bbl_ManSopToTruth(): SOP is represented incorrectly.jjggjggggggggggggggggggjgggggggh&hffggggxhhggggggggggggggggggggggggggggggggggggggggggggfjgPgPgPgPgPgPgPgPgjgjgPgPgjgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgjgfPgPgPgPgPgPgfjgjgjgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgPgjgParse_FormulaParserEqn(): Different number of opening and closing parentheses (). Parse_FormulaParserEqn(): No operation symbol before constant 0. Parse_FormulaParserEqn(): No operation symbol before constant 1. Parse_FormulaParserEqn(): There is no variable before AND, EXOR, or OR. Parse_FormulaParserEqn(): An opening parenthesis follows a var without operation sign. Parse_FormulaParserEqn(): There is no opening parenthesis Parse_FormulaParserEqn(): Unknown operation Parse_FormulaParserEqn(): The negation sign or an opening parenthesis inside the variable name. Parse_FormulaParserEqn(): The parser cannot find var "%s" in the input var list. Parse_FormulaParserEqn(): The variable name "%s" follows another var without operation sign. Parse_FormulaParserEqn(): Something is left in the operation stack Parse_FormulaParserEqn(): Something is left in the function stack Parse_FormulaParserEqn(): The input string is empty Parse_StackFnPush(): Stack size is too small!Parse_StackFnPush(): Trying to extract data from the empty stack!Parse_StackOpPush(): Stack size is too small!Parse_StackOpPush(): Trying to extract data from the empty stack!Node < p->vCutsOld->nSizesrc/opt/cut/cutApi.cCut_Cut_t *Cut_NodeReadCutsOld(Cut_Man_t *, int)Node < p->vCutsTemp->nSizeCut_Cut_t *Cut_NodeReadCutsTemp(Cut_Man_t *, int)Cut_NodeReadCutsNew(p, Node) == NULLvoid Cut_NodeSetTriv(Cut_Man_t *, int)void Cut_NodeTryDroppingCuts(Cut_Man_t *, int)pCut->nLeaves > 0src/opt/cut/cutCut.cvoid Cut_CutPrint(Cut_Cut_t *, int)%d : {%d : %5d %5d %5d %5d %5d Cannot merge5pParams->nVarsMax >= 3 && pParams->nVarsMax <= CUT_SIZE_MAXsrc/opt/cut/cutMan.cCut_Man_t *Cut_ManStart(Cut_Params_t *)Skipping computation of truth table for more than %d inputs. Current cuts = %8d. (Trivial = %d.) Peak cuts = %8d. Total allocated = %8d. Total deallocated = %8d. Cuts filtered = %8d. Nodes saturated = %8d. (Max cuts = %d.) Cuts per node = %8.1f The cut size = %8d bytes. Peak memory = %8.2f MB. Total nodes = %8d. DAG nodes = %8d. Tree nodes = %8d. Nodes w/o cuts = %8d. Mapping delay = %8d. Merge Union FilterMap cut_stats.txt%-20s %6.1f Skipping computation of truth tables for sequential cuts with more than 5 inputs.Cut computation statistics:pCut0->nLeaves >= pCut1->nLeavessrc/opt/cut/cutMerge.cCut_Cut_t *Cut_CutMergeTwo2(Cut_Man_t *, Cut_Cut_t *, Cut_Cut_t *)Count == nNodesCut_Cut_t *Cut_CutMergeTwo(Cut_Man_t *, Cut_Cut_t *, Cut_Cut_t *)Cut_Cut_t *Cut_CutMergeTwo3(Cut_Man_t *, Cut_Cut_t *, Cut_Cut_t *)Cut_Cut_t *Cut_CutMergeTwo4(Cut_Man_t *, Cut_Cut_t *, Cut_Cut_t *)Cut_Cut_t *Cut_CutMergeTwo5(Cut_Man_t *, Cut_Cut_t *, Cut_Cut_t *)src/opt/cut/cutNode.cCut_Cut_t *Cut_NodeComputeCuts(Cut_Man_t *, int, int, int, int, int, int, int)pList0->nLeaves == 1void Cut_NodeDoComputeCuts(Cut_Man_t *, Cut_List_t *, int, int, int, Cut_Cut_t *, Cut_Cut_t *, int, int)pList1->nLeaves == 1pTemp0->nLeaves == (unsigned)Limit && pTemp1->nLeaves == (unsigned)LimitCut_Cut_t *Cut_NodeUnionCuts(Cut_Man_t *, Vec_Int_t *)Cut_NodeReadCutsNew(p, Root) == NULLpTop != NULLCut_Cut_t *Cut_NodeUnionCutsSeq(Cut_Man_t *, Vec_Int_t *, int, int)Cut_NodeReadCutsTemp(p, CutSetNum) == NULLpCut1->nLeaves == 1int Cut_NodeMapping(Cut_Man_t *, Cut_Cut_t *, int, int, int)pCut0->nLeaves == 1pCut->nLeaves > 0 && pCut->nLeaves <= CUT_SIZE_MAXsrc/opt/cut/cutList.hvoid Cut_ListAdd(Cut_List_t *, Cut_Cut_t *)p->pParams->fSeq || pCut->nLeaves > 1int Cut_CutProcessTwo(Cut_Man_t *, Cut_Cut_t *, Cut_Cut_t *, Cut_List_t *)p->vNodeAttrs != NULLppTail == pSuperList->ppTail[a]int Cut_CutFilterOne(Cut_Man_t *, Cut_List_t *, Cut_Cut_t *)pPrev->pNext == pTempint Cut_CutFilterOld(Cut_Man_t *, Cut_Cut_t *, Cut_Cut_t *)******************* These are contained cuts:pMan->pParams->nVarsMax >= 3 && pMan->pParams->nVarsMax <= CUT_SIZE_MAXsrc/opt/cut/cutOracle.cCut_Oracle_t *Cut_OracleStart(Cut_Man_t *)pMan->pParams->fRecordTotal time Vec_PtrEntry( p->vCutsNew, Node ) == NULLvoid Cut_OracleNodeSetTriv(Cut_Oracle_t *, int)pList0 && pList1Cut_Cut_t *Cut_OracleComputeCuts(Cut_Oracle_t *, int, int, int, int, int)Vec_IntEntry(p->vCutPairs, iCutStart) == 0void Cut_OracleTryDroppingCuts(Cut_Oracle_t *, int)i == (int)pCut0->nLeaves && k == (int)pCut1->nLeavesCut_Cut_t *Cut_CutMerge(Cut_Oracle_t *, Cut_Cut_t *, Cut_Cut_t *)Skipping computation of truth table for more than 8 inputs.Cut computation statistics with oracle:aG CvW\gAw KL*LALXLoLLLLLLLM'M>MUMlMMMMMMcells22_daomap_iwls.txtRead %d cells from file "%s". Added %d cells to the table. BASIC: Total = %d. Good = %d. Entry = %d. Cells: Diffs: Equals: VAR %d: Total = %d. Good = %d. Entry = %d. Supp Canoncelllib22.txtFunctions found = %10d. Functions not found = %10d. Library composed of %d functions is written into file "%s". src/opt/cut/cutPre22.cvoid Cut_CellCrossBar(Cut_Cell_t *)Type < 22void Cut_CellTruthElem(unsigned int *, unsigned int *, unsigned int *, unsigned int *, int, int) const 0 const 1 a ab (ab)' a<+>b 0s abc (abc)' 1p a(b+c) (a(b+c))' 2s a<+>b<+>c 3p a<+>bc 4p a(b<+>c) (a(b<+>c))' 5s ab+bc+ac 6s abc+a'b'c' (abc+a'b'c')' 7 ab+bc+a'c 8s a'bc+ab'c+abc' (a'bc+ab'c+abc')' 9p ab'c'+bc (ab'c'+bc)' Box usage:Cut_CellDumpToFile: Cannout open output file.Cut_CellDumpToFile: Cell manager is not defined.Cut_CellTruthLookup: Cell manager is not defined.src/opt/cut/cutSeq.cvoid Cut_NodeComputeCutsSeq(Cut_Man_t *, int, int, int, int, int, int, int, int, int)pCut->nVarsMax < 6src/opt/cut/cutTruth.cvoid Cut_TruthNCanonicize(Cut_Cut_t *)pCut->pLeaves[i] == pCut1->pLeaves[k]unsigned int Cut_TruthPhase(Cut_Cut_t *, Cut_Cut_t *)Div %5d : Best single = %5d.%sDiv %5d : Best double = %5d.%sDiv %5d : Best double = %5d. Best single = %5d.%sDiv %5d : Best double = %5d. Best single = %5d. Best complement = %5d.%sTotal single = %3d. Total double = %3d. Total compl = %3d. Warning: The limit on the number of extracted divisors has been reached.nFanins > 1 && nCubes > 0src/opt/fxu/fxuCreate.cFxu_Matrix *Fxu_CreateMatrix(Fxu_Data_t *)The problem is too large to be solved by "fxu" (%d cubes and %d cube pairs) iCube == nCubesTotaliPair == nPairsStores_pLits[ pOrder[0] ] < s_pLits[ pOrder[nFanins-1] ]Matrix: [vars x cubes] = [%d x %d] Lits = %d Density = %.5f%% 1-cube divs = %6d. (Total = %6d) 2-cube divs = %6d. (Total = %6d)iNum < vInputsNew->nSizevoid Fxu_CreateCoversNode(Fxu_Matrix *, Fxu_Data_t *, int, Fxu_Cube *, Fxu_Cube *)nCubes == Abc_SopGetCubeNum(pSopCover)The total number of variables is more than 1,000,000.The total number of cube pairs of the network is more than 10,000,000.Command "fx" takes a long time to run in such cases. It is suggestedthat the user changes the network by reducing the size of logic node andconsequently the number of cube pairs to be processed by this command.It can be achieved as follows: "st; if -K " or "st; renode -s -K "as a proprocessing step, while selecting as approapriate.The current network does not have SOPs to perform extraction.The contents of the heap: Level %d: Counter == p->pTree[Counter]->HNumsrc/opt/fxu/fxuHeapD.cvoid Fxu_HeapDoublePrint(FILE *, Fxu_HeapDouble *)%2d=%3d End of the heap printout. pDiv->HNum == p->ivoid Fxu_HeapDoubleCheck(Fxu_HeapDouble *)Weight1 >= Weight2void Fxu_HeapDoubleCheckOne(Fxu_HeapDouble *, Fxu_Double *)(pDiv)->HNum >= 1 && (pDiv)->HNum <= p->nItemsAllocvoid Fxu_HeapDoubleUpdate(Fxu_HeapDouble *, Fxu_Double *)void Fxu_HeapDoubleDelete(Fxu_HeapDouble *, Fxu_Double *)src/opt/fxu/fxuHeapS.cvoid Fxu_HeapSinglePrint(FILE *, Fxu_HeapSingle *)pSingle->HNum == p->ivoid Fxu_HeapSingleCheck(Fxu_HeapSingle *)void Fxu_HeapSingleCheckOne(Fxu_HeapSingle *, Fxu_Single *)(pSingle)->HNum >= 1 && (pSingle)->HNum <= p->nItemsAllocvoid Fxu_HeapSingleUpdate(Fxu_HeapSingle *, Fxu_Single *)void Fxu_HeapSingleDelete(Fxu_HeapSingle *, Fxu_Single *)pSpotsrc/opt/fxu/fxuList.cvoid Fxu_ListDoubleAddPairMiddle(Fxu_Double *, Fxu_Pair *, Fxu_Pair *)pSpot != pList->pTailFxu_ListDoubleAddPairPlace() is called!pVar1->iVar < pVar2->iVarsrc/opt/fxu/fxuMatrix.cvoid Fxu_MatrixAddSingle(Fxu_Matrix *, Fxu_Var *, Fxu_Var *, int)\\\Z\h[\Z\\t[Z[[Z$[ %)+/5;=CGIOSYaegkmq %379=KQ[]agou{  #-39;AKQWY_eikw)+57;=GUY[_mqsw %'-?CEIOU]ci  ')/QW]ew #+/=AGIMSU[ey '7EKOQUWamsypLit1 && pLit2src/opt/fxu/fxuPair.cvoid Fxu_PairCanonicize(Fxu_Cube **, Fxu_Cube **)Code == 15int Fxu_PairCompare(Fxu_Pair *, Fxu_Pair *)pCube1->pVar == pCube2->pVarFxu_Pair *Fxu_PairAlloc(Fxu_Matrix *, Fxu_Cube *, Fxu_Cube *)pVar == pPair->pCube2->pVarvoid Fxu_PairAdd(Fxu_Pair *)matrix.txtMatrix has %d vars, %d cubes, %d literals, %d divisors. Divisors selected so far: single = %d, double = %d. The double divisors are: Divisor #%3d (lit=%d,%d) (w=%2d): <%d, %d> (b=%d)The cubes are: Cube #%3d: <%d %d> (d=%d) (b=%d)The single divisors are: Single-cube divisor #%5d: Var1 = %4d. Var2 = %4d. Weight = %2d pDiv->Weight <= WeightMaxsrc/opt/fxu/fxuPrint.cvoid Fxu_MatrixPrintDivisorProfile(FILE *, Fxu_Matrix *)The double divisors profile: Weight < -1 divisors = %6d Weight -1 divisors = %6d Weight %3d divisors = %6d End of divisor profile printout nPairsMax < nPairsTotalsrc/opt/fxu/fxuReduce.cint Fxu_PreprocessCubePairs(Fxu_Matrix *, Vec_Ptr_t *, int, int)iPair == nPairsTotaliPair == nPairsMaxpCubeLast == NULL || pCubeLast->pVar != pVarThe SOPs of the nodes are not SCC-free. Run "bdd; sop" before "fx".The SOPs of the nodes contain duplicated cubes. Run "bdd; sop" before "fx".nVarsC1 > 0src/opt/fxu/fxuSelect.cFxu_Double *Fxu_MatrixFindDouble(Fxu_Matrix *, int *, int *, int, int)nVarsC2 > 0piVarsC1[0] < piVarsC2[0]Coin > 0int Fxu_SelectSCD(Fxu_Matrix *, int, Fxu_Var **, Fxu_Var **)iVar1C < iVar2CFxu_Double *Fxu_MatrixFindComplementSingle(Fxu_Matrix *, Fxu_Single *)nVarsC1 == 1Fxu_Single *Fxu_MatrixFindComplementDouble2(Fxu_Matrix *, Fxu_Double *)nVarsC2 == 1iVar1 < iVar2Vec_PtrSize(vSingles) % 3 == 0src/opt/fxu/fxuSingle.cvoid Fxu_MatrixComputeSingles(Fxu_Matrix *, int, int)void Fxu_MatrixComputeSinglesOne(Fxu_Matrix *, Fxu_Var *)void Fxu_MatrixComputeSinglesOneCollect(Fxu_Matrix *, Fxu_Var *, Vec_Ptr_t *)pDouble->Weight == Fxu_HeapDoubleReadMaxWeight( p->pHeapDouble )src/opt/fxu/fxuUpdate.cvoid Fxu_Update(Fxu_Matrix *, Fxu_Single *, Fxu_Double *)pSingle->Weight == Fxu_HeapSingleReadMaxWeight( p->pHeapSingle )Fxu_SingleCountCoincidence( p, pVar1, pVar2 ) == 0void Fxu_UpdateSingle(Fxu_Matrix *)pCubeUse->pOrder == NULLvoid Fxu_UpdateDoublePairs(Fxu_Matrix *, Fxu_Double *, Fxu_Var *)pCubeUse->lLits.nItems == pPair->nBase + 1pCubeRem->lLits.nItems == 0Fxu_UpdatePairCompare( (Fxu_Pair**)p->vPairs->pArray, (Fxu_Pair**)p->vPairs->pArray + p->vPairs->nSize - 1 ) < 0void Fxu_UpdatePairsSort(Fxu_Matrix *, Fxu_Double *)int Fxu_UpdatePairCompare(Fxu_Pair **, Fxu_Pair **)pDivCur->Weight == pPair->nBase - 1void Fxu_UpdateCleanOldDoubles(Fxu_Matrix *, Fxu_Double *, Fxu_Cube *)pPair->nLits1 == nLits1void Fxu_UpdateMatrixDoubleCreateCubes(Fxu_Matrix *, Fxu_Cube *, Fxu_Cube *, Fxu_Double *)pPair->nLits2 == nLits2pPair->nBase == nBasepLit1->pCube->pOrder == NULLvoid Fxu_UpdateMatrixSingleClean(Fxu_Matrix *, Fxu_Var *, Fxu_Var *, Fxu_Var *)pCube->pOrdervoid Fxu_UpdateAddNewDoubles(Fxu_Matrix *, Fxu_Cube *)Vec_WecSize( pFxchMan->vCubes ) == ( Vec_IntSize( pFxchMan->vOutputID ) / pFxchMan->nSizeOutputID )src/opt/fxch/Fxch.cvoid Fxch_CubesUnGruping(Fxch_Man_t *) [FXCH] Elapsed Time[FXCH] +-> Init[FXCH] +-> ExtrAbc_NtkIsSopLogic( pNtk )int Abc_NtkFxchPerform(Abc_Ntk_t *, int, int, int)QAbc_NtkFxchPerform(): Nodes have duplicated fanins. FXCH is not performed.Abc_NtkFxchPerform(): The network check has failed.iDiv < Vec_FltSize( pFxchMan->vDivWeights )src/opt/fxch/FxchDiv.cint Fxch_DivAdd(Fxch_Man_t *, int, int, int)int Fxch_DivRemove(Fxch_Man_t *, int, int, int)Vec_IntSize( vCube1 ) == 3void Fxch_DivSepareteCubes(Vec_Int_t *, Vec_Int_t *, Vec_Int_t *) Lits =%7d Divs =%8d int Fxch_DivNormalize(Vec_Int_t *)Qsrc/opt/fxch/FxchMan.cvoid Fxch_ManMapLiteralsIntoCubes(Fxch_Man_t *, int)pFxchMan->nVars < nVarsvoid Fxch_ManUpdate(Fxch_Man_t *, int)Fxch_ManGetLit( pFxchMan, iCube0, 0) == Fxch_ManGetLit( pFxchMan, iCube1, 0)Vec_IntSize( pFxchMan->vPairs ) % 2 == 0Vec_IntSize( pFxchMan->vCubesToUpdate )Vec_IntSize( pFxchMan->vSCC ) % 2 == 0Extr =%7d Lit0 < Lit1int Fxch_ManDivSingleCube(Fxch_Man_t *, int, int, int)p->nSize % 2 == 0int Vec_IntUniqifyPairs(Vec_Int_t *)Vec_IntSize( pFxchMan->vLevels ) == iVarNewint Fxch_ManCreateCube(Fxch_Man_t *, int, int)void Fxch_ManExtractDivFromCube(Fxch_Man_t *, const int, const int, const int)RetValue == Vec_IntSize( pFxchMan->vDiv )void Fxch_ManExtractDivFromCubePairs(Fxch_Man_t *, const int)vCubepBin->Cap <= 0xAAAAsrc/opt/fxch/FxchSCHashTable.cint Fxch_SCHashTableInsert(Fxch_SCHashTable_t *, Vec_Wec_t *, uint32_t, uint32_t, uint32_t, uint32_t, char)( iEntry != (int)pBin->Size ) && ( pBin->Size != 0 )int Fxch_SCHashTableRemove(Fxch_SCHashTable_t *, Vec_Wec_t *, uint32_t, uint32_t, uint32_t, uint32_t, char)SubCube Hash Table at %p %20s %20s Memory Usage (MB)%20d %18.2f pNode->uTruth == p->pTable[i]->uTruthsrc/opt/rwr/rwrDec.cvoid Rwr_ManPreprocess(Rwr_Man_t *)p->pMap[pNode->uTruth] < 222pNode->uTruth == (Dec_GraphDeriveTruth(pGraph) & 0xFFFF)!Rwr_IsComplement(pNode)Dec_Graph_t *Rwr_NodePreprocess(Rwr_Man_t *, Rwr_Node_t *)src/opt/rwr/rwrEva.cint Rwr_NodeRewrite(Rwr_Man_t *, Cut_Man_t *, Abc_Obj_t *, int, int, int)!Abc_ObjIsCi(pObj)void Rwr_CutIsBoolean_rec(Abc_Obj_t *, Vec_Ptr_t *, int)void Rwr_CutCountNumNodes_rec(Abc_Obj_t *, Cut_Cut_t *, Vec_Ptr_t *)p->vClasses->nSize == 222void Rwr_ScoresReport(Rwr_Man_t *)CLASS %3d: Subgr = %3d. Total gain = %6d. %2d: S=%5d. A=%5d. G=%6d. nNodesSaved >= nNodesAddedDec_Graph_t *Rwr_CutEvaluate(Rwr_Man_t *, Abc_Obj_t *, Cut_Cut_t *, Vec_Ptr_t *, int, int, int *, int)uTruth < (1<<16)src/opt/rwr/rwrExp.cvoid Rwt_Man4ExploreCount(unsigned int)Number of cuts considered = %8d. Classes occurring at least once = %8d. Occurence = %6d. Num classes = %4d. Occurence = %6d. Num classes = %4d. Repr = npnclass_stats4.txt%d classes written into file "%s". The largest number of occurence = %8d. Counter <= CountMaxvoid Rwt_Man5ExplorePrint()nnclass_stats5.txtThe numbe of NPN classes = %d. Computing NPN classesnpnclass_stats5.txtStarting level %d (at %d nodes). Considered = %5d M. Found = %8d. Classes = %6d. Trying %7d. Total canonical = %4d. Total used = %5d. Total cuts tries = %8d. Bad cuts found = %8d. Total subgraphs = %8d. Used NPN classes = %8d. Nodes rewritten = %8d. Start Cuts Resynthesis Mffc Eval Update Rewriting statistics:src/opt/rwr/rwrPrint.cvoid Rwr_NodePrint_rec(FILE *, Rwr_Node_t *) tt= lev=%d vol=%dgraph_lib.txt Class %3d. Func %6d. Roots = %3d. Vol = %3d. Sum = %3d. npn4_aig_array.txtstatic unsigned short s_RwtAigSubgraphs[] = { }; The number of nodes saved = %d. SavingThe number of classes = %d. Canonical nodes = %d. The number of nodes loaded = %d. LoadingRwr_ManLoadFromFile: Cannot open file "%s". The number of nodes loaded = %d.                 " "! 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Converting to AIGs has failed. The PI count of careset (%d) and logic network (%d) differ. Careset is not used. Performing optimization with %d external care clauses. src/opt/mfs/mfsDiv.cvoid Abc_MfsWinMarkTfi_rec(Abc_Obj_t *, Vec_Ptr_t *)int Abc_MfsNodeDeref_rec(Abc_Obj_t *)int Abc_MfsWinVisitMffc(Abc_Obj_t *)p->vDivs == NULLVec_Ptr_t *Abc_MfsComputeDivisors(Mfs_Man_t *, Abc_Obj_t *, int)UUUUUUUU33333333p->pCnf->pVarNums[pObjPo->Id] >= 0src/opt/mfs/mfsInter.csat_solver *Abc_MfsCreateSolverResub(Mfs_Man_t *, int *, int, int)Vec_IntSize(p->vProjVarsCnf) == Vec_PtrSize(p->vDivs)Vec_IntSize(p->vProjVarsCnf) == Vec_IntSize(p->vProjVarsSat)nFanins == nCandsunsigned int *Abc_NtkMfsInterplateTruth(Mfs_Man_t *, int *, int, int)Hop_Obj_t *Abc_NtkMfsInterplate(Mfs_Man_t *, int *, int)Nodes = %d. Try = %d. Resub = %d. Div = %d. SAT calls = %d. Timeouts = %d. MaxDivs = %d. Attempts : Remove %6d out of %6d (%6.2f %%) Resub %6d out of %6d (%6.2f %%) Reduction: Nodes %6d out of %6d (%6.2f %%) Edges %6d out of %6d (%6.2f %%) Power( %5.2f, %4.2f%%) Swappable edges = %d. Total edges = %d. Ratio = %5.2f. Nodes = %d. Try = %d. Total mints = %d. Local DC mints = %d. Ratio = %5.2f. Nodes resyn = %d. Ratio = %5.2f. Total AIG node gain = %d. Timeouts = %d. WinGiaIntALL333333?Q?>src/opt/mfs/mfsResub.cint Abc_NtkMfsTryResubOnce(Mfs_Man_t *, int *, int)Abc_InfoHasBit(pData, p->nCexes)int Abc_NtkMfsSolveSatResub(Mfs_Man_t *, Abc_Obj_t *, int, int, int)%5d : Lev =%3d. Leaf =%3d. Node =%3d. Divs =%3d. Fanin = %4d (%d/%d), MFFC = %d Node %d: Fanin %d can be removed. nWords <= p->nDivWordsNode %d: Fanin %d can be replaced by divisor %d. Node %d: Cannot find replacement for fanin %d. int Abc_NtkMfsSolveSatResub2(Mfs_Man_t *, Abc_Obj_t *, int, int)iFanin2 >= 0 || iFanin2 == -1Node %5d : Level = %2d. Divs = %3d. Fanins = %d/%d (out of %d). MFFC = %d Node %d: Fanins %d/%d can be removed. %3d: %2d %2d Node %d: Fanins %d/%d can be replaced by divisors %d/%d. Vec_PtrSize(p->vMfsFanins) == nCands + 2/JRetValue == l_Undef || RetValue == l_True || RetValue == l_Falsesrc/opt/mfs/mfsSat.cint Abc_NtkMfsSolveSat_iter(Mfs_Man_t *)!Abc_InfoHasBit(p->uCare, Mint)int Abc_NtkMfsSolveSat(Mfs_Man_t *, Abc_Obj_t *)Node %4d : Care = %2d. Total = %2d. p->nFanins != 1 ?src/opt/mfs/mfsStrash.cvoid Abc_MfsConvertAigToHop_rec(Aig_Obj_t *, Hop_Man_t *)!Hop_IsComplement((Hop_Obj_t *)pObj->pData)Aig_ManCoNum(pMan) == 1Hop_Obj_t *Abc_MfsConvertAigToHop(Aig_Man_t *, Hop_Man_t *)void Abc_MfsConvertHopToAig_rec(Hop_Obj_t *, Aig_Man_t *)src/opt/mfs/mfsWin.cvoid Abc_MfsComputeRoots_rec(Abc_Obj_t *, int, int, Vec_Ptr_t *)Vec_PtrSize(vRoots) > 0Vec_Ptr_t *Abc_MfsComputeRoots(Abc_Obj_t *, int, int)Total symm = %8d. Structural symm = %8d. Total non-sym = %8d. Total var pairs = %8d. Sat runs SAT = %8d. Sat runs UNSAT = %8d. Structural Matrix Counting Fraiging SAT Total func supps = %8d. Total struct supps = %8d. Traversal Vec_Int_t *Vec_VecEntryInt(Vec_Vec_t *, int)src/opt/sim/simSeq.cVec_Ptr_t *Sim_SimulateSeqRandom(Abc_Ntk_t *, int, int)Number of support targets after simulation = %5d. Targets = %5d. Solved = %5d. Fifo = %5d. Targets = %5d. Solved = %5d. Fifo = %5d. SAT runs = %3d. Abc_NodeIsTravIdCurrent(pNode)src/opt/sim/simSupp.cint Sim_ComputeSuppRoundNode(Sim_Man_t *, int, int)!Sim_SuppFunHasVar(p->vSuppFun, Output, iNumCi)RetValue >= 0void Sim_SolveTargetsUsingSat(Sim_Man_t *, int)pModel != NULLSim_SolveSuppModelVerify( p->pNtk, pModel, Input, Output )Total = %8d. Sym = %8d. NonSym = %8d. Remaining = %8d. Sim_UtilMatrsAreDisjoint( p )src/opt/sim/simSym.cint Sim_ComputeTwoVarSymms(Abc_Ntk_t *, int)Extra_BitMatrixIsClique( pMatSym )src/opt/sim/simSymSat.cint Sim_SymmsGetPatternUsingSat(Sym_Man_t *, unsigned int *)int Sim_SymmsSatProveOne(Sym_Man_t *, int, int, int, unsigned int *)nPairsTotal >= nPairsSym + nPairsNonSymsrc/opt/sim/simSymSim.cvoid Sim_SymmsSimulate(Sym_Man_t *, unsigned int *, Vec_Ptr_t *)Abc_NtkCiNum(pNtk) + 10 < (1<<16)src/opt/sim/simSymStr.cvoid Sim_SymmsStructCompute(Abc_Ntk_t *, Vec_Ptr_t *, Vec_Ptr_t *)pMap[pNode1->Id] != pMap[pNode2->Id]void Sim_SymmsAppendFromGroup(Abc_Ntk_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Int_t *, int *)pMap[pNode1->Id] >= 0pMap[pNode2->Id] >= 0Sim_HasBit(pSupport, Ind1) == Sim_HasBit(pSupport, Ind2)void Sim_SymmsTransferToMatrix(Extra_BitMat_t *, Vec_Int_t *, unsigned int *)nSize > 0 && nWords > 0src/opt/sim/simUtils.cVec_Ptr_t *Sim_UtilInfoAlloc(int, int, int)void Sim_UtilSimulateNode(Sim_Man_t *, Abc_Obj_t *, int, int, int)void Sim_UtilSimulateNodeOne(Abc_Obj_t *, Vec_Ptr_t *, int, int)void Sim_UtilTransferNodeOne(Abc_Obj_t *, Vec_Ptr_t *, int, int, int)Output %2d :void Sim_UtilCountPairsAll(Sym_Man_t *)!fForwardOnly || !fBackwardOnlysrc/opt/ret/retArea.cint Abc_NtkRetimeMinArea(Abc_Ntk_t *, int, int, int, int)Abc_NtkLatchNum(pNtk) == Vec_PtrSize(pNtk->vBoxes)Abc_NtkRetimeMinArea(): Network check has failed. Abc_ObjIsLatch(Abc_ObjFanin0(pObj))int Abc_NtkRetimeMinAreaInitValues_rec(Abc_Obj_t *)Abc_Obj_t *Abc_NtkRetimeMinAreaConstructNtk_rec(Abc_Ntk_t *, Abc_Obj_t *)Abc_NtkRetimeMinAreaConstructNtk(): Network check has failed. Abc_ObjIsBo(pLatchOut) && Abc_ObjIsLatch(pLatch) && Abc_ObjIsBi(pLatchIn)void Abc_NtkRetimeMinAreaUpdateLatches(Abc_Ntk_t *, Vec_Ptr_t *, int, int)Abc_ObjFanoutNum(pObj) > 0!Abc_ObjFanin0(pLatchIn)->fMarkA_o1_i15Mode > 0 && Mode < 7src/opt/ret/retCore.cint Abc_NtkRetime(Abc_Ntk_t *, int, int, int, int, int, int, int)Cleanup before retiming removed %d dangling nodes and %d dangling latches. Reduction in area = %3d. Reduction in delay = %3d. int Abc_NtkRetimeDebug(Abc_Ntk_t *)Unknown retiming option.DelayBest == DelayBest2src/opt/ret/retDelay.cint Abc_NtkRetimeMinDelay(Abc_Ntk_t *, Abc_Ntk_t *, int, int, int, int)IterBest == IterBest2%s Iter = %3d. Delay = %3d. Latches = %5d. Delta = %6.2f. Ratio = %4.2f %% FwdBwd%s : Starting delay = %3d. Final delay = %3d. IterBest = %2d (out of %2d). Forward BackwardPerforming analysis:!Abc_ObjFanin0(pLatch)->fMarkAsrc/opt/ret/retFlow.cVec_Ptr_t *Abc_NtkMaxFlow(Abc_Ntk_t *, int, int)L = %6d. %s max-flow = %6d. Min-cut = %6d. Abc_NtkMaxFlow() error! The computed min-cut is not a cut!Abc_NtkRetimeForward(): Network check has failed. _o2_i2pLatch == Vec_PtrEntry(vBoxesOld, Vec_PtrSize(vBoxesOld) - st__count(tLatches) + Index)src/opt/ret/retIncrem.cint Abc_NtkRetimeFinalizeLatches(Abc_Ntk_t *, st__table *, int, int)int Abc_NtkRetimeNodeIsEnabled(Abc_Obj_t *, int)Abc_ObjIsLatch(pNext)void Abc_NtkRetimeNode(Abc_Obj_t *, int, int)Abc_ObjFaninNum(pNext->pCopy) == 0pLatchTop && Abc_ObjIsLatch(pLatchTop)void Abc_NtkRetimeShareLatches(Abc_Ntk_t *, int)Stopped after %d latch moves. Abc_NtkRetimeFinalizeLatches(): Internal error.The miter for initial state computation has %d AIG nodes. SAT solving timepSop && !Abc_SopIsExorType(pSop)src/opt/ret/retInit.cint Abc_ObjSopSimulate(Abc_Obj_t *)Abc_NtkRetimeBackwardInitialFinish(): Network check has failed. void Abc_NtkCycleInitStateSop(Abc_Ntk_t *, int, int)Abc_NtkIsSopLogic(pNtkCone)int Abc_NtkRetimeVerifyModel(Abc_Ntk_t *, Vec_Int_t *, int *)%d outputs (out of %d) have a value mismatch. Abc_NtkRetimeInitialValues(): The SAT problem timed out. DC latch values are used.Abc_NtkRetimeInitialValues(): The problem is unsatisfiable. DC latch values are used.Abc_NtkIsLogic( pNtk )src/opt/ret/retLvalue.cint Abc_NtkRetimeLValue(Abc_Ntk_t *, int, int)Abc_NtkRetimeLValue(): Network check has failed. Vec_Int_t *Abc_NtkRetimeGetLags(Abc_Ntk_t *, int, int)The best clock period is %3d. (Currently, network is not modified.) Vec_PtrSize(vLatches) == Abc_NtkLatchNum(pNtk)Vec_Ptr_t *Abc_ManCollectLatches(Abc_Ntk_t *)Period = %3d. Iterations = %3d. Infeasible %s Period = %3d. Iterations = %3d. Feasible int Abc_NtkRetimeUpdateLValue(Abc_Ntk_t *, Vec_Ptr_t *, Vec_Ptr_t *, int)int Abc_NtkRetimeSearch_rec(Abc_Ntk_t *, Vec_Ptr_t *, Vec_Ptr_t *, int, int, int, int)Abc_NtkRetimeGetLags() error: The upper bound on the clock period cannot be computed. max delay constraint = %d ERROR: max delay constraint (%d) must be > current max delay (%d) netlist type = netlist/logic/strash/***unknown***/ initial reg count = %d initial levels = %d src/opt/fret/fretMain.cAbc_Ntk_t *Abc_FlowRetime_MinReg(Abc_Ntk_t *, int, int, int, int, int, int, int, int, int)Abc_ObjFanoutNum(pObj) == 1!Abc_ObjFaninC0(pObj)Abc_ObjIsBi(pNext)Abc_ObjFaninNum(pNext) <= 1Abc_ObjIsBo(pNext)Abc_ObjFaninNum(pNext) == 1!Abc_ObjFaninC0(pNext) final reg count = %d final levels = %d max-flow1 = %d max-flow2 = %d void Abc_FlowRetime_FixLatchBoxes(Abc_Ntk_t *, Vec_Ptr_t *)Abc_ObjFanoutNum(pBi) == 1!Abc_ObjFaninC0(pBo)!Abc_ObjIsComplement(Abc_ObjFanin0(pBi))Abc_ObjFaninNum(pBi) == 0Abc_ObjFanoutNum(pBi) == 0Abc_ObjFaninNum(pBo) == 0Abc_ObjFanoutNum(pBo) == 0Abc_ObjIsLatch(pSrc)void Abc_FlowRetime_CopyInitState(Abc_Obj_t *, Abc_Obj_t *)Abc_ObjFanin0(pDest) == pSrc!Abc_ObjFaninC0(pDest)node %d type=%d lev=%d tedge=%d (%x%s) fanouts {%d[%d](%d),} fanins {node %d type=%d %s fanouts {%d , node %d type=%d mark=%d %s Abc_Ntk_t *Abc_FlowRetime_NtkSilentRestrash(Abc_Ntk_t *, int)int Abc_FlowRetime_GetLag(Abc_Obj_t *)(int)Abc_ObjId(pObj) < Vec_IntSize(pManMR->vLags)void Abc_FlowRetime_SetLag(Abc_Obj_t *, int) forward iteration %d restoring network. regs = %d backward iteration %d Abc_ObjIsBo(pBo) && Abc_ObjIsBi(pBi)int Abc_FlowRetime_ImplementCut(Abc_Ntk_t *)!pManMR->fIsForward || !FTEST(pObj, VISITED_E) || FTEST(pObj, VISITED_R)FTEST(pObj, FLOW)Vec_PtrSize(vMove) > 0Vec_PtrSize( vFreeRegs ) min-cut = %d (unmoved = %d) Verifying latency along all paths...pObjCopyAbc_Ntk_t *Abc_FlowRetime_NtkDup(Abc_Ntk_t *)pNextCopypNext->Type == pNextCopy->TypeAbc_ObjFanoutNum( pObj ) == Abc_ObjFanoutNum( pObjCopy )Abc_ObjFaninNum( pObj ) == Abc_ObjFaninNum( pObjCopy )Abc_NtkObjNum( pNtk ) == Abc_NtkObjNum( pNtkCopy )Abc_NtkLatchNum( pNtk ) == Abc_NtkLatchNum( pNtkCopy )Abc_NtkPoNum( pNtk ) == Abc_NtkPoNum( pNtkCopy )Abc_NtkPiNum( pNtk ) == Abc_NtkPiNum( pNtkCopy )!Abc_ObjIsComplement(pBi)void Abc_FlowRetime_RemoveLatchBubbles(Abc_Obj_t *)!Abc_ObjIsComplement(pBo)void Abc_FlowRetime_UpdateLags_forw_rec(Abc_Obj_t *)!Abc_ObjIsPo(pObj)void Abc_FlowRetime_UpdateLags_back_rec(Abc_Obj_t *)***unknown***mapped ok ERROR: Can not retime with black/white boxes pushing bubbles out of latch boxesFlow-based minimum-register retiming...WARNING: no equivalent init state. setting all initial states to don't-cares ERROR: no-latch path (inter) ERROR: mult-latch path ERROR: extra-latch path to outputs ERROR: no-latch path (end)pManMR->vSinkDistHistsrc/opt/fret/fretFlow.cvoid dfsfast_preorder(Abc_Ntk_t *)pPredint dfsfast_e(Abc_Obj_t *, Abc_Obj_t *)!pManMR->fIsForwardint dfsfast_r(Abc_Obj_t *, Abc_Obj_t *)int dfsplain_e(Abc_Obj_t *, Abc_Obj_t *)int dfsplain_r(Abc_Obj_t *, Abc_Obj_t *)src/opt/fret/fretime.hvoid FSETPRED(Abc_Obj_t *, Abc_Obj_t *)min_dist < Vec_IntSize(pManMR->vSinkDistHist)void dfsfast_e_retreat(Abc_Obj_t *)void dfsfast_r_retreat(Abc_Obj_t *)?}+ initial states {0,1,x} = {%d, %d, %d} + %d UNKNOWNpManMR->pInitNtksrc/opt/fret/fretInit.cint Abc_FlowRetime_SolveBackwardInit(Abc_Ntk_t *)!Abc_ObjIsBo(pObj)!Abc_ObjIsBi(pObj) solving for init state (%d nodes)... Abc_ObjIsPi( pInitObj )pManMR->pInitNtk->pModel!Abc_LatchIsInitNone( pObj )Abc_ObjIsPi(pInitObj)void Abc_FlowRetime_UpdateBackwardInit(Abc_Ntk_t *)Abc_ObjFanoutNum( pInitObj ) == 0Vec_PtrSize(vPi) > 0pOrigObjAbc_Obj_t *Abc_FlowRetime_CopyNodeToInitNtk(Abc_Obj_t *)Abc_ObjFaninNum(pOrigObj) == 1Abc_SopGetVarNum((char*)pData) == Abc_ObjFaninNum(pOrigObj)pInitObjAbc_NtkPoNum( pInitNtk ) == 1int Abc_FlowRetime_PartialSat(Vec_Ptr_t *, int)!Abc_ObjIsPo( pObj )pPartNextpObj->pCopy == pPartObjvoid Abc_FlowRetime_ConstrainInit()!Abc_FlowRetime_PartialSat( vNodes, 0 )Abc_FlowRetime_PartialSat( vNodes, high )!Abc_FlowRetime_PartialSat( vNodes, low ) conflict term = %d <=> %d/%d creating %d bias structures void Abc_FlowRetime_UpdateForwardInit_rec(Abc_Obj_t *)void Abc_FlowRetime_SimulateNode(Abc_Obj_t *)Abc_ObjRegular(pObj)pBddpObj->pDataAbc_ObjFaninNum(pObj) <= Hop_ManPiNum(pHop)void Abc_FlowRetime_SimulateSop(Abc_Obj_t *, char *)pReg == pObjvoid Abc_FlowRetime_EvalHop_rec(Hop_Man_t *, Hop_Obj_t *, int *, int *)void Abc_LatchSetInitNone(Abc_Obj_t *)Abc_Obj_t *Abc_FlowRetime_UpdateBackwardInit_rec(Abc_Obj_t *)!Abc_ObjIsPi(pOrigObj)!Abc_ObjIsPo(pOrigObj)!Abc_ObjIsBo( pOrigFanin )pManMR->pInitToOrigvoid Abc_FlowRetime_SetInitToOrig(Abc_Obj_t *, Abc_Obj_t *)Abc_ObjFaninNum(*pResult)int Abc_FlowRetime_ObjFirstNonLatchBox(Abc_Obj_t *, Abc_Obj_t **)nItems < p->nSizevoid Vec_PtrReorder(Vec_Ptr_t *, int)void Abc_FlowRetime_ClearInitToOrig(Abc_Obj_t *)id < pManMR->sizeInitToOrigvoid Abc_FlowRetime_GetInitToOrig(Abc_Obj_t *, Abc_Obj_t **, int *)Abc_ObjFaninNum(pInit)SUCCESSFAILURE updating init state no init state computation: all-don't-care solution search for initial state conflict...pManMR->vTimeEdgessrc/opt/fret/fretTime.cvoid Abc_FlowRetime_InitTiming(Abc_Ntk_t *)!Vec_PtrSize(FTIMEEDGES(pObj))void Abc_FlowRetime_ConstrainConserv(Abc_Ntk_t *) subiter %d : constraints = {cons, exact} = %d, %d refinement: over under = %d refined nodes = !Vec_PtrSize( vNodes )void Abc_FlowRetime_ConstrainConserv_forw(Abc_Ntk_t *)(int)pObj->Level <= pManMR->maxDelaypNext->fMarkB!Vec_PtrSize(vNodes)void Abc_FlowRetime_ConstrainConserv_back(Abc_Ntk_t *)Abc_ObjIsBo(pBo)void Abc_FlowRetime_ConstrainExact_forw(Abc_Obj_t *)!Vec_PtrSize( FTIMEEDGES(pObj) )!Abc_ObjIsLatch(pReg)(int)pReg->Level <= pManMR->maxDelayvoid Abc_FlowRetime_ConstrainExact_back(Abc_Obj_t *) donepPars->nWindow > 0 && pPars->nWindow < 100src/opt/res/resCore.cRes_Man_t *Res_ManAlloc(Res_Par_t *)pPars->nCands > 0 && pPars->nCands < 100Reduction in nodes = %5d. (%.2f %%) Reduction in edges = %5d. (%.2f %%) Winds = %d. Nodes = %d. (Ave = %5.1f) Divs = %d. (Ave = %5.1f) WinsTriv = %d. SimsEmpt = %d. Const = %d. WindUsed = %d. Cands = %d. Proved = %d.Divisors Strashing Simulation Candidates SAT solver sat unsat simul Interpol Undating int Abc_NtkResynthesize(Abc_Ntk_t *, Res_Par_t *)%5d (lev=%2d) : Win = %3d/%3d/%4d/%3d D = %3d D+ = %3d AIG = %4d puTruthAbc_NtkResynthesize(): Network check has failed. (int)pObj->Level >= p->nLevLeafMinsrc/opt/res/resDivs.cvoid Res_WinDivisors(Res_Win_t *, int)void Res_WinMarkTfi_rec(Res_Win_t *, Abc_Obj_t *)int Res_NodeDeref_rec(Abc_Obj_t *)int Res_WinVisitMffc(Abc_Obj_t *)pObj->pNtk == pAig && Abc_ObjIsPo(pObj)src/opt/res/resSat.cvoid *Res_SatProveUnsat(Abc_Ntk_t *, Vec_Ptr_t *)iPat < nPatsLimitint Res_SatSimulate(Res_Sim_t *, int, int)Abc_NtkIsStrash(pAig)src/opt/res/resSim.cvoid Res_SimAdjust(Res_Sim_t *, Abc_Ntk_t *, int)p->nBytesIn % 32 == 0void Res_SimSetDerivedBytes(Res_Sim_t *, int)void Res_SimPerformOne(Abc_Obj_t *, Vec_Ptr_t *, int)void Res_SimTransferOne(Abc_Obj_t *, Vec_Ptr_t *, int)nPats > 0 && nPats < nWords * 8 * (int) sizeof(unsigned)void Res_SimPadSimInfo(Vec_Ptr_t *, int, int)Dc = %7.2f %% On = %7.2f %% Off = %7.2f %% pInfoNode[i] == 0 || pInfoNode[i] == 0xffvoid Res_SimCollectPatterns(Res_Sim_t *, int)pInfo[i] == 0 || pInfo[i] == 0xffOn = %3d Off = %3d pInfo[0] == 0 || pInfo[0] == ~0int Res_SimVerifyValue(Res_Sim_t *, int)Abc_NtkHasAig(p->pNode->pNtk)src/opt/res/resStrash.cAbc_Ntk_t *Res_WndStrash(Res_Win_t *)windowRes_WndStrash(): Network check has failed. p->nWinTfiMax > 0src/opt/res/resWin.cint Res_WinCollectLeavesAndNodes(Res_Win_t *)Vec_VecSize(p->vMatrix) > p->nWinTfiMaxp->nLevTravMin >= 0void Res_WinComputeRoots_rec(Abc_Obj_t *, int, int, Vec_Ptr_t *)Vec_PtrSize(p->vRoots) > 0int Res_WinComputeRoots(Res_Win_t *)int Res_WinMarkPaths_rec(Abc_Obj_t *, Abc_Obj_t *, int)void Res_WinFinalizeRoots_rec(Abc_Obj_t *, Vec_Ptr_t *)int Res_WinFinalizeRoots(Res_Win_t *)Vec_PtrFind(p->vLeaves, pObj) == -1void Res_WinAddMissing_rec(Res_Win_t *, Abc_Obj_t *, int)int Res_WinCompute(Abc_Obj_t *, int, int, Res_Win_t *)nWinTfiMax > 0 && nWinTfiMax < 10nWinTfoMax >= 0 && nWinTfoMax < 10Abc_NtkHasAig(pNew)src/opt/lpk/lpkCore.cAbc_Ntk_t *Abc_NtkDecFromTruth(word *, int, int)Abc_Obj_t *Abc_NtkLutMinDecompose(Abc_Ntk_t *, Vec_Ptr_t *, word *, int, int)p->pIfMan == NULLvoid Lpk_IfManStart(Lpk_Man_t *)pRoot->Type == KIT_DSD_AND || pRoot->Type == KIT_DSD_XOR || pRoot->Type == KIT_DSD_PRIMEint Lpk_ExploreCut(Lpk_Man_t *, Lpk_Cut_t *, Kit_DsdNtk_t *) Mffc = %2d. Mapped = %2d. Gain = %3d. Depth increase = %d. SReds = %d. Node %5d : Mffc size = %5d. Cuts = %5d. C%02d: L= %2d/%2d V= %2d/%d N= %d W= %4.2f Node %5d : Mffc size = %5d. Cuts = %5d. Level = %2d. Req = %2d. Abc_ObjLevel(pObjNew) <= Requiredint Lpk_ResynthesizeNodeNew(Lpk_Man_t *)Performed resynthesis: Gain = %2d. Level = %2d. Req = %2d. int Lpk_Resynthesize(Abc_Ntk_t *, Lpk_Par_t *)Resynthesis for %d %d-LUTs with %d non-MFFC LUTs, %d crossbars, and %d-input cuts. Node gain = %5d. (%.2f %%) Edge gain = %5d. (%.2f %%) Muxes = %4d. Dsds = %4d.Nodes = %5d (%3d) Cuts = %5d (%4d) Changes = %5d Iter = %2d Benefit = %d. Non-DSD:CSuppsEval MuxAn MuxSp DsdAn DsdSp Other9j@B@B@BLpk_Resynthesize: The network check has failed.src/opt/lpk/lpkAbcDec.cAbc_Obj_t *Lpk_Implement_rec(Lpk_Man_t *, Abc_Ntk_t *, Vec_Ptr_t *, Lpk_Fun_t *)nLeavesOld < Vec_PtrSize(vLeaves)Abc_Obj_t *Lpk_Implement(Lpk_Man_t *, Abc_Ntk_t *, Vec_Ptr_t *, int)p->nLutK >= 3 && p->nLutK <= 6int Lpk_Decompose_rec(Lpk_Man_t *, Lpk_Fun_t *)p->nVars > p->nLutKp2->nVars <= (int)p->nLutK!pResMux || (pResMux->DelayEst <= (int)p->nDelayLim && pResMux->AreaEst <= (int)p->nAreaLim)p->uSupp == Kit_BitMask(p->nVars)src/opt/lpk/lpkAbcMux.cLpk_Res_t *Lpk_MuxAnalize(Lpk_Man_t *, Lpk_Fun_t *)p->fSupportsnSuppSize0 < (int)p->nVarsnSuppSize1 < (int)p->nVarsVar >= 0 && Var < (int)p->nVarsLpk_Fun_t *Lpk_MuxSplit(Lpk_Man_t *, Lpk_Fun_t *, int, int)p->nAreaLim >= 2iVarVac < (int)p->nVarsp->uSupp == Kit_TruthSupport(pTruth, p->nVars)nTruths > 0src/opt/lpk/lpkAbcDsd.cint Lpk_FunComputeMinSuppSizeVar(Lpk_Fun_t *, unsigned int **, int, unsigned int **, unsigned int)pObj->Type == KIT_DSD_PRIMEunsigned int Lpk_ComputeBoundSets_rec(Kit_DsdNtk_t *, int, Vec_Int_t *, int)Vec_Int_t *Lpk_ComputeBoundSets(Kit_DsdNtk_t *, int)(uSupport & 0xFFFF0000) == 0(uBoundSet & (uBoundSet >> 16)) == 0void Lpk_FunCompareBoundSets(Lpk_Fun_t *, Vec_Int_t *, int, unsigned int, unsigned int, Lpk_Res_t *)nVarsBS <= (int)p->nLutK - nCofDepthpRes->DelayEst <= (int)p->nDelayLimpRes->AreaEst <= (int)p->nAreaLimnCofDepth >= 1 && nCofDepth <= 3int Lpk_DsdAnalizeOne(Lpk_Fun_t *, unsigned int *(*)[16], Kit_DsdNtk_t **, char *, int, Lpk_Res_t *)nCofDepth < (int)p->nLutK - 1p->nLutK >= 3Lpk_Res_t *Lpk_DsdAnalize(Lpk_Man_t *, Lpk_Fun_t *, int)nShared >= 0 && nShared <= 3pRes1->nBSVars <= (int)p->nLutK - 1pRes2->nBSVars <= (int)p->nLutK - 2nShared == 3pRes3->nBSVars <= (int)p->nLutK - 3k == nVarsNewsrc/opt/lpk/lpkAbcUtil.cint Lpk_FunSuppMinimize(Lpk_Fun_t *)p->fSupports == 0void Lpk_FunComputeCofSupps(Lpk_Fun_t *)jt?src/opt/lpk/lpkCut.cCloudNode *Lpk_CutTruthBdd_rec(CloudManager *, Hop_Man_t *, Hop_Obj_t *, int)((unsigned)(ABC_PTRUINT_T)pObj->pData) & 0xffff0000Hop_ObjIsAnd(pObj)((unsigned)(ABC_PTRUINT_T)pFanin->pCopy) & 0xffff0000CloudNode *Lpk_CutTruthBdd(Lpk_Man_t *, Lpk_Cut_t *)unsigned int *Lpk_CutTruth_rec(Hop_Man_t *, Hop_Obj_t *, int, Vec_Ptr_t *, int *)pCut->nNodes > 0unsigned int *Lpk_CutTruth(Lpk_Man_t *, Lpk_Cut_t *, int)iCount <= Vec_PtrSize(p->vTtNodes)int Lpk_NodeCutsCheckDsd(Lpk_Man_t *, Lpk_Cut_t *)pFanin->fMarkA == 1pCutNew->uSign[0] || pCutNew->uSign[1]int Lpk_NodeCutsOneFilter(Lpk_Cut_t *, int, Lpk_Cut_t *)void Lpk_NodePrintCut(Lpk_Man_t *, Lpk_Cut_t *, int)pCut->pLeaves[i] < pCut->pLeaves[i+1]void Lpk_NodeCutSignature(Lpk_Cut_t *)void Lpk_NodeCutsOne(Lpk_Man_t *, Lpk_Cut_t *, int)(int)pCut->nNodesDup < p->pPars->nLutsOverp->nCuts < LPK_CUTS_MAXpCutNew->nNodes <= p->nMffc + pCutNew->nNodesDupint Lpk_NodeCuts(Lpk_Man_t *)LEAVES: NODES:pPars->nLutsMax <= 16src/opt/lpk/lpkMan.cLpk_Man_t *Lpk_ManStart(Lpk_Par_t *)pPars->nVarsMax > 0 && pPars->nVarsMax <= 16$ 2iLit >= 0src/opt/lpk/lpkMap.cIf_Obj_t *Lpk_MapTree_rec(Lpk_Man_t *, Kit_DsdNtk_t *, If_Obj_t **, int, If_Obj_t *)pObj->nFans == 2Scores: Prios: src/opt/lpk/lpkMulti.cint Lpk_FindHighest(Kit_DsdNtk_t **, int *, int, int *, int *)uSupps[i] <= 0xFFFFiVarMax != -1Decision: piLits[i] >= 0If_Obj_t *Lpk_MapTreeMulti_rec(Lpk_Man_t *, Kit_DsdNtk_t **, int *, int *, int, If_Obj_t **, int, int *)nSize == 1If_Obj_t *Lpk_MapTreeMulti(Lpk_Man_t *, unsigned int *, int, If_Obj_t **)Cof%d%d: ppNtks[i]->pSupps[0] <= 0xFFFFint Kit_DsdLitIsLeaf(Kit_DsdNtk_t *, int)unsigned int Kit_DsdLitSupport(Kit_DsdNtk_t *, int)After restructuring with priority:nVars > 3src/opt/lpk/lpkMux.cIf_Obj_t *Lpk_MapTreeMux_rec(Lpk_Man_t *, unsigned int *, int, If_Obj_t **)Cofactoring w.r.t. var %c (%d -> %d+%d supp vars): TrueMint0 >= 0 && TrueMint1 >= 0If_Obj_t *Lpk_MapSuppRedDec_rec(Lpk_Man_t *, unsigned int *, int, If_Obj_t **)FalseMint0 >= 0 && FalseMint1 >= 0nVars == 8void Lpk_TryDec(word *, int)UUUU3333src/opt/lpk/lpkSets.cunsigned int Lpk_ComputeSets_rec(Kit_DsdNtk_t *, int, Vec_Int_t *)unsigned int Lpk_ComputeSets(Kit_DsdNtk_t *, Vec_Int_t *)pEntry->SRed > 0void Lpk_ComposeSets(Vec_Int_t *, Vec_Int_t *, int, int, Lpk_Set_t *, int *, int)Var = %c Size = %2d Over = %2d SRed = %2d Evaluating variable %c: unsigned int Lpk_MapSuppRedDecSelect(Lpk_Man_t *, unsigned int *, int, int *, int *)nBits <= 32unsigned int Kit_BitMask(int)Subsets(%d): Selected the following subset:Could not select a subset. Exploring support-reducing bound-sets of function:src/opt/nwk/nwkAig.cvoid Nwk_ManColleacReached_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, Vec_Int_t *)Vec_IntSize(vMaps) == Nwk_ObjId(ppCopies[Gia_ObjId(p,pObj)])Nwk_Man_t *Nwk_ManCreateFromGia(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t **)ppCopies[Gia_ObjId(p,pObj)] != NULLVec_IntSize(vMaps) == Vec_IntSize(vNodes) + Abc_MaxInt(Vec_IntSize(vPPis), Vec_IntSize(vLeaves)) + 1Nwk_ManPiNum(pNtk) == Nwk_ManPoNum(pNtk)void Nwk_ManDeriveMinCut(Gia_Man_t *, int)Min-cut: %d -> %d. Nodes %d -> %d. Common = %d. Diff0 = %d. Diff1 = %d. Gia_ObjIsConst0(pObj) || Gia_ObjIsRo(p, pObj) || Gia_ObjIsAnd(pObj)Node %d has duplicated fanin %d. Nwk_ManCheck(): Object %d has fanin %d which does not have a corresponding fanout. Nwk_ManCheck(): Object %d has fanout %d which does not have a corresponding fanin. src/opt/nwk/nwkBidec.cHop_Obj_t *Nwk_NodeIfNodeResyn(Bdc_Man_t *, Hop_Man_t *, Hop_Obj_t *, int, Vec_Int_t *, unsigned int *, float)Resynthesis is not performed for networks whose nodes are less than 2 inputs.Node %d has fanin %d that is not in a topological order. Box %d has input %d that is not in a topological order. src/opt/nwk/nwkDfs.cint Nwk_ManVerifyTopoOrder(Nwk_Man_t *)Nwk_ManVerifyTopoOrder(pNtk)int Nwk_ManLevelBackup(Nwk_Man_t *)void Nwk_ManLevel_rec(Nwk_Obj_t *)Nwk_ManVerifyLevel(pNtk)Vec_Vec_t *Nwk_ManLevelize(Nwk_Man_t *)Nwk_ObjLevel(pObj) <= nLevelsNwk_ObjIsNode(pObj)void Nwk_ManDfsNodes_rec(Nwk_Obj_t *, Vec_Ptr_t *)void Nwk_ManDfsReverse_rec(Nwk_Obj_t *, Vec_Ptr_t *)Nwk_ObjIsNode( pNode )void Nwk_ManSupportNodes_rec(Nwk_Obj_t *, Vec_Ptr_t *)pFanin->nFanouts > 0int Nwk_ObjDeref_rec(Nwk_Obj_t *)int Nwk_ObjMffcLabel(Nwk_Obj_t *)pObj->pMan == pFanin->pMansrc/opt/nwk/nwkFanio.cvoid Nwk_ObjAddFanin(Nwk_Obj_t *, Nwk_Obj_t *)i == k + 1void Nwk_ObjDeleteFanin(Nwk_Obj_t *, Nwk_Obj_t *)pFaninOld != pFaninNewvoid Nwk_ObjPatchFanin(Nwk_Obj_t *, Nwk_Obj_t *, Nwk_Obj_t *)pObj != pFaninOldpObj != pFaninNewpObj->pMan == pFaninOld->pManpObj->pMan == pFaninNew->pManNwk_ObjPatchFanin(); Error! Node %d is not among the fanins of node %d... !Nwk_ObjIsCo(pNodeFrom) && !Nwk_ObjIsCo(pNodeTo)void Nwk_ObjTransferFanout(Nwk_Obj_t *, Nwk_Obj_t *)pNodeFrom->pMan == pNodeTo->pManNwk_ObjFanoutNum(pNodeFrom) > 0Nwk_ObjFanoutNum(pNodeFrom) == 0Nwk_ObjFanoutNum(pNodeTo) == nFanoutsOld + Vec_PtrSize(vFanouts)pNodeOld->pMan == pNodeNew->pManvoid Nwk_ObjReplace(Nwk_Obj_t *, Nwk_Obj_t *)Nwk_ObjFanoutNum(pNodeOld) > 0pObj->MarkA == 0src/opt/nwk/nwkFlow.cint Nwk_ManRetimeVerifyCutForward(Nwk_Man_t *, Vec_Ptr_t *)Forward: Max-flow = %4d -> !RetValueVec_Ptr_t *Nwk_ManRetimeCutForward(Nwk_Man_t *, int, int)Nwk_ObjHasFlow(pObj)!Nwk_ObjIsCo(pObj)Min-cut = %4d. Unmoved = %4d. Backward: Max-flow = %4d -> Vec_Ptr_t *Nwk_ManRetimeCutBackward(Nwk_Man_t *, int, int)void Nwk_ObjSetVisitedBot(Nwk_Obj_t *)void Nwk_ObjSetVisitedTop(Nwk_Obj_t *)Nwk_ManRetimeVerifyCutForward(): Internal cut verification failed.LUTs by size: %d:%d nameless_%s_dump.blif%-15s : pi = %5d po = %5d ci = %5d co = %5d node = %5d edge = %5d aig = %6d lev = %3d delay = %5.2f power = %7.2f src/opt/nwk/nwkMap.cIf_Man_t *Nwk_ManToIf(Aig_Man_t *, If_Par_t *, Vec_Ptr_t *)Vec_PtrEntry(vAigToIf, i) == NULLHop_Obj_t *Nwk_NodeIfToHop(Hop_Man_t *, If_Man_t *, If_Obj_t *)Aig_ManCiNum(p) == If_ManCiNum(pIfMan)Nwk_Man_t *Nwk_ManFromIf(If_Man_t *, Aig_Man_t *, Vec_Ptr_t *)Aig_ManCoNum(p) == If_ManCoNum(pIfMan)Aig_ManNodeNum(p) == If_ManAndNum(pIfMan)Nwk_ManCheck( pNtk )int Aig_ObjLevel(Aig_Obj_t *)Nwk_NodeIfToHop(): Computing local AIG has failed.Memory usage stats: Preprocessing = %.2f MB. Solving = %.2f MB. iLut1 < iLut2src/opt/nwk/nwkMerge.cvoid Nwk_ManGraphHashEdge(Nwk_Grf_t *, int, int)pEntry->iNode1 <= p->nObjsvoid Nwk_ManGraphPrepare(Nwk_Grf_t *)pEntry->iNode2 <= p->nObjspEntry->iNode1 <= p->nVertspEntry->iNode2 <= p->nVertspnEdges[i] > 0p->pVerts[i]->nEdges == pnEdges[i]pIdToPair[ p->vPairs->pArray[i] ] == -1void Nwk_ManGraphSortPairs(Nwk_Grf_t *)i < pIdToPair[i]nSize == Vec_IntSize(p->vPairs)p->pLists1[0] == 0void Nwk_ManGraphCheckLists(Nwk_Grf_t *)pVertex->nEdges == 1pNext->nEdges == i || pNext->nEdges > NWK_MAX_LISTp->pLists2[0] == 0p->pLists2[1] == 0pVertex->nEdges == j || pVertex->nEdges > NWK_MAX_LISTpOther->nEdges == 1void Nwk_ManGraphUpdate(Nwk_Grf_t *, Nwk_Vrt_t *, Nwk_Vrt_t *)void Nwk_ManGraphSolve(Nwk_Grf_t *)pVertex->nEdges == j || j == NWK_MAX_LIST%s %d %dp->nEdges == nEdgesNwk_Grf_t *Nwk_ManLutMergeReadGraph(char *)Readingvoid Nwk_ManCollectNonOverlapCands(Nwk_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *, Nwk_LMPars_t *)pVertex->nEdges > 0void Nwk_ManGraphListInsert(Nwk_Grf_t *, Nwk_Vrt_t *)void Nwk_ManGraphListExtract(Nwk_Grf_t *, Nwk_Vrt_t *)*pListvoid Nwk_ManGraphListDelete(Nwk_Grf_t *, int *, Nwk_Vrt_t *)k < pThis->nEdgesvoid Nwk_ManGraphVertexRemoveEdge(Nwk_Vrt_t *, Nwk_Vrt_t *)Nwk_ObjFanoutNum(pObj) == 0src/opt/nwk/nwkObj.cvoid Nwk_ManDeleteNode(Nwk_Obj_t *)!Nwk_ObjIsCi(pObj)void Nwk_ManDeleteNode_rec(Nwk_Obj_t *)Aig_ObjIsNode(pNode)src/opt/nwk/nwkSpeedup.cint Aig_ManSpeedupNode_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)src/opt/nwk/nwkStrash.cvoid Nwk_ManStrashNode_rec(Aig_Man_t *, Hop_Obj_t *)Aig_Obj_t *Nwk_ManStrashNode(Aig_Man_t *, Nwk_Obj_t *)Aig_Man_t *Nwk_ManStrash(Nwk_Man_t *)int Aig_ObjSetLevel(Aig_Obj_t *, int)Nwk_ObjFaninNum(pNode) == 0 || pPinPerm[0] < Nwk_ObjFaninNum(pNode)src/opt/nwk/nwkTiming.cvoid Nwk_ManDelayTraceSortPins(Nwk_Obj_t *, int *, float *)pPinPerm[i] < Nwk_ObjFaninNum(pNode)Nwk_ObjIsNode(pObj) || Nwk_ObjIsCi(pObj) || Nwk_ObjIsCo(pObj)float Nwk_NodeComputeArrival(Nwk_Obj_t *, int)float Nwk_NodeComputeRequired(Nwk_Obj_t *, int)Nwk_ObjFanin(pFanout,pPinPerm[iFanin]) == pObjNwk_ObjFanin(pFanout,iFanin) == pObjfloat Nwk_NodePropagateRequired(Nwk_Obj_t *, int)tSlack + 0.01 > 0.0float Nwk_ManDelayTraceLut(Nwk_Man_t *)Nwk_ManVerifyTiming(): Object %d has different arrival time (%.2f) from computed (%.2f). Nwk_ManVerifyTiming(): Object %d has different required time (%.2f) from computed (%.2f). void Nwk_ManDelayTracePrint(Nwk_Man_t *)Nwk_ObjLevel(pTemp1) <= Nwk_ObjLevel(pTemp2)void Nwk_NodeUpdateAddToQueue(Vec_Ptr_t *, Nwk_Obj_t *, int, int)Nwk_ObjLevel(pTemp1) >= Nwk_ObjLevel(pTemp2)void Nwk_NodeUpdateArrival(Nwk_Obj_t *)Nwk_ManTimeLess( tArrival, Nwk_ObjRequired(pObj), (float)0.01 )void Nwk_NodeUpdateRequired(Nwk_Obj_t *)Nwk_ManTimeEqual( tRequired, Nwk_ObjRequired(pObj), (float)0.01 )Nwk_ObjIsNode(pObj) || Nwk_ObjIsCo(pObj)int Nwk_ObjLevelNew(Nwk_Obj_t *)void Nwk_ManUpdateLevel(Nwk_Obj_t *)int Nwk_ManVerifyLevel(Nwk_Man_t *)Object %6d: Mismatch betweeh levels: Actual = %d. Correct = %d. pObj->pMan == pObjNew->pManvoid Nwk_ManUpdate(Nwk_Obj_t *, Nwk_Obj_t *, Vec_Vec_t *)pObj != pObjNewNwk_ObjFanoutNum(pObj) > 0Nwk_ObjIsNode(pObj) && !Nwk_ObjIsCo(pObjNew)Nwk_ManGetAigNodeNum(): Local AIG of node %d is not assigned. ObjId = %5d. Fanins = Fanouts = # BLIF file written by procedure Nwk_ManDumpBlif() Reducing node %d fanins from %d to %d. Support minimization reduced support of %d nodes. MinbasepObj->pFanio[iFan0] == pObj->pFanio[iFan1]src/opt/nwk/nwkUtil.cvoid Nwk_ManRemoveDupFaninsNode(Nwk_Obj_t *, int, int, Vec_Int_t *)Removing duplicated fanins of node %d (fanins %d and %d). Nwk_ManDumpBlif(): Network does not have POs.The distribution of fanins and fanouts in the network: Number Nodes with fanin Nodes with fanoutsrc/opt/rwt/rwtDec.cvoid Rwt_ManPreprocess(Rwt_Man_t *)!Rwt_IsComplement(pNode)Dec_Graph_t *Rwt_NodePreprocess(Rwt_Man_t *, Rwt_Node_t *)Calculated gain = %8d. Truth                 " "! " " !$&$&%&$ & %(*(*(* )* ) *)**,.,, . -- ...022 12 2 2124646564 6 56 6 656898 : 98 : : ::8:<><>><>< > => >>>>>@BBABAB BBBBBADFEFEF FFEFFF!HJHJIHJH J IJ JJJJJJJJLLMLNL N ML N LNNLLNNLNLNLLNPRPR R RRRRRRR!R#R$R%Q$R'TVTVTVVVTVV T!U V$T%V%U$T'V'U&ZZ Z ZZY X$Z$Z'Y&\^\^\]^ ^^\]^ ^!^"^#\$^$\%^%]$^&^'baba``b`b`bb`!`#b$`'a&dfdff f fffffeff#f'f/f0jhhjjhhjjjj%j-nnn n nnnlnnn+n5pprpqr rrpqrrprpprqr!r)vvuvtvuv vvuvvvut#u"t&v&t'v+v/xxzzyz z z z zzzzzzzz!z'z+z/z0y4z9z:~|~~ | ~~~~%~-~7 +59? #)39  %'+/9:D %)-37=A!).03:C #3=DED ? 03DK%=ACE!=J   3 #-/.E!#%'3=%$7AED !:=ag 98? 7=b=%%$AMNM    O X    + *5=?IW V X  /579=?EDKYi   X+?I#'/CKNO_ae" "!"I!N"%$%$&&E&()**=*Q*e*-Z2 24 5>:=:D9D> =<=<D<S>>BDBBDHHHH&IMNDMHNR QU0]:bddit y DDDhN :)0)3= *V: D   = D S $&!:0 6 4)40434:4=4D5: =:EDI:NNQ&XY$XaYXXYX]$]`h iDhhm:phu:zDyD~~D0~)0:))3=)0hjj,, *V,)00)0,h,0eg -4Sqv{0]eg 4SWv)  ~!!&{&).*{*....2 10=0D0S220220'2{2<<===r>EDDM0R3T)T0Z Z{ZZ^` f d)d0d3d:d=dDi0p)p0v3z zz|  )03:=DDRXrNu#'9h#'Nb'3H'{K,r9h{3H#''{=*   o *{3=!!!!r.:>{BLR3RRRRR%TZ3ZZZZinzz,,3=D!D!''{K{3==1D.8rN)->CM=2`*0g9h '&N&u&-2!22292f=$=JJJ:NCNMNN=NN2NRNRVVZ]]]]rffm z=zzy^~9~h{3|3|o{{vHG~=ND.-'== '=14!*'*-...2229B99=AAAArEDIBHHHsIHAHoHHL:LQbPQPUB]Bddi8m*l9mll.mlq*p0pgppppu x3xH|':!b#h~K>9.b#KrQSz33H!:8(0(0=0 =    0*.=  &$**))*.=..-.H.0=0G00$2$9.>=@=DzDH3HHLbLP#PPUFZZ]jmrrrrv~''O'ONsd)0{{S{)0!!.   {3#&,,{2C2225*89*>I=>>>>B AD FJ3NQVY]aaeXe~iJqv=y,~)-!VTF*S{{$~|": :{ ={ =       K  3 = '$ '$ * * - 0 6 8 8 < B }J 'N 'N R Z )Z 0] 0a 0f f h m p {t 3y P}   y  = = b = ' D  M S =  q % 3 y  ? ? y    O  / I o  ! 5  $ I   ) 3 = = -    Y  C$ * - 2 2 1 5 .9 : : O< B F H L YR R V ^ ` =f j l v Sx z   ' K = " 8 a - o }    / ' K C   + {  $ 0  { N '    '     + { =<=?iko~,-/<=>?hio<=?VWXYZ[_hiln}`afiov~vxpFanDatasrc/opt/cgt/cgtAig.cvoid Cgt_ManDetectFanout_rec(Aig_Man_t *, Aig_Obj_t *, int, Vec_Ptr_t *)void Cgt_ManDetectFanout(Aig_Man_t *, Aig_Obj_t *, int, Vec_Ptr_t *)Vec_PtrSize(vFanout) > 0void Cgt_ManCollectVisited_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)Aig_ObjIsCi(pObjLo)Aig_Obj_t *Cgt_ManConstructCareCondition(Cgt_Man_t *, Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *)Aig_Man_t *Cgt_ManDeriveAigForGating(Cgt_Man_t *)CG_miterAig_ManRegNum(pFrame) == 0Aig_Man_t *Cgt_ManDupPartition(Aig_Man_t *, int, int, int, Aig_Man_t *, Vec_Vec_t *, int *)partitionVec_PtrSize(vGates) > 0Aig_Obj_t *Cgt_ManBuildClockGate(Aig_Man_t *, Vec_Ptr_t *)Aig_Man_t *Cgt_ManDeriveGatedAig(Aig_Man_t *, Vec_Vec_t *, int, int *)!(pObj->fMarkA && pObj->fMarkB)iFan/2 < p->nFansAllocint Aig_ObjFanoutNext(Aig_Man_t *, int)ObjId < p->nFansAllocint Aig_ObjFanout0Int(Aig_Man_t *, int)  Vec_VecSize(p->vGatesAll) == Aig_ManCoNum(p->pFrame)src/opt/cgt/cgtCore.cvoid Cgt_ClockGatingRangeCheck(Cgt_Man_t *, int, int)%5d : D =%4d. C =%5d. Var =%6d. Pr =%5d. Cex =%5d. F =%4d. Saved =%6d. Aig_ManCoNum(p->pFrame) == Saig_ManRegNum(p->pAig)Vec_Vec_t *Cgt_ClockGatingCandidates(Aig_Man_t *, Aig_Man_t *, Cgt_Par_t *, Vec_Int_t *)Nodes: Before CG = %6d. After CG = %6d. (%6.2f %%). Total after CG = %6d. Vec_PtrSize(vInfo) > 1void Vec_PtrReallocSimInfo(Vec_Ptr_t *)RetValue != 0void sat_solver_compress(sat_solver *)=src/opt/cgt/cgtDecide.cvoid Cgt_ManCollectFanoutPos_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)Gating signals = %6d. Gated flops = %6d. (Total flops = %6d.) Complete gates = %6d. Gated transitions = %5.2f %%. Clock gate candidate is invalid!Saig_ManRegNum(pAig) > 0src/opt/cgt/cgtMan.cCgt_Man_t *Cgt_ManCreate(Aig_Man_t *, Aig_Man_t *, Cgt_Par_t *)The PI count of care (%d) and AIG (%d) differ. Careset is not used. Params: LevMax = %d. CandMax = %d. OdcMax = %d. ConfMax = %d. VarMin = %d. FlopMin = %d. SAT : Calls = %d. Unsat = %d. Sat = %d. Fails = %d. Recycles = %d. p->pSat && p->pCnfsrc/opt/cgt/cgtSat.cint Cgt_CheckImplication(Cgt_Man_t *, Aig_Obj_t *, Aig_Obj_t *)!Aig_IsComplement(pMiter)Aig_Regular(pGate) != pMitersrc/opt/csw/cswInt.hAig_Obj_t *Csw_ObjChild0Equiv(Csw_Man_t *, Aig_Obj_t *) >&>>>*nFansNew < pCut->nFaninssrc/opt/csw/cswCut.cint Csw_CutSupportMinimize(Csw_Man_t *, Csw_Cut_t *)k == nFansNewp->nLeafMax > 0int Csw_CutMerge(Csw_Man_t *, Csw_Cut_t *, Csw_Cut_t *, Csw_Cut_t *)pCut->nFanins > 2Aig_Obj_t *Csw_ObjTwoVarCut(Csw_Man_t *, Csw_Cut_t *)Aig_Obj_t *Csw_ObjSweep(Csw_Man_t *, Aig_Obj_t *, int)pCut->nFanins == 0iVar < pCut->nFaninspCut->nFanins > 0pCut->Cost > 0pCut->pFanins[i] == pCut1->pFanins[k]unsigned int Cut_TruthPhase(Csw_Cut_t *, Csw_Cut_t *)pC0->nFanins >= pC1->nFaninsint Csw_CutMergeOrdered(Csw_Man_t *, Csw_Cut_t *, Csw_Cut_t *, Csw_Cut_t *)pCutMax != NULLCsw_Cut_t *Csw_CutFindFree(Csw_Man_t *, Aig_Obj_t *)int Csw_CutFindCost(Csw_Man_t *, Csw_Cut_t *)nCutsMax >= 2src/opt/csw/cswMan.cCsw_Man_t *Csw_ManStart(Aig_Man_t *, int, int, int)nLeafMax <= 16Aig_ManCiNum(p->pManAig) == Aig_ManCiNum(p->pManRes)Beg = %7d. End = %7d. (%6.2f %%) Try = %7d. Cuts = %8d. Triv0 = %6d. Triv1 = %6d. Triv2 = %6d. Cut-replace = %6d. Cuts Hashing EQGyU)] C k 1 g # ]  a  = WCg!i Y 7yEm!k)_=u#{7qQ!QAsE5c/Kg{pCut->nFanins <= 16src/opt/csw/cswTable.cunsigned int Csw_CutHash(Csw_Cut_t *)pRes->fPhase == Aig_ManObj( p->pManRes, pCut->iNode )->fPhaseAig_Obj_t *Csw_TableCutLookup(Csw_Man_t *, Csw_Cut_t *)Aig_Regular(pRes)->fPhase != Aig_ManObj( p->pManRes, pCut->iNode )->fPhasepTemp != pTempNextsrc/opt/dar/darBalance.cvoid Dar_BalanceUniqify(Aig_Obj_t *, Vec_Ptr_t *, int)void Dar_BalanceCone_rec(Aig_Obj_t *, Aig_Obj_t *, Vec_Ptr_t *)Vec_Ptr_t *Dar_BalanceCone(Aig_Obj_t *, Vec_Vec_t *, int)Aig_ObjLevel(Aig_Regular(pObjLeft)) == Aig_ObjLevel(Aig_Regular(pObjRight))int Dar_BalanceFindLeft(Vec_Ptr_t *)void Dar_BalancePermute(Aig_Man_t *, Vec_Ptr_t *, int, int)Aig_Obj_t *Dar_BalanceBuildSuper(Aig_Man_t *, Vec_Ptr_t *, Aig_Type_t, int)Aig_Obj_t *Dar_BalanceBuildSuperTop(Aig_Man_t *, Vec_Ptr_t *, Aig_Type_t, int, int)!Aig_IsComplement(pObjOld)Aig_Obj_t *Dar_Balance_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Vec_t *, int, int)!Aig_ObjIsBuf(pObjOld)Aig_ObjIsNode(pObjOld)pObjOld->pData == NULLAig_ManVerifyTopoOrder(p)Aig_Man_t *Dar_ManBalance(Aig_Man_t *, int)!Aig_ObjFaninC0(pObj)void Dar_BalancePrintStats(Aig_Man_t *)!Aig_ObjFaninC1(pObj) %d(Type != AIG_OBJ_AND || !Aig_ObjIsConst1(Aig_Regular(p0))Aig_Obj_t *Aig_ObjCreateGhost(Aig_Man_t *, Aig_Obj_t *, Aig_Obj_t *, Aig_Type_t)p1 == NULL || !Aig_ObjIsConst1(Aig_Regular(p1))Dar_ManBalance(): The check has failed.There is no EXOR gates.pCut->nLeaves < 2src/opt/dar/darCore.cint Dar_ManRewrite(Aig_Man_t *, Dar_RwrPar_t *)pCut->uTruth == 0 || pCut->uTruth == 0xFFFFpCut->uTruth == 0xAAAA || pCut->uTruth == 0x5555(int)Aig_Regular(pObjNew)->Level <= Requiredp->GainBest <= nNodeBefore - nNodeAfterNodes = %6d. Total cuts = %6d. 4-input cuts = %6d. Cut size = %2d. Truth size = %2d. Total mem = %5.2f MB !Aig_ObjIsNone(pObj)src/opt/dar/darInt.hvoid Dar_ObjSetCuts(Aig_Obj_t *, Dar_Cut_t *)Aig_ManRewrite: The network check has failed.Cuts for node %d: Dar_ObjCuts(pObj) == NULLsrc/opt/dar/darCut.cDar_Cut_t *Dar_ObjPrepareCuts(Dar_Man_t *, Aig_Obj_t *)Dar_Cut_t *Dar_ObjComputeCuts(Dar_Man_t *, Aig_Obj_t *, int)Dar_ObjCuts(pFaninR0) != NULLDar_ObjCuts(pFaninR1) != NULL!pCut->fUsediVar >= 0 && iVar <= 2unsigned int Dar_CutTruthSwapAdjacentVars(unsigned int, int)int Dar_CutFindValue(Dar_Man_t *, Dar_Cut_t *)Dar_Cut_t *Dar_CutFindFree(Dar_Man_t *, Aig_Obj_t *)int Dar_CutMerge(Dar_Cut_t *, Dar_Cut_t *, Dar_Cut_t *)pC0->nLeaves >= pC1->nLeavesint Dar_CutMergeOrdered(Dar_Cut_t *, Dar_Cut_t *, Dar_Cut_t *)int Dar_CutFilter(Aig_Obj_t *, Dar_Cut_t *)pDom->fUsed && pCut->fUsedint Dar_CutCheckDominance(Dar_Cut_t *, Dar_Cut_t *)unsigned int Dar_CutTruthStretch(unsigned int, int, unsigned int)unsigned int Dar_CutTruthPhase(Dar_Cut_t *, Dar_Cut_t *)int Dar_CutSuppMinimize(Dar_Cut_t *)k == nLeavesDDDD0000"""" W``k == 222src/opt/dar/darLib.cvoid Dar_LibReturnCanonicals(unsigned int *)p->iObj == p->nObjsvoid Dar_LibSetup(Dar_Lib_t *, Vec_Int_t *, Vec_Int_t *)p->nSubgrTotal == Vec_IntSize(vOuts)Counter == Vec_IntSize(vPrios)nNodesTotal == p->nNodesTotalnNodes0Total == p->nNodes0Totalvoid Dar_LibPrepare(int)s_DarLib != NULLvoid Dar_LibStop()Class >= 0 && Class < 222void Dar_LibIncrementScore(int, int, int)Out >= 0 && Out < s_DarLib->nSubgr[Class]pPlace[pPrios[Out]] == Out Output priorities (total = %d): s_DarLib->pScore[i][Out2] >= s_DarLib->pScore[i][Out]void Dar_LibDumpPriorities()Printed == s_DarLib->nSubgrTotalpCut->nLeaves == 4int Dar_LibCutMatch(Dar_Man_t *, Dar_Cut_t *)(int)pObj->Num < s_DarLib->nNodes0Max + 4void Dar_LibEvalAssignNums(Dar_Man_t *, int, Aig_Obj_t *)(int)Dar_LibObj(s_DarLib, pObj->Fan0)->Num < s_DarLib->nNodes0Max + 4(int)Dar_LibObj(s_DarLib, pObj->Fan1)->Num < s_DarLib->nNodes0Max + 4pObj->Num > 3int Dar_LibEval_rec(Dar_LibObj_t *, int, int, int, float *)p->LevelBest <= Requiredvoid Dar_LibEval(Dar_Man_t *, Aig_Obj_t *, Dar_Cut_t *, int, int *)Vec_IntSize(vCutLits) == 4int Dar2_LibCutMatch(Gia_Man_t *, Vec_Int_t *, unsigned int)void Dar2_LibEvalAssignNums(Gia_Man_t *, int)int Dar2_LibEval_rec(Dar_LibObj_t *, int)int Dar2_LibEval(Gia_Man_t *, Vec_Int_t *, unsigned int, int, Vec_Int_t *)(uTruth >> 16) == 0p_OutBest != -1Vec_IntSize(vLeavesBest2) == 4int Dar2_LibBuildBest(Gia_Man_t *, Vec_Int_t *, int)Tried = %8d. Beg = %8d. End = %8d. Gain = %6d. (%6.2f %%). Cut mem = %d MB Cuts = %8d. Tried = %8d. Used = %8d. Bad = %5d. Skipped = %5d. Ave = %.2f. Bufs = %5d. BufMax = %5d. BufReplace = %6d. BufFix = %6d. Levels = %4d. G = %6d (%5.2f %%) S = %8d (%5.2f %%) R = %7d src/opt/dar/darPrec.cchar **Dar_ArrayAlloc(int, int, int)unsigned int Dar_TruthPermute(unsigned int, char *, int, int)unsigned int Dar_TruthPolarize(unsigned int, int, int)void Dar_Truth4VarNPN(unsigned short **, char **, char **, unsigned char **)uMap[uTruth] != 0 NodesBeg = %8d. NodesEnd = %8d. Gain = %6d. (%6.2f %%). Tried = %6d. Below = %5d. Extended = %5d. Used = %5d. Levels = %4d. Aig_Regular((Aig_Obj_t *)pNode->pFunc)->Level < (1<<24)-1src/opt/dar/darRefact.cint Dar_RefactTryGraph(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *, Kit_Graph_t *, int, int)nNodesSaved2 == nNodesSavedint Dar_ManRefactor(Aig_Man_t *, Dar_RefPar_t *)Dar_ManRefactor: The network check has failed.Starting: Balance: Rewrite: Refactor: RewriteZ: RefactorZ: Synthesis timeChoicing time Warning: Due to high fanout count of some nodes, level updating is disabled.Gz?RQ? ?ףp= 4\(\?mJR?q= ףp?=m?Cl?㥛 ?/iVar == 2src/opt/dau/dauCanon.cint Abc_TtCountOnesInCofsFast6_rec(word, int, int, int *)iVar == 5int Abc_TtCountOnesInCofsFast_rec(word *, int, int, int *)nWords > 1iVar > 5nVars >= 3int Abc_TtCountOnesInCofsFast(word *, int, int *)Abc_TtEqual( pCopy1, pCopy2, nWords )void Abc_TtCofactorTest10(word *, int, int)Copy == pTruth[0]int Abc_Tt6CofactorPermNaive(word *, int, int)Best <= pTruth[0]Abc_TtEqual( pTruth, pCopy, nWords )int Abc_TtCofactorPermNaive(word *, int, int, int)Abc_TtCompareRev(pTruth, pBest, nWords) == 1unsigned int Abc_TtCanonicizePerm(word *, int, char *)uCanonPhase == 0Abc_TtEqual(pTruth, pRepTruth, p->nWords)int Abc_TtHieRetrieveOrInsert(Abc_TtHieMan_t *, int, word *, word *)unsigned int Abc_TtCanonicizeHie(Abc_TtHieMan_t *, word *, int, char *, int)i == pMan->nVarsint Abc_TgExpendSymmetry(Abc_TgMan_t *, char *)unsigned int Abc_TtCanonicizeAda(Abc_TtHieMan_t *, word *, int, char *, int)!(nAlg && p == NULL)Abc_TgCannonVerify(&tgMan)unsigned int Abc_TtCanonicizeCA(Abc_TtHieMan_t *, word *, int, char *, int)Abc_TgCannonVerify(&tgManCopy)Num1 < Num2 && Num2 < 4int Abc_TtCompare2VarCofsRev(word *, int, int, int, int)nWords >= 2nWords >= 4unsigned int Abc_TtSemiCanonicize(word *, int, char *, int *, int)void Abc_TtImplementNpnConfig(word *, int, char *, unsigned int)int Abc_TtCanonicizePhaseVar6(word *, int, int)w == -1int Abc_TtCanonicizePhaseVar5(word *, int, int)*pTruth == nTruthvoid Abc_TtVerifySmallTruth(word *, int)void Abc_TgCreateGroups(Abc_TgMan_t *)j == n + 1int Abc_TgSplitGroup(Abc_TgMan_t *, TiedGroup *, int *)jVar >= 0void Abc_TgPurgeSymmetry(Abc_TgMan_t *, int)pMan->pGroup[0].iStart == 0iv < 0 && jv < 0int Abc_TtIsSymmetricHigh(Abc_TgMan_t *, int, int, int)Vec_IntSize(vPhase) == 0int Abc_TgRecordPhase1(Abc_TgMan_t *)Abc_TgCannonVerify(pMan)void Abc_TgSplitGroupsByScc(Abc_TgMan_t *)pMan->symLink[k] < 0 || pOut[j] == pOut[i]void Abc_TgCalcScc(Abc_TgMan_t *, int *, int)Abc_TgIsInitPerm(pVars, pDirs, nGvars)void Abc_TgFirstPermutation(Abc_TgMan_t *)int Abc_TgNextPermutation(Abc_TgMan_t *)idx < pMan->nGVars - 1void Abc_TgSwapAdjacentSymGroups(Abc_TgMan_t *, int)pMan->pPermT[ix] == iVar && pMan->pPermT[ix + 1] == jVark == pMan->nGVarsvoid Abc_TgSimpleEnumeration(Abc_TgMan_t *)Abc_TtEqual(pTruth, pCopy, nWords)int Abc_TgSymGroupPerm(Abc_TgMan_t *, int, int)pPermE[i] == pMan->pPermT[i]void CheckConfig(Abc_TgMan_t *)pMan->pPermTRev[(int)pMan->pPermT[i]] == iUUUUUUUU33333333""""""""DDDDDDDD 00000000""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333d7 D 2ICanonical form verification failed!ABC_CONST(0x0%d }, { nVars >= 1 && nVars <= 8src/opt/dau/dauCount.cint Abc_TtCountOnesInCofsQuick_rec(word *, int, int *)Res1 == Res2void Abc_TtCountOnesInCofsTest2()Store1[i] == Store2[i]void Abc_TtCountOnesInCofsTest() !a *!b !a * b a *!b a * b a + b%c %c """"""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333KKKKKKKKKKKKKKKKKKK#*1>KXUUUUUUUU33333333""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333src/opt/dau/dauDsd.cint *Dau_DsdComputeMatches(char *)pStr1 < pLimit1 || pStr2 < pLimit2int Dau_DsdNormalizeCompare(char *, int *, int, int)void Dau_DsdNormalize_rec(char *, char **, int *)pStore - pBuffer == *p - pOldint Dau_DsdCountAnds_rec(char *, char **, int *)word Dau_Dsd6TruthCompose_rec(word, word *, int)Func == s_Truths6[0] || Func == s_Truths6Neg[0]word Dau_Dsd6ToTruth_rec(char *, char **, int *, word *)**p == '{' && *q2 == '}'*p == q2*pOld - 'a' < nVarsi == nVarsword Dau_Dsd6ToTruth(char *)void Dau_DsdTruth6Compose_rec(word, word (*)[64], word *, int, int)nWordsF > 1void Dau_DsdTruthCompose_rec(word *, word (*)[64], word *, int, int)**p - 'a' >= 0 && **p - 'a' < nVarsvoid Dau_DsdToTruth_rec(char *, char **, int *, word **, word *, int)word *Dau_DsdToTruth(char *, int)Pos < DAU_MAX_STRint Dau_DsdPerform_rec(word, char *, int, int *, int)nVarsNew > 0Cof0[v] != Cof1[v](%c%c)(%c!%c)(!%c%c)(!%c!%c)[%c%c]nSizeNonDec > 0int Dau_DsdCheck1Step(void *, word *, int, int *)pVarPrios[i] >= 0 && pVarPrios[i] < nVarsInitint Dau_Dsd6DecomposeSingleVar(Dau_Dsd_t *, word *, int *, int)int Dau_DsdDecomposeSingleVar(Dau_Dsd_t *, word *, int *, int)nVars > 0 && nVars <= nVarsInitint Dau_DsdDecomposeInt(Dau_Dsd_t *, word *, int)fSplitPrime || Status != 1int Dau_DsdDecompose(word *, int, int, int, char *)int Dau_DsdDecomposeLevel(word *, int, int, int, char *, int *)[dc{abef}](())_npn/npn/dsd10.txtnSizeNonDec == 0void Dau_DsdTest555()%s -> %s Finished trying %d decompositions. Time3v > uint Dau_Dsd6DecomposeDoubleVarsOne(Dau_Dsd_t *, word *, int *, int, int, int)pBuffer[0]v != uvoid Dau_DsdInsertVarCache(Dau_Dsd_t *, int, int, int)Status > 0 && Status < 4p->Cache[v][u] == 0strlen(pStr) < 8int Dau_DsdAddVarDef(Dau_Dsd_t *, char *)p->nVarsUsed < 32<%c%c%s%c>int Dau_DsdFindVarDef(int *, int, int)nVars > 2int Dau_DsdWritePrime(Dau_Dsd_t *, word *, int *, int)vBest != -1nNonDecSize == 0int Dau_DsdDecomposeDoubleVarsOne(Dau_Dsd_t *, word *, int *, int, int, int)Status != 0int Dau_DsdFindSupportOne(Dau_Dsd_t *, word *, int *, int, int, int)int Abc_TtCheckEqualCofs(word *, int, int, int, int, int)iVar < jVarnVarsInit >= 0 && nVarsInit <= 16void Dau_DsdInitialize(Dau_Dsd_t *, int)%s%c%s%s%s%s%c%s%c%s%s%s%s%s%s%cVARIABLE NUMBER %d: *aKKKKKKKKKKKKKKKKKKK#*1>KXUUUUUUUU33333333src/opt/dau/dauGia.cint Dau_DsdToGiaCompose_rec(Gia_Man_t *, word, int *, int)int Dau_DsdToGia2_rec(Gia_Man_t *, char *, char **, int *, int *, Vec_Int_t *)int Dau_DsdToGia2(Gia_Man_t *, char *, int *, Vec_Int_t *)nFans > 1int Dau_DsdBalance(Gia_Man_t *, int *, int, int)int Dau_DsdToGia_rec(Gia_Man_t *, char *, char **, int *, int *, Vec_Int_t *)int Dau_DsdToGia(Gia_Man_t *, char *, int *, Vec_Int_t *)Vec_IntSize(vLeaves) <= DAU_DSD_MAX_VARint Dsm_ManTruthToGia(void *, word *, Vec_Int_t *, Vec_Int_t *)Calls = %d. NonDSD = %d. Non1Step = %d. void *Dsm_ManDeriveGia(void *, int)void Gia_ObjSetAndLevel(Gia_Man_t *, Gia_Obj_t *)void Gia_ObjSetXorLevel(Gia_Man_t *, Gia_Obj_t *)Gia_ObjIsMux(p,pObj)void Gia_ObjSetMuxLevel(Gia_Man_t *, Gia_Obj_t *)void Gia_ObjSetBufLevel(Gia_Man_t *, Gia_Obj_t *)src/opt/dau/dauMerge.cint Dau_DsdMergeStatus_rec(char *, char **, int *, int, int *)nTotal > 1void Dau_DsdMergeSubstitute_rec(Dau_Sto_t *, char *, char **, int *, int *, int)Status == 3Status != 3void Dau_DsdRemoveBraces_rec(char *, char **, int *)**p == ')' || **p == ']'char *Dau_DsdMerge(char *, int *, char *, int *, int, int, int)(%s%s)[!(a[be])!(c!df)]void Dau_DsdMergeMatches(char *, int *)pDsd[i]-'a' < DAU_MAX_VARvoid Dau_DsdMergeVarPres(char *, int *, int *, int)pVarPres[i] == 1 || pVarPres[i] == 2int Dau_DsdMergeCreateMaps(int *, int, int *, int *)pDsd[pMatches[i]] == '>'void Dau_DsdMergeInlineDefinitions(char *, int *, Dau_Sto_t *, char *, int)pRes - pBegin < DAU_MAX_STRGHHH!H.H|HHHHHHNNNNNNWWL[[.[[ \||} }}(}1}‚˂҂ """"""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333UUUUUUUU33333333 nVars == nVarsB + nVarsFsrc/opt/dau/dauNonDsd.cint Dau_DecCheckSetTop5(word *, int, int, int, int, int, int *, word *, word *)nVarsF >= 1 && nVarsF <= 5s == nVarsSb == nVarsB-nVarsSint Dau_DecCheckSetTop6(word *, int, int, int, int, int, int *, word *, word *)nVarsF >= 6nVars >= 3 && nVars <= 16int Dau_DecCheckSetTopOld(word *, int, int, int, int, int, word **, word **, word **)nVars == nVarsF + nVarsBnVarsF >= 1 && nVarsF <= nVars - 2nVarsB >= 2 && nVarsB <= nVars - 1nVarsS >= 0 && nVarsS <= nVarsB - 2maskS > 0 && maskS < (1 << nVarsB)i == nVarsS(maskS & uMaskValue) == uMaskValuevoid Dau_DecSortSet(unsigned int, int, int *, int *, int *)S =%2d D =%2d C =%2d x=void Dau_DecPrintSet(unsigned int, int, int) y=xThe %d-variable set family contains %d sets: c == nVars - sizeBvoid Dau_DecMoveFreeToLSB(word *, int, int *, int *, int, int)Abc_TtHasVar( p, nVars, v )Vec_Int_t *Dau_DecFindSets_int(word *, int, int **)pStr[v] - 'a' < nVarsvoid Dau_DecVarReplace(char *, int *, int)int Dau_DecDecomposeSet(word *, int, unsigned int, word *, word *, int *, int *, int *, int *, int *)nVarsS >= 0 && nVarsS <= 6nVarsF + nVarsS + 1 <= 6nVarsU + nVarsS <= 6c == nVarsint Dau_DecVerify(word *, int, char *, char *)nWordsD >= 1nWordsC > 1 Verification failed%24s int Dau_DecPerform(word *, int, unsigned int)nVarsD == nVarsU + nVarsSnVarsC == nVarsF + nVarsS + 1void Dau_DecTrySets(word *, int, int)This %d-variable function has %d decomposable variable sets: Set %4d : int Dau_DecCheckSetAny(word *, int, int, int, int, word *, word *, word *)int Dau_DecCheckSet5(word *, int, int, int, int, word *, word *, word *)fFound0c >= 2void Dau_DecGetMinterm(word *, int, int, int)int Dau_DecCheckSet6(word *, int, int, int, int, word *, word *, word *) Decomposition does not existFinished %08x. Classes = %6d. tTemp == tCursrc/opt/dau/dauNpn.cvoid Dau_TruthEnum(int)Computed %d NPN classes of %d variables. tableW%d.dataFinished reading file "%s". File reading((tNorm >> Digit) & 1) == 0int Dau_AddFunction(word, int, unsigned int *, Vec_Int_t *, Vec_Int_t *)Nodes = %2d. New = %6d. Total = %6d. New = %6d. Total = %6d. nSupp == 6 || !Abc_Tt6HasVar(uTruth, nVars-1-nSupp)void Dau_NetworkEnum(int)Exact NPN computation timeNodes = %2d. Semi-canonical = %8d. Canonical = %8d. Total = %8d.npn%d%d.ttdDumped file "%s" with %10d classes after exploring %10d frontiers. nVars == 4 || nVars == 5void Dau_DumpFuncs(Vec_Mem_t *, Vec_Int_t *, int, int)func%d_min%d.tt%04x %08x Dumped %8d %d-node %d-input functions into file. N =%2d | C =%12.0f New%d =%10d All%d =%10d | New%d =%8d All%d =%8d Two =%6d Vec_MemEntryNum(vTtMem) == Vec_IntSize(vNodSup)int Dau_InsertFunction(Abc_TtHieMan_t *, word *, int, int, int, int, Vec_Mem_t *, Vec_Int_t *, int, abctime)nVars >= 3 && nVars <= nInputs && nInputs <= 6void Dau_FunctionEnum(int, int, int, int, int, int)n-1 == (NodSup >> 16)!Abc_Tt6HasVar(*pTruth, nSupp)n-2 == (NodSup >> 16)p->vTable == NULL && p->vNexts == NULLvoid Vec_MemHashAlloc(Vec_Mem_t *, int)Final results:""""""""DDDDDDDD 00000000UUUUUUUU33333333""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333Cannot alloc memory for table.Cannot alloc memory for marks.4&<&C&J&Q&X&_&f&t&m&z0i11G10z0i11G1011e11111111011110""""""""DDDDDDDD 00000000src/opt/dau/dauNpn2.cchar *Dau_ParseFormulaEndToken(char *)word Dau_ParseFormula_rec(char *, char *)pBeg[pEnd-pBeg-1] == ')'~((~~d&~(~~b&c))^(~(~a&~d)&~(~c^~b)))r == tvoid Dau_ParseFormulaTest()int Dau_ParseFormulaAig_rec(Gia_Man_t *, char *, char *)func_enum_aigVerification failed in line %d: %s Verification succeeded for %d functions and failed for %d functions. lib4var.txtFinish constructing AIG for %d structures. pTable[i] < ivoid Dtt_ManRenum(int, unsigned int *, int *)The total number of NPN classes = %d. Class < (unsigned)p->nClassesvoid Dtt_ManAddVisited(Dtt_Man_t *, unsigned int, int)p->pNodes[Class] == np->pVisited[Class]void Dtt_ManProcessVisited(Dtt_Man_t *)tCur == (((word)Truth << 32) | (word)Truth)Vec_Int_t *Dtt_ManCollect(Dtt_Man_t *, unsigned int, Vec_Int_t *)nObjs == Vec_IntSize(p->vTruths)void Dtt_ManAddFunction(Dtt_Man_t *, int, int, int, int, unsigned int)nObjs == Vec_IntSize(p->vConfigs)nObjs == Vec_IntSize(p->vClasses)nNodes < 32%c =%2d | C =%12.0f | New%d =%10d All%d =%10d | Multi =%10d | N = %2d : NPN = %6d n=%d : Prev < Entryvoid Dtt_PrintMulti1(Dtt_Man_t *)Log < 15void Dtt_PrintMulti(Dtt_Man_t *)n=%2d : All = %7d Ave = %6.2f [%08x(%03d),%d%d%d%d%d,%d%d%d%d%d]~(~%s&~%s)~(%s&%s)~(~%s&%s)~(%s&~%s)~(%s^%s)~%cvoid Dtt_MakePI(int, char *)%08x = %s void Dtt_ProcessType(int *, int)int Dtt_Check(unsigned int, unsigned int, unsigned int, int *)void Dtt_FindNP(Dtt_Man_t *, unsigned int, unsigned int, unsigned int, int *, int *, int)Dumped file "%s". int Dtt_ManGetFun(Dtt_Man_t *, unsigned int, int)NPN classes for each node count (N):䋏䋏 20?0([<{)]>} p->nMem < p->nMemAllocsrc/opt/dau/dauTree.cDss_Obj_t *Dss_ObjAllocNtk(Dss_Ntk_t *, int, int, int)i == (int)pObj->nFansDss_Obj_t *Dss_ObjCreateNtk(Dss_Ntk_t *, int, Vec_Int_t *)!Dss_IsComplement(pObj)void Dss_NtkPrint_rec(Dss_Ntk_t *, Dss_Obj_t *)int Dss_NtkCreate_rec(char *, char **, int *, Dss_Ntk_t *, word *)Dss_ObjFaninC(pObj, k)void Dss_NtkCheck(Dss_Ntk_t *)pFanin->Type != DAU_DSD_XOR!Dss_ObjFaninC(pObj, 0)nPerms == (int)Dss_Regular(p->pRoot)->nSuppvoid Dss_NtkTransform(Dss_Ntk_t *, int *)Type != DAU_DSD_MUX || Vec_IntSize(vFaninLits) == 3Dss_Obj_t *Dss_ObjCreate(Dss_Man_t *, int, Vec_Int_t *, word *)Type != DAU_DSD_MUX || !Abc_LitIsCompl(Vec_IntEntry(vFaninLits, 0))Type != DAU_DSD_MUX || !Abc_LitIsCompl(Vec_IntEntry(vFaninLits, 1)) || !Abc_LitIsCompl(Vec_IntEntry(vFaninLits, 2))Type != DAU_DSD_AND || Abc_LitIsCompl(Vec_IntEntry(vFaninLits, i)) || Dss_ObjType(pFanin) != DAU_DSD_ANDType != DAU_DSD_XOR || Dss_ObjType(pFanin) != DAU_DSD_XORpPrev == NULL || Dss_ObjCompare(p->vObjs, pPrev, pFanin) <= 0p->nCache == 0void Dss_ManCacheAlloc(Dss_Man_t *)p->nCache != 0void Dss_ManCacheFree(Dss_Man_t *)Time begin Time decompTime lookupTime end void Dss_ManPrint_rec(FILE *, Dss_Man_t *, Dss_Obj_t *, int *, int *)nSupp == (int)Dss_VecObj(p->vObjs, Abc_Lit2Var(iDsdLit))->nSuppvoid Dss_ManPrintOne(FILE *, Dss_Man_t *, int, int *)int Dss_ManCheckNonDec_rec(Dss_Man_t *, Dss_Obj_t *)dss_tts.txtTotal number of objects = %8d Non-DSD objects (max =%2d) = %8d Non-DSD structures = %8d Memory used for objects = %6.2f MB. Memory used for array = %6.2f MB. Memory used for hash table = %6.2f MB. Memory used for cache = %6.2f MB. Cache hits = %8d %8d Cache misses = %8d %8d Cache entries = %8d %8d (*pnSupp) <= nVarsvoid Dss_ManComputeTruth_rec(Dss_Man_t *, Dss_Obj_t *, int, word *, int *, int *)word *Dss_ManComputeTruth(Dss_Man_t *, int, int, int *)nSupp == (int)Dss_Regular(pObj)->nSuppp->nVars == pNtk->nVarsint Dss_NtkRebuild(Dss_Man_t *, Dss_Ntk_t *)Type == DAU_DSD_AND || pPerm == NULLint Dss_ManOperation(Dss_Man_t *, int, int *, int, unsigned char *, word *)!Dss_IsComplement(pChild)(int)pFun->nFans == Dss_VecLitSuppSize(p->vObjs, pFun->iDsd)Dss_Fun_t *Dss_ManOperationFun(Dss_Man_t *, int *, int)%d %d -> %d pMapGtoL[g] >= 0Dss_Ent_t *Dss_ManSharedMap(Dss_Man_t *, int *, int *, int **, unsigned int)Paramater DAU_MAX_VAR (%d) smaller than LUT size (%d). iDsd[0] <= iDsd[1]int Dss_ManMerge(Dss_Man_t *, int *, int *, int **, unsigned int, int, unsigned char *, word *)nFans[0] == Dss_VecLitSuppSize(p->vObjs, iDsd[0])nFans[1] == Dss_VecLitSuppSize(p->vObjs, iDsd[1])nFans[0] + nFans[1] <= nKLutSize + Dss_WordCountOnes(uSharedMask)(int)pFun->nFans <= nKLutSizenSupp == (int)pFun->nFansiDsd0 <= iDsd1int Mpm_FuncCompute(Dss_Man_t *, int, int, Vec_Str_t *, int *, int *)(int)pFun->nFans <= *pnLeavespObj->Type == DAU_DSD_PRIMEint Dss_ObjCheckTransparent(Dss_Man_t *, Dss_Obj_t *)(!(a!(bh))[cde]!(fg))Dss_Obj_t *Dss_ObjFanin(Vec_Ptr_t *, Dss_Obj_t *, int)Dss_Obj_t *Dss_ObjChild(Vec_Ptr_t *, Dss_Obj_t *, int)(Type == DAU_DSD_PRIME) == (pTruth != NULL)unsigned int Dss_ObjHashKey(Dss_Man_t *, int, Vec_Int_t *, word *)p->nFans >= 2int Dss_FunWordNum(Dss_Fun_t *)ERROR. No variable in the support of f, but f isn't constant! nNested < DSC_MAX_VARsrc/opt/dsc/dsc.cint *Dsc_ComputeMatches(char *)int Dsc_CountAnds_rec(char *, char **, int *)UUUUUUUU33333333DSC ERROR: Final DSC node found, but differs from target function.tCur == pCells[k].uTruthsrc/opt/sfm/sfmArea.cVec_Int_t *Abc_NtkPrecomputeCellPairs(Mio_Cell2_t *, int)In this library, %d cell pairs have equal functions (for example, %s and %s). nCells == Vec_IntSize(vFirst)Vec_Int_t *Abc_NtkPrecomputeFirsts(Mio_Cell2_t *, int)%3d : %8s Fanins = %d } Index = %d Gain = %6.2f Used records = %d. All records = %d. void Abc_NtkPrecomputeCellPairsTest()int Abc_ObjChangeEval(Abc_Obj_t *, Vec_Int_t *, Vec_Int_t *, int, int *)iFanin > 0 && pNodeInfo[3*iFanin] != -1void Abc_ObjChangePerform(Abc_Obj_t *, Vec_Int_t *, Vec_Int_t *, int, Vec_Int_t *, Vec_Ptr_t *, Vec_Ptr_t *, Mio_Cell2_t *)Abc_ObjFanoutNum(pNext) == 0Total gain in area = %6.2f after %d changes (including %d inverters). """"""""DDDDDDDD 00000000src/opt/sfm/sfmCnf.cint Sfm_TruthToCnf(word, word *, int, Vec_Int_t *, Vec_Str_t *)Nodes = %d. Try = %d. Resub = %d. Div = %d (ave = %d). SAT calls = %d. Timeouts = %d. MaxDivs = %d. OthSfm_ObjIsNode(p, iNode)src/opt/sfm/sfmCore.cint Sfm_NodeResubSolve(Sfm_Ntk_t *, int, int, int)f >= 0 && f < Sfm_ObjFaninNum(p, iNode)%5d : Lev =%3d. Leaf =%3d. Node =%3d. Div=%3d. Fanin =%4d (%d/%d). MFFC = %d iFaninRem != -1Vec_IntEntry(p->vDivs, iVar) != iFaninSkipNode %d: Fanin %d (%d) can be removed. Node %d: Fanin %d (%d) can be replaced by divisor %d (%d). Obj %3d : Fixed %d Empty %d Truth Performing MFS with %d PIs, %d POs, %d nodes (%d flexible, %d fixed, %d empty). Vec_IntEntry(&p->vId2Var, iObj) > 0src/opt/sfm/sfmInt.hint Sfm_ObjSatVar(Sfm_Ntk_t *, int)src/opt/sfm/sfmDec.cSfm_Dec_t *Sfm_DecStart(Sfm_Par_t *, Mio_Library_t *, Abc_Ntk_t *)Level count mismatch at node %d. int Sfm_DecPrepareSolver(Sfm_Dec_t *)p->iTarget < nWinSizeGate != -1nSatVars == sat_solver_nvars(p->pSat)Vec_IntSize(vRoots) == 1%s-SET of object %d (divs = %d) with gate "%s" and fanins: Implications: %s%d(%d) Counts[c][0] >= 0 && Counts[c][1] >= 0void Sfm_DecVarCost(Sfm_Dec_t *, word (*)[8], int, int (*)[2])int Sfm_MffcDeref_rec(Abc_Obj_t *)int Sfm_DecMffcAreaReal(Abc_Obj_t *, Vec_Int_t *, Vec_Int_t *)Area1 == Area2nAssump <= SFM_SUPP_MAXint Sfm_DecPeformDec_rec(Sfm_Dec_t *, word *, int *, int *, int, word (*)[8], int, int) Object %d Divs = %d. Nodes = %d. Mffc = %d. Mffc area = %.2f. Pat0 = %d. Pat1 = %d. Cofactor: Abc_Lit2Var(Impls[0]) == Abc_Lit2Var(Impls[1])Found variable %s%d. Vec_IntSize(&p->vImpls[!c]) < SFM_WIN_MAX-10nFinal <= 6Found %d-input AND/OR gate. Best var %d p->pPars->fArea == 1int Sfm_DecPeformDec2(Sfm_Dec_t *, Abc_Obj_t *) Node %4d : MFFC %2d p->pPars->nDecMax <= SFM_DEC_MAXDec %d: Pat0 = %2d Pat1 = %2d NO DEC. Dec %d: Pat0 = %2d Pat1 = %2d Supp = %d nSupp[i] <= p->pPars->nVarMaxRetValue <= 2p->AreaMffc <= AreaThisGainThis >= 0Best %d: %d iLibObjBest >= 0nSupp[iBest] <= p->pPars->nVarMaxp->pPars->fArea == 0int Sfm_DecPeformDec3(Sfm_Dec_t *, Abc_Obj_t *)int Abc_NtkDfsCheck_rec(Abc_Obj_t *, Abc_Obj_t *)void Abc_NtkDfsReverseOne_rec(Abc_Obj_t *, Vec_Int_t *, int, int)int Abc_NtkDfsOne_rec(Abc_Obj_t *, Vec_Int_t *, int, int)%d:%d(%d) nMffcMax > 0void Sfm_DecMarkMffc(Abc_Obj_t *, int, int, int, Vec_Int_t *, Vec_Int_t *, Sfm_Tim_t *, Sfm_Mit_t *)Vec_IntSize(vMffc) <= nMffcMaxint Sfm_DecExtract(Abc_Ntk_t *, Sfm_Par_t *, Abc_Obj_t *, Vec_Int_t *, Vec_Int_t *, Vec_Wec_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Sfm_Tim_t *, Sfm_Mit_t *)Vec_IntSize(vRoots) > 0Vec_IntSize(vMffc) <= pPars->nMffcMaxnOldSize == Vec_IntSize(vMap)Vec_IntSize(vMap) == Vec_IntSize(vGates)Limit < Vec_IntSize(vGates)Abc_Obj_t *Sfm_DecInsert(Abc_Ntk_t *, Abc_Obj_t *, int, Vec_Int_t *, Vec_Wec_t *, Vec_Int_t *, Vec_Ptr_t *, int, int, Vec_Wrd_t *, Vec_Int_t *, Sfm_Mit_t *)Limit == Vec_IntSize(vMap)iGateNew >= 0 && iGateNew != iGate && iFaninNew >= 0Abc_ObjFaninNum(pObjNew) == Mio_GateReadPinNum((Mio_Gate_t *)pObjNew->pData)Node = %d. Try = %d. Change = %d. Const0 = %d. Const1 = %d. Buf = %d. Inv = %d. Gate = %d. AndOr = %d. Effort = %d. NoDec = %d. MaxDiv = %d. MaxWin = %d. AveDiv = %d. AveWin = %d. Calls = %d. (Sat = %d. Unsat = %d.) Over = %d. T/O = %d. Lib Win Cnf Sat Sat UnsatTimingALL Cone sizes: Gate sizes: void Abc_NtkAreaOpt2(Sfm_Dec_t *)void Abc_NtkDelayOpt(Sfm_Dec_t *)Vec_IntSize(&p->vObjGates) - Limit > 0Vec_IntSize(&p->vObjGates) - Limit <= 2p->pMit || p->DelayMin == 0 || p->DelayMin == Sfm_ManReadObjDelay(p, Abc_ObjId(pObjNew))Node %5d %5d : I =%3d. Cand = %5d (%6.2f %%) Old =%8.2f. New =%8.2f. Final =%8.2f. WNS =%8.2f. Remapping parameters: TFO = %d. TFI = %d. FanMax = %d. WinMax = %d. Confl = %d. MffcMin = %d. MffcMax = %d. DecMax = %d. Pivot = %d. Win = %d. Delta = %.2f ps. 0-cost = %s. Effort = %s. Sim = %s. p->iTarget == pObj->iTempvoid Sfm_ObjSetupSimInfo(Abc_Obj_t *)p->pPars->fUseSimAbc_ObjFaninNum(pObj) <= 6word Sfm_ObjSimulate(Abc_Obj_t *)void Sfm_NtkSimulate(Abc_Ntk_t *)Best : NO DEC.""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333The number of assumption is more than MFFC size.iFanin >= 0 && iFanin < nFaninssrc/opt/sfm/sfmLib.cint Sfm_LibFindComplInputGate(Vec_Wrd_t *, int, int, int, int *)nVars <= SFM_SUPP_MAXSfm_Lib_t *Sfm_LibStart(int, int, int)InTop >= 0 && InTop < (int)pCellTop->nFaninsword Sfm_LibTruth6Two(Mio_Cell2_t *, Mio_Cell2_t *, int)(int)pCellBot->nFanins + (int)pCellTop->nFanins == k + 1void Sfm_LibTruth8Two(Mio_Cell2_t *, Mio_Cell2_t *, int, word *)void Sfm_LibPrepareAdd(Sfm_Lib_t *, word *, int *, int, Mio_Cell2_t *, Mio_Cell2_t *, int)Vec_IntSize(&p->vProfs) == p->nObjspCellBot->Id < 128pCellTop->Id < 128k == nFaninsSfm_Lib_t *Sfm_LibPrepare(int, int, int, int, int)Skipping gate "%s" with non-DSD function %s nFanins >= 2 && nFanins <= nVarsAbc_TtEqual(tTemp1, tCur, p->nWords)Library processing: Var = %d. Cell = %d. Fun = %d. Obj = %d. Ave = %.2f. Skip = %d. Rem = %d. %-20s(F = %d A =%6.2f Num =%5d Hit =%4d !Abc_TtIsConst0(pTruth, p->nWords) && !Abc_TtIsConst1(pTruth, p->nWords) && !Abc_TtEqual(pTruth, s_Truth8[0], p->nWords) && !Abc_TtOpposite(pTruth, s_Truth8[0], p->nWords)int Sfm_LibFindDelayMatches(Sfm_Lib_t *, word *, int *, int, Vec_Ptr_t *, Vec_Ptr_t *)Not found in the precomputed library: int Sfm_LibImplementSimple(Sfm_Lib_t *, word *, int *, int, Vec_Int_t *, Vec_Wec_t *)pGate == pCellB->pMioGateint Sfm_LibImplementGatesArea(Sfm_Lib_t *, int *, int, int, Vec_Int_t *, Vec_Wec_t *)pGate == pCellT->pMioGate./src/map/mio/exp.h""""""""DDDDDDDD 00000000UUUUUUUU33333333There is no current library.Vec_IntSize(vArray) == 0 && Vec_StrEntry(vFixed, i) == (char)0src/opt/sfm/sfmNtk.cvoid Sfm_CheckConsistency(Vec_Wec_t *, int, int, Vec_Str_t *)Fanin + nPos < Vec_WecSize(vFanins)Vec_IntSize(vArray) == 1 && Vec_StrEntry(vFixed, i) == (char)0Vec_IntSize(vArray) == Vec_IntCap(vArray)void Sfm_CreateFanout(Vec_Wec_t *, Vec_Wec_t *)Vec_IntSize(vLevels) == 0void Sfm_CreateLevel(Vec_Wec_t *, Vec_Int_t *, Vec_Str_t *)Vec_IntSize(vLevelsR) == 0void Sfm_CreateLevelR(Vec_Wec_t *, Vec_Int_t *, Vec_Str_t *)void Sfm_NtkRemoveFanin(Sfm_Ntk_t *, int, int)!Sfm_ObjIsPo(p, iFanin)void Sfm_NtkAddFanin(Sfm_Ntk_t *, int, int)Vec_IntFind( Sfm_ObjFiArray(p, iNode), iFanin ) == -1Vec_IntFind( Sfm_ObjFoArray(p, iFanin), iNode ) == -1void Sfm_NtkDeleteObj_rec(Sfm_Ntk_t *, int)void Sfm_NtkUpdate(Sfm_Ntk_t *, int, int, int, word)Sfm_ObjFaninNum(p, iNode) <= 6p->pPars->nTfoLevMax > 0src/opt/sfm/sfmSat.cint Sfm_NtkWindowToSolver(Sfm_Ntk_t *)Vec_IntSize(p->vRoots) > 0Vec_IntEntry(p->vTfo, 0) != p->iPivotNodeVec_IntSize(p->vDivIds) <= 6word Sfm_ComputeInterpolant(Sfm_Ntk_t *)!Abc_InfoHasBit( (unsigned *)pSign, p->nCexes)Vec_IntEntry(&p->vId2Var, iObj) == -1void Sfm_ObjSetSatVar(Sfm_Ntk_t *, int, int)void Sfm_ObjCleanSatVar(Sfm_Ntk_t *, int)The problem is UNDEC.The problem is SAT.Abc_ObjFaninNum(pNode) <= 6src/opt/sfm/sfmTim.cvoid Sfm_TimNodeRequired(Sfm_Tim_t *, Abc_Obj_t *)void Sfm_TimCriticalPath_int(Sfm_Tim_t *, Abc_Obj_t *, Vec_Int_t *, int)int Sfm_TimCriticalPath(Sfm_Tim_t *, int)DeltaCrit > 0 && DeltaCrit < Scl_Flt2Int(1000.0)Sfm_Tim_t *Sfm_TimStart(Mio_Library_t *, Scl_Con_t *, Abc_Ntk_t *, int)Max delay = %.2f. Path = %d (%d). Vec_IntSize(vTimeNodes) > 0 && Vec_IntSize(vTimeNodes) <= 2void Sfm_TimUpdateTiming(Sfm_Tim_t *, Vec_Int_t *)p->DeltaCrit > 0int Sfm_TimSortArrayByArrival(Sfm_Tim_t *, Vec_Int_t *, int)-ABC_INFINITY/2 < Time && Time < ABC_INFINITY/2Window >= 0 && Window <= 100int Sfm_TimPriorityNodes(Sfm_Tim_t *, Vec_Int_t *, int)i == Mio_GateReadPinNum(pGate)void Sfm_TimGateRequired(Sfm_Tim_t *, Mio_Gate_t *, int **, int *)void Sfm_TimNodeArrival(Sfm_Tim_t *, Abc_Obj_t *)void Sfm_TimUpdateClean(Sfm_Tim_t *)void Sfm_TimGateArrival(Sfm_Tim_t *, Mio_Gate_t *, int **, int *)Sfm_ObjIsNode(p, iObj)src/opt/sfm/sfmWin.cint Sfm_ObjRef_rec(Sfm_Ntk_t *, int)int Sfm_ObjDeref_rec(Sfm_Ntk_t *, int)Sfm_ObjIsNode( p, iObj )int Sfm_ObjMffcSize(Sfm_Ntk_t *, int)void Sfm_NtkDfs_rec(Sfm_Ntk_t *, int, Vec_Int_t *, Vec_Wec_t *, Vec_Int_t *, Vec_Int_t *)void Sfm_NtkComputeRoots_rec(Sfm_Ntk_t *, int, int, Vec_Int_t *, Vec_Int_t *)Sfm_ObjFaninNum(p, iFanout) > 1void Sfm_NtkAddDivisors(Sfm_Ntk_t *, int, int)Sfm_ObjIsNode( p, iNode )int Sfm_NtkCreateWindow(Sfm_Ntk_t *, int, int)Vec_IntSize(p->vDivs) <= p->pPars->nWinSizeMaxVec_IntSize(p->vTfo) > 0Leaves = %5d. Nodes = %5d. Roots = %5d. Divs = %5d. Degree*Prev >= Entrysrc/opt/sbd/sbd.cint Sbd_CountConfigVars(Vec_Int_t *, int, int)Counting topologies for %d inputs and %d degree-%d nodes. Nodes = %2d : This = %8d All = %8d Params = %3d. Qsrc/opt/sbd/sbdCnf.cint Sbd_TruthToCnf(word, int, Vec_Int_t *, Vec_Str_t *) nTimeValidDivs > 0src/opt/sbd/sbdCore.cvoid Sbd_ManUpdateOrder(Sbd_Man_t *, int)void Sbd_ManWindowSim_rec(Sbd_Man_t *, int)Vec_IntSize(p->vDivVars) == Vec_IntSize(p->vDivValues)int Sbd_ManWindow(Sbd_Man_t *, int)Vec_IntSize(p->vDivVars) < Vec_IntSize(p->vWinObjs)Vec_IntSize(p->vDivValues) <= 64Computing %d offset and %d onset minterms for node %d. i == PivotVarint Sbd_ManCheckConst(Sbd_Man_t *, int)Found stuck-at-%d node %d. nCares[0] >= nMintCount && nCares[1] >= nMintCountp->Pivot == Pivotvoid Sbd_ManPrintObj(Sbd_Man_t *, int)Node %d. Useful divisors = %d. Lev : Sims: Ctrl: Exploring %d x %d covering table. Abc_TtGetBit(&MatrC[0][i], nDivs) == Abc_TtGetBit(&MatrC[1][i], nDivs)int Sbd_ManExplore(Sbd_Man_t *, int, word *)MatrC[n][i]Generated matrix with %d x %d entries. OnsetOffsetGenerated cover with %d entries. Candidate support: Node %d: Undecided. Node %d: SAT. Node %d: UNSAT. int Sbd_ManExplore2(Sbd_Man_t *, int, word *)nRows <= 64Node %d: UNSAT. Vec_IntSize(p->vDivSet) < nLeavesint Sbd_ManExploreCut(Sbd_Man_t *, int, int, int *, int *, Sbd_Str_t *, int *)The cut at node %d is not topological. Truth != SBD_SAT_UNDEC && Truth != SBD_SAT_SATnNodesBot == nNodesBot1 + nNodesBot2nNodesBot == p->pPars->nLutSizenNodesTop <= p->pPars->nLutSize-1nNodesDiff >= 0 && nNodesDiff <= 3nNodesBot == 2*p->pPars->nLutSizenNodesBot > p->pPars->nLutSizenNodesBot <= 2*p->pPars->nLutSizenNodesTop <= p->pPars->nLutSize-2nNodesDiff >= 0 && nNodesDiff <= 2nNodesBot2 == p->pPars->nLutSizenNodesBot1 == p->pPars->nLutSize-1nNodesBot2 <= p->pPars->nLutSizenNodesBot1 <= p->pPars->nLutSize-1nLeaves <= p->pPars->nCutSizeint Sbd_ManExplore3(Sbd_Man_t *, int, int *, Sbd_Str_t *)nLeaves == nSizeFreeVar - FreeVarStart <= SBD_FVAR_MAXiFan0 != iFan1int Sbd_ManMergeCuts(Sbd_Man_t *, int)Vec_IntEntry(p->vLutLevs, Node) == 0pCutRes[0] <= p->pPars->nLutSizeDelay %d. void Sbd_ManFindCut_rec(Gia_Man_t *, Gia_Obj_t *)void Sbd_ManFindCutUnmark_rec(Gia_Man_t *, Gia_Obj_t *)pCut[0] <= p->pPars->nLutSizevoid Sbd_ManFindCut(Sbd_Man_t *, int, Vec_Int_t *)Vec_IntEntry(p->vMirrors, Pivot) == -1int Sbd_ManImplement(Sbd_Man_t *, int, word)Replacing node %d by literal %d. Vec_IntSize(p->vLutLevs) == iObjLastVec_IntEntry(p->vLutLevs, Pivot) == iCurLevint Sbd_ManImplement2(Sbd_Man_t *, int, int, Sbd_Str_t *)Vec_IntEntry(p->vLits, Vec_IntSize(p->vLits)-nStrs+i) == -1i == Vec_IntSize(p->vMirrors)i == Vec_IntSize(p->vLutLevs)!iNewLev || iNewLev < iCurLevvoid Sbd_ManDeriveMapping_rec(Sbd_Man_t *, Gia_Man_t *, int)Vec_IntSize(vLeaves) <= p->pPars->nLutSizevoid Sbd_ManDeriveMapping(Sbd_Man_t *, Gia_Man_t *)void Sbd_ManDerive_rec(Gia_Man_t *, Gia_Man_t *, int, Vec_Int_t *)Gia_Man_t *Sbd_NtkPerform(Gia_Man_t *, Sbd_Par_t *)K = %d. S = %d. N = %d. P = %d. Try = %d. Use = %d. C = %d. 1 = %d. 2 = %d. 3a = %d. 3b = %d. Lev = %d. CovQbfint Sbd_ManAddCube2(word (*)[64], int, word *)nRows <= nRowLimitint Sbd_ManAddCube1(int, word *, int, word)Cannot find a feasible cover.PPPP!Gia_ObjIsBuf(pObj)src/opt/sbd/sbdCut.cvoid Sbd_StoMergeCuts(Sbd_Sto_t *, int)!Gia_ObjIsMux(p->pGia, pObj)nCutsR > 0 && nCutsR < nCutNumnLutSize <= nCutSizeSbd_Sto_t *Sbd_StoAlloc(Gia_Man_t *, Vec_Int_t *, int, int, int, int, int)nCutSize < SBD_CUT_NO_LEAFnCutSize > 1 && nCutSize <= SBD_MAX_CUTSIZEnCutNum > 1 && nCutNum < SBD_MAX_CUTNUMiObj == Vec_IntSize(p->vDelays)void Sbd_StoComputeCutsObj(Sbd_Sto_t *, int, int, int)iObj == Vec_IntSize(p->vLevels)iObj == Vec_WecSize(p->vCuts)iObj == p->Pivotvoid Sbd_StoSaveBestDelayCut(Sbd_Sto_t *, int, int *)iObj == Vec_IntSize(p->vRefs)void Sbd_StoRefObj(Sbd_Sto_t *, int, int)iMirror < iObjLit0m == -1p->Pivot == iObjint Sbd_StoObjBestCut(Sbd_Sto_t *, int, int, int *)pCutBest->nLeaves <= SBD_DIV_MAXRunning cut computation with LutSize = %d CutSize = %d CutNum = %d: CutPair = %.0f Merge = %.0f (%.2f %%) Eval = %.0f (%.2f %%) Cut = %.0f (%.2f %%) Cut/Node = %.2f Spec = %4d Over = %4d Lev = %4d nSizeB > nSizeCint Sbd_CutSetCutIsContainedOrder(Sbd_Cut_t *, Sbd_Cut_t *)(uTruth[0] & 1) == 0int Sbd_CutComputeTruth(Sbd_Sto_t *, Sbd_Cut_t *, Sbd_Cut_t *, int, int, Sbd_Cut_t *, int)(int)pCutR->nLeaves <= nOldSupp(int)(t & 1) == 0int Sbd_CutComputeTruth6(Sbd_Sto_t *, Sbd_Cut_t *, Sbd_Cut_t *, int, int, Sbd_Cut_t *, int)word Abc_Tt6Expand(word, int *, int, int *, int)int Abc_Tt6MinBase(word *, int *, int)nCuts >= 0int Sbd_CutSetAddCut(Sbd_Cut_t **, int, int)void Sbd_StoComputeDelay(Sbd_Sto_t *, int, Sbd_Cut_t **, int)p->iCutBest >= 0DelayMin < ABC_INFINITYint Sbd_CutSetCheckArray(Sbd_Cut_t **, int)pCut0->nLeaves <= SBD_MAX_CUTSIZEpCut0->Sign == Sbd_CutGetSign(pCut0)pCut0->pLeaves[m] < pCut0->pLeaves[n]Vec_IntSize(vThis) == 0void Sbd_CutAddZero(Sbd_Sto_t *, int)pCut0->nLeaves > 4 && pCut1->nLeaves > 4int Sbd_CutCompare2(Sbd_Cut_t *, Sbd_Cut_t *)""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333UUUUUUUU33333333src/opt/sbd/sbdCut2.cSbd_Srv_t *Sbd_ManCutServerStart(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, int, int, int, int)int Sbd_ManCutIsTopo_rec(Gia_Man_t *, Vec_Int_t *, int)Cut of node %d is not tological int Sbd_ManCutIsTopo(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, int)void Vec_IntIsOrdered(Vec_Int_t *)void Sbd_ManCutReload(Vec_Int_t *, Vec_Int_t *, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Vec_IntEntry(vMirrors, Entry) == -1Vec_IntEntry(vLutLevs, Entry) <= LevStopint Sbd_ManCutCollect_rec(Gia_Man_t *, Vec_Int_t *, int, int, Vec_Int_t *, Vec_Int_t *)int Sbd_ManCutReduceTop(Gia_Man_t *, Vec_Int_t *, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, int)Vec_IntEntry(vLutLevs, Entry) == LevStopVec_IntSize(p->vCut) <= p->nCutSizeint Sbd_ManCutServerFirst(Sbd_Srv_t *, int, int *)int Sbd_ManCutExpandOne(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, int, int)ÎЎݎ掓pStr->nVarIns <= 6src/opt/sbd/sbdLut.cint Sbd_ProblemAddClauses(sat_solver *, int, int, int *, Sbd_Str_t *)pStr->nVarIns <= SBD_DIV_MAXvoid Sbd_ProblemAddClausesInit(sat_solver *, int, int, int *, Sbd_Str_t *)%s%d : iLit == Vec_IntSize(vLits)void Sbd_ProblemPrintSolution(int, Sbd_Str_t *, Vec_Int_t *)nIters == 1void Sbd_ProblemCollectSolution(int, Sbd_Str_t *, Vec_Int_t *)Vec_IntSize(vDivSet) <= SBD_DIV_MAXint Sbd_ProblemSolve(Gia_Man_t *, Vec_Int_t *, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, int, Sbd_Str_t *)nVars + nStrs + nPars <= 256Solution found:src/opt/sbd/sbdPath.cint Sbc_ManAddInternalToPath_rec(Gia_Man_t *, int, Vec_Bit_t *)void Sbc_ManCriticalPath_rec(Gia_Man_t *, int *, int, int, Vec_Bit_t *, int)void Sbc_ManDelayTrace(Gia_Man_t *)pLevels[iFan] + 1 == pLevels[i]AIG = %d. LUT = %d. Lev = %d. Path nodes = %d. Path edges = %d. (%d.) No mapping is available.nLuts >= 1 && nLuts <= 2src/opt/sbd/sbdSat.cVec_Int_t *Sbd_ProblemSetup(Sbd_Pro_t *, int, int, int)iVar == p->nPars + p->nVars + p->nDivsVec_IntEntry(vCnf, i) != -1void Sbd_ProblemLoad1(Sbd_Pro_t *, Vec_Int_t *, int, int *, int, sat_solver *)nLits <= 8void Sbd_ProblemLoad2(Sbd_Pro_t *, Vec_Wec_t *, int, int *, int, sat_solver *)Number of topo vars = %d. sat_solver *Sbd_SolverTopo(int, int, int, int (*)[38][6], int (*)[8], int *, int, int *)Added %d node connectivity constraints. Added %d fanin connectivity constraints. Added %d fanin exclusivity constraints. Added %d node ordering constraints. Added %d two-node non-triviality constraints. Req < MAX_D-1Number of total vars = %d. pDelays[i] < MAX_D-2 | %2d %c | void Sbd_SolverTopoTest()Found %d solutions. nUnused == N - n + 1void Sbd_SolverSynth(int, int, int, int (*)[6])iFan0 < M+niFan1 < M+n {%d, %d}%s // %d M <= 6 && N <= MAX_Nword Sbd_SolverTruth(int, int, int, int (*)[6], int *)M <= MAX_M && N <= MAX_Nword *Sbd_SolverTruthWord(int, int, int, int (*)[6], int *, word *, int)Number of parameters %d x %d = %d. Iter %3d : Mint = %3d. Conflicts =%8d. pLuts[i][k] - M < N - 1int Sbd_SolverFunc(int, int, int, int (*)[6], word *, int *)Finished after %d iterations and %d conflicts. Result (compl = %d): Solution: Solution does not exist.src/opt/sbd/sbdWin.csat_solver *Sbd_ManSatSolver(sat_solver *, Gia_Man_t *, Vec_Int_t *, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, int)Vec_IntEntry( vMirrors, iObj ) < 0sat_solver_nvars(pSat) == nVars + SBD_FVAR_MAXword Sbd_ManSolve(sat_solver *, int, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Vec_IntSize(vDivVars) == Vec_IntSize(vDivValues)int Sbd_ManSolve2(sat_solver *, int, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Abc_Lit2Var(Entry) < 64word Sbd_ManSolverSupp(Vec_Int_t *, int *, int *)Cube[nVars] == '\0'void Sbd_ManSolverPrint(Vec_Int_t *)Pivot = %4d. Divs = %4d. SAT with %d vars and %d cubes. Vec_IntSize(vInds) == nCareMints[0] + nCareMints[1]int Sbd_ManCollectConstants(sat_solver *, int *, int, word **, Vec_Int_t *)Vec_IntSize(vDivVars) < 64int Sbd_ManCollectConstantsNew(sat_solver *, Vec_Int_t *, int, int, word *, word *)int sat_solver_add_and(sat_solver *, int, int, int, int, int, int)UNSAT.src/sat/bsat/satMem.cchar *Sat_MmFixedEntryFetch(Sat_MmFixed_t *)p->nChunks > 0void Sat_MmFixedRestart(Sat_MmFixed_t *)char *Sat_MmFlexEntryFetch(Sat_MmFlex_t *, int)Clause ID = %d. Proof = %d. {Resolvent: {Clause %2d : 0 0 (int)pConflict->nLits <= p->nResLitsAllocsrc/sat/bsat/satInter.cint Int_ManProofTraceOne(Int_Man_t *, Sto_Cls_t *, Sto_Cls_t *)p->pTrail[i] == pReason->pLits[0]Int_ManProofGet(p, pReason) > 0%d * %d %d 0 Recording clause %d: Cannot find variable %d in the temporary resolvent. Recording clause %d: The resolved variable %d is in the wrong polarity. lit_var(p->pResLits[v1]) == VarRecording clause %d: Ran out of space for intermediate resolvent. Recording clause %d: Trying to resolve the clause with more than one opposite literal. Recording clause %d: The final resolvent is wrong. p->nResLits == (int)pFinal->nLitsp->pProofNums[pFinal->Id-1] != p->CounterpClause->nLits > 0int Int_ManProofRecordOne(Int_Man_t *, Sto_Cls_t *)!pClause->fRootp->nTrailSize == p->nRootSizepClause->nLits == 1Found last conflict after adding unit clause number %d! (int)pClause->fA == (Counter < (int)p->pCnf->nClausesA)int Int_ManProcessRoots(Int_Man_t *)(int)pClause->fRoot == (Counter < (int)p->pCnf->nRoots)p->pCnf->nClauses == Counterp->pCnf->pTail->nLits == 0lit_check(pClause->pLits[0], p->pCnf->nVars)p->nVarsAB <= 8void Int_ManPrepareInter(Int_Man_t *)VarAB >= 0 && VarAB < p->nVarsABpCnf->nVars > 0 && pCnf->nClauses > 0int Int_ManInterpolate(Int_Man_t *, Sto_Man_t *, int, unsigned int **)proof.cnf_Vars = %d. Roots = %d. Learned = %d. Resol steps = %d. Ave = %.2f. Mem = %.2f MB pCur->pLits[1] == LitFSto_Cls_t *Int_ManPropagateOne(Int_Man_t *, lit)lit_check(Lit, p->pCnf->nVars)void Int_ManWatchClause(Int_Man_t *, Sto_Cls_t *, lit)Found root level conflict!nVarsAB <= Vec_IntSize(p->vVarsAB)src/sat/bsat/satInterA.cint Inta_ManGlobalVars(Inta_Man_t *)p->pVarTypes[v] != LargeNumint Inta_ManProofTraceOne(Inta_Man_t *, Sto_Cls_t *, Sto_Cls_t *)Inta_ManProofGet(p, pReason) > 0lit_var(Entry) == VarVec_IntSize(p->vResLits) == (int)pFinal->nLitsint Inta_ManProofRecordOne(Inta_Man_t *, Sto_Cls_t *)int Inta_ManProcessRoots(Inta_Man_t *)VarAB >= 0 && VarAB < Vec_IntSize(p->vVarsAB)void Inta_ManPrepareInter(Inta_Man_t *)void *Inta_ManInterpolate(Inta_Man_t *, Sto_Man_t *, abctime, void *, int)Vars = %d. Roots = %d. Learned = %d. Resol steps = %d. Ave = %.2f. Mem = %.2f MB VarAB >= 0 && VarAB < Vec_IntSize(pMan->vVarsAB)Aig_Man_t *Inta_ManDeriveClauses(Inta_Man_t *, Sto_Man_t *, int)Sto_Cls_t *Inta_ManPropagateOne(Inta_Man_t *, lit)void Inta_ManWatchClause(Inta_Man_t *, Sto_Cls_t *, lit)src/sat/bsat/satInterB.cint Intb_ManGlobalVars(Intb_Man_t *)int Intb_ManGetGlobalVar(Intb_Man_t *, int)int Intb_ManProofTraceOne(Intb_Man_t *, Sto_Cls_t *, Sto_Cls_t *)Intb_ManProofGet(p, pReason) > 0v < (int)pReason->nLitsint Intb_ManProofRecordOne(Intb_Man_t *, Sto_Cls_t *)int Intb_ManProcessRoots(Intb_Man_t *)void Intb_ManPrepareInter(Intb_Man_t *)void *Intb_ManInterpolate(Intb_Man_t *, Sto_Man_t *, void *, int)Aig_Man_t *Intb_ManDeriveClauses(Intb_Man_t *, Sto_Man_t *, int)Sto_Cls_t *Intb_ManPropagateOne(Intb_Man_t *, lit)void Intb_ManWatchClause(Intb_Man_t *, Sto_Cls_t *, lit)src/sat/bsat/satInterP.cint Intp_ManProofTraceOne(Intp_Man_t *, Sto_Cls_t *, Sto_Cls_t *)Vec_PtrSize(p->vAntClas) == pFinal->Id - p->nAntStartIntp_ManProofGet(p, pReason) > 0int Intp_ManProofRecordOne(Intp_Man_t *, Sto_Cls_t *)int Intp_ManProcessRoots(Intp_Man_t *)Vec_PtrSize(vClauses) == pClause->Idvoid Intp_ManUnsatCoreVerify(Sto_Man_t *, Vec_Int_t *)void *Intp_ManUnsatCore(Intp_Man_t *, Sto_Man_t *, int, int)p->pCnf->pEmpty->Id - p->nAntStart == Vec_PtrSize(p->vAntClas) - 1Root clauses = %d. Learned clauses = %d. UNSAT core size = %d. UNSAT contains %d learned clauses: %6d : %6d : Sto_Cls_t *Intp_ManPropagateOne(Intp_Man_t *, lit)void Intp_ManWatchClause(Intp_Man_t *, Sto_Cls_t *, lit)UNSAT core verification FAILED. The core verification problem is trivially UNSAT.src/sat/bsat/satProof.c(pNode->pEnts[k] >> 2)void Sat_ProofCheck0(Vec_Set_t *)pNode->Id > 0int Sat_ProofReduce(Vec_Set_t *, void *, int)pFanin->Id > 0hProofPivot >= 1 && hProofPivot <= Vec_SetHandCurrent(vProof)satset *Proof_NodeRead(Vec_Set_t *, int)h <= Vec_SetHandCurrent(p)./src/misc/vec/vecSet.hvoid Vec_SetShrinkS(Vec_Set_t *, int)nWords < (1 << p->nPageSize)int Vec_SetAppendS(Vec_Set_t *, int)nEnts > 0int Proof_NodeWordNum(int)void Vec_SetShrink(Vec_Set_t *, int)ٕA@@z?''2<<<<src/sat/bsat/satSolver.cint sat_solver_get_var_value(sat_solver *, int)void sat_solver_set_var_activity(sat_solver *, int *, int)end - begin > 1int sat_solver_clause_new(sat_solver *, lit *, lit *, int)learnt >= 0 && learnt < 2!(h & 1)clause_id(c) == veci_size(&s->act_clas)begin[0] < s->size*2begin[1] < s->size*2lit_neg(begin[0]) < s->size*2lit_neg(begin[1]) < s->size*2sat_solver_dl(s) == 0int sat_solver_count_assigned(sat_solver *)lits[1] == false_litint sat_solver_propagate(sat_solver *)!s->wlists[2*var].sizevoid sat_solver_setnvars(sat_solver *, int)!s->wlists[2*var+1].sizeint sat_solver_simplify(sat_solver *)s->nLearntMax > 0void sat_solver_reducedb(sat_solver *)nLearnedOld == Sat_MemEntryNum(pMem, 1)nLearnedOld == (int)s->stats.learntspSortValues[Id] >= 0pSortValues[pPerm[0]] <= pSortValues[pPerm[nLearnedOld-1]]c->mark == 0s->stats.learnts == (unsigned)jCounter == nLearnedOldCounter == (int)s->stats.learntsreduceDB: Keeping %7d out of %7d clauses (%5.2f %%) s->iVarPivot >= 0 && s->iVarPivot <= s->sizevoid sat_solver_rollback(sat_solver *)s->iTrailPivot >= 0 && s->iTrailPivot <= s->qtailbegin < endint sat_solver_addclause(sat_solver *, lit *, lit *)| %9.0f | %7.0f %8.0f | %7.0f %7.0f %8.0f %7.1f | %6.3f %% | lit_var(p) < s->sizeint sat_solver_push(sat_solver *, int)sat_solver_dl(s) > 0void sat_solver_pop(sat_solver *)int sat_solver_solve(sat_solver *, lit *, lit *, ABC_INT64_T, ABC_INT64_T, ABC_INT64_T, ABC_INT64_T)Running SAT solver with parameters %d and %d and %d. s->root_level == sat_solver_dl(s)int sat_solver_solve_lexsat(sat_solver *, int *, int)Abc_LitIsCompl(pLits[iLitFail])int sat_solver_minimize_assumptions(sat_solver *, int *, int, int)int sat_solver_minimize_assumptions2(sat_solver *, int *, int, int)s->pStore == NULLvoid sat_solver_store_alloc(sat_solver *)s->orderpos[v] != -1void order_update(sat_solver *, int)Failed to realloc memory from %.1f MB to %.1f MB. nInts + 3 < (1 << p->nPageSize)src/sat/bsat/satClause.hint Sat_MemAppend(Sat_Mem_t *, int *, int, int, int)k <= v->sizevoid veci_resize(veci *, int)a >= 1.0./src/misc/util/utilDouble.hxdbl Xdbl_FromDouble(double)!(Exp>>16) && (Mnt>>47)==(word)1xdbl Xdbl_Create(word, word)clause *Sat_MemClause(Sat_Mem_t *, int, int)p->BookMarkH[1] >= Sat_MemHand(p, 1, 2) && p->BookMarkH[1] <= hLimitint Sat_MemCompactLearned(Sat_Mem_t *, int)c->lrnc->lits[c->size] == Sat_MemHand(p, iNew, kNew)nInts == Sat_MemClauseSize(c)iNew <= i && kNew < (1 << p->nPageSize)void sat_solver_canceluntil_rollback(sat_solver *, int)s->qtail == s->qheadlbool sat_solver_search(sat_solver *, ABC_INT64_T)void act_var_bump_factor(sat_solver *, int)void act_var_rescale(sat_solver *)void act_var_bump_global(sat_solver *, int)h != 0void sat_solver_analyze(sat_solver *, int, veci *)void act_var_bump(sat_solver *, int)int sat_solver_lit_removable(sat_solver *, int, int)s->reasons[v] != 0veci_size(cls) > 0void sat_solver_record(sat_solver *, veci *)void act_var_decay(sat_solver *)next >= 0 && next < s->sizeint order_select(sat_solver *, float)child < sizeint sat_solver_decision(sat_solver *, lit)veci_size(&s->trail_lim) > 0void sat_solver_canceluntil(sat_solver *, int)veci_size(&s->tagged) == 0void sat_solver_analyze_final(sat_solver *, int, int)var_level(s, x) > 0lit_var(q) >= 0 && lit_var(q) < s->size==================================[MINISAT]===================================| Conflicts | ORIGINAL | LEARNT | Progress || | Clauses Literals | Limit Clauses Literals Lit/Cl | |==============================================================================sat_solver_solve_lexsat(): A satisfying assignment should exist.@@@@?@src/sat/bsat/satSolver2.cclause *solver2_propagate(sat_solver2 *)var_level(s, x) == 0(var_unit_clause(s, Var) == NULL) != fLitIsFalsesolver2_dlevel(s) == 0int sat_solver2_simplify(sat_solver2 *)void sat_solver2_setnvars(sat_solver2 *, int)int sat_solver2_addclause(sat_solver2 *, lit *, lit *, int)i == begin || lit_var(*(i-1)) != lit_var(*i)count < end-begins->nLearntMaxvoid sat_solver2_reducedb(sat_solver2 *)void sat_solver2_rollback(sat_solver2 *)s->pPrf1 == NULL || (s->hProofPivot >= 1 && s->hProofPivot <= Vec_SetHandCurrent(s->pPrf1))s->pPrf2 == NULLint sat_solver2_solve(sat_solver2 *, lit *, lit *, ABC_INT64_T, ABC_INT64_T, ABC_INT64_T, ABC_INT64_T)s->conf_final.size > 0s->root_level == solver2_dlevel(s)==================================[MINISAT]=================================== | Conflicts | ORIGINAL | LEARNT | Progress | | | Clauses Literals | Limit Clauses Literals Lit/Cl | | ============================================================================== (ProofId >> 2) > 0void proof_chain_start(sat_solver2 *, clause *)p->iFirst >= 0void Prf_ManChainStart(Prf_Man_t *, clause *)p->pInfo == NULLvoid Prf_ManChainResolve(Prf_Man_t *, clause *)p->pInfo != NULLclause_id(c) - p->iFirst < Prf_ManSize(p)Entry < 64 * p->nWordsvoid proof_chain_resolve(sat_solver2 *, clause *, int)int Prf_ManChainStop(Prf_Man_t *)int Vec_SetAppend(Vec_Set_t *, int *, int)size < 1 || begin[0] >= 0int clause2_create_new(sat_solver2 *, lit *, lit *, int, int)size < 2 || begin[1] >= 0size < 1 || lit_var(begin[0]) < s->sizesize < 2 || lit_var(begin[1]) < s->sizeproof_idclause_id(c) == (int)s->stats.clausesId >= 0 && Id < veci_size(&s->act_clas)void act_clause2_bump(sat_solver2 *, clause *)v >= 0 && v < s->size && !s->units[v]void var_set_unit_clause(sat_solver2 *, int, cla)void order_update(sat_solver2 *, int)void Prf_ManAddSaved(Prf_Man_t *, int, int)p->iFirst2 == -1void Prf_ManCompact(Prf_Man_t *, int)Entry - p->iFirst >= 0 && Entry - p->iFirst < nSizevoid solver2_canceluntil_rollback(sat_solver2 *, int)int solver2_analyze_final(sat_solver2 *, clause *, int)s->root_level >= veci_size(&s->trail_lim)var_level(s,x)solver2_dlevel(s) > 0void solver2_canceluntil(sat_solver2 *, int)lbool solver2_search(sat_solver2 *, ABC_INT64_T)proof_id > 0var_value(s,i) != varXint solver2_analyze(sat_solver2 *, clause *, veci *)c != 0x >= 0 && x < s->sizeveci_size(&s->mark_levels) == 0level < veci_size(&s->trail_lim)void var_lev_set_mark(sat_solver2 *, int)void solver2_record(sat_solver2 *, veci *, int)int order_select(sat_solver2 *, float)int solver2_assume(sat_solver2 *, lit)Vec_Int_t *Prf_ManUnsatCore(Prf_Man_t *)Prf_ManSize(p) > 0interpolantGia_ManPoNum(pGia) == 0src/sat/bsat/satSolver2i.cvoid *Int2_ManReadInterpolant(sat_solver2 *)int Int2_ManChainResolve(Int2_Man_t *, clause *, int, int)Gia_ManRegNum(p) == 0Gia_Man_t *Gia_ManInterTest(Gia_Man_t *)Total interpolation timeiVarA >= 0 && iVarB >= 0int sat_solver2_add_buffer(sat_solver2 *, int, int, int, int, int)int sat_solver2_add_xor(sat_solver2 *, int, int, int, int, int, int)@src/sat/bsat/satSolver3.cint sat_solver3_get_var_value(sat_solver3 *, int)s->VarActType == 1void sat_solver3_set_var_activity(sat_solver3 *, int *, int)int sat_solver3_clause_new(sat_solver3 *, lit *, lit *, int)sat_solver3_dl(s) == 0int sat_solver3_count_assigned(sat_solver3 *)int sat_solver3_propagate(sat_solver3 *)void sat_solver3_setnvars(sat_solver3 *, int)int sat_solver3_simplify(sat_solver3 *)void sat_solver3_reducedb(sat_solver3 *)void sat_solver3_rollback(sat_solver3 *)int sat_solver3_addclause(sat_solver3 *, lit *, lit *)int sat_solver3_push(sat_solver3 *, int)sat_solver3_dl(s) > 0void sat_solver3_pop(sat_solver3 *)s->root_level == sat_solver3_dl(s)int sat_solver3_solve(sat_solver3 *, lit *, lit *, ABC_INT64_T, ABC_INT64_T, ABC_INT64_T, ABC_INT64_T)int sat_solver3_solve_lexsat(sat_solver3 *, int *, int)int sat_solver3_minimize_assumptions(sat_solver3 *, int *, int, int)int sat_solver3_minimize_assumptions2(sat_solver3 *, int *, int, int)void order_update(sat_solver3 *, int)void sat_solver3_canceluntil_rollback(sat_solver3 *, int)lbool sat_solver3_search(sat_solver3 *, ABC_INT64_T)void act_var_bump_factor(sat_solver3 *, int)void act_var_rescale(sat_solver3 *)void act_var_bump_global(sat_solver3 *, int)void sat_solver3_analyze(sat_solver3 *, int, veci *)void act_var_bump(sat_solver3 *, int)int sat_solver3_lit_removable(sat_solver3 *, int, int)void sat_solver3_record(sat_solver3 *, veci *)void act_var_decay(sat_solver3 *)int order_select(sat_solver3 *, float)int sat_solver3_decision(sat_solver3 *, lit)void sat_solver3_canceluntil(sat_solver3 *, int)void sat_solver3_analyze_final(sat_solver3 *, int, int)src/sat/bsat/satSolver3.hint sat_solver3_var_literal(sat_solver3 *, int)sat_solver3_solve_lexsat(): A satisfying assignment should exist.The clause contains two literals of the same variable: %d and %d. pPrev != NULLsrc/sat/bsat/satStore.cint Sto_ManChangeLastClause(Sto_Man_t *)pPrev->fA == 1pPrev->nLits == 1Error: Cannot open output file (%s). p %d %d %d %d Error: Wrong char (%c) in the input file. Error: Cannot open input file (%s). Warning: Skipping line: "%s" Sto_Man_t *Sto_ManLoadClauses(char *)Error: The actual number of clauses (%d) is different than declared (%d). More than one empty clause!Error: The last clause was not saved.pSat->pFile == NULLsrc/sat/bsat/satTrace.cvoid Sat_SolverTraceStart(sat_solver *, char *)p %d %d %d 5 Qsrc/sat/bsat/satTruth.cint *Tru_ManLookup(Tru_Man_t *, word *)p->pTable != NULLvoid Tru_ManResize(Tru_Man_t *)pThis->HandleCounter == Vec_SetEntryNum(p->pMem)(*pSpot & 1) == 0int Tru_ManInsert(Tru_Man_t *, word *)nVars > 0 && nVars <= 16Tru_Man_t *Tru_ManAlloc(int)!i || p->hIthVars[i] > p->hIthVars[i-1]Lookups = %d. Entries = %d. v >= 0 && v < p->nVarsword *Tru_ManVar(Tru_Man_t *, int)(h & 1) == 0word *Tru_ManFunc(Tru_Man_t *, int)%s%d%s starts : %16.0f conflicts : %16.0f decisions : %16.0f propagations : %16.0f starts : %10d conflicts : %10d decisions : %10d propagations : %10d src/sat/bsat/satUtil.cvoid Sat_SolverDoubleClauses(sat_solver *, int)int sat_solver2_var_value(sat_solver2 *, int)Sat_SolverWriteDimacs(): Cannot open the ouput file.Vec_IntSize( vLits ) > 1src/sat/xsat/xsatSolver.cunsigned int xSAT_SolverClaNew(xSAT_Solver_t *, Vec_Int_t *, int)fLearnt == 0 || fLearnt == 1Lits[1] == NegLitunsigned int xSAT_SolverPropagate(xSAT_Solver_t *)pCla->fMark == 0void xSAT_SolverReduceDB(xSAT_Solver_t *)src/sat/xsat/xsatMemory.hunsigned int xSAT_MemAppend(xSAT_Mem_t *, int)p->nSize > nPrevSizep->nCap >= nPrevCapvoid xSAT_MemGrow(xSAT_Mem_t *, unsigned int)p->nCap > 0src/sat/xsat/xsatWatchList.hvoid xSAT_WatchListPush(xSAT_WatchList_t *, xSAT_Watcher_t)iEntry < v->nCapxSAT_WatchList_t *xSAT_VecWatchListEntry(xSAT_VecWatchList_t *, int)iEntry < v->nSize!xSAT_HeapInHeap( p, n )src/sat/xsat/xsatHeap.hvoid xSAT_HeapInsert(xSAT_Heap_t *, int)k <= v->nSizevoid xSAT_WatchListShrink(xSAT_WatchList_t *, int)j < xSAT_WatchListSize( v )void xSAT_WatchListRemove(xSAT_WatchList_t *, unsigned int)p->iFirst == p->iEmptysrc/sat/xsat/xsatBQueue.hvoid xSAT_BQueuePush(xSAT_BQueue_t *, unsigned int)ConfCRef != CRefUndefvoid xSAT_SolverAnalyze(xSAT_Solver_t *, unsigned int, Vec_Int_t *, int *, unsigned int *)Vec_StrEntry( s->vAssigns, xSAT_Lit2Var( Lits[1] ) ) == xSAT_LitSign( ( Lits[1] ) )int xSAT_SolverIsLitRemovable(xSAT_Solver_t *, int, int)(unsigned) Vec_IntEntry( s->vReasons, v ) != CRefUndefxSAT_SolverDecisionLevel(s) == 0src/sat/xsat/xsatSolverAPI.cint xSAT_SolverSimplify(xSAT_Solver_t *)int xSAT_SolverSolve(xSAT_Solver_t *)| * Trail Queue : %6d | * Inc : %6d | * lbd < %3d | conflicts : %10ld decisions : %10ld propagations : %10ld ==========================================[ BLACK MAGIC ]================================================| - Restarts: | - Reduce Clause DB: | - Minimize Asserting: || | | |=========================================================================================================PARSE ERROR! Unexpected char: %c There is no parameter line.vec_uint_size(lits) > 1src/sat/satoko/solver.cunsigned int solver_clause_create(solver_t *, vec_uint_t *, unsigned int)f_learnt == 0 || f_learnt == 1lits[1] == neg_litunsigned int solver_propagate(solver_t *)[Satoko] Checking for trail(%u) inconsistencies... [Satoko] Inconsistent trail: %u %u void solver_debug_check_trail(solver_t *)[Satoko] Inconsistent trail assignment: %u, %u [Satoko] Trail OK. [Satoko] Checking clauses (%d)... [Satoko] FOUND UNSAT CLAUSE]: (%d) void solver_debug_check_clauses(solver_t *)[Satoko] All SAT - OK [Satoko] Checking clauses (%d)... [Satoko] FOUND UNSAT CLAUSE: (%d) void solver_debug_check(solver_t *, int)src/sat/satoko/cdb.hunsigned int cdb_append(struct cdb *, unsigned int)p->size > prev_sizep->cap >= prev_capvoid cdb_grow(struct cdb *, unsigned int)p->cap > 0src/sat/satoko/utils/vec/vec_uint.hunsigned int *vec_uint_data(vec_uint_t *)p->data != NULLvoid vec_uint_reserve(vec_uint_t *, unsigned int)idx >= 0 && idx < p->sizeunsigned int vec_uint_at(vec_uint_t *, unsigned int)(idx >= 0) && (idx < vec_char_size(p))src/sat/satoko/utils/vec/vec_char.hvoid vec_char_assign(vec_char_t *, unsigned int, char)(idx >= 0) && (idx < vec_uint_size(p))void vec_uint_assign(vec_uint_t *, unsigned int, unsigned int)i >= 0 && i < p->sizesrc/sat/satoko/utils/vec/vec_int.hint vec_int_at(vec_int_t *, unsigned int)!heap_in_heap(p, entry)src/sat/satoko/utils/heap.hvoid heap_insert(heap_t *, unsigned int)void vec_int_resize(vec_int_t *, unsigned int)(i >= 0) && (i < vec_int_size(p))void vec_int_assign(vec_int_t *, unsigned int, int)src/sat/satoko/utils/vec/vec_sdbl.hsdbl_t vec_sdbl_at(vec_sdbl_t *, unsigned int)p->cap >= new_sizevoid vec_uint_shrink(vec_uint_t *, unsigned int)idx < vec_wl->capsrc/sat/satoko/watch_list.hstruct watch_list *vec_wl_at(vec_wl_t *, unsigned int)idx < vec_wl->sizewlvoid watch_list_push(struct watch_list *, struct watcher, unsigned int)size <= wl->sizevoid watch_list_shrink(struct watch_list *, unsigned int)p->i_first == p->i_emptysrc/sat/satoko/utils/b_queue.hvoid b_queue_push(b_queue_t *, unsigned int)cref != UNDEFvoid solver_analyze(solver_t *, unsigned int, vec_uint_t *, unsigned int *, unsigned int *)lit_value(s, lits[1]) == SATOKO_LIT_TRUEsdbl_t *vec_sdbl_data(vec_sdbl_t *)src/sat/satoko/utils/sdbl.hint lit_is_removable(solver_t *, unsigned int, unsigned int)var_reason(s, var) != UNDEFp && p->sizeunsigned int vec_uint_pop_back(vec_uint_t *)value >= 1.0sdbl_t double2sdbl(double)clause->f_mark == 0void solver_reduce_cdb(solver_t *)reduceDB: Keeping %7d out of %7d clauses (%5.2f %%) i < watch_list_size(wl)void watch_list_remove(struct watch_list *, unsigned int, unsigned int)var_dlevel(s, var) > 0void solver_analyze_final(solver_t *, unsigned int)var_value(s, lit2var(lit)) == SATOKO_VAR_UNASSINGvoid solver_new_decision(solver_t *, unsigned int)dest != NULL && src != NULLvoid vec_uint_duplicate(vec_uint_t *, const vec_uint_t *)void vec_uint_resize(vec_uint_t *, unsigned int)char vec_char_at(vec_char_t *, unsigned int)void vec_uint_print(vec_uint_t *)Vector has %u(%u) entries: {?ffffff?'2,?user_optssrc/sat/satoko/solver_api.cvoid satoko_configure(satoko_t *, satoko_opts_t *)solver_dlevel(s) == 0int satoko_simplify(solver_t *)lit2var(lit) < (unsigned)satoko_varnum(s)void satoko_assump_push(solver_t *, int)vec_uint_size(s->assumptions) > 0void satoko_assump_pop(solver_t *)int satoko_solve(solver_t *)nlits >= 2int satoko_minimize_assumptions(satoko_t *, int *, int, int)s->status == SATOKO_OKvoid satoko_bookmark(satoko_t *)void satoko_unbookmark(satoko_t *)void satoko_rollback(satoko_t *)solver_has_marks(s)void satoko_unmark_cone(satoko_t *, int *, int)wrt_lrnt == 0 || wrt_lrnt == 1void satoko_write_dimacs(satoko_t *, char *, int, int)zero_var == 0 || zero_var == 1failed to realloc memory from %.1f mb to %.1f mb. void vec_sdbl_reserve(vec_sdbl_t *, unsigned int)void vec_char_reserve(vec_char_t *, unsigned int)new_size <= p->capvoid vec_sdbl_shrink(vec_sdbl_t *, unsigned int)p->cap > new_sizevoid vec_char_shrink(vec_char_t *, unsigned int)(i >= 0) && (i < vec_sdbl_size(p))void vec_sdbl_assign(vec_sdbl_t *, unsigned int, sdbl_t)Satoko in inconsistent stateError: Cannot open output file.Unable to add clause: Couldn't open file: %s pos != NULLsrc/sat/satoko/cnf_reader.cvoid skip_spaces(char **)Parsing error. Unexpected char: %c. &Ltܖcsat_networkABC_AddGate: The PI/PPI gate "%s" has fanins. ABC_AddGate: The fanin gate "%s" is not in the network. ABC_AddGate: The constant gate "%s" has fanins. ABC_AddGate: The AND gate "%s" no fanins. ABC_AddGate: The NAND gate "%s" no fanins. ABC_AddGate: The OR gate "%s" no fanins. ABC_AddGate: The NOR gate "%s" no fanins. ABC_AddGate: The XOR gate "%s" no fanins. ABC_AddGate: The XOR gate "%s" has more than two fanins. ABC_AddGate: The XNOR gate "%s" no fanins. ABC_AddGate: The XNOR gate "%s" has more than two fanins. ABC_AddGate: The inverter gate "%s" does not have exactly one fanin. ABC_AddGate: The buffer gate "%s" does not have exactly one fanin. ABC_AddGate: The PO/PPO gate "%s" does not have exactly one fanin. ABC_AddGate: The same gate "%s" is added twice. src/sat/csat/csat_apis.cvoid ABC_Network_Finalize(ABC_Manager)ABC_AddTarget: The target gate "%s" is not in the network. ABC_AddTarget: The value of gate "%s" is not 0 or 1. mng->nog == Vec_PtrSize(mng->vNodes)void ABC_SolveInit(ABC_Manager)enum CSAT_StatusT ABC_Solve(ABC_Manager)abc_test.benchchar *ABC_GetNodeName(ABC_Manager, Abc_Obj_t *)ABC_AddGate: Unknown gate type.ABC_Check_Integrity: The internal network check has failed.ABC_AddTarget: The target has no gates.ABC_SolveInit: Target is not specified by ABC_AddTarget().ABC_Solve: Target network is not derived by ABC_SolveInit().ABC_Dump_Bench_File: Dumping BENCH has failed.Msat_SolverReadDecisionLevel(p) == 0src/sat/msat/msatClause.cint Msat_ClauseCreate(Msat_Solver_t *, Msat_IntVec_t *, int, Msat_Clause_t **)iLevelCur != -1pC->pData[1] == LitFint Msat_ClausePropagate(Msat_Clause_t *, Msat_Lit_t, int *, Msat_Lit_t *)i >= 2int Msat_ClauseSimplify(Msat_Clause_t *, int *)Lit == MSAT_LIT_UNASSIGNED || Lit == pC->pData[0]void Msat_ClauseCalcReason(Msat_Solver_t *, Msat_Clause_t *, Msat_Lit_t, Msat_IntVec_t *)Msat_SolverReadAssignsArray(p)[MSAT_LIT2VAR(pC->pData[i])] == MSAT_LITNOT(pC->pData[i])i < nClausesvoid Msat_ClauseRemoveWatch(Msat_ClauseVec_t *, Msat_Clause_t *)NULL pointerAct = %.4f src/sat/msat/msatClauseVec.cvoid Msat_ClauseVecShrink(Msat_ClauseVec_t *, int)void Msat_ClauseVecWriteEntry(Msat_ClauseVec_t *, int, Msat_Clause_t *)Msat_Clause_t *Msat_ClauseVecReadEntry(Msat_ClauseVec_t *, int)src/sat/msat/msatMem.cchar *Msat_MmFixedEntryFetch(Msat_MmFixed_t *)char *Msat_MmFlexEntryFetch(Msat_MmFlex_t *, int)i+1 < p->vHeap->nCapsrc/sat/msat/msatOrderH.cvoid Msat_OrderClean(Msat_Order_t *, Msat_IntVec_t *)vCone->pArray[i] < p->vIndex->nSizeHOKAY(p, n)void Msat_HeapInsert(Msat_Order_t *, int)src/sat/msat/msatQueue.cvoid Msat_QueueInsert(Msat_Queue_t *, int)p->iLast < p->nVarsPȗPȗPȗPȗPȗzȗzȗzȗzȗzȗzȗzȗzȗzȗzȗzȗzȗzȗzȗzȗzȗzȗzȗPȗzȗzȗzȗzȗzȗzȗzȗzȗzȗzȗkȗzȗqȗVariable %d is larger than the number of allocated variables (%d). Num < p->nClausessrc/sat/msat/msatSolverApi.cMsat_Clause_t *Msat_SolverReadClause(Msat_Solver_t *, int)p->nVarsAlloc >= nVarsvoid Msat_SolverClean(Msat_Solver_t *, int)?C solver (%d vars; %d clauses; %d learned): starts : %d conflicts : %d decisions : %d propagations : %d inspects : %d Msat_IntVecReadSize(p->vTrailLim) == 0src/sat/msat/msatSolverCore.cint Msat_SolverSolve(Msat_Solver_t *, Msat_IntVec_t *, int, int)Solving -- conflicts=%d learnts=%d progress=%.4f %% ffffff?+?i == MSAT_LIT2VAR(p->pAssigns[i])src/sat/msat/msatSolverIo.cvoid Msat_SolverPrintAssignment(Msat_Solver_t *)%3d : %.4f c Produced by Msat_SolverWriteDimacs() on %s Current assignments are: Original clauses: Learned clauses: Variable activity: Msat_QueueReadSize(p->pQueue) == 0src/sat/msat/msatSolverSearch.cint Msat_SolverAssume(Msat_Solver_t *, Msat_Lit_t)%-*dassume(%s%d) %-*dbind(%s%d) int Msat_SolverSimplifyDB(Msat_Solver_t *)!Msat_ClauseIsLocked( p, pLearned[i])void Msat_SolverRemoveLearned(Msat_Solver_t *)Msat_SolverReadDecisionLevel(p) == p->nLevelRootMsat_Type_t Msat_SolverSearch(Msat_Solver_t *, int, int, int, Msat_SearchParams_t *)%-*d**CONFLICT** Var != MSAT_ORDER_UNKNOWN && Var >= 0 && Var < p->nVarsvoid Msat_SolverCancel(Msat_Solver_t *)%-*dcancel(%s%d) %-*dunbind(%s%d) pC != NULLvoid Msat_SolverAnalyze(Msat_Solver_t *, Msat_Clause_t *, Msat_IntVec_t *, int *)%-*dLearnt { } at level %d Msat_IntVecReadSize(vLits) != 0Msat_Clause_t *Msat_SolverRecord(Msat_Solver_t *, Msat_IntVec_t *)11?src/sat/msat/msatVec.cint Msat_IntVecReadEntry(Msat_IntVec_t *, int)void Msat_IntVecWriteEntry(Msat_IntVec_t *, int, int)void Msat_IntVecShrink(Msat_IntVec_t *, int)int Msat_IntVecPop(Msat_IntVec_t *)src/sat/cnf/cnfCut.cCnf_Cut_t *Cnf_CutCreate(Cnf_Man_t *, Aig_Obj_t *)pCutBest != NULLpCutBest->nLeaves <= 4pObj->nRefs > 0void Cnf_CutDeref(Cnf_Man_t *, Cnf_Cut_t *)pCut->pFanins[iVar] == iFanvoid Cnf_CutRemoveIthVar(Cnf_Cut_t *, int, int)Cnf_Cut_t *Cnf_CutCompose(Cnf_Man_t *, Cnf_Cut_t *, Cnf_Cut_t *, int)pCutRes->nFanins <= pCut->nFanins + pCutFan->nFaninsunsigned int Cnf_TruthPhase(Cnf_Cut_t *, Cnf_Cut_t *)!#&()*+,-.0123456789:;<=>?ABCDEFGHIJKLMNOPQRSTUVWXYZ[]abcdefghijklmnopqrstuvwxyz|jN2~bF * v  Z > " n R6fJ.z^B&r V:jN2~bF*vZ>" n !R!!!6"""#f###J$$$.%z%%&^&&&B'''&(r(( )V))):***+j++,N,,,2-~--.b...F///*0v001Z111>222"3n334R44465556f666J777.8z889^999B:::&;r;; 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C 7o=D o>D7= o=6QC =Q6o+C =QDo6 o+6=QD 7o=pC p=7o>C p=D7o s=o7D o6W=7vC 7vDo= go7=D =Q6ovC =6o+vQC Z=o6D Z=6goD p=o7vC >C7vp=o 7Z=oD yo7=D ?bn bn?& ?Dn ?cn b1?n ?b:n 1D?n :n?c bn?K ?b&nK bT?n cn?T bn?j ?:bnj Dn?j sn?c bn?* ?b-n Dn?* cn?- 1nb* :b-n ?D1n* c-:n ?bn*K ?-bnK ?DTn* ?-Tcn ?jbn* ?-jbn ?Djn* s-n?c bn?E ?b&nE bH?n cn?H ?b1nE ?:bnE ?Hb1n ?:Hcn ?bnEK &nE?bK ?HbTn ?cHTn ?jbnE :nb?jE ?Hjbn s?cHn bd?n ?-bdn Dd?n gn?c ?d1bn ?:dbn ?Dd1n g:n?c ?dbnK -nb?dK ?DdTn g?cTn ?djbn ?db-nj ?Ddnj g?scn 4b?n ?4b&n 4D?n ?4cn ?n7b ?:7bn ?n7D cn7? ?4bnK &nK?4b ?D4Tn ?c4Tn ?j7bn 7:b?jn ?D7Tn s?7cn ?b=n ?-=bn =n?D cn?= =n7b Abn ?D7=n Acn ?=nbK =bn?-K =bT?n c=?Tn =b7nj bnAj ?Dj=n scAn ?4bnE &nE?4b ?H4bn ?c4Hn 7?bnE 7bn?:E ?H7bn 7c?Hn 4bn?EK &n?E4bK 4bH?Tn c4H?Tn 7bn?jE 7j?E:nb ?Hn7bT 7cHs?n ?=dbn =b-?dn ?Dd=n c=?gn ?d7bn bdAn ?D7dn gcAn =bn?dK =d-n?bK ?Hn=bT g?Tc=n ?dn=bj Adnbj ?Hn=bj Agnsc ?Pb bP?& ?DP ?cP b1?P ?b:P 1D?P :c?P bQ?P ?QbP& bT?P cQ?P bP?j ?:QbP DP?j sP?c bP?* ?b-P DP?* c-?P ?Pb1* ?:P-b ?DP1* ?cP:- ?QbP* ?-QbP ?QDP* ?cQ-P ?Pjb* ?-Pbj ?DP*j s?Pc- bW?P ?WbP& bH?P cW?P ?Wb1P ?:WbP ?HPb1 ?cW:P ?WbQn bWn?Q& Zb?P ?PZc ?WjbP ?Wb:Qn ?Zb1P s?ZcP bd?P ?-WbP Dd?P gP?c ?dPb1 ?:dbP ?Dd1P g?P:c ?QdbP ?Wb-Qn ?ZbdP g?ZcP ?dPbj ?Wb-Pj ?DdPj g?scP o?b ?bo& o?D oc? 7bo? ob?: 7o?D ?co: ob?Q o?bQ& ob?T ?Qoc ob?p o:?pb op?D ocs? =bo? ob?- =Do? ?co- 7o=b Aob o?D7= Aoc o?=bQ o-?bQ o?D=Q oc?=Q p=bo? opAb ?pDo= osAc ob?W o?bW& ob?H ?Hoc ?W7ob o:?bW o?H7b o:H?c o?bWQ obW?Q& ?DoZ oc?Z ?pobW ?pbo:W ?Zo7b s?oZc ob?v o-?vb ov?D ocg? 7vbo? ovAb ?vD7o goAc ?vobQ ?vbo-Q ?Zo=b go?Zc ?pvob Aopvb ?pvoD yoAc R< R R5=B >R=a =RM R+=M =RT R+=T =Rj =R>M R5=T s=R 4R RH=5 g>=R Rd=M =R+dM RH=T gR=T Rd=j >M=Rd RH=j gs=R R

o=5RB o>=Ra S= S=+ S=T S=a S=p S>= Sp=T s=S RWo< o!RW< RHo< oHRa< 5WR< o8RW< oHR5< oH8R< oWS< S=R =RvH5 g=Ro> S=v v=S+ S=Z gS= p=Sv v>S= SZp= y=S ,R< R<& RB,n Ra,n ,.R< R8,n ,R<.B ,R8a< ,Mn =R =R5,B >n-Ra ,R=M -R=M ,R=T -R=T ,R=j -R=j =RT,5 =Rs- ,ER4 ,R4&E R4,H ,R4H& ,R45E ,R48E ,R4H5 ,R4H8 ,R4ME n-Rd =RH,5 g=R-> =Rd,M =R-dM =RH,T g=R-T =Rj,d >M-dn =RH,j s=Rg- R<,P o,5=RB o->Ra S=, S-o S,=T =TS- S,p= o-S> S=p,T S-s= ,RoW o&R,W ,RoH oH&,R o,R5W o8,RW oH,R5 oH8,R SWo, S<&oW S,oZ oZ&S< Sp<,W SpR =R5oH, go->R ovS, Svo- S,Z= S-go Sv,p= o-pSv S=Zp, S-yo Rn R5=D >R=D Un=M =RU+M V=R V+=R Rj=U >M=Un V5=R >nV= R4UnU=d =RHU5 g=R>U =RUdM dMn=U+ Vd=R =RgV =RjUd >nd=Uj V=RH5 V>ng= U

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AND-gate rule is violated %d times. int Cnf_CutCountClauses(Aig_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Int_t *)pObj == Vec_PtrEntryLast(vNodes)int Cnf_CountCnfSize(Aig_Man_t *)Vars = %d Clauses = %d nOutputs == Aig_ManCoNum(p)Cnf_Dat_t *Cnf_DeriveFastClauses(Aig_Man_t *, int)nOutputs == Aig_ManRegNum(p)iSatVar > 0int Cnf_ObjGetLit(Vec_Int_t *, Aig_Obj_t *, int)Unusual 2!Unusual 1!FastCnfGeneration: Internal error!!!p->pMan == NULLsrc/sat/cnf/cnfMan.cvoid Cnf_DataCollectFlipLits(Cnf_Dat_t *, int, Vec_Int_t *)void Cnf_DataLiftAndFlipLits(Cnf_Dat_t *, int, Vec_Int_t *)c Result of efficient AIG-to-CNF conversion using package CNF void *Cnf_DataWriteIntoSolverInt(void *, Cnf_Dat_t *, int, int)pSatvoid *Cnf_DataWriteIntoSolver2(Cnf_Dat_t *, int, int)iVar < pCnf->nVarsvoid Cnf_DataTranformPolarity(Cnf_Dat_t *, int)iVarA > 0 && iVarB > 0 && iVarC > 0int Cnf_DataAddXorClause(void *, int, int, int)Cnf_WriteIntoFile(): Output file cannot be opened.src/sat/cnf/cnfMap.cvoid Cnf_CutAssignAreaFlow(Cnf_Man_t *, Dar_Cut_t *, int *)int Cnf_CutSuperAreaFlow(Vec_Ptr_t *, int *)pFan->nRefs != 0src/sat/cnf/cnfPost.cvoid Cnf_ManPostprocess_old(Cnf_Man_t *)Total gain = %d. Vars = %d. void Cnf_ManPostprocess(Cnf_Man_t *)pFan->nRefs == 0Aig_ObjIsAnd(pObj)src/sat/cnf/cnfUtil.cint Aig_ManScanMapping_rec(Cnf_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)int Cnf_ManScanMapping_rec(Cnf_Man_t *, Aig_Obj_t *, Vec_Ptr_t *, int)pCutBest->Cost < 127Literal %d is out-of-bound for %d variables. There is no zero-terminator in line %d. Warning! The number of clauses (%d) is different from declaration (%d). int Cnf_DataSolveFromFile(char *, int, int, int, int, int, int, int **, int)Incorrect parameters.Incorrect input file.The problem is trivially UNSAT.src/sat/cnf/cnfWrite.cVec_Int_t *Cnf_ManWriteCnfMapping(Cnf_Man_t *, Vec_Ptr_t *)pCut->nFanins < 5Cnf_Dat_t *Cnf_ManWriteCnf(Cnf_Man_t *, Vec_Ptr_t *, int)p->pSopSizes[uTruth] >= 0nOutputs == Aig_ManCoNum(p->pManAig)nOutputs == Aig_ManRegNum(p->pManAig)pVars[k] <= Aig_ManObjNumMax(p->pManAig)OutVar <= Aig_ManObjNumMax(p->pManAig)pLits - pCnf->pClauses[0] == nLiteralspClas - pCnf->pClauses == nClausesCnf_Dat_t *Cnf_ManWriteCnfOther(Cnf_Man_t *, Vec_Ptr_t *)OutVar <= Aig_ManObjNumMax(p)Cnf_Dat_t *Cnf_DeriveSimple(Aig_Man_t *, int)Cnf_Dat_t *Cnf_DeriveSimpleForRetiming(Aig_Man_t *)Cannot find object with Id %d in the given AIG. src/sat/bmc/bmcBCore.cvoid Bmc_ManBCoreCollect_rec(Gia_Man_t *, int, int, Vec_Int_t *, Vec_Int_t *)iFrame >= 0 && iOut >= 0Vec_Int_t *Bmc_ManBCoreCollect(Gia_Man_t *, int, int, sat_solver *)pObj->Value == 1Gia_ObjFanin0(pObj)->Value == 3SAT solver returned UNSAT after %7d conflicts. void Bmc_ManBCorePerform(Gia_Man_t *, Bmc_BCorePar_t *)UNSAT core contains %d (out of %d) learned clauses. int sat_solver_add_const(sat_solver *, int, int)int sat_solver_add_constraint(sat_solver *, int, int, int)int sat_solver_add_buffer(sat_solver *, int, int, int)The BMC problem is SAT.Timeout of conflict limit is reached.src/sat/bmc/bmcBmc.cAig_Man_t *Saig_ManFramesBmc(Aig_Man_t *, int)Aig_Man_t *Saig_ManFramesBmcLimit(Aig_Man_t *, int, int)Running "bmc". AIG: PI/PO/Reg = %d/%d/%d. Node = %6d. Lev = %5d. Time-frames (%d): PI/PO = %d/%d. Node = %6d. Lev = %5d. Time-frames after rewriting: Node = %6d. Lev = %5d. int Saig_ManBmcSimple(Aig_Man_t *, int, int, int, int, int, int *, int, int)CNF: Variables = %6d. Clauses = %7d. Literals = %8d. Solving output %2d of frame %3d ... Solved %2d outputs of frame %3d. Conf =%8.0f. Imp =%11.0f. The BMC problem is trivially UNSAT''KSaig_ObjIsLo(p, pObj)src/sat/bmc/bmcBmc2.cint Abs_ManExtendOneEval_rec(Vec_Ptr_t *, Aig_Man_t *, Aig_Obj_t *, int)Aig_ManRegNum(p) > 0Vec_Ptr_t *Abs_ManTernarySimulate(Aig_Man_t *, int, int)Ternary sim found non-zero output in frame %d. Used %5.2f MB. Ternary sim proved all outputs in the first %d frames. Used %5.2f MB. pRes != NULLAig_Obj_t *Saig_BmcIntervalConstruct_rec(Saig_Bmc_t *, Aig_Obj_t *, int, Vec_Int_t *)Aig_Obj_t *Saig_BmcIntervalToAig_rec(Saig_Bmc_t *, Aig_Man_t *, Aig_Obj_t *)Aig_Man_t *Saig_BmcIntervalToAig(Saig_Bmc_t *)!Aig_IsComplement(pObjNew)void Saig_BmcLoadCnf(Saig_Bmc_t *, Cnf_Dat_t *)Vec_PtrSize(p->vTargets) > 0int Saig_BmcSolveTargets(Saig_Bmc_t *, int, int *)Running "bmc2". AIG: PI/PO/Reg = %d/%d/%d. Node = %6d. Lev = %5d. Params: FramesMax = %d. NodesDelta = %d. ConfMaxOne = %d. ConfMaxAll = %d. %4d : F =%5d. O =%4d. And =%8d. Var =%8d. Conf =%7d. %4.0f MB%9.2f secReached timeout (%d seconds). p->iFrameFail * Saig_ManPoNum(p->pAig) + p->iOutputFail + 1 == nOutsSolvedint Saig_BmcPerform(Aig_Man_t *, int, int, int, int, int, int, int, int, int *, int, int)No output failed in %d frames. %9.2f sec Reached limit on the number of timeframes (%d). Reached global conflict limit (%d). Reached local conflict limit (%d). Value >= ABS_ZER && Value <= ABS_UNDvoid Abs_ManSimInfoSet(Vec_Ptr_t *, Aig_Obj_t *, int, int)i < Vec_PtrSize(p->vAig2Frm)void Saig_BmcObjSetFrame(Saig_Bmc_t *, Aig_Obj_t *, int, Aig_Obj_t *)Aig_Obj_t *Saig_BmcObjChild0(Saig_Bmc_t *, Aig_Obj_t *, int)./src/sat/bsat/satVec.hSAT solver became UNSAT after adding clauses.Saig_BmcGenerateCounterExample(): Counter-example is invalid.@'Pproperty: safe<%d> bug-free-depth: %d f >= 0src/sat/bmc/bmcBmc3.cint Saig_ManBmcCountNonternary_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *, unsigned int *, int, int *)Saig_ManBmcSimInfoGet( pInfo, Aig_ManCo(p, 0) ) == SAIG_TER_UNDvoid Saig_ManBmcCountNonternary(Aig_Man_t *, Vec_Ptr_t *, int)Frame %5d Detected terminary PO in frame %d. void Saig_ManBmcDfs_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)int Saig_ManBmcCountRefed(Aig_Man_t *, Vec_Ptr_t *)Supergates: %d=%d(%d) Cannot open file %s .model test n%d n%d test.blifLStart(P) = %d LDelta(Q) = %d LRatio(R) = %d ReduceDB = %d Vars = %d Used = %d (%.2f %%) Buffs = %d. Dups = %d. Hash hits = %d. Hash misses = %d. UniProps = %d. p->pAig->vSeqModelVec == NULLvoid Saig_Bmc3ManStop(Gia_ManBmc_t *)int Saig_ManBmcCreateCnf_rec(Gia_ManBmc_t *, Aig_Obj_t *, int)uTruth != 0 && uTruth != 0xffffiEntry * 5 == Vec_IntSize(p->vData)iEntry == Vec_IntSize(p->vId2Lit)void Saig_ManBmcCreateCnf_iter(Gia_ManBmc_t *, Aig_Obj_t *, int, Vec_Int_t *)int Saig_ManBmcRunTerSim_rec(Gia_ManBmc_t *, Aig_Obj_t *, int)Running "bmc3". PI/PO/Reg = %d/%d/%d. And =%7d. Lev =%6d. ObjNums =%6d. Params: FramesMax = %d. Start = %d. ConfLimit = %d. TimeOut = %d. SolveAll = %d. Stopping BMC because all 2^%d reachable states are visited. Stopping BMC because all targets are disproved or timed out. Reached gap timeout (%d seconds). Bmc3 got callbacks. p->pTime4Outs[i] > 0int Saig_ManBmcScalable(Aig_Man_t *, Saig_ParBmc_t *)Frame %5d Output %5d Time(ms) %8d %8d %4d %s : Var =%8.0f. Cla =%9.0f. Conf =%7.0f. Learn =%7.0f. %9.2f sec Output %*d was asserted in frame %2d (solved %*d out of %*d outputs). Quitting due to callback on fail. status == l_UndefCEX =%5d. T/O =%4d. %9.2f sec Runtime: CNF = %.1f sec (%.1f %%) UNSAT = %.1f sec (%.1f %%) UNDEC = %.1f sec (%.1f %%)Value >= SAIG_TER_ZER && Value <= SAIG_TER_UNDvoid Saig_ManBmcSimInfoSet(unsigned int *, Aig_Obj_t *, int)!Aig_ObjIsNode(pObj) || Saig_ManBmcMapping(p, pObj)int Saig_ManBmcLiteral(Gia_ManBmc_t *, Aig_Obj_t *, int)ObjNum >= 0vFrame != NULLint Saig_ManBmcSetLiteral(Gia_ManBmc_t *, Aig_Obj_t *, int, int)Saig_ManBmcCofEqual(uTruth, v)int Saig_ManBmcReduceTruth(int, int *)uTruth > 0 && uTruth < 0xffffvoid Saig_ManBmcAddClauses(Gia_ManBmc_t *, int, int *, int)Lits[b] > 1%5d : 0 =%7d 1 =%7d x =%7d all =%7d out = %s Finished %d frames. First x-valued PO is in frame %d. src/sat/bmc/bmcBmcAnd.cvoid Bmc_MnaCollect_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, unsigned int *)void Bmc_MnaCollect(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, unsigned int *)pObj->Value == GIA_UNDvoid Bmc_MnaSelect_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)Gia_ObjFanin0(pObj)->Value + Gia_ObjFaninC0(pObj) == GIA_ONEGia_ObjFanin1(pObj)->Value + Gia_ObjFaninC1(pObj) == GIA_ONEvoid Bmc_MnaBuild_rec(Gia_Man_t *, Gia_Obj_t *, Gia_Man_t *, Vec_Int_t *, Vec_Int_t *)Vec_IntEntry(vMap, Gia_ObjId(p, pObj)) != -1void Bmc_MnaBuild(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Gia_Man_t *, Vec_Int_t *, Vec_Int_t *)Frame %4d : Roots = %6d Leaves = %6d Cone = %6d Gia_Man_t *Gia_ManBmcUnroll(Gia_Man_t *, int, int, int, Vec_Int_t **)Vec_IntEntry( p->vId2Var, iObj ) == 0int Gia_ManBmcAssignVarIds(Bmc_Mna_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)pCnf->pVarNums[0] > 0void Gia_ManBmcAddCnf(Bmc_Mna_t *, Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)pCnf->pVarNums[i] >= 0 && pCnf->pVarNums[i] < pCnf->nVarsVec_IntEntry(p->vId2Var, iObj) > 0pCnf->pClauses[0][i] > 1 && pCnf->pClauses[0][i] < 2 * pCnf->nVars%4d : PI =%9d. AIG =%9d. Var =%8d. In =%6d. And =%9d. Cla =%9d. Conf =%9d. Mem =%7.1f MB SAT solver reached conflict/runtime limit in frame %d. frames.aigiFramePi == Gia_ManPiNum(pMan->pFrames)Abc_Cex_t *Gia_ManBmcCexGen(Bmc_Mna_t *, Gia_Man_t *, int)Unfolding for %d frames with first non-trivial PO %d. pClauseThis[nLits] > 1 && pClauseThis[nLits] < 2*Gia_ManObjNum(p->pFrames)void Gia_ManBmcAddCnfNew_rec(Bmc_Mna_t *, Gia_Obj_t *)nLits <= 9Output %d is trivially SAT. pPars->nTimeOut >= 0int Gia_ManBmcPerform(Gia_Man_t *, Bmc_AndPar_t *)Value >= GIA_ZER && Value <= GIA_UNDvoid Gia_ManTerSimInfoSet(unsigned int *, int, int) Error in CNF generation: Constant literal! Dumped unfolded frames into file "frames.aig".Gia_ManRegNum(p) == Vec_IntSize(vFFLits)src/sat/bmc/bmcBmci.cvoid Bmc_BmciUnfold(Gia_Man_t *, Gia_Man_t *, Vec_Int_t *, int)int Bmc_BmciPart_rec(Gia_Man_t *, Vec_Int_t *, int, Gia_Man_t *, Vec_Int_t *, Vec_Int_t *)iLit >= 2Gia_Man_t *Bmc_BmciPart(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Gia_ManPoNum(pPart) > 0Vec_IntSize(vPartMap) == Gia_ManObjNum(pPart)Vec_IntSize(vInit0) == Gia_ManRegNum(p)int Bmc_BmciPerform(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, int, int, int, int)Vec_IntSize(vInit1) == Gia_ManRegNum(p)Vec_IntSize(vLits0) == Vec_IntSize(vLits1)Vec_IntSize(vMiters) == Gia_ManRegNum(p)Reached a fixed point after %d frames. Gia_ObjIsCi(pObj) || Vec_IntEntry( vSatMap, Vec_IntEntry(vPartMap, i) ) == -1Vec_IntEntry(vSatMap, Abc_Lit2Var(iLit)) > 0Timeout reached after %d seconds. (iLit0 >= 2 || iLit1 >= 2) && iLit0 != iLit1Frame %4d : Vars =%7d Clause =%10d Conflict =%10d AIG =%7d Miters =%5d SAT =%5d Gia_ManRegNum(pGia) > 0src/sat/bmc/bmcBmcG.cBmcg_Man_t *Bmcg_ManStart(Gia_Man_t *, Bmc_AndPar_t *)int Bmcg_ManUnfold_rec(Bmcg_Man_t *, int, int)int Bmcg_ManCollect_rec(Bmcg_Man_t *, int)Gia_ManPoNum(p->pFrames) == f * Gia_ManPoNum(p->pGia)Gia_Man_t *Bmcg_ManUnfold(Bmcg_Man_t *, int, int)Vec_PtrSize(&p->vGia2Fr) == f+k+1Var =%8.0f. Cla =%9.0f. Learn =%9.0f. Conf =%9.0f. S = %3d. Unfolding CNF generationCNF simplify SAT solving Other TOTAL void Bmcg_ManAddCnf(Bmcg_Man_t *, bmcg_sat_solver *, Cnf_Dat_t *)Gia_ManPoNum(p->pFrames) == (f + pPars->nFramesAdd) * Gia_ManPoNum(pGia)int Bmcg_ManPerformOne(Gia_Man_t *, Bmc_AndPar_t *)Output %*d was asserted in frame %2d (solved %*d out of %*d outputs). @33?src/sat/bmc/bmcBmcS.cvoid Bmc_SuperBuildTents_rec(Gia_Man_t *, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, int)void Gia_ManCountTents_rec(Gia_Man_t *, int, Vec_Int_t *)int Gia_ManCountTents(Gia_Man_t *)void Gia_ManCountRanks_rec(Gia_Man_t *, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, int)int Gia_ManCountRanks(Gia_Man_t *)Tents = %6d. Cands = %6d. %10.2f %% Bmcs_Man_t *Bmcs_ManStart(Gia_Man_t *, Bmc_AndPar_t *)int Bmcs_ManUnfold_rec(Bmcs_Man_t *, int, int)int Bmcs_ManCollect_rec(Bmcs_Man_t *, int)Gia_Man_t *Bmcs_ManUnfold(Bmcs_Man_t *, int, int)void Bmcs_ManAddCnf(Bmcs_Man_t *, satoko_t *, Cnf_Dat_t *)int Bmcs_ManPerformOne(Gia_Man_t *, Bmc_AndPar_t *)ThData[i].fWorking == 0int Bmcs_ManPerform_Solve(Bmcs_Man_t *, int, pthread_t *, Par_ThData_t *, int, int *)int Bmcs_ManPerformMulti(Gia_Man_t *, Bmc_AndPar_t *)pPars->nProcs < PAR_THR_MAXint Bmcs_ManPerform(Gia_Man_t *, Bmc_AndPar_t *)pCex->nPis == pCexCare->nPissrc/sat/bmc/bmcCexCare.cAbc_Cex_t *Bmc_CexCareExtendToObjects(Gia_Man_t *, Abc_Cex_t *, Abc_Cex_t *)pCex->nRegs == pCexCare->nRegspCex->nBits == pCexCare->nBitsGia_ObjTerSimGet1(pObj)Vec_IntSize(vPriosIn) == pCex->nPis * (pCex->iFrame + 1)void Bmc_CexCarePropagateFwdOne(Gia_Man_t *, Abc_Cex_t *, int, Vec_Int_t *)Abc_Cex_t *Bmc_CexCareMinimizeAig(Gia_Man_t *, int, Abc_Cex_t *, int, int, int)Original : Counter == pCex->nPis * (pCex->iFrame + 1)Vec_IntSize(vPriosFf) == pCex->nRegs * (pCex->iFrame + 1)PI- PPI-: PI+ PPI-: PI- PPI+: PI+ PPI+: Final : Minimized: void Gia_ObjTerSimRo(Gia_Man_t *, Gia_Obj_t *)!Gia_ObjTerSimGetC( pTemp )Gia_Obj_t *Gia_ObjRoToRi(Gia_Man_t *, Gia_Obj_t *)void Gia_ObjTerSimAnd(Gia_Obj_t *)!Gia_ObjTerSimGetC( Gia_ObjFanin0(pObj) )!Gia_ObjTerSimGetC( Gia_ObjFanin1(pObj) )void Gia_ObjTerSimCo(Gia_Obj_t *)Given CEX has PO whose index is out of range for the AIG.Counter-example is invalid.Given CEX does to have same number of flops as the AIG.Given CEX does to have same number of inputs as the AIG.Counter-example verification has failed.Counter-example verification succeeded.src/sat/bmc/bmcCexCut.cint Bmc_GiaGenerateJust_rec(Gia_Man_t *, int, int, Vec_Bit_t *, Vec_Bit_t *)void Bmc_GiaGenerateJustNonRec(Gia_Man_t *, int, Vec_Bit_t *, Vec_Bit_t *)void Bmc_GiaGenerateJust(Gia_Man_t *, Abc_Cex_t *, Vec_Bit_t **, Vec_Bit_t **)Vec_BitEntry(vJustis, Gia_ManObjNum(p) * pCex->iFrame + Gia_ObjId(p, pObj)) == 0Vec_BitEntry(vJustis, Gia_ManObjNum(p) * pCex->iFrame + Gia_ObjId(p, pObj)) == 1i == iFrEndGia_Man_t *Bmc_GiaGenerateGiaAllFrames(Gia_Man_t *, Abc_Cex_t *, Vec_Bit_t **, int, int)pObj->Value > 0Gia_Man_t *Bmc_GiaGenerateGiaAllOne(Gia_Man_t *, Abc_Cex_t *, Vec_Bit_t **, int, int)Gia_Man_t *Bmc_GiaTargetStates(Gia_Man_t *, Abc_Cex_t *, int, int, int, int, int, int)iFrBeg < iFrEndCurrent CEX does not fail AIG "%s". miter3.aigsrc/sat/bmc/bmcCexDepth.cGia_Man_t *Bmc_CexBuildNetwork2(Gia_Man_t *, Abc_Cex_t *, int)pCex->nPis == Gia_ManCiNum(p)fStart <= pCex->iFramepObj->fMark0 == 1pObj->fMark1 == 0Gia_Man_t *Bmc_CexBuildNetwork2_(Gia_Man_t *, Abc_Cex_t *, int)Processing CEX in frame %d (max frames %d). Frame %5d : miter2.aigGIA with additional properties is written into "miter2.aig".Counter-example care-set verification has failed.Aig_ObjFanin0(pObj)->iData >= 0src/sat/bmc/bmcCexMin1.cvoid Saig_ManCexMinDerivePhasePriority_rec(Aig_Man_t *, Aig_Obj_t *)Aig_ObjFanin1(pObj)->iData >= 0pObj->iData >= 0void Saig_ManCexMinDerivePhasePriority(Aig_Man_t *, Abc_Cex_t *, Vec_Vec_t *, Vec_Vec_t *, int, Vec_Int_t *)Vec_IntSize(vFramePPsOne) == 0Vec_Vec_t *Saig_ManCexMinCollectPhasePriority_(Aig_Man_t *, Abc_Cex_t *, Vec_Vec_t *)Vec_Vec_t *Saig_ManCexMinCollectPhasePriority(Aig_Man_t *, Abc_Cex_t *, Vec_Vec_t *)void Saig_ManCexMinCollectReason_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Int_t *, int)fPhase0 && fPhase1!fPhase0 || !fPhase1pCex->nPis == Saig_ManPiNum(pAig)Vec_Vec_t *Saig_ManCexMinComputeReason(Aig_Man_t *, Abc_Cex_t *, int)pCex->nRegs == Saig_ManRegNum(pAig)pCex->iPo >= 0 && pCex->iPo < Saig_ManPoNum(pAig)pAig->nConstrs == 0Aig_Man_t *Saig_ManCexMinDupWithCubes(Aig_Man_t *, Vec_Vec_t *)Lit >= 0 && Lit < 2 * Aig_ManRegNum(pAig)Reason size = %d. Ave = %d. aigcube.aigIntermediate AIG is written into file "%s". ./src/aig/saig/saig.hAig_Obj_t *Saig_ObjLoToLi(Aig_Man_t *, Aig_Obj_t *)int Saig_ObjRegId(Aig_Man_t *, Aig_Obj_t *)p->vTruths == NULLsrc/sat/bmc/bmcCexMin2.cint Gia_ManAnnotateUnrolling(Gia_Man_t *, Abc_Cex_t *, int)Value == (Value0 & Value1)iFrame >= 0 && iFrame <= pCex->iFrameGia_Man_t *Gia_ManCreateUnate(Gia_Man_t *, Abc_Cex_t *, int, int, int)(Gia_ManGetTwo(p, pCex->iFrame, pObj) >> 1)pCex->nPis == Gia_ManPiNum(p)Abc_Cex_t *Gia_ManCexMin(Gia_Man_t *, Abc_Cex_t *, int, int, int, int, int)pCex->iPo < Gia_ManPoNum(p)iFrameStart >= 0 && iFrameStart <= pCex->iFramenRealPis < Gia_ManPiNum(p)cex/stats.txtcex/aig_stats.txtGia_ManRegNum(p) > 0src/sat/bmc/bmcCexTools.cGia_Man_t *Bmc_CexPerformUnrolling(Gia_Man_t *, Abc_Cex_t *)unroll.aigGia_Man_t *Bmc_CexBuildNetwork(Gia_Man_t *, Abc_Cex_t *)unate.aigvoid Bmc_CexPrint(Abc_Cex_t *, int, int)pCex->nRegs > 0Abc_Cex_t *Bmc_CexInnerStates(Gia_Man_t *, Abc_Cex_t *, Abc_Cex_t **, int)Gia_ManPo(p, pCex->iPo)->fMark0 == 1Inner states: void Bmc_CexCareBits_rec(Gia_Man_t *, Gia_Obj_t *)fCompl0 == 1 && fCompl1 == 1fCompl0 == 0 || fCompl1 == 0void Bmc_CexCareBits2_rec(Gia_Man_t *, Gia_Obj_t *)pCexState->nRegs == 0Abc_Cex_t *Bmc_CexCareBits(Gia_Man_t *, Abc_Cex_t *, Abc_Cex_t *, Abc_Cex_t *, int, int)Gia_ManPo(p, pCexState->iPo)->fMark0 == 1Care bits: Abc_Cex_t *Bmc_CexEssentialBitOne(Gia_Man_t *, Abc_Cex_t *, int, Abc_Cex_t *, int *)iBit < pCexState->nBitspCexState->nBits == pCexCare->nBitsAbc_Cex_t *Bmc_CexEssentialBits(Gia_Man_t *, Abc_Cex_t *, Abc_Cex_t *, int)Essentials: Vec_IntSize(vPat) == Gia_ManCiNum(p)void Gia_ManCountCareBits(Gia_Man_t *, Vec_Wec_t *)Stats over %d patterns: Average care-nodes = %d (%6.2f %%) train-images.idx3-ubyteRetValue == Sizeunsigned char *Mnist_ReadImages1_()EssentialNot essentialCE-induced network is written into file "unroll.aig".CE-induced network is written into file "unate.aig".Counter-example min-set verification has failed.No output asserted in %d frames. Resource limit reached. src/sat/bmc/bmcChain.cGia_Man_t *Gia_ManVerifyCexAndMove(Gia_Man_t *, Abc_Cex_t *)Gia_ManPiNum(p) == Gia_ManPiNum(pNew)Gia_Man_t *Gia_ManDupPosAndPropagateInit(Gia_Man_t *)Gia_ManPoNum(p) == Gia_ManPoNum(pNew)Vec_IntSize(vSatIds) == Gia_ManPiNum(p)sat_solver *Gia_ManDeriveSatSolver(Gia_Man_t *, Vec_Int_t *)p->nRegs == 0Gia_ObjFaninLit0p(p, pObj) != 0Gia_Man_t *Bmc_ChainCleanup(Gia_Man_t *, Vec_Int_t *)Gia_ObjFaninLit0p(p, pObj) == 0BMC could not detect a failed output in %d frames with %d conflicts. !Iter || pCex->iFrame > 0int Bmc_ChainTest(Gia_Man_t *, int, int, int, int, Vec_Ptr_t **)Vec_IntFind(vOutputs, pCex->iPo) >= 0Iter %4d : Depth =%5d FailPo =%5d UndecPo =%5d AIG =%8d Completed a CEX chain with %d segments, %d frames, and %d failed POs (out of %d). BMC Init CleanTotal number of CEXes collected = %d. void Gia_ObjMakePoConst0(Gia_Man_t *, Gia_Obj_t *)Finished all POs.Number of patterns = %d. %3c Off0 Off1 On0 On1 Diff %c . Vec_StrSize(vSop) == nCubes * (nVars + 3) + 1src/sat/bmc/bmcClp.cint Bmc_CollapseIrredundant(Vec_Str_t *, int, int)int Bmc_CollapseIrredundantFull(Vec_Str_t *, int, int)int Bmc_CollapseExpandRound2(sat_solver *, Vec_Int_t *, Vec_Int_t *, int, int)fOnOffSetLit == -1int Bmc_CollapseExpandRound(sat_solver *, sat_solver *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, int, int, int)int Bmc_CollapseExpand(sat_solver *, sat_solver *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, int, int, int)int Bmc_CollapseExpand2(sat_solver *, sat_solver *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, int, int, int)int Bmc_ComputeCanonical2(sat_solver *, Vec_Int_t *, Vec_Int_t *, int)Vec_Str_t *Bmc_CollapseOneInt2(Gia_Man_t *, int, int, int, int, int, int)Vec_Str_t *Bmc_CollapseOneOld(Gia_Man_t *, int, int, int, int, int)!fComplete[0] || !fComplete[1]Processed output with %d supp vars. The resulting SOP exceeded %d cubes. The best cover contains %d cubes. Onset mintermOnset expand Offset mintermOffset expand Vec_Str_t *Bmc_CollapseOne_int3(sat_solver *, sat_solver *, sat_solver *, sat_solver *, int, int, int, int, int, int)Vec_Str_t *Bmc_CollapseOne_int2(sat_solver *, sat_solver *, int, int, int, int, int, int)Vec_Str_t *Bmc_CollapseOne_int(sat_solver *, int, int, int, int, int, int)void Gia_ObjFlipFaninC0(Gia_Obj_t *)Gia_ManCiNum(pGold) == Gia_ManCiNum(pOld)src/sat/bmc/bmcEco.cGia_Man_t *Bmc_EcoMiter(Gia_Man_t *, Gia_Man_t *, Vec_Int_t *)Gia_ManCoNum(pGold) == Gia_ManCoNum(pOld) - 1Gia_ObjIsAnd(pRoot)Gia_ManPiNum(pNew) == Gia_ManCiNum(pGold) + 1Gia_ManPoNum(pNew) == Gia_ManCoNum(pGold) + 1 + Vec_IntSize(vFans)int Bmc_EcoSolve(sat_solver *, int, Vec_Int_t *)Cube %d : int Bmc_EcoPatch(Gia_Man_t *, int, int)Gia_ManPoNum(p) == nOuts + 1 + nInsVec_IntSize(vVars) == nInseco_gold.aigeco_old.aigeco_miter.aigResource limit exceeded.Cannot be patched.Patch is computed.nVars == Vec_IntSize(vVars)src/sat/bmc/bmcExpand.cint Abc_ObjExpandCubesTry(Vec_Str_t *, sat_solver *, Vec_Int_t *)int Abc_ObjExpandCubes(Vec_Str_t *, Gia_Man_t *, int)void Abc_NtkExpandCubes(Abc_Ntk_t *, Gia_Man_t *, int)Abc_NtkCiNum(pNtk) == Gia_ManCiNum(pGia)Abc_NtkCoNum(pNtk) == Gia_ManCoNum(pGia)Abc_ObjFaninNum(pObj) == Gia_ManCiNum(pGia)Gia_ManCiNum(pNew) == Gia_ManCiNum(pGia)7 pVnSizeOld >= 2src/sat/bmc/bmcFault.cvoid Cnf_AddCardinConstrPairWise(sat_solver *, Vec_Int_t *, int, int)K > 0 && K < nSizeOldvoid Cnf_AddCardinConstrGeneral(sat_solver *, Vec_Int_t *, int, int)K > 0 && K < nBitsGia_ManPiNum(pNew) == Gia_ManRegNum(p) + 2 * Gia_ManPiNum(p) + (fFfOnly ? Gia_ManRegNum(p) : Gia_ManAndNum(p))Gia_Man_t *Gia_ManFaultUnfold(Gia_Man_t *, int, int)iFuncVars == Vec_IntSize(vMap)Gia_Man_t *Gia_ManStuckAtUnfold(Gia_Man_t *, Vec_Int_t *)Gia_ManPiNum(pNew) == Gia_ManCiNum(p) + 2 * Gia_ManAndNum(p)Gia_Man_t *Gia_ManFlipUnfold(Gia_Man_t *, Vec_Int_t *)Gia_ManPiNum(pNew) == Gia_ManCiNum(p) + Gia_ManAndNum(p)Gia_Man_t *Gia_ManFOFUnfold(Gia_Man_t *, Vec_Int_t *)Gia_ManPiNum(pNew) == Gia_ManCiNum(p) + 4 * Gia_ManAndNum(p)Expecting alphabetic symbol (instead of "%c") after negation (~) Unknown symbol (%c) in the formula (%s) The number of input variables (%d) should be 2 The number of parameters should be between 1 and %d pForm[i] >= 'a' && pForm[i] <= 'z'void Gia_FormStrTransform(char *, char *)*pThis != '~'char *Gia_ManFormulaEndToken(char *)void Gia_ManPrintFormula_rec(char *, char *)Oper == '?'pEndNew[0] == ':'Using formula: int Gia_ManRealizeFormula_rec(Gia_Man_t *, int *, int *, char *, char *, int)strlen(pForm) < 100Gia_Man_t *Gia_ManFormulaUnfold(Gia_Man_t *, char *, int)Gia_ManPiNum(pNew) == Gia_ManCiNum(p) + nPars * (fFfOnly ? Count : Gia_ManAndNum(p))Gia_ManPiNum(pNew) == Gia_ManPiNum(p)Gia_Man_t *Gia_ManFaultCofactor(Gia_Man_t *, Vec_Int_t *)Vec_IntSize(vTests) % nIter == 0void Gia_ManDumpTests(Vec_Int_t *, int, char *)Vec_IntSize(vValues) == Gia_ManCiNum(p)void Gia_ManDumpTestsSimulate(Gia_Man_t *, Vec_Int_t *)Vec_IntSize(vValues) == Gia_ManRegNum(p)void Gia_ManDumpTestsDelay(Vec_Int_t *, int, char *, Gia_Man_t *)nVars == 2 * Gia_ManPiNum(p) + Gia_ManRegNum(p)fault_stats.txtint Gia_ManFaultAddOne(Gia_Man_t *, Cnf_Dat_t *, sat_solver *, Vec_Int_t *, int, int, Gia_Man_t *)Timeout reached after dumping %d untestable faults. Untestable fault %4d : Wrong symbol (%c) in the input file. Vec_IntSize(vPars) == Vec_IntSize(vMap)int Gia_ManFaultAnalyze(sat_solver *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, int)Vec_IntEntry(vLits, v) == 1Vec_IntEntry(vMap, v) == 1Vec_IntEntry(vLits, v) == 0Iteration %3d has determined %5d (out of %5d) parameters after %6d SAT calls. newfaults.txtVec_IntSize(vTests) % nFuncVars == 0int Gia_ManFaultDumpNewFaults(Gia_Man_t *, int, Vec_Int_t *, Vec_Int_t *, Bmc_ParFf_t *)Dumped %d new multiple faults into file "%s". The number of symbols in the input patterns (%d) does not divide evenly on the number of test variables (%d). int Gia_ManFaultPrepare(Gia_Man_t *, Gia_Man_t *, Bmc_ParFf_t *, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Gia_Man_t **, Cnf_Dat_t **, sat_solver **, int)Reading %d pre-computed test patterns from file "%s". Reading %d pre-computed test patterns from previous rounds. Timeout reached after %d seconds and adding %d tests. The problem is UNSAT after adding %d tests. Iter%6d : Var =%10d Solver timeTimeout reached after %d seconds and %d iterations. The problem is UNSAT after %d iterations. Using miter with: AIG nodes = %6d. CNF variables = %6d. CNF clauses = %8d. FFTEST is computing test patterns for fault model "%s"... FFTEST is computing test patterns for %sdelay faults... single FFTEST is computing test patterns for %sstuck-at faults... FFTEST is computing test patterns for %scomplement faults... FFTEST is computing test patterns for %sfunctionally observable faults... Unrecognized algorithm (%d). Options: Untestable faults = %s. Using %sstrict cardinality %d. non-Faults at FF outputs only = yes. Runtime limit = %d sec. Golden model = %s. Verbose = %s. Vec_IntSize(vPars) == Gia_ManPiNum(pM) - nFuncVarsvoid Gia_ManFaultTest(Gia_Man_t *, Gia_Man_t *, Bmc_ParFf_t *)The problem is UNSAT after %d iterations. Testing runtime_tests.txtDumping %d pairs of test patterns (total %d pattern) into file "%s". Dumping %d test patterns into file "%s". Vec_IntSize(vTests) == Iter * nFuncVarsThere are untestable faults. There is no untestable faults. Fault computation runtimeThe circuit is rectifiable. The circuit is not rectifiable (or equivalent to the golden one). Rectification runtime_untest.txtDumped %d untestable multiple faults into file "%s". Dumped %d ways of rectifying the circuit into file "%s". int Cnf_AddCardinConstr(sat_solver *, Vec_Int_t *)The number of opening and closing parentheses is not equal.The last symbol should be the closing parenthesis ")".The first symbol should be the opening parenthesis "(".The input test patterns are not given.This should never happen.src/sat/bmc/bmcFx.cDivisors = %d. int Bmc_FxSolve(sat_solver *, int, int, Vec_Int_t *, int, int, int *, Vec_Wec_t *)iVar >= 0 && iVar < Vec_IntSize(vVars).p %d Cubes = %d. Reduced = %d. Lits = %d Out %3d %sset onOnset = %5d. Offset = %5d. Onset = %5d. Offset = %5d. Vec_IntSize(vDivs) % 4 == 0void Bmc_FxAddClauses(sat_solver *, Vec_Int_t *, int, int) Iteration %d (Aux = %d) Vec_IntSize(vVar2Sat) <= nCiVars + Extraint Bmc_FxComputeOne(Gia_Man_t *, int, int)p->nBins < p->SizeMask + 1int Tab_TabHashAdd(Tab_Tab_t *, int *, int, int)!pEnt->Next || pEnt->Next != pBin->Tablevoid Tab_TabRehash(Tab_Tab_t *)LitA[0] >= 0 && LitB[0] >= 0Div_Type_t Div_FindType(int *, int *, int *, int *)LitA[0] != LitB[0]LitA[1] != LitB[1]LitA[0] >= 0 && LitA[1] >= 0LitB[0] >= 0 && LitB[1] == -1LitA != LitBDiv_Type_t Bmc_FxDivOr(int, int, int *, int *)Div_Type_t Bmc_FxDivXor(int, int, int *, int *)LitC != LitCnDiv_Type_t Bmc_FxDivMux(int, int, int, int, int *, int *)Abc_Lit2Var(LitC) == Abc_Lit2Var(LitCn)Abc_Lit2Var(LitC) != Abc_Lit2Var(LitT)Abc_Lit2Var(LitC) != Abc_Lit2Var(LitE)Lit0 = %5d. Lit1 = %5d. Lit2 = %5d. Func = %s. Cost = %3d. TimeoutMismatchsrc/sat/bmc/bmcGen.cint Gia_ManTestSatEnum(Gia_Man_t *)Finished generating %d assignments. SAT solver timesrc/sat/bmc/bmcICheck.csat_solver *Bmc_DeriveSolver(Gia_Man_t *, Gia_Man_t *, Cnf_Dat_t *, int, int, int)nFramesMax > 0void Bmc_PerformICheck(Gia_Man_t *, int, int, int, int)Solving M-inductiveness for design %s with %d AND nodes and %d flip-flops: Gia_ManPoNum(pMiter) == 2 * Gia_ManPoNum(p)Gia_ManRegNum(pMiter) == 2 * Gia_ManRegNum(p)Timeout reached after %d seconds. i == Abc_Lit2Var(Lit)M =%4d : AIG =%8d. SAT vars =%8d. SAT conf =%8d. S =%6d. (%6.2f %%) void Bmc_PerformFindFlopOrder_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)Gia_ObjIsPo(p, pObj) || Gia_ObjIsRo(p, pObj)void Bmc_PerformFindFlopOrder(Gia_Man_t *, Vec_Int_t *)Vec_IntSize(vRegs) == Gia_ManCoNum(p)iReg >= 0 && iReg < Gia_ManRegNum(p)Vec_IntSize(vRegs) == Gia_ManRegNum(p)int Bmc_PerformISearchOne(Gia_Man_t *, int, int, int, int, int, Vec_Int_t *)I = %4d : ICheck: Timeout reached after %d seconds. I = %4d : AIG =%8d. SAT vars =%8d. SAT conf =%8d. S =%6d. (%6.2f %%) M = %4d : AIG =%8d. SAT vars =%8d. SAT conf =%8d. S =%6d. (%6.2f %%) Solving M-inductiveness for design %s with %d AND nodes and %d flip-flops with %s %s flop order: reversedirectnaturalThe set contains %d (out of %d) next-state functions with 0-based numbers: v < Gia_ManRegNum(p)Gia_Obj_t *Gia_ManRi(Gia_Man_t *, int)iVarF >= 0 && iVarA >= 0 && iVarB >= 0 && iVarC >= 0int sat_solver_add_xor_and(sat_solver *, int, int, int, int)The problem is satisfiable (the current set is not M-inductive).Problem is satisfiable.src/sat/bmc/bmcInse.cvoid Gia_ManInseSimulateObj(Gia_Man_t *, int)(pData0[i] & pData1[i]) == 0void Gia_ManInseFindStarting(Gia_Man_t *, int, Vec_Int_t *, Vec_Int_t *)Vec_IntSize(vInputs) % Gia_ManPiNum(p) == 0Vec_Int_t *Gia_ManInseSimulate(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)iBit == Vec_IntSize(vInputs)Vec_IntEntry(vInit, i) == 2 || Vec_IntEntry(vInit, i) == (int)pObj->fMark0Running with %d frames, %d words, and %sgiven init state. Frame =%6d : Values =%6d (out of %6d) Frame =%6d : Values =%6d (out of %6d) After %d frames, found a sequence to produce %d x-values (out of %d). src/sat/bmc/bmcLoad.cint Bmc_LoadAddCnf(void *, int)Frame%4d : Vars = %6d Clas = %6d UNSAT UNDEC Callbacks = %d. Loadings = %d. 6+5+5+5+56+5+5+5+5+5+5+5+5+5+5+56+5+5+5+56 666$616>6p->nObjs <= MAJ_NOBJSsrc/sat/bmc/bmcMaj.cint Maj_ManMarkup(Maj_Man_t *)The number of parameter variables = %d. Realization of %d-input majority using %d MAJ3 gates: %02d = MAJ( %02dint Maj_ManAddCnfStart(Maj_Man_t *)Vec_IntSize(vArray) > 0int Maj_ManExactSynthesis(int, int, int, int, int)Running exact synthesis for %d-input majority with %d MAJ3 gates... Iter %3d : Var =%5d Cla =%6d Conf =%9d int Exa_ManMarkup(Exa_Man_t *)%s_%d_%d.blif# Realization of the %d-input function %s using %d two-input gates: .model %s_%d_%d .outputs F %02d Solution was dumped into file "%s". Realization of given %d-input function using %d two-input gates: %02d = 4'b%d%d%d1(%02d = 4'b%d%d%d0(int Exa_ManAddCnfStart(Exa_Man_t *, int)pPars->nVars <= 10void Exa_ManExactSynthesis(Bmc_EsPar_t *)Running exact synthesis for %d-input function with %d two-input gates... The problem timed out after %d sec. void Exa3_ManExactSynthesis(Bmc_EsPar_t *)Running exact synthesis for %d-input function with %d %d-input LUTs... Added = %d. Tried = %d. int Maj_ManFindFanin(Maj_Man_t *, int, int)iMint < (1 << p->nVars)int Maj_ManEval(Maj_Man_t *)int Exa_ManFindFanin(Exa_Man_t *, int, int)int Exa_ManEval(Exa_Man_t *)int Exa3_ManMarkup(Exa3_Man_t *)int Exa3_ManAddCnfStart(Exa3_Man_t *, int)nLits <= 2*p->nLutSize+2int Exa3_ManAddCnf2(Exa3_Man_t *, int)int Exa3_ManFindFanin(Exa3_Man_t *, int, int)i < n && j < n && i < jint Exa3_ManIsUsed2(Exa3_Man_t *, int, int, int, int)i < n && j < n && k < n && i < j && j < kint Exa3_ManIsUsed3(Exa3_Man_t *, int, int, int, int, int)nLits <= p->nLutSize+2int Exa3_ManAddCnf(Exa3_Man_t *, int)int Exa3_ManEval(Exa3_Man_t *)Realization of given %d-input function using %d %d-input LUTs: %02d = %d'bThe problem has no solution.޴{{{{,{{{{{{{{{{{,{{{{޴Y`gtsrc/sat/bmc/bmcMaj2.cint Maj_ManExactSynthesis2(int, int, int, int, int, int, int)The problem has no solution after %2d iterations. void Exa_ManExactSynthesis2(Bmc_EsPar_t *)void Exa3_ManExactSynthesis2(Bmc_EsPar_t *) Node %2d +%d -> %d [{Z{Z{Z{Z,\{Z{Z{Z{Z{Z{Z{Z{Z{Z{Z{Z,\{Z{Z{Z{Z[Y[`[g[t[[[dLdSdjdSdSdSdqdSdSdSdSdSdSdSdxdSdSdSdSdSdSdSdSdSdSdSdSdSdSdSddSdSdSdSdSdSdSdSdSdSdSdSdSdSdSdSdSdSdSdSdSdSdSdSdSdSdSdSdSdSdSddUUUUUUUU33333333Obj == nObjssrc/sat/bmc/bmcMaj3.cvoid Maj3_ManFirstAndLevel(Vec_Int_t *, int *, int *, int, int)Vec_IntEntry(p->vLevels, 0) == 1int Maj3_ManMarkup(Maj3_Man_t *)p->nObjs <= MAJ3_OBJSp->nNodes == Vec_IntSum(p->vLevels)Variable map for problem with %d inputs, %d nodes and %d levels: . + %3d%c Count <= 3int Maj3_ManAddCnfStart(Maj3_Man_t *)nLits2 > 0 && nLits2 <= 5int Maj3_ManAddCnf(Maj3_Man_t *, int)p->nLits[0] > 0int Maj3_ManAddConstraintsLazy(Maj3_Man_t *)Lazy =%9d void Zyx_SetConstVar(Zyx_Man_t *, int, int)Vec_IntEntry(p->vVarValues, Var) == -1int Zyx_ManAddCnfStart(Zyx_Man_t *)Using %d active functionality vars and %d active topology vars (out of %d SAT vars). p->pPars->fMajority == (pTruth == NULL)Vec_Wrd_t *Zyx_ManTruthTables(Zyx_Man_t *, word *)Vec_Int_t *Zyx_ManCreateSymVarPairs(word *, int)i >= p->pPars->nVars && i < p->nObjsint Zyx_ManCollectFanins(Zyx_Man_t *, int)nFanins == p->nLits[1]int Zyx_ManAddCnfLazyTopo(Zyx_Man_t *)bmcg_sat_solver_read_cex_varvalue(p->pSat, Zyx_FuncVar(p, i-1, k)) == 1bmcg_sat_solver_read_cex_varvalue(p->pSat, Zyx_FuncVar(p, i , k)) == 0bmcg_sat_solver_read_cex_varvalue(p->pSat, Zyx_TopoVar(p, i-1, p->pFanins[i][k])) == 0bmcg_sat_solver_read_cex_varvalue(p->pSat, Zyx_TopoVar(p, i , p->pFanins[i][k])) == 1bmcg_sat_solver_read_cex_varvalue(p->pSat, Zyx_TopoVar(p, i-1, p->pFanins[i-1][k])) == 1bmcg_sat_solver_read_cex_varvalue(p->pSat, Zyx_TopoVar(p, i , p->pFanins[i-1][k])) == 0Entry[0] < Entry[1]Node[j] >= p->pPars->nVarsbmcg_sat_solver_read_cex_varvalue(p->pSat, Zyx_TopoVar(p, Node[1], Entry[0])) == 0bmcg_sat_solver_read_cex_varvalue(p->pSat, Zyx_TopoVar(p, Node[1], Entry[1])) == 1nFanins == p->pPars->nLutSizeint Zyx_ManAddCnfBlockSolution(Zyx_Man_t *)!p->pPars->fMajority || p->pPars->nLutSize == 3int Zyx_ManAddCnfLazyFunc2(Zyx_Man_t *, int)!p->pPars->fMajority && p->pPars->nLutSize < 4int Zyx_ManAddCnfLazyFunc(Zyx_Man_t *, int)void Zyx_ManExactSynthesis(Bmc_EsPar_t *)Running exact synthesis for %d-input function with %d %d-input %s... MAJ-gatesLUTsBecame UNSAT after adding constraints for minterm %d Finished enumerating %d solutions. Node representation has %d chars (expecting %d chars). The output node in line %s is not correct. Structure %3d : Verification successful. Structure %3d : Verification FAILED. Implementation: Specification: p->VarMarks[i][f] > 0int Maj3_ManFindFanin(Maj3_Man_t *, int, int *)nFanins == 3int Maj3_ManEval(Maj3_Man_t *)void Maj3_ManPrintSolution(Maj3_Man_t *)int Zyx_ManIsUsed2(Zyx_Man_t *, int, int, int, int)int Zyx_ManIsUsed3(Zyx_Man_t *, int, int, int, int, int)int Zyx_ManEval(Zyx_Man_t *)iMint < (1 << p->pPars->nVars)Iter %6d : Cla =%9d Lazy =%6d Realization of given %d-input function using %d %d-input %s: %02d = MAJ3-%d-%d.boolabmaj3Dumped solution into file "%s". int Abc_TtWriteHexRev(char *, word *, int)Became UNSAT after adding lazy constraints.Invalid truth table size.Expecting '-' after LUT size before node count.Expecting '-' after truth table before LUT size.The number of nodes in the structure is not correct.This tester does not support structures with more than 16 inputs.This tester does not support nodes with more than 6 inputs.This tester does not support functions with more than 8 inputs.xxxxxx!vInit || Vec_IntSize(vInit) == Gia_ManRegNum(p)src/sat/bmc/bmcMaxi.cGia_Man_t *Gia_ManMaxiUnfold(Gia_Man_t *, int, int, Vec_Int_t *)Gia_ManPiNum(pNew) == 2 * Gia_ManRegNum(p) + nFrames * Gia_ManPiNum(p)Vec_Int_t *Gia_ManMaxiPerform(Gia_Man_t *, Vec_Int_t *, int, int, int)Running with %d frames and %sgiven init state. Subset =%6d Timeout reached after %d seconds and %d iterations. The problem is SAT after %d iterations. Reached fixed point with %d entries after %d iterations. iFirst < iLast && iFirst + 110 > iLastsrc/sat/bmc/bmcMesh.cint Bmc_MeshAddOneHotness(satoko_t *, int, int)X <= 100 && Y <= 100 && T <= 100 && G <= 100void Bmc_MeshTest(Gia_Man_t *, int, int, int, int)The graph has %d inputs: and %d nodes: %c=%c%c SAT variable count is %d (%d time vars + %d graph vars + %d config vars + %d aux vars) pN[g][0] >= 0 && pN[g][1] >= 0Problem has no solution. Finished adding %d clauses. Started solving... Computation timed out. status == SATOKO_SATAdding %d one-hotness clauses. Satisfying solution found. The %d x %d mesh with latency %d with %d active cells (%d nodes and %d buffers): Y\X %-2d %-2d %c%-2d * src/sat/bmc/bmcMesh2.cint Bmc_MeshAddOneHotness2(sat_solver *, int, int)void Bmc_MeshTest2(Gia_Man_t *, int, int, int, int)pN[g][0] < g && pN[g][1] < gVec_PtrSize(vCexesIn) == Vec_IntSize(vOutMap)src/sat/bmc/bmcMulti.cVec_Int_t *Gia_ManProcessOutputs(Vec_Ptr_t *, Vec_Ptr_t *, Vec_Int_t *)Vec_PtrEntry(vCexesOut, iOut) == NULL%3s : PI =%6d PO =%6d FF =%7d ND =%7d Solved =%7d (%5.1f %%) Size =%7d (%5.1f %%) MultiProve parameters: Global timeout = %d sec. Local timeout = %d sec. Time increase = %d %%. Gap timout = %d sec. Per-output timeout = %d msec. Use synthesis = %d. Dump final = %d. Verbose = %d. SIMGlobal timeout (%d sec) is reached. Some outputs are SAT (%d out of %d) after %d frames. BMCGap timeout (%d sec) is reached. SYNThe number of POs proved UNSAT by synthesis = %d. _out.aigFinal AIG was dumped into file "%s". Vec_PtrSize(p->vSeqModelVec) == Gia_ManPoNum(p)int Gia_ManMultiProve(Gia_Man_t *, Bmc_MulPar_t *)%2d : %8d (%6.2f %%) Extra space = %d (%6.2f %%) Vec_IntSize(p->vOrder) == 0src/sat/bmc/bmcUnroll.cvoid Unr_ManSetup(Unr_Man_t *, int)Vec_IntSize(p->vObjLim) == 0((pInts - p->pObjs) & 1) == 0pInts - p->pObjs == nIntsMemory usage = %6.2f MB pUnrObj->fItIsPi && f >= (int)pUnrObj->hFan1Gia_Man_t *Unr_ManUnrollFrame(Unr_Man_t *, int)p->pObjs + hStart == p->pEndGia_ManPoNum(p->pFrames) == (f + 1) * Gia_ManPoNum(p->pGia)Unroll UnrollSframes0.aigframes1.aigvoid Vec_IntWriteMaxEntry(Vec_Int_t *, int, int)h >= 0 && h < p->pEnd - p->pObjsUnr_Obj_t *Unr_ManObj(Unr_Man_t *, int)void Unr_ManObjSetValue(Unr_Obj_t *, int)pFanin->RankCur < pFanin->RankMaxint Unr_ManFanin0Value(Unr_Man_t *, Unr_Obj_t *)pObj->uRDiff0 < pFanin->RankMaxint Unr_ManFanin1Value(Unr_Man_t *, Unr_Obj_t *)pObj->uRDiff1 < pFanin->RankMaxP?pPars->nVarsMax > 1 && pPars->nVarsMax < 16src/bool/bdc/bdcCore.cBdc_Man_t *Bdc_ManAlloc(Bdc_Par_t *)Bi-decomposition stats: Calls = %d. Nodes = %d. Reuse = %d. ANDs = %d. ORs = %d. Weak = %d. Muxes = %d. Memory = %.2f K CacheCheckp->nNodesNew == 0void Bdc_ManPrepare(Bdc_Man_t *, Vec_Ptr_t *)PI %s%d & %s%d Root = %s%d. void Bdc_ManDecPrint_rec(Bdc_Man_t *, Bdc_Fun_t *)F = Constant %d!(nVars <= p->pPars->nVarsMaxint Bdc_ManDecompose(Bdc_Man_t *, unsigned int *, unsigned int *, int, Vec_Ptr_t *, int)%5d : Nodes = %5d. Total = %8d. Id < p->nNodessrc/bool/bdc/bdcInt.hBdc_Fun_t *Bdc_FunWithId(Bdc_Man_t *, int)pF->puOff && pF->puOnvoid Bdc_IsfStart(Bdc_Man_t *, Bdc_Isf_t *) 0 : Const 1Bdc_ManDecompose(): Internal verification failed.!Kit_TruthIsConst0(pIsfR->puOff, p->nVars)src/bool/bdc/bdcDec.cint Bdc_DecomposeUpdateRight(Bdc_Man_t *, Bdc_Isf_t *, Bdc_Isf_t *, Bdc_Isf_t *, Bdc_Fun_t *, Bdc_Type_t)!Kit_TruthIsConst0(pIsfR->puOn, p->nVars)pIsfL->uSupp == 0int Bdc_DecomposeFindInitialVarSet(Bdc_Man_t *, Bdc_Isf_t *, Bdc_Isf_t *, Bdc_Isf_t *)pIsfR->uSupp == 0Kit_TruthSupport(pIsf->puOn, p->nVars) == Kit_TruthSupport(pIsf->puOff, p->nVars)int Bdc_DecomposeOr(Bdc_Man_t *, Bdc_Isf_t *, Bdc_Isf_t *, Bdc_Isf_t *)pIsf->uSupp == Kit_TruthSupport(pIsf->puOn, p->nVars)!Kit_TruthIsConst0(pIsfL->puOn, p->nVars)!Kit_TruthIsConst0(pIsfL->puOff, p->nVars)pIsfL->uUniqpIsfR->uUniqBdc_Fun_t *Bdc_ManCreateGate(Bdc_Man_t *, Bdc_Fun_t *, Bdc_Fun_t *, Bdc_Type_t)Kit_TruthIsDisjoint(pIsf->puOn, pIsf->puOff, p->nVars)Bdc_Fun_t *Bdc_ManDecompose_rec(Bdc_Man_t *, Bdc_Isf_t *)nLeftVars > 0int Bdc_DecomposeGetCost(Bdc_Man_t *, int, int)nRightVars > 0UUUUUUUU33333333 Z@src/bool/bdc/bdcSpfd.cvoid Bdc_SpfdPrint_rec(Bdc_Nod_t *, int, Vec_Ptr_t *)nGatesMax < (1<<8)void Bdc_SpfdDecompose(word, int, int, int)nCands < (1<<12)(1<<(nVars-1))*(1<<(nVars-1)) < (1<<12)Storage size = %d (%d * %d * %d * %d). c == 5 * nVars * (nVars - 1) / 2Selected %6d gates on level %2d. c < nSizeFunction can be implemented using %d gates. Vec_IntEntry(vWeight, pPerm[0]) <= Vec_IntEntry(vWeight, pPerm[c-1])Best SPFD = %d. Selected %6d gates (out of %6d) on level %2d. int Bdc_SpfdCheckOverlap(Bdc_Ent_t *, Bdc_Ent_t *, Bdc_Ent_t *)Allocating %.2f MB of internal memory. Added %d + %d + 0 = %d. Total = %8d. Trying %7d x %7d. Reached limit of %d functions. Added %d + %d + 1 = %d. Total = %8d. func6v6n_bin.txtfunc6v6nW_bin.txtfunc6v5n_bin.txtfunc6v5nW_bin.txtCostBest > 0word Bdc_SpfdFindBest(Vec_Wrd_t *, Vec_Int_t *, word, word, int *)Selected %8d with cost %2d and weight %d: Trying: *** ITER %2d Produce solution with cost %2d (with adj cost %4d). Total = %8d. Best init = %4d. Best cost = %4d. Function can be implemented using 1 gate.Function is an elementary variable.Function is a constant.p->pTable[pIsf->uSupp] == p->pNodessrc/bool/bdc/bdcTable.cBdc_Fun_t *Bdc_TableLookup(Bdc_Man_t *, Bdc_Isf_t *)Kit_TruthIsConst1( pIsf->puOff, p->nVars )!Mvc_CoverIsEmpty(pCover)src/bool/dec/decFactor.cDec_Graph_t *Dec_Factor(char *)!Mvc_CoverIsTautology(pCover)Dec_Edge_t Dec_Factor_rec(Dec_Graph_t *, Mvc_Cover_t *)Mvc_CoverReadCubeNum(pQuo)Mvc_Cover_t *Dec_ConvertSopToMvc(char *)Dec_GraphIsVar( pGraph )src/bool/dec/dec.hint Dec_GraphVarInt(Dec_Graph_t *)%6s = Dec_GraphLeaveNum(pGraph) >= 0src/bool/dec/decUtil.cDdNode *Dec_GraphDeriveBdd(DdManager *, Dec_Graph_t *)Dec_GraphLeaveNum(pGraph) <= pGraph->nSizeunsigned int Dec_GraphDeriveTruth(Dec_Graph_t *)Dec_GraphLeaveNum(pGraph) <= 5src/bool/kit/kitBdd.cDdNode *Kit_SopToBdd(DdManager *, Kit_Sop_t *, int)Kit_GraphLeaveNum(pGraph) >= 0DdNode *Kit_GraphToBdd(DdManager *, Kit_Graph_t *)Kit_GraphLeaveNum(pGraph) <= pGraph->nSizenVars <= 5src/bool/kit/kitCloud.cCloudNode *Kit_TruthToCloud5_rec(CloudManager *, unsigned int, int, int)nNodes == Cloud_DagSize( dd, pFunc )int Kit_CreateCloud(CloudManager *, CloudNode *, Vec_Int_t *)nNodes < dd->nNodesLimitVec_IntSize(vNodes) == nNodesVec_IntSize(vNodes) <= Vec_PtrSize(vStore)unsigned int *Kit_CloudToTruth(Vec_Int_t *, int, Vec_Ptr_t *, int)(int)Mux.e < i && (int)Mux.t < i && (int)Mux.v < nVarsunsigned int *Kit_TruthCompose(CloudManager *, unsigned int *, int, unsigned int **, int, Vec_Ptr_t *, Vec_Int_t *)pFan0[2*Var + 0] == pFan0[2*Var + 1]void Kit_TruthCofSupports(Vec_Int_t *, Vec_Int_t *, int, Vec_Int_t *, unsigned int *)pFan1[2*Var + 0] == pFan1[2*Var + 1]Kit_TruthCompose(): Internal failure!!!"(nVars <= 100000src/bool/kit/cloud.cCloudManager *Cloud_Init(int, int)nBits < 32dd->one->s == dd->nSignCurvoid Cloud_Restart(CloudManager *)logratio > 0void Cloud_CacheAllocate(CloudManager *, CloudOper, int)logratio < dd->bitsNode(t) >= dd->tUnique && (t) < dd->tUnique+dd->nNodesAllocCloudNode *Cloud_MakeNode(CloudManager *, CloudVar, CloudNode *, CloudNode *)(e) >= dd->tUnique && (e) < dd->tUnique+dd->nNodesAllocv < Cloud_V(t) && v < Cloud_V(e)f <= gCloudNode *cloudBddAnd(CloudManager *, CloudNode *, CloudNode *)(f) >= dd->tUnique && (f) < dd->tUnique+dd->nNodesAllocCloudNode *Cloud_bddAnd(CloudManager *, CloudNode *, CloudNode *)(g) >= dd->tUnique && (g) < dd->tUnique+dd->nNodesAllocCloudNode *Cloud_bddOr(CloudManager *, CloudNode *, CloudNode *)CloudNode *Cloud_bddXor(CloudManager *, CloudNode *, CloudNode *)(n) >= dd->tUnique && (n) < dd->tUnique+dd->nNodesAllocCloudNode *Cloud_Support(CloudManager *, CloudNode *)int Cloud_SupportSize(CloudManager *, CloudNode *)res == Counterint Cloud_DagCollect(CloudManager *, CloudNode *)res != dd->zeroCloudNode *Cloud_GetOneCube(CloudManager *, CloudNode *)Constant 0.Constant 1.!Cloud_IsConstant(bCube)void Cloud_bddPrintCube(CloudManager *, CloudNode *)bCube1 == dd->zero[%d]'bCube1 != dd->zeroThe number of unique table nodes allocated = %12d. The number of unique table nodes present = %12d. The number of unique table hits = %12d. The number of unique table misses = %12d. The number of unique table steps = %12d. The number of cache hits = %12d. The number of cache misses = %12d. The current signature = %12d. The total memory in use = %12d. CloudNode *cloudMakeNode(CloudManager *, CloudVar, CloudNode *, CloudNode *)((int)v) >= 0 && ((int)v) < dd->nVars!Cloud_IsComplement(t)t && eCloud needs restart! 00000000!١ۡޡpNtk->nNodes < pNtk->nNodesAllocsrc/bool/kit/kitDsd.cKit_DsdObj_t *Kit_DsdObjAlloc(Kit_DsdNtk_t *, Kit_Dsd_t, int)Id < pNtk->nVarsvoid Kit_DsdPrint2_rec(FILE *, Kit_DsdNtk_t *, int)pObj->nFans == 0pObj->nFans == 1void Kit_DsdPrint_rec(FILE *, Kit_DsdNtk_t *, int)char *Kit_DsdWrite_rec(char *, Kit_DsdNtk_t *, int)unsigned int *Kit_DsdTruthComputeNode_rec(Kit_DsdMan_t *, Kit_DsdNtk_t *, int)pNtk->nVars <= p->nVarsunsigned int *Kit_DsdTruthCompute(Kit_DsdMan_t *, Kit_DsdNtk_t *)unsigned int *Kit_DsdTruthComputeNodeOne_rec(Kit_DsdMan_t *, Kit_DsdNtk_t *, int, unsigned int)!uSupp || uSupp != (uSupp & ~(1<nFansunsigned int *Kit_DsdTruthComputeOne(Kit_DsdMan_t *, Kit_DsdNtk_t *, unsigned int)uSupp > 0unsigned int *Kit_DsdTruthComputeNodeTwo_rec(Kit_DsdMan_t *, Kit_DsdNtk_t *, int, unsigned int, int, unsigned int *)pObj->Type != KIT_DSD_CONST1pObj->Type != KIT_DSD_VARnPartial == 1nPartial < pObj->nFansunsigned int *Kit_DsdTruthComputeTwo(Kit_DsdMan_t *, Kit_DsdNtk_t *, unsigned int, int, unsigned int *)int Kit_DsdCountLuts_rec(Kit_DsdNtk_t *, int, int, int *)int Kit_DsdExpandNode_rec(Kit_DsdNtk_t *, Kit_DsdNtk_t *, int)Kit_DsdNtk_t *Kit_DsdExpand(Kit_DsdNtk_t *)uSupps[i]void Kit_DsdCompSort(int *, unsigned int *, unsigned short *, int, unsigned int *)Priority[i] != 16iVarBest != -1k == nVars!Abc_LitIsCompl(iLitFanin)int Kit_DsdShrink_rec(Kit_DsdNtk_t *, Kit_DsdNtk_t *, int, int *)Kit_DsdNtk_t *Kit_DsdShrink(Kit_DsdNtk_t *, int *)uSupport <= 0xFFFFunsigned int Kit_DsdGetSupports_rec(Kit_DsdNtk_t *, int)p->pSupps == NULLunsigned int Kit_DsdGetSupports(Kit_DsdNtk_t *)p->nNodes == 1int Kit_DsdCountAigNodes_rec(Kit_DsdNtk_t *, int)(int)pObj->nFans == 3pNtk0->nVars == 4int Kit_DsdCheckVar4Dec2(Kit_DsdNtk_t *, Kit_DsdNtk_t *)pNtk1->nVars == 4pObj->nFans > 0void Kit_DsdDecompose_rec(Kit_DsdNtk_t *, Kit_DsdObj_t *, unsigned int, unsigned short *, int)uSupp == (uSupp0 = (unsigned)Kit_TruthSupport(pTruth, pObj->nFans))pTruth[0] == 0xAAAAAAAA!Kit_TruthIsEqual(pCofs2[0], pCofs2[1], pObj->nFans)uSupp == (uSupp0 | uSupp1 | (1<nFans, i )fPairs[0][3] && fPairs[1][2]Kit_DsdNtk_t *Kit_DsdDecomposeInt(unsigned int *, int, int)pNtk->pNodes[0] == pObjFunction: Cof%d0: Cof%d1: 5npn/npn4.txt%3d : Non-DSD function %s %s non-DSD = %d implementable = %d nLimit < 5int Kit_DsdCofactoring(unsigned int *, int, int *, int, int) Processing prime function with %d support variables: nStep <= nLimitnCofLevel < 5void Kit_DsdPrintCofactors(unsigned int *, int, int, int) Variables { Max = %2d. Supps = %2d. F = 0F = (!d*(!c*(!b*!a)))F = (!d*(!c*!b))F = (!d*(!c*(b+a)))F = (!d*(!c*!(b*a)))F = (!d*!c)F = (!d*16(a,b,c))F = (!d*17(a,b,c))F = (!d*18(a,b,c))F = (!d*19(a,b,c))F = (!d*CA(!b,!c,a))F = (!d*(c+!(!b*!a)))F = (!d*!(c*!(!b*!a)))F = (!d*(c+b))F = (!d*3D(a,b,c))F = (!d*!(c*b))F = (!d*(c+(b+!a)))F = (!d*6B(a,b,c))F = (!d*!(c*!(b+a)))F = (!d*7E(a,b,c))F = (!d*!(c*(b*a)))F = (!d)F = 0116(a,b,c,d)F = 0117(a,b,c,d)F = 0118(a,b,c,d)F = 0119(a,b,c,d)F = 011A(a,b,c,d)F = 011B(a,b,c,d)F = 29((!b*!a),c,d)F = 2B((!b*!a),c,d)F = 012C(a,b,c,d)F = 012D(a,b,c,d)F = 012F(a,b,c,d)F = 013C(a,b,c,d)F = 013D(a,b,c,d)F = 013E(a,b,c,d)F = 013F(a,b,c,d)F = 0168(a,b,c,d)F = 0169(a,b,c,d)F = 016A(a,b,c,d)F = 016B(a,b,c,d)F = 016E(a,b,c,d)F = 016F(a,b,c,d)F = 017E(a,b,c,d)F = 017F(a,b,c,d)F = 0180(a,b,c,d)F = 0181(a,b,c,d)F = 0182(a,b,c,d)F = 0183(a,b,c,d)F = 0186(a,b,c,d)F = 0187(a,b,c,d)F = 0189(a,b,c,d)F = 018B(a,b,c,d)F = 018F(a,b,c,d)F = 0196(a,b,c,d)F = 0197(a,b,c,d)F = 0198(a,b,c,d)F = 0199(a,b,c,d)F = 019A(a,b,c,d)F = 019B(a,b,c,d)F = 019E(a,b,c,d)F = 019F(a,b,c,d)F = 42(a,(!c*!b),d)F = 46(a,(!c*!b),d)F = 4A(a,(!c*!b),d)F = CA((!c*!b),!d,a)F = 01AC(a,b,c,d)F = 01AD(a,b,c,d)F = 01AE(a,b,c,d)F = 01AF(a,b,c,d)F = 01BC(a,b,c,d)F = 01BD(a,b,c,d)F = 01BE(a,b,c,d)F = 01BF(a,b,c,d)F = 01E8(a,b,c,d)F = 01E9(a,b,c,d)F = 01EA(a,b,c,d)F = 01EB(a,b,c,d)F = 25((!b*!a),c,d)F = !CA(d,c,(!b*!a))F = (d+!(!c*(!b*!a)))F = 16(b,c,d)F = 033D(a,b,c,d)F = 17(b,c,d)F = ((!d*!a)+(!c*!b))F = !(!(!c*!b)*!(!d*!a))F = 0358(a,b,c,d)F = 0359(a,b,c,d)F = 035A(a,b,c,d)F = 035B(a,b,c,d)F = 035E(a,b,c,d)F = 035F(a,b,c,d)F = 0368(a,b,c,d)F = 0369(a,b,c,d)F = 036A(a,b,c,d)F = 036B(a,b,c,d)F = 036C(a,b,c,d)F = 036D(a,b,c,d)F = 036E(a,b,c,d)F = 036F(a,b,c,d)F = 037C(a,b,c,d)F = 037D(a,b,c,d)F = 037E(a,b,c,d)F = 18(b,c,d)F = 03C1(a,b,c,d)F = 19(b,c,d)F = 03C5(a,b,c,d)F = 03C6(a,b,c,d)F = 03C7(a,b,c,d)F = CA(!c,!d,b)F = 03D4(a,b,c,d)F = 03D5(a,b,c,d)F = 03D6(a,b,c,d)F = 03D7(a,b,c,d)F = 03D8(a,b,c,d)F = 03D9(a,b,c,d)F = 03DB(a,b,c,d)F = 03DC(a,b,c,d)F = 03DD(a,b,c,d)F = 03DE(a,b,c,d)F = (d+!(!c*!b))F = ((d+c)*(b+a))F = 0661(a,b,c,d)F = 0662(a,b,c,d)F = 0663(a,b,c,d)F = (!(d*c)*(b+a))F = 0667(a,b,c,d)F = 29((b+a),c,d)F = 066B(a,b,c,d)F = 2B((b+a),c,d)F = 0672(a,b,c,d)F = 0673(a,b,c,d)F = 0676(a,b,c,d)F = 0678(a,b,c,d)F = 0679(a,b,c,d)F = 067A(a,b,c,d)F = 067B(a,b,c,d)F = 067E(a,b,c,d)F = 24((b+a),c,d)F = 0691(a,b,c,d)F = 0693(a,b,c,d)F = 26((b+a),c,d)F = 0697(a,b,c,d)F = !CA(d,c,(b+a))F = 06B0(a,b,c,d)F = 06B1(a,b,c,d)F = 06B2(a,b,c,d)F = 06B3(a,b,c,d)F = 06B4(a,b,c,d)F = 06B5(a,b,c,d)F = 06B6(a,b,c,d)F = 06B7(a,b,c,d)F = 06B9(a,b,c,d)F = 06BD(a,b,c,d)F = 2C((b+a),c,d)F = 06F1(a,b,c,d)F = 06F2(a,b,c,d)F = CA((b+a),!d,c)F = (d+!(!c*!(b+!a)))F = 0776(a,b,c,d)F = 16((b*a),c,d)F = 0779(a,b,c,d)F = 077A(a,b,c,d)F = 077E(a,b,c,d)F = 07B0(a,b,c,d)F = 07B1(a,b,c,d)F = 07B4(a,b,c,d)F = 07B5(a,b,c,d)F = 07B6(a,b,c,d)F = 07BC(a,b,c,d)F = 07E0(a,b,c,d)F = 07E1(a,b,c,d)F = 07E2(a,b,c,d)F = 07E3(a,b,c,d)F = 07E6(a,b,c,d)F = 07E9(a,b,c,d)F = 1C((b*a),c,d)F = 07F1(a,b,c,d)F = 07F2(a,b,c,d)F = (d+!(!c*!(b*a)))F = (d+c)F = 1668(a,b,c,d)F = 1669(a,b,c,d)F = 166A(a,b,c,d)F = 166B(a,b,c,d)F = 166E(a,b,c,d)F = 167E(a,b,c,d)F = 1681(a,b,c,d)F = 1683(a,b,c,d)F = 1686(a,b,c,d)F = 1687(a,b,c,d)F = 1689(a,b,c,d)F = 168B(a,b,c,d)F = 168E(a,b,c,d)F = 1696(a,b,c,d)F = 1697(a,b,c,d)F = 1698(a,b,c,d)F = 1699(a,b,c,d)F = 169A(a,b,c,d)F = 169B(a,b,c,d)F = 169E(a,b,c,d)F = 16A9(a,b,c,d)F = 16AC(a,b,c,d)F = 16AD(a,b,c,d)F = 16BC(a,b,c,d)F = (d+E9(a,b,c))F = 177E(a,b,c,d)F = 178E(a,b,c,d)F = 1796(a,b,c,d)F = 1798(a,b,c,d)F = 179A(a,b,c,d)F = 17AC(a,b,c,d)F = (d+E8(a,b,c))F = (d+E7(a,b,c))F = 19E1(a,b,c,d)F = 19E3(a,b,c,d)F = (d+E6(a,b,c))F = 1BD8(a,b,c,d)F = (d+CA(b,c,a))F = (d+(c+(!b*!a)))F = (d+(c+!b))F = (d+(c+(b+a)))src/bool/kit/kitFactor.cKit_Graph_t *Kit_SopFactor(Vec_Int_t *, int, int, Vec_Int_t *)uCubeKit_Edge_t Kit_SopFactorTrivialCube_rec(Kit_Graph_t *, unsigned int, int, int)iLit != -1void Kit_FactorTest(unsigned int *, int)Vars = %2d. Cubes = %3d. FFNodes = %3d. FF_memory = %3d. Kit_SopCubeNum(cSop) > 0Kit_Edge_t Kit_SopFactor_rec(Kit_Graph_t *, Kit_Sop_t *, int, Vec_Int_t *)Kit_SopCubeNum(cQuo) > 0Kit_SopCubeNum(cSimple) == 1Kit_Edge_t Kit_SopFactorLF_rec(Kit_Graph_t *, Kit_Sop_t *, Kit_Sop_t *, int, Vec_Int_t *)??0 <= iLeaf && iLeaf < nLeavessrc/bool/kit/kitGraph.cKit_Graph_t *Kit_GraphCreateLeaf(int, int, int)unsigned int Kit_GraphToTruth(Kit_Graph_t *)Kit_GraphLeaveNum(pGraph) <= 5Kit_Graph_t *Kit_TruthToGraph(unsigned int *, int, Vec_Int_t *)Kit_Graph_t *Kit_TruthToGraph2(unsigned int *, unsigned int *, int, Vec_Int_t *)Finished proceessing %d functions with %d variables. Function %3d : AND2 = %3d Lev = %3d Kit_TruthToGia(): Converting truth table to AIG has failed for function:Kit_TruthToGia2(): Converting truth table to AIG has failed for function:Kit_TruthToHop(): Converting truth table to AIG has failed for function:src/bool/kit/kitIsop.cint Kit_TruthIsop2(unsigned int *, unsigned int *, int, Vec_Int_t *, int, int)Kit_TruthIsImply( puTruth1, pResult, nVars )Kit_TruthIsImply( pResult, puTruth0, nVars )Kit_TruthIsImply( puTruth0, pResult, nVars )Kit_TruthIsImply( pResult, puTruth1, nVars )int Kit_TruthIsop(unsigned int *, int, Vec_Int_t *, int)Kit_TruthIsEqual( puTruth, pResult, nVars )void Kit_TruthIsopPrintCover(Vec_Int_t *, int, int)unsigned int *Kit_TruthIsop_rec(unsigned int *, unsigned int *, int, Kit_Sop_t *, Vec_Int_t *)k == pcRes->nCubesunsigned int Kit_TruthIsop5_rec(unsigned int, unsigned int, int, Kit_Sop_t *, Vec_Int_t *)src/bool/kit/kitPla.cint Kit_PlaIsComplement(char *)void Kit_PlaComplement(char *)char *Kit_PlaCreateFromIsop(void *, int, Vec_Int_t *)void Kit_PlaToIsop(char *, Vec_Int_t *)char *Kit_PlaFromTruth(void *, unsigned int *, int, Vec_Int_t *)char *Kit_PlaFromIsop(Vec_Str_t *, int, Vec_Int_t *)char *Kit_PlaFromTruthNew(unsigned int *, int, Vec_Int_t *, Vec_Str_t *)pTruth[0] == (unsigned)Kit_PlaToTruth6(pResult, nVars)*((ABC_UINT64_T*)pTruth) == Kit_PlaToTruth6(pResult, nVars)ABC_UINT64_T Kit_PlaToTruth6(char *, int)pSop != NULLvoid Kit_PlaToTruth(char *, int, Vec_Ptr_t *, unsigned int *, unsigned int *)Kit_PlaToTruth(): SOP is represented incorrectly.Kit_SopCubeNum(cDiv) == 1src/bool/kit/kitSop.cvoid Kit_SopDivideByCube(Kit_Sop_t *, Kit_Sop_t *, Kit_Sop_t *, Kit_Sop_t *, Vec_Int_t *)Kit_SopCubeNum(cSop) >= Kit_SopCubeNum(cDiv)void Kit_SopDivideInternal(Kit_Sop_t *, Kit_Sop_t *, Kit_Sop_t *, Kit_Sop_t *, Vec_Int_t *)i2 < Kit_SopCubeNum(cSop)nCubesRem == Kit_SopCubeNum(vRem)void Kit_SopCommonCubeCover(Kit_Sop_t *, Kit_Sop_t *, Vec_Int_t *)Kit_SopCubeNum(cResult) > 0int Kit_SopDivisor(Kit_Sop_t *, Kit_Sop_t *, int, Vec_Int_t *)UUUUUUUU33333333UUUUUUUU33333333x{yzyŎ?ts瑢ʑ)gHg-J̯^ h&޽\ȢɢɢaɢȢʢWˢˢ:ˢˢYҢ\բӢԢӢߢwߢ=ߢZߢ ߢ lh<0nO M + y01000""""DDDD 0000 %)+/5;=CGIOSYaegkmq %379=KQ[]agou{  #-39;AKQWY_eikw)+57;=GUY[_mqsw %'-?CEIOU]ci  ')/QW]ew #+/=AGIMSU[ey '7EKOQUWamsy!#')3?AQSY]_iq   # % + / 5 C I M O U Y _ k q w   ! 1 9 = I W a c g o u {      # ) - ? G Q W ] e o {   % / 1 A [ _ a m s w      ! + - = ? O U i y !'/5;KWY]kqu}  %)1CGMOSY[gk!%+9=?Qisy{ '-9EGY_cio #)+17AGS_qsy} '-7CEIOW]gim{!/3;EMYkoqu %)+7=ACI_egk} %39=EOUimou #'3A]cw{57;CIMUgqw}13EIQ[y!#-/5?MQik{}#%/17;AGOUYeks '+-3=EKOUs !#59?AKS]ciqu{} %+/=IMOmq 9IKQgu{src/bool/kit/kitTruth.cvoid Kit_TruthSwapAdjacentVars(unsigned int *, unsigned int *, int, int)void Kit_TruthSwapAdjacentVars2(unsigned int *, unsigned int *, int, int)void Kit_TruthStretch(unsigned int *, unsigned int *, int, int, unsigned int, int)void Kit_TruthShrink(unsigned int *, unsigned int *, int, int, unsigned int, int)pPerm[i] != pPerm[i+1]void Kit_TruthPermute(unsigned int *, unsigned int *, int, char *, int)int Kit_TruthVarInSupport(unsigned int *, int, int)void Kit_TruthCofactor0(unsigned int *, int, int)int Kit_TruthCofactor0Count(unsigned int *, int, int)void Kit_TruthCofactor1(unsigned int *, int, int)void Kit_TruthCofactor0New(unsigned int *, unsigned int *, int, int)void Kit_TruthCofactor1New(unsigned int *, unsigned int *, int, int)int Kit_TruthVarIsVacuous(unsigned int *, unsigned int *, int, int)void Kit_TruthExist(unsigned int *, int, int)void Kit_TruthExistNew(unsigned int *, unsigned int *, int, int)void Kit_TruthForall(unsigned int *, int, int)void Kit_TruthForallNew(unsigned int *, unsigned int *, int, int)void Kit_TruthUniqueNew(unsigned int *, unsigned int *, int, int)int Kit_TruthBooleanDiffCount(unsigned int *, int, int)void Kit_TruthMuxVar(unsigned int *, unsigned int *, unsigned int *, int, int)void Kit_TruthMuxVarPhase(unsigned int *, unsigned int *, unsigned int *, int, int, int)int Kit_TruthVarsSymm(unsigned int *, int, int, int, unsigned int *, unsigned int *)int Kit_TruthVarsAntiSymm(unsigned int *, int, int, int, unsigned int *, unsigned int *)void Kit_TruthChangePhase(unsigned int *, int, int)int Kit_TruthMinCofSuppOverlap(unsigned int *, int, int *)iBestVar != -1int Kit_TruthBestCofVar(unsigned int *, int, unsigned int *, unsigned int *)unsigned int Kit_TruthHash(unsigned int *, int)nVars <= 20int Kit_TruthCountMinterms(unsigned int *, int, int *, int *)pBytesInit[0] == nTotaliVar == nVarspRes[i] == Kit_TruthCofactor0Count(pTruth, nVars, i)tt\s%04drt ; bdd; sop; ps void Kit_TruthPrintProfile_int(unsigned int *, int)nTotalMints == nTotalMints0 + nTotalMints1v != iVarCof00 >= 0 && Cof00 <= nMints1Cof01 >= 0 && Cof01 <= nMints1Cof10 >= 0 && Cof10 <= nMints1Cof11 >= 0 && Cof11 <= nMints1Coz00 >= 0 && Coz00 <= nMints1Coz01 >= 0 && Coz01 <= nMints1Coz10 >= 0 && Coz10 <= nMints1Coz11 >= 0 && Coz11 <= nMints1 V: %8c M: U: void Kit_TruthPrintProfile(unsigned int *, int)Unique:Common:Total:maxNCycles = %d minNCycles = %d average NCycles = %.3f src/bool/lucky/lucky.cvoid luckyCanonicizer(word *, word *, word *, int, char *, char *, unsigned int *)unsigned int luckyCanonicizer1_simple(word *, word *, word *, int, char *, unsigned int)unsigned int Kit_TruthSemiCanonicize_new_internal(word *, int, char *)iQ*blockSize < 64src/bool/lucky/luckyFast16.cvoid arrangeQuoters_superFast_lessThen5(word *, int, int, int, int, int, int, int, char *, unsigned int *)jQ*blockSize < 64kQ*blockSize < 64lQ*blockSize < 643*blockSize < 64int minTemp0_fast(word *, int, int, int *)2*blockSize < 64int minTemp1_fast(word *, int, int, int *)int minTemp2_fast(word *, int, int, int, int, int *)int minTemp3_fast(word *, int, int, int, int, int, int *)nVars > 6 && nVars <= 16void luckyCanonicizer_final_fast_16Vars(word *, int, int, int *, char *, unsigned int *)void luckyCanonicizer_final_fast_16Vars1(word *, int, int, int *, char *, unsigned int *)unsigned int luckyCanonicizer_final_fast(word *, int, char *)unsigned int luckyCanonicizer_final_fast1(word *, int, char *)DDDDDDDD""""""""00000000 aaaaaaaaaaaaaaaaqqqqqqqqqqqqqqqqΣϣ(ϣkϣ""""""""DDDDDDDD 00000000src/bool/lucky/luckyFast6.ciVar >= 0 && iVar < 5word Extra_Truth6MinimumRoundOne(word, int, char *, unsigned int *)word Extra_Truth6MinimumRoundOne_noEBFC(word, int, char *, unsigned int *)eѣPѣPѣPѣPѣPѣPѣPѣPѣPѣoѣPѣPѣoѣPѣPѣPѣPѣPѣPѣPѣPѣPѣPѣPѣPѣPѣPѣPѣPѣPѣPѣoѣѣѣӣңӣӣӣңӣӣӣӣӣӣӣңӣӣӣӣӣӣӣӣӣӣӣӣӣӣӣңӣӣӣӣӣӣӣӣӣӣӣӣӣӣӣӣӣӣӣӣӣӣӣӣӣӣӣӣӣӣӣңsrc/bool/lucky/luckyRead.c""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333src/bool/lucky/luckySwap.cvoid Kit_TruthChangePhase_64bit(word *, int, int)void Kit_TruthSwapAdjacentVars_64bit(word *, int, int)unsigned int Kit_TruthSemiCanonicize_Yasha(word *, int, char *)unsigned int Kit_TruthSemiCanonicize_Yasha1(word *, int, char *, int *)void Kit_TruthSemiCanonicize_Yasha_simple(word *, int, int *)UUUUUUUU33333333""""""""DDDDDDDD 00000000@vBBCB F,FsCPIXI`InI|IIITTT[U 0 && nGs < 5src/bool/rsb/rsbDec6.cunsigned int Rsb_DecCheck(int, word *, word **, int, unsigned int *, int *, int *)(~f[w] & CofA) && (f[w] & CofA)(f[k] & CofA) && (~f[w] & CofB)nCands <= 4void Rsb_DecPrintTable(word *, int, int, Vec_Int_t *) %3d !Rsb_DecTryCex( f, iCexT0, iCexF0 )int Rsb_DecInitCexes(int, word *, word **, int, int, word *, Vec_Int_t *)!Rsb_DecTryCex( f, iCexT0, iCexF1 )!Rsb_DecTryCex( f, iCexT1, iCexF0 )!Rsb_DecTryCex( f, iCexT1, iCexF1 )Offset : Onset : Result : Func : Div%3d : Solution : Num < nGsint Rsb_DecVerify(Rsb_Man_t *, int, word *, word **, int, unsigned int, word *, word *)Verified orig decomp with %d vars {nGs < nGsAllunsigned int Rsb_ManPerform(Rsb_Man_t *, int, word *, word **, int, int, int)nGs < 200int Rsb_ManPerformResub6(Rsb_Man_t *, int, word, Vec_Wrd_t *, word *, word *, int)nCexes < 64void Rsb_DecRecordCex(word **, int, int, int, word *, int)Verification of CEX has failed: g[%d](A) != g[%d](B)!!! word Abc_Tt6Isop(word, word, int, int *)(uOn & ~uRes2) == 0(uRes2 & ~uOnDc) == 0void Abc_TtPrintBinary(word *, int)Verification of CEX has failed: f(A) == f(B)!!!nLeafMax <= 20src/bool/rsb/rsbMan.cRsb_Man_t *Rsb_ManAlloc(int, int, int, int)nDivMax <= 200Edge (%d,%d)/%d Target: Allocated %d literal clusters Entering recursion %d Checking solution: FOUND! FAILED! Creating Edges: Grouped: AND OR %d edges created. There is no edges unvisited... Exiting recursion. New Literal Cluster found: %08Xpol == '+' || pol == '-'src/bool/rpo/literal.hLiteral_t *Lit_Alloc(unsigned int *, int, int, char)Lit_GroupLiterals with op not defined.src/proof/pdr/pdrCnf.cint Pdr_ObjSatVar2(Pdr_Man_t *, int, Aig_Obj_t *, int, int)sat_solver *Pdr_ManNewSolver(sat_solver *, Pdr_Man_t *, int, int)p->pCnf2->pObj2Count[Aig_ObjId(pObj)] >= 0int Pdr_ObjSatVar2FindOrAdd(Pdr_Man_t *, int, Aig_Obj_t *, int *)iVarNew > 0iSatVar >= 0int Pdr_ObjRegNum1(Pdr_Man_t *, int, int)RegId >= 0 && RegId < Aig_ManRegNum(p->pAig)iSatVar > 0 && iSatVar < Vec_IntSize(vVar2Ids)int Pdr_ObjRegNum2(Pdr_Man_t *, int, int)sat_solver *Pdr_ManNewSolver1(sat_solver *, Pdr_Man_t *, int, int)p->vVar2Reg == NULLsat_solver *Pdr_ManNewSolver2(sat_solver *, Pdr_Man_t *, int, int)Vec_IntEntry( p->pvId2Vars + Entry, k ) > 0Vec_IntSize(vLits) < pCube->nLitssrc/proof/pdr/pdrCore.cPdr_Set_t *Pdr_ManReduceClause(Pdr_Man_t *, int, Pdr_Set_t *)i < pCube->nLits!Pdr_SetIsInit(pCubeMin, -1)p->iUseFrame > 0int Pdr_ManPushClauses(Pdr_Man_t *)(*ppCube)->Lits[i] != -1int ZPdr_ManSimpleMic(Pdr_Man_t *, int, Pdr_Set_t **)(*ppCube)->nLits > 0micResult != -1int ZPdr_ManDown(Pdr_Man_t *, int, Pdr_Set_t **, Pdr_Set_t *, Hash_Int_t *, Pdr_Set_t *, int *)Adding cube to frame %d. pCubeMin->Lits[i] >= 0(pCubeMin->Lits[i] / 2) < Aig_ManRegNum(p->pAig)pCubeMin->nLits > 0int Pdr_ManGeneralize(Pdr_Man_t *, int, Pdr_Set_t *, Pdr_Set_t **, Pdr_Set_t **)ppCubeMin != NULLRetValue1 == 1pCubeMin->Lits[i] != -1int Pdr_ManBlockCube(Pdr_Man_t *, Pdr_Set_t *)!Pdr_SetIsInit(pThis->pState, -1)pPred == NULLpCubeMin == NULLpPred != NULLVec_PtrSize(p->vSolvers) == 0int Pdr_ManSolveInt(Pdr_Man_t *)iFrame == Vec_PtrSize(p->vSolvers)-1Output %*d was trivially asserted in frame %2d (solved %*d out of %*d outputs). Vec_PtrEntry(p->vCexes, p->iOutCur) == NULLQuitting due to callback on fail in frame %d. p->pTime4Outs[p->iOutCur] > 0Reached gap timeout (%d seconds) in frame %d. Reached timeout (%d seconds) in frame %d. Reached conflict limit (%d) in frame %d. Computation cancelled by the callback in frame %d. p->pPars->fUseAbsOutput %*d was asserted in frame %2d (%2d) (solved %*d out of %*d outputs). Timing out on output %*d in frame %d. pCube == NULLVarMax = %d. FrameMax = %d. QueMax = %d. TimeMax = %d. MonoCNF = %s. SkipGen = %s. SolveAll = %s. pAig->pSeqModel != NULL || p->vCexes != NULLint Pdr_ManSolve(Aig_Man_t *, Pdr_Par_t *)_inv.plaDumped inductive invariant in file "%s". timeoutIntersection: Pred:Cube:Failed initiationVec_VecSize(p->vClauses) == k + 1src/proof/pdr/pdrIncr.cVec_Ptr_t *IPdr_ManPushClausesK(Pdr_Man_t *, int)RetValue != -1Frame[%4d]Cube[%4d] = Cube[%d][%d] not inductive! Vec_PtrSize(p->vSolvers) == ksat_solver *IPdr_ManSetSolver(Pdr_Man_t *, int, int)Vec_IntSize(p->vActVars) == kVec_VecSize(vClauses) >= 2int IPdr_ManRebuildClauses(Pdr_Man_t *, Vec_Vec_t *)Vec_VecSize(p->vClauses) == 0Cube[%d][%d] cannot be pushed from R0 to R1. RebuildClauses: %d out of %d cubes reused in R1. vClausesint IPdr_ManRestoreClauses(Pdr_Man_t *, Vec_Vec_t *, Vec_Int_t *)IPDR: Checking the reloaded length-%d trace... Passed! IPDR: Pushing the reloaded clauses. Before: IPDR: Finished pushing. After: int IPdr_ManSolveInt(Pdr_Man_t *, int, int)Reached conflict limit (%d) in frame. int IPdr_ManSolve(Aig_Man_t *, Pdr_Par_t *)int IPdr_ManCheckCubeReduce(Pdr_Man_t *, Vec_Ptr_t *, Pdr_Set_t *, int)UNSAT at the last frame. nCores = %d (out of %d).SAT at the last frame.int Abc_NtkDarIPdr(Abc_Ntk_t *, Pdr_Par_t *)Frame Clauses Max Queue Flops Cex %3d :%10.2f sec CEX =%4d T/O =%3dpCube->Lits[n] >= 0 && pCube->Lits[n] < 2*Aig_ManRegNum(p->pAig)src/proof/pdr/pdrInv.cVec_Int_t *Pdr_ManCountFlops(Pdr_Man_t *, Vec_Ptr_t *)C=%4d. F=%4d Clause: {Abc_Lit2Var(pCube->Lits[n]) < Saig_ManRegNum(p)Aig_Man_t *Pdr_ManDupAigWithClauses(Aig_Man_t *, Vec_Ptr_t *)Aig_ManDupSimple(): The check has failed. aig_with_clauses.aigDumped modified AIG into file "aig_with_clauses.aig". Cannot open file "%s" for writing invariant. # Inductive invariant for "%s" # Clauses of the last timeframe for "%s" # generated by PDR in ABC on %s .o 1 .ob inv Inductive invariant was written into file "%s". Clauses of the last timeframe were written into file "%s". Invariant F[%d] : %d clauses with %d flops (out of %d) (cex = %d, ave = %.2f) void Pdr_ManVerifyInvariant(Pdr_Man_t *)Verification of clause %d failed. Verification of %d clauses has failed. Verification of invariant with %d clauses was successful. int Pdr_ManDeriveMarkNonInductive(Pdr_Man_t *, Vec_Ptr_t *)Invariant contains %d clauses with %d literals and %d flops (out of %d). int Pdr_InvCheck_int(Gia_Man_t *, Vec_Int_t *, int, sat_solver *, int)Coverage check failed for output %d. Finished checking clause %d (out of %d)... Inductiveness check failed for clause %d. sat_solver_nvars(pSat) == pCnf->nVarsint Pdr_InvCheck(Gia_Man_t *, Vec_Int_t *, int)Vec_Int_t *Pdr_InvMinimize(Gia_Man_t *, Vec_Int_t *, int)Removing clause %d. Invariant minimization reduced %d clauses (out of %d). Invariant minimization did not change the invariant. Removing lit %d from clause %d. Invariant minimization reduced %d literals (out of %d). MaxEntry == Gia_ManRegNum(p)src/proof/pdr/pdrMan.cVec_Int_t *Pdr_ManDeriveFlopPriorities3(Gia_Man_t *, int)Block =%5d Oblig =%6d Clause =%6d Call =%6d (sat=%.1f%%) Cex =%4d Start =%4d unsat sat Generalize Push clauseTernary simContainmentRefinement Abc_Cex_t *Pdr_ManDeriveCex(Pdr_Man_t *)f == nFramesCEX for output %d is not valid. Vec_IntEntry( p->vMapFf2Ppi, Flop ) == iAbc_Cex_t *Pdr_ManDeriveCexAbs(Pdr_Man_t *)Vec_IntEntry(p->vAbsFlops, Flop) == 0iPPI < pCex->nPissrc/proof/pdr/pdrSat.csat_solver *Pdr_ManCreateSolver(Pdr_Man_t *, int)Vec_VecSize(p->vClauses) == kk < Vec_PtrSize(p->vSolvers) - 1sat_solver *Pdr_ManFetchSolver(Pdr_Man_t *, int)Vec_Int_t *Pdr_ManLitsToCube(Pdr_Man_t *, int, int *, int)Vec_IntSize(p->vLits) >= 0 && Vec_IntSize(p->vLits) <= nArrayVec_Int_t *Pdr_ManCubeToLits(Pdr_Man_t *, int, Pdr_Set_t *, int, int)void Pdr_ManSetPropertyOutput(Pdr_Man_t *, int)void Pdr_ManSolverAddClause(Pdr_Man_t *, int, Pdr_Set_t *)void Pdr_ManCollectValues(Pdr_Man_t *, int, Vec_Int_t *, Vec_Int_t *)int Pdr_ManCheckCube(Pdr_Man_t *, int, Pdr_Set_t *, Pdr_Set_t **, int, int, int)src/proof/pdr/pdrTsim.cvoid Pdr_ManCollectCone_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Int_t *, Vec_Int_t *)int Pdr_ManExtendOneEval(Aig_Man_t *, Aig_Obj_t *)Saig_ObjIsLo(pAig, pObj)int Pdr_ManExtendOne(Aig_Man_t *, Aig_Obj_t *, Vec_Int_t *, Vec_Int_t *)Aig_ObjIsTravIdCurrent(pAig, pObj)Value == PDR_ZER || Value == PDR_ONEAig_ObjId(pObj) < Aig_ObjId(pFanout)Value2 == PDR_UNDAig_ObjIsNode(pFanout)Pdr_ManSimInfoGet(pAig, pObj) == PDR_UNDvoid Pdr_ManExtendUndo(Aig_Man_t *, Vec_Int_t *)Saig_ObjIsLo( pAig, pObj )void Pdr_ManDeriveResult(Aig_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Trying to justify cube Pdr_Set_t *Pdr_ManTernarySim(Pdr_Man_t *, int, Pdr_Set_t *)Saig_ObjIsLo( p->pAig, pObj )Vec_IntSize(vRes) > 0Value >= PDR_ZER && Value <= PDR_UNDvoid Pdr_ManSimInfoSet(Aig_Man_t *, Aig_Obj_t *, int)Vec_IntSize(vPrio) == Aig_ManRegNum(pAig)src/proof/pdr/pdrTsim2.cTxs_Man_t *Txs_ManStart(Pdr_Man_t *, Aig_Man_t *, Vec_Int_t *)void Txs_ManCollectCone_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, Vec_Int_t *)void Txs_ManForwardPass(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)(int)pObj->fMark0 == Vec_IntEntry(vCoVals, i)!value0 || !value1void Txs_ManBackwardPass(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Vec_IntSize(vFfLits) > 0void Txs_ManSelectJustPath(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)void Txs_ManPropagatePrio(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *)Gia_ObjTerSimGetX(pObj)void Txs_ManVerify(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Gia_ObjTerSimGet0(pObj)int Txs_ObjIsJust(Gia_Man_t *, Gia_Obj_t *)src/proof/pdr/pdrTsim3.cTxs3_Man_t *Txs3_ManStart(Pdr_Man_t *, Aig_Man_t *, Vec_Int_t *)void Txs3_ManCollectCone_rec(Txs3_Man_t *, Gia_Obj_t *)Pdr_Set_t *Txs3_ManTernarySim(Txs3_Man_t *, int, Pdr_Set_t *)Vec_IntSize(p->vTemp) == Vec_IntSize(p->vPiLits) + Vec_IntSize(p->vFfLits) + 1k == 0 || !Pdr_SetIsInit(pRes, -1)nSize >= 0 && nSize < (1<<30)src/proof/pdr/pdrUtil.cPdr_Set_t *Pdr_SetAlloc(int)Vec_IntSize(vLits) + Vec_IntSize(vPiLits) < (1<<30)Pdr_Set_t *Pdr_SetCreate(Vec_Int_t *, Vec_Int_t *)iRemove >= 0 && iRemove < pSet->nLitsPdr_Set_t *Pdr_SetCreateFrom(Pdr_Set_t *, int)k == p->nTotalnLits >= 0 && nLits <= pSet->nLitsPdr_Set_t *Pdr_SetCreateSubset(Pdr_Set_t *, int *, int)pLits[i] >= 0pOld->nLits > 0int Pdr_SetContains(Pdr_Set_t *, Pdr_Set_t *)pNew->nLits > 0*pNewInt != -1*pOldInt != -1int Pdr_SetContainsSimple(Pdr_Set_t *, Pdr_Set_t *)pCube->Lits[i] != -1int Pdr_SetIsInit(Pdr_Set_t *, int)Frame = %2d. Prio = %8d. int Pdr_NtkFindSatAssign_rec(Aig_Man_t *, Aig_Obj_t *, int, Pdr_Set_t *, int)src/proof/abs/absDup.cvoid Gia_ManDupAbsFlops_rec(Gia_Man_t *, Gia_Obj_t *)Vec_Int_t *Gia_GlaCollectAssigned(Gia_Man_t *, Vec_Int_t *)Gia_ManPoNum(p) == 1void Gia_ManGlaCollect(Gia_Man_t *, Vec_Int_t *, Vec_Int_t **, Vec_Int_t **, Vec_Int_t **, Vec_Int_t **)Vec_IntSize(vGateClasses) == Gia_ManObjNum(p)void Gia_ManDupAbsGates_rec(Gia_Man_t *, Gia_Obj_t *)Gia_Man_t *Gia_ManDupAbsGates(Gia_Man_t *, Vec_Int_t *)!Abc_LitIsCompl(pObj->Value)!Abc_LitIsCompl(pCopy->Value)Flop-level abstraction: Excluded FFs = %d Included FFs = %d (%.2f %%) and there are other FF classes...Gate-level abstraction: PI = %d PPI = %d FF = %d (%.2f %%) AND = %d (%.2f %%) Obj = %d (%.2f %%) Vec_IntEntry(vAbs, nFrames+1) == Vec_IntSize(vAbs)void Gia_ManPrintObjClasses(Gia_Man_t *)Gia_ManObjNum(p) <= nObjMaskpCountAll[0] == (iStop - iStart)iStop == Vec_IntSize(vAbs)Gia_ManPrintFlopClasses(): The number of flop map entries differs from the number of flops.Gia_ManPrintGateClasses(): The number of flop map entries differs from the number of flops.Frame Core F0 F1 F2 F3 ...(@D,A= ףp#= ףp#@X<<@src/proof/abs/absGla.cunsigned int Ga2_ObjComputeTruth_rec(Gia_Man_t *, Gia_Obj_t *, int)Val0 + Val1 > Nint Ga2_ManBreakTree_rec(Gia_Man_t *, Gia_Obj_t *, int, int)Val0 < N && Val1 < Nvoid Ga2_ManCollectNodes_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, int)void Ga2_ManCollectLeaves_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, int)int Ga2_ManMarkup(Gia_Man_t *, int, int)Gia_ObjFanin0(pObjRi)->fPhaseVec_IntSize(vLeaves) <= NGia_ManObj(p, Leaf)->fPhaseMarked AND nodes = %6d. stats_gla%s%s.txt%s pi=%d ff=%d and=%d mem=%d bmc=%d ff=%d and=%dMemory: AIG %10.3f MB (%6.2f %%) Memory: SAT Memory: Proof Memory: Map Memory: Refine Memory: Hash Memory: Other Memory: TOTAL SAT solver: Var = %d Cla = %d Conf = %d Lrn = %d Reduce = %d Cex = %d ObjsAdded = %d Hash hits = %d. Hash misses = %d. Hash overs = %d. Concurrent calls = %d. unsigned int Ga2_ObjComputeTruthSpecial(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, Vec_Int_t *)Entry >= 0nUsed > 0Vec_IntEntry(vLits, pUsed[0]) <= Vec_IntEntry(vLits, pUsed[nUsed-1])Entry > 1!Ga2_ObjTruthDepends(Res, i)Vec_Int_t *Ga2_ManCnfCompute(unsigned int, int, Vec_Int_t *)void Ga2_ManCnfAddStatic(sat_solver2 *, Vec_Int_t *, Vec_Int_t *, int *, int, int)nAbs > 0void Ga2_ManShrinkAbs(Ga2_Man_t *, int, int, int)nValues > 0nSatVars > 0Ga2_ObjCnf0(p, pObj) != NULLGa2_ObjCnf1(p, pObj) != NULLGa2_ObjId(p,pObj) >= 0void Ga2_ManAbsTranslate_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, int)Vec_Int_t *Ga2_ManAbsTranslate(Ga2_Man_t *)p->pGia != NULL && p->pGia->vGateClasses != NULLvoid Ga2_ManRestart(Ga2_Man_t *)Gia_ManPi(p->pGia, 0)->fPhasep->pSat->pPrf2 == NULLp->pPars->iFrame < 0%12d : Obj =%6d ff Fanins: void Ga2_ManRefinePrintPPis(Ga2_Man_t *)Ga2_ObjIsLeaf(p, pObj)Gia_ObjIsAnd(pObj) || Gia_ObjIsCi(pObj) Current PPIs (%d): void Ga2_GlaPrepareCexAndMap(Ga2_Man_t *, Abc_Cex_t **, Vec_Int_t **)Vec_Int_t *Ga2_ManRefine(Ga2_Man_t *)int Ga2_GlaAbsCount(Ga2_Man_t *, int, int)%4d :%5c%5.0f MBglabs.aig_gla.aigp->pPars->fDumpMabs || p->pPars->fDumpVabsvoid Ga2_GlaDumpAbsracted(Ga2_Man_t *, int)Dumping miter with abstraction map into file "%s"... Dumping abstracted model into file "%s"... Abc_FrameIsBridgeMode()void Gia_Ga2SendAbsracted(Ga2_Man_t *, int)void Gia_Ga2SendCancel(Ga2_Man_t *, int)Gia_ManPoNum(pAig) == 1int Gia_ManPerformGla(Gia_Man_t *, Abs_Par_t *)Sequential miter is trivially UNSAT. Sequential miter is trivially SAT. Running gate-level abstraction (GLA) with the following parameters: FrameMax = %d ConfMax = %d Timeout = %d Limit = %d %% Limit2 = %d %% RatioMax = %d %% LrnStart = %d LrnDelta = %d LrnRatio = %d %% Skip = %d SimpleCNF = %d Dump = %d %s will be continously dumped into file "%s". Abstracted modelMiter with abstraction mapwrite_status %s.status Frame %% Abs PPI FF LUT Confl Cex Vars Clas Lrns Time Mem nVarsOld == p->pSat->sizep->pSat->pPrf2 != NULLStatus == l_FalseForcing restart because abstraction grew from %d to %d (more than %d %%). GLA completed %d frames and proved abstraction derived in frame %d GLA reached timeout %d sec in frame %d with a %d-stable abstraction. GLA exceeded %d conflicts in frame %d with a %d-stable abstraction. GLA found that the size of abstraction exceeds %d %% in frame %d during refinement. GLA found that the size of abstraction exceeds %d %% in frame %d. GLA finished %d frames and produced a %d-stable abstraction. Gia_ManPerformGlaOld(): CEX verification has failed! True counter-example detected in frame %d. Runtime: InitializingRuntime: Solver UNSATRuntime: Solver SAT Runtime: Refinement Runtime: Other Runtime: TOTAL v >= 0 && v <= 4unsigned int Ga2_ObjTruthDepends(unsigned int, int)iLitOut > 1void Ga2_ManAddToAbsOneStatic(Ga2_Man_t *, Gia_Obj_t *, int, int)Gia_ObjIsConst0(pObj) || Gia_ObjIsRo(p->pGia, pObj) || Gia_ObjIsAnd(pObj)Ga2_ObjFindLit(p, pObj, f) == -1void Ga2_ObjAddLit(Ga2_Man_t *, Gia_Obj_t *, int, int)void Ga2_ManCnfAddDynamic(Ga2_Man_t *, int, int *, int, int)Ga2_ObjIsAbs0(p, pObj)void Ga2_ManAddToAbsOneDynamic(Ga2_Man_t *, Gia_Obj_t *, int)Lit < 10000000Vec_IntSize(p->vLits) > 1 && Vec_IntSize(p->vLits) < 6Vec_IntSize(p->vLits) < 5Vec_IntEntry(p->vLits, 0) <= Vec_IntEntryLast(p->vLits)Vec_IntSize(p->vLits) == 5pTable + 5 < pTable + 6 * p->nTableint *Saig_ManBmcLookup(Ga2_Man_t *, int *)void Ga2_ManSetupNode(Ga2_Man_t *, Gia_Obj_t *, int)Vec_PtrSize(p->vCnfs) == 2 * Vec_IntSize(p->vValues)Ga2_ObjCnf0(p, pObj) == NULLGia_ObjIsAnd(pObj) || Gia_ObjIsRo(p->pGia, pObj)Vec_Int_t *Ga2_ObjCnf0(Ga2_Man_t *, Gia_Obj_t *)Vec_Int_t *Ga2_ObjCnf1(Ga2_Man_t *, Gia_Obj_t *)!Gia_ObjIsConst0(pObj)int Ga2_ObjSatValue(Ga2_Man_t *, Gia_Obj_t *, int)./src/sat/bsat/satSolver2.hint Ga2_ObjIsAbs0(Ga2_Man_t *, Gia_Obj_t *)%4.2fk%4.1fk%4.0fk%4.2fm%4.1fm%4.0fmGa2_ObjId(p,pObj) >= 0 && Ga2_ObjId(p,pObj) < Vec_IntSize(p->vValues)int Ga2_ObjFindLit(Ga2_Man_t *, Gia_Obj_t *, int)s->qhead == s->qtailvoid sat_solver2_bookmark(sat_solver2 *)p->iFirst == -1./src/sat/bsat/satProof2.hvoid Prf_ManRestart(Prf_Man_t *, Vec_Int_t *, int, int)void Prf_ManGrow(Prf_Man_t *, int)UUUU3333 Unsat core: j@pObj->fConst || pObj->fRo || pObj->fAndsrc/proof/abs/absGlaOld.cvoid Gia_GlaPrepareCexAndMap(Gla_Man_t *, Abc_Cex_t **, Vec_Int_t **)Gia_ObjIsAnd(pGiaObj)void Gla_ManCollectInternal_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)void Gla_ManCollect(Gla_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)pRef->fVisit == 0void Gia_ManRefSetAndPropFanout_rec(Gla_Man_t *, Gia_Obj_t *, int, Vec_Int_t *, int)(int)pRef->Prio > 0Gia_ObjIsAnd(pFanout)void Gla_ManRefSelect_rec(Gla_Man_t *, Gia_Obj_t *, int, Vec_Int_t *, int) Refinement verification has failed!!! Vec_Int_t *Gla_ManRefinement2(Gla_Man_t *)Object has value mismatch Counter-example verification has failed!!! Vec_IntSize( vFanins ) <= 4void Gla_ManCollectFanins(Gla_Man_t *, Gla_Obj_t *, int, Vec_Int_t *)void Gia_ManDupMapped_rec(Gia_Man_t *, Gia_Obj_t *, Gia_Man_t *)~pFanin->ValueGia_Man_t *Gia_ManDupMapped(Gia_Man_t *, Vec_Int_t *)!Gia_ObjIsTravIdCurrent(p, pObj)!~pObj->Value~Gia_ObjFanin0(pObj)->ValueVec_IntSize(pNew->vLutConfigs) == Gia_ManObjNum(pNew)pGia0->vGateClasses != 0Gla_Man_t *Gla_ManStart(Gia_Man_t *, Abs_Par_t *)(int)pObj->Value < Gia_ManObjNum(p->pGia)~Gia_ManObj(pGia0, pMapping[k])->ValueGla_Man_t *Gla_ManStart2(Gia_Man_t *, Abs_Par_t *)SAT solver: Var = %d Cla = %d Conf = %d Lrn = %d Reduce = %d Cex = %d Objs+ = %d int Gla_ManTranslate_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, int)nUsageCount >= 0Vec_Int_t *Gla_ManTranslate(Gla_Man_t *)pObj->fAbs == 0void Gla_ManExplorePPis(Gla_Man_t *, Vec_Int_t *)pGlaObj->nFanins == 1void Gla_ManAddClauses(Gla_Man_t *, int, int, Vec_Int_t *)pGla->fAbs == 0void Gia_GlaAddToAbs(Gla_Man_t *, Vec_Int_t *, int)Vec_IntEntry( &Gla_ManObj(p, iObj)->vFrames, iFrame ) > 0void Gla_ManRollBack(Gla_Man_t *)Gla_ManObj( p, iObj )->fAbs == 1iSat > 0int Gla_ManGetOutLit(Gla_Man_t *, int)Vec_Int_t *Gla_ManUnsatCore(Gla_Man_t *, int, sat_solver2 *, int, int, int *, int *)void Gia_GlaSendAbsracted(Gla_Man_t *, int)void Gia_GlaSendCancel(Gla_Man_t *, int)int Gia_ManPerformGlaOld(Gia_Man_t *, Abs_Par_t *, int)pPars->nFramesMax == 0 || pPars->nFramesStart <= pPars->nFramesMaxFrameMax = %d ConfMax = %d Timeout = %d RatioMin = %d %%. LearnStart = %d LearnDelta = %d LearnRatio = %d %%. Timeout %d sec in frame %d with a %d-stable abstraction. Exceeded %d conflicts in frame %d with a %d-stable abstraction. The ratio of abstracted objects is less than %d %% in frame %d. Abstraction stopped for unknown reason in frame %d. GLA completed %d frames with a %d-stable abstraction. Counter-example detected in frame %d. Gla_Obj_t *Gla_ManObj(Gla_Man_t *, int)pObj > p->pObjs && pObj < p->pObjs + p->nObjsint Gla_ObjId(Gla_Man_t *, Gla_Obj_t *)Vec_Int_t *Gla_ManCollectPPis(Gla_Man_t *, Vec_Int_t *)!pGla->fPo && !pGla->fRiint Gla_ManCheckVar(Gla_Man_t *, int, int)int Gla_ManGetVar(Gla_Man_t *, int, int)int sat_solver2_add_const(sat_solver2 *, int, int, int, int)Sequential miter is trivially UNSAT.Sequential miter is trivially SAT.RetValue == 0 || RetValue == -1src/proof/abs/absIter.cint Gia_IterTryImprove(Gia_Man_t *, int, int)Gia_Man_t *Gia_ManShrinkGla(Gia_Man_t *, int, int, int, int, int, int)p->vGateClasses != NULLObj =%7d iFrame <= nFrameMaxiFrame <= iFrame0Frame =%6d Removing Removed = %d. (%.2f %%) Aig_ManRegNum(pAig) == Vec_IntSize(vFlopClasses)src/proof/abs/absOldCex.cVec_Int_t *Saig_ManCbaFilterFlops(Aig_Man_t *, Abc_Cex_t *, Vec_Int_t *, Vec_Int_t *, int)Vec_IntSize(vAbsFfsToAdd) > nFfsToSelectSaig_ManPiNum(pAig) + Vec_IntSize(vMapEntries) == pAbsCex->nPisAig_Man_t *Saig_ManDupWithCubes(Aig_Man_t *, Vec_Vec_t *)iInput >= p->nInputs && iInput < Aig_ManCiNum(p->pAig)Vec_Int_t *Saig_ManCbaReason2Inputs(Saig_ManCba_t *, Vec_Int_t *)Entry >= 0 && Entry < Aig_ManCiNum(p->pFrames)Abc_Cex_t *Saig_ManCbaReason2Cex(Saig_ManCba_t *, Vec_Int_t *)void Saig_ManCbaFindReason_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Int_t *, Vec_Int_t *)!pObj->fPhaseVec_Int_t *Saig_ManCbaFindReason(Saig_ManCba_t *)Saig_ManPiNum(pAig) == pCex->nPisAig_Man_t *Saig_ManCbaUnrollWithCex(Aig_Man_t *, Abc_Cex_t *, int, Vec_Int_t **, Vec_Vec_t **)Saig_ObjIsLi(p->pAig, pObjLi)void Saig_ManCbaShrink(Saig_ManCba_t *)Level = %4d StateBits = %4d (%6.2f %%) CareBits = %4d (%6.2f %%) pCex->iFrame == pCare->iFrameint Saig_ManCexVerifyUsingTernary(Aig_Man_t *, Abc_Cex_t *, Abc_Cex_t *)pCex->nBits == pCare->nBits!Abc_InfoHasBit(pCex->pData, iBit)!Abc_InfoHasBit(pCare->pData, iBit)Frame PIs = %4d (essential = %4d) AIG PIs = %4d (essential = %4d) Real Care Saig_ManCbaFilterInputs(): The PI count of AIG (%d) does not match that of cex (%d). pAbs->pSeqModel == NULLVec_Int_t *Saig_ManCbaPerform(Aig_Man_t *, int, Saig_ParBmc_t *)Adding %d registers to the abstraction (total = %d). Saig_ObjIsLi(p, pObj)Aig_Obj_t *Saig_ObjLiToLo(Aig_Man_t *, Aig_Obj_t *)void Saig_ObjCexMinSim(Aig_Obj_t *)BMC did not detect a CEX with the given depth.Resource limit is reached during BMC. '@B @BCounter-example verification is successful. Output %d of miter "%s" was asserted in frame %d. pAbs->vCiNumsOrig != NULLsrc/proof/abs/absOldRef.cint Saig_ManCexFirstFlopPi(Aig_Man_t *, Aig_Man_t *)Adding %d registers to the abstraction (total = %d). Entry >= Saig_ManPiNum(p)Aig_Man_t *Saig_ManCexRefine(Aig_Man_t *, Aig_Man_t *, Vec_Int_t *, int, int, int, int, int, int *, int *, int *)Entry < Aig_ManCiNum(p)Vec_IntEntry(vFlops, i-1) != EntryRemapping counter-example from %d to %d primary inputs. Vec_IntSize(vFlopsNewBest) == nFfToAddMaxint Saig_ManCexRefineStep(Aig_Man_t *, Vec_Int_t *, Vec_Int_t *, Abc_Cex_t *, int, int, int, int)Filtering flops based on cost (%d -> %d). Vec_Int_t *Saig_ManCexAbstractionFlops(Aig_Man_t *, Gia_ParAbs_t *)Init : ITER %4d : gabs.aigRefinements is stopped because flop reduction is less than %d%% Saig_ManCexRemap(): The initial counter-example is invalid.Saig_ManCexRemap(): Counter-example is invalid.Discovered a true counter-example!Running property directed reachability...Refinement did not happen. Discovered a true counter-example.Gia_ManCexAbstractionRefine(): Abstraction latch map is missing.Refining abstraction...Performing counter-example-based refinement.iInput >= 0 && iInput < Aig_ManCiNum(p->pAig)src/proof/abs/absOldSat.cVec_Int_t *Saig_RefManReason2Inputs(Saig_RefMan_t *, Vec_Int_t *)Abc_Cex_t *Saig_RefManReason2Cex(Saig_RefMan_t *, Vec_Int_t *)void Saig_RefManFindReason_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Int_t *, Vec_Int_t *)(int)Aig_ObjFanin0(pObj)->fPhase == Aig_ObjFaninC0(pObj)Vec_Int_t *Saig_RefManFindReason(Saig_RefMan_t *)Aig_Man_t *Saig_ManUnrollWithCex(Aig_Man_t *, Abc_Cex_t *, int, Vec_Int_t **)Saig_ManRegNum(pAig) == pCex->nRegsiPiNum >= 0 && iPiNum < Aig_ManCiNum(p->pFrames)Vec_Vec_t *Saig_RefManOrderLiterals(Saig_RefMan_t *, Vec_Int_t *, Vec_Int_t *)Abc_Cex_t *Saig_RefManCreateCex(Saig_RefMan_t *, Vec_Int_t *, Vec_Int_t *)Aig_ManRegNum(p->pFrames) == 0Abc_Cex_t *Saig_RefManRunSat(Saig_RefMan_t *, int)Total PIs = %d. Essential PIs = %d. nCoreLits > 0AnalizeFinal selected %d assumptions (out of %d). Conflicts = %d. Entry >= 0 && Entry < Aig_ManCiNum(p->pAig)Vec_Int_t *Saig_RefManRefineWithSat(Saig_RefMan_t *, Vec_Int_t *)Assumpts = %2d. Intermediate instance is %5s. Conflicts = %2d. Saig_ManExtendCounterExampleTest3(): The PI count of AIG (%d) does not match that of cex (%d). Reduced CEX verification has failed.Internal Error!!! SAT solver timed out.Internal Error!!! The resulting problem is SAT.The problem is trivially UNSAT. The CEX is real.Constructed frames are incorrect.src/proof/abs/absOldSim.cint Saig_ManExtendOneEval(Vec_Ptr_t *, Aig_Obj_t *, int)int Saig_ManExtendOneEval2(Vec_Ptr_t *, Aig_Obj_t *, int)!Saig_ManSimInfo2IsOld( Value )void Saig_ManSetAndDriveImplications_rec(Aig_Man_t *, Aig_Obj_t *, int, int, Vec_Ptr_t *)f < fMaxAig_ObjIsCi(pObj) || Aig_ObjIsNode(pObj) || Aig_ObjIsConst1(pObj)p->pFanData!Aig_ObjIsConst1(pObj)void Saig_ManExplorePaths_rec(Aig_Man_t *, Aig_Obj_t *, int, int, Vec_Ptr_t *)(unsigned *)Vec_PtrEntry(vSimInfo,1) - (unsigned *)Vec_PtrEntry(vSimInfo,0) >= Abc_BitWordNum(2*(pCex->iFrame+1))Vec_Int_t *Saig_ManProcessCex(Aig_Man_t *, int, Abc_Cex_t *, Vec_Ptr_t *, int)Value == SAIG_ONE_NEWValue == SAIG_ONESaig_ManExtendCounterExampleTest2(): The PI count of AIG (%d) does not match that of cex (%d). Total new PIs = %3d. Non-removable PIs = %3d. Value >= SAIG_ZER && Value <= SAIG_UNDvoid Saig_ManSimInfoSet(Vec_Ptr_t *, Aig_Obj_t *, int, int)int Saig_ManSimInfo2And(int, int)int Saig_ManSimInfo2SetOld(int)pCexAbs->iPo == 0src/proof/abs/absOut.cAbc_Cex_t *Gia_ManCexRemap(Gia_Man_t *, Abc_Cex_t *, Vec_Int_t *)Gia_ManCexRemap(): Counter-example is invalid. Gia_ManGlaRefine(): Abstraction gate map is missing. Gia_ManGlaRefine(): The PI counts in GLA and in CEX do not match. Gia_ManGlaRefine(): The initial counter-example is invalid. Vec_IntSize(vPis) + Vec_IntSize(vPPis) == Gia_ManPiNum(pAbs)int Gia_ManGlaRefine(Gia_Man_t *, Abc_Cex_t *, int, int)Procedure &gla_refine found a real counter-example in frame %d. Vec_IntEntry( p->vGateClasses, iObjId ) == 0Additional objects = %d. iFrame >= 0 && iFrame <= p->iFrameVec_Int_t *Gia_ManGetStateAndCheckCex(Gia_Man_t *, Abc_Cex_t *, int)void Gia_ManCheckCex(Gia_Man_t *, Abc_Cex_t *, int)Vec_IntSize(vInit) == Vec_IntSize(vFlops)Gia_Man_t *Gia_ManTransformFlops(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *)iFlopId >= 0 && iFlopId < Gia_ManRegNum(p)Gia_ManNewRefine(): Abstraction gate map is missing. Refining with %d-frame CEX, starting in frame %d, with %d extra frames. Gia_ManNewRefine(): The PI counts in GLA and in CEX do not match. Gia_ManNewRefine(): The initial counter-example is invalid. Gia_ManNewRefine(): The initial counter-example is correct. pNew->vGateClasses == NULLint Gia_ManNewRefine(Gia_Man_t *, Abc_Cex_t *, int, int, int)Shortened CEX does not hold for the abstraction of the fast-forwarded model.Shortened CEX holds for the abstraction of the fast-forwarded model.src/proof/abs/absPth.cint Abs_CallBackToStop(int)void *Abs_ProverThread(void *)Proved abstraction %d. Disproved abstraction %d. Cancelled abstraction %d. void Gia_GlaProveAbsracted(Gia_Man_t *, int, int) Trying to prove abstraction %d. void Gia_GlaProveCancel(int)int Gia_GlaProveCheck(int)Gia_ManPoNum(pGia) == 1src/proof/abs/absRef.cRnm_Man_t *Rnm_ManStart(Gia_Man_t *)SensetizationJustificationVerification Total calls = %d. Average refine = %.1f. GIA mem = %.3f MB. Other mem = %.3f MB. void Rnm_ManCollect_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, int)Gia_ObjIsCi(pObj) || Gia_ObjIsAnd(pObj)void Rnm_ManCollect(Rnm_Man_t *)(int)pObj->Value == Vec_IntSize(p->vMap) + Vec_IntSize(p->vObjs)int Rnm_ManSensitize(Rnm_Man_t *)Gia_ObjIsRo(p->pGia, pObj) || Gia_ObjIsAnd(pObj) || Gia_ObjIsCo(pObj)!pRnm->fPPiiBit == p->pCex->nBitspRnm->fVisit == 0void Rnm_ManJustifyPropFanout_rec(Rnm_Man_t *, Gia_Obj_t *, int, Vec_Int_t *)(int)pRnm->Prio > 0void Rnm_ManJustify_rec(Rnm_Man_t *, Gia_Obj_t *, int, Vec_Int_t *)Gia_ObjIsConst0(pObj) || pObj->Valuesrc/proof/abs/absRef.hRnm_Obj_t *Rnm_ManObj(Rnm_Man_t *, Gia_Obj_t *, int)(int)pObj->Value < p->nObjsFramef >= 0 && f <= p->pCex->iFrameAbstraction refinement runtime statistics:Output value is incorrect.Selected PPI %3d : selected PPIfrontier (original PI or PPI)abstracted nodefree variablesrc/proof/abs/absRefSelect.cVec_Int_t *Rnm_ManFilterSelected(Rnm_Man_t *, Vec_Int_t *)iDom0 == iDom1src/proof/abs/absRpm.cvoid Gia_ManAddDom(Gia_Man_t *, Gia_Obj_t *, int)void Gia_ManComputeDoms(Gia_Man_t *)Support computationp->vDoms == NULLvoid Gia_ManTestDoms2(Gia_Man_t *)Gia_ObjFanin0(pDom) == pObjGia_ObjIsAnd(pDom)void Gia_ManTestDoms(Gia_Man_t *)Fanoutless flops = %d. void Gia_ManCountPisNodes_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, Vec_Int_t *)int Abs_GiaSortNodes(Gia_Man_t *, Vec_Int_t *)Vec_IntSize(vSupp) == 2 * nSizevoid Abs_ManSupport1_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)int Abs_ManSupport1(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)void Abs_ManSupport2_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)nSize0 > 0int Abs_ManSupport3(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)!pTemp->fMark1Gia_ObjRefNum(p, pTemp) > 0!Gia_ObjIsTravIdCurrent(p, pFan1)!Gia_ObjIsTravIdCurrent(p, pFan0)Res || (Mark[0] && Mark[1])int Abs_GiaCofPrint(word *, int, int, int)nSize0 > 0 && nSize0 <= nSizeint Abs_GiaCheckTruth(word *, int, int)i <= nStrIter %3d : PI = %5d (%6.2f %%) And = %6d (%6.2f %%) Dom = %5d (%6.2f %%) void Abs_RpmPerformMark(Gia_Man_t *, int, int, int)Gia_ObjRefNum( p, pObj ) > 0nSize0 > 0 && nSize0 <= nCutMaxNodes =%3d Size =%3d Size0 =%3d %3sGia_ObjIsAnd(pNode)int Abs_GiaObjDeref_rec(Gia_Man_t *, Gia_Obj_t *)Gia_ObjRefNum(p, pFanin) > 0int Abs_GiaObjRef_rec(Gia_Man_t *, Gia_Obj_t *)int Abs_ManSupport2(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)FAILURE.src/proof/abs/absRpmOld.cint Gia_ManDupFf2In_rec(Gia_Man_t *, Gia_Obj_t *)Original AIG:After FF-2-PI tranformation:After min-area retiming:After PI-2-FF transformation:After PI trimming:e@src/proof/abs/absVta.cVec_Ptr_t *Gia_VtaAbsToFrames(Vec_Int_t *)Vec_IntSize(vAbs) == Vec_VecSize(vFrames) + 2Vec_Int_t *Gia_VtaFramesToAbs(Vec_Vec_t *)Vec_IntEntry(vAbs, Vec_IntEntry(vAbs,0)+1) == Vec_IntSize(vAbs)Vec_IntSize(p) % nWords == 0int Vec_IntDoubleWidth(Vec_Int_t *, int)pThis != NULLVec_Int_t *Vta_ManCollectNodes(Vta_Man_t *, int)!pThis->fVisitVta_ValIs1(pThis0, Gia_ObjFaninC0(pObj)) && Vta_ValIs1(pThis1, Gia_ObjFaninC1(pObj))void Vta_ManSatVerify(Vta_Man_t *)Vta_ValIs0(pThis0, Gia_ObjFaninC0(pObj)) || Vta_ValIs0(pThis1, Gia_ObjFaninC1(pObj))pThis->Value == VTA_VAR0Vta_ValIs0(pThis0, Gia_ObjFaninC0(pObj))Vta_ValIs1(pThis0, Gia_ObjFaninC0(pObj))Abc_Cex_t *Vta_ManRefineAbstraction(Vta_Man_t *, int)pThis->Prio < VTA_LARGEpThis->Prio > 0pThis0->Prio <= pThis1->PriopThis->fVisit == 0pThis->Value != 0pThis0 && pThis1pThis0pThis->Prio >= 0 && pThis->Prio <= pTop->PrioGia_ObjIsAnd(pObj) || Gia_ObjIsRo(p->pGia, pObj) || Gia_ObjIsConst0(pObj) || Gia_ObjIsPi(p->pGia, pObj)pThis0->Prio <= pThis->PriopThis1->Prio <= pThis->PriopThis0->Prio == pThis->PriopThis1->Prio == pThis->PrioGia_ManObjNum(pGia) <= (int)p->nObjMaskVta_Man_t *Vga_ManStart(Gia_Man_t *, Abs_Par_t *)pGia->vObjClasses != NULLVec_Int_t *Vta_ManUnsatCore(int, sat_solver2 *, int, int, int *, int *)iFrame < nFramesint Vta_ManAbsPrintFrame(Vta_Man_t *, Vec_Int_t *, int, int, int, abctime, int) ...%5.1f GBpThis->iObj == iObj && pThis->iFrame == iFramevoid Vga_ManAddClausesOne(Vta_Man_t *, int, int)%d*%d pThis->fAdded == 1void Vga_ManRollBack(Vta_Man_t *, int)void Gia_VtaSendAbsracted(Vta_Man_t *, int)void Gia_VtaSendCancel(Vta_Man_t *, int)vabs.aigMemory: AIG Memory: SAT Memory: Proof Memory: Map Memory: Other Memory: TOTAL int Gia_VtaPerformInt(Gia_Man_t *, Abs_Par_t *)Running variable-timeframe abstraction (VTA) with the following parameters: FramePast = %d FrameMax = %d ConfMax = %d Timeout = %d RatioMin = %d %% Frame %% Abs %% Confl Cex Vars Clas Lrns Core Time Mem Vec_PtrSize(p->vFrames) > 0(vCore != NULL) == (Status == 1)pAig->vObjClasses == NULL && f < p->pPars->nFramesStartvtabs.aigAbstraction is not produced because first frame is not solved. Vec_PtrSize(p->vCores) > 0VTA completed %d frames with a %d-stable abstraction. Gia_VtaPerform(): CEX verification has failed! Vta_Obj_t *Vta_ManObj(Vta_Man_t *, int)int Vta_ObjId(Vta_Man_t *, Vta_Obj_t *)!Gia_ObjIsPi(p->pGia, pObj)void Vta_ObjPreds(Vta_Man_t *, Vta_Obj_t *, Gia_Obj_t *, Vta_Obj_t **, Vta_Obj_t **)Gia_ObjIsRo(p->pGia, pObj) && pThis->iFrame > 0iObj >= 0 && iFrame >= -1Vta_Obj_t *Vga_ManFindOrAdd(Vta_Man_t *, int, int)int sat_solver2_add_constraint(sat_solver2 *, int, int, int, int, int)void Vga_ManDelete(Vta_Man_t *, int, int)pThis != NULL && pThis->fAddedint Vga_ManGetOutLit(Vta_Man_t *, int)FVec_IntEntry(vVta, nFrames+1) == Vec_IntSize(vVta)src/proof/abs/absUtil.cVec_Int_t *Gia_VtaConvertToGla(Gia_Man_t *, Vec_Int_t *)nObjs <= nObjMaskGia_ObjIsRo(p, pObj) || Gia_ObjIsAnd(pObj) || Gia_ObjIsConst0(pObj)Vec_Int_t *Gia_VtaConvertFromGla(Gia_Man_t *, Vec_Int_t *, int)void Gia_FlaConvertToGla_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)ةiةةة3ة-ݩݩݩީfݩQvec[%d] = %s Saig_ObjIsPi( pAigNew, pObjPivot )src/proof/live/liveness.cchar *retrieveTruePiName(Abc_Ntk_t *, Aig_Man_t *, Aig_Man_t *, Aig_Obj_t *)index < Aig_ManCiNum( pAigNew ) - Aig_ManRegNum( pAigNew )SAVE_BIEREpObjOld->pData == pObjPivotSaig_ObjIsLo( pAigNew, pObjPivot )char *retrieveLOName(Abc_Ntk_t *, Aig_Man_t *, Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *)SAVED_LO%s__%sSHADOWassert_fairLIVENESSdummyStr[0] != '\0'assume_fairFAIRNESSAig_ManCheck( pNew )Aig_Man_t *LivenessToSafetyTransformation(int, Abc_Ntk_t *, Aig_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *)(Aig_Obj_t *)Vec_PtrEntry(pNew->vCos, Saig_ManPoNum(pNew)+Aig_ObjCioId(pObjSavedLo)-Saig_ManPiNum(p)-1) == pObjSavedLiSaig_ManPiNum( p ) + 1 == Saig_ManPiNum( pNew )Saig_ManRegNum( pNew ) == Saig_ManRegNum( p ) * 2 + 1 + liveLatch + fairLatchFlop[%d] = %s Flop copied [%d] = %s Aig_Man_t *LivenessToSafetyTransformationAbs(int, Abc_Ntk_t *, Aig_Man_t *, Vec_Int_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *)Saig_ManRegNum( pNew ) == Saig_ManRegNum( p ) + Vec_IntSize( vFlops ) + 1 + liveLatch + fairLatchlive2safeAig_Man_t *LivenessToSafetyTransformationOneStepLoop(int, Abc_Ntk_t *, Aig_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *)assert_safetyAssertNumber of safety property found = %d assume_safetyAssumeNumber of assume_safety property found = %d int Abc_CommandAbcLivenessToSafety(Abc_Frame_t *, int, char **)1slhdirective == IGNORE_LIVENESS_KEEP_SAFETY_MODE || directive == IGNORE_SAFETY_KEEP_LIVENESS_MODEusage: l2s [-1lsh] performs Armin Biere's live-to-safe transformation -1 : no shadow logic, presume all loops are self loops -l : ignore liveness and fairness outputs -s : ignore safety assertions and assumptions -h : print command usage int Abc_CommandAbcLivenessToSafetyAbstraction(Abc_Frame_t *, int, char **)Formula %d: AST is created, Well-formedness check PASSED, AST will be ignored for formula %d, no extra logic will be added for this formula Signal check FAILED!! No AST has been created for formula %d, no extra logic will be added Aig_Man_t *LivenessToSafetyTransformationWithLTL(int, Abc_Ntk_t *, Aig_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *, int *, Vec_Ptr_t *)pNegatedSafetyConjunction != NULLcheckAllBoolHaveAIGPointer( topNodeOfAST )n%d__%sGF_flopint Abc_CommandAbcLivenessToSafetyWithLTL(Abc_Frame_t *, int, char **)1slhfA new circuit is produced with %d POs - one for safety and %d for liveness. one additional input is added (due to Biere's nondeterminism) shadow flops are not created if the original circuit is combinational non-property POs are suppressed numOfLtlPropOutput == 0A new circuit is produced with %d PO - only for liveness property; safety properties are ignored, if any. one additional input is added (due to Biere's nondeterminism) shadow flops are not created if the original circuit is combinational non-property POs are suppressed usage: l3s [-1lsh] Circuit without any fairness propertyCircuit without any liveness propertyNo safety property is specified, hence no safety gate is createdThe input AIG contains no register, returning the original AIG as it isA new circuit is produced with 1 PO - only for liveness property; safety properties are ignored, if any. one additional input is added (due to Biere's nondeterminism) shadow flops are not created if the original circuit is combinational non-property POs are suppressedA new circuit is produced with 2 POs - one for safety and one for liveness. one additional input is added (due to Biere's nondeterminism) shadow flops are not created if the original circuit is combinational non-property POs are suppressedliveness output is conjoined with safety assertionsWARNING!! No safety property is found, a new (negated) constant 1 output is created Currently aborting, need to take care when Vec_PtrSize( vTopASTNodeArray ) == 0Well-formedness check FAILED!!Signal check PASSEDThe input network was not strashed, strashing....New circuit is produced ignoring safety outputs! Only liveness and fairness outputs are considered. Shadow registers are not createdA new circuit is produced with 1 PO - only for safety property; liveness properties are ignored, if any. no additional input is added (due to Biere's nondeterminism) shadow flops are not created non-property POs are suppressedA new circuit is produced with 2 POs - one for safety and one for liveness. one additional input is added (due to Biere's nondeterminism) shadow flops are not created non-property POs are suppressed ILLEGAL FLAG: aborting.... Number of liveness property found = %d Number of fairness property found = %d Saig_ManPiNum = %d, Reg Num = %d, before everything, before Pi cleanup src/proof/live/liveness_sim.cAig_Man_t *LivenessToSafetyTransformationOneStepLoopSim(Abc_Ntk_t *, Aig_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *)Aig_Man_t *LivenessToSafetyTransformationSim(Abc_Ntk_t *, Aig_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *)Saig_ManPoNum( pNew ) == 1 The input network was not strashed, strashing.... Circuit without any fairness property Circuit without any liveness property3$&%&&&&e%&&&&$&&&&&&&&&&&&&&#&&&&&&&&&&&%$&&&&&&&&&&&&&&&&s&))*.+H*+*)*w,m-+-U.,*.--,////0)2)2)2/4l4444444 5 6\66666666888888888src/proof/live/ltl_parser.cint isUnexpectedEOS(char *, int) Invalid LTL formula: unexpected end of string... Invalid LTL formula: expecting temporal operator at the position %d.... FAULTING POINT: formula = %s startOfSuffixString = %d, formula[%d] = %c Invalid LTL formula: expecting valid variable name token...abortingnode->left != NULLvoid traverseAbstractSyntaxTree(ltlNode *)node->right != NULL~ node->right == NULLnode->left == NULLvoid traverseAbstractSyntaxTree_postFix(ltlNode *)nextNode->type == EVENTUALLYvoid populateAigPointerUnitGF(Aig_Man_t *, ltlNode *, Vec_Ptr_t *, Vec_Vec_t *)nextToNextNode->pObjnextToNextNode->pObj == NULLpLtlNode->type != BOOLAig_Obj_t *buildLogicFromLTLNode_combinationalOnly(Aig_Man_t *, ltlNode *)pLtlNode->leftpLtlNode->rightleftAigObjrightAigObjpLtlNode->right == NULLAig_Obj_t *buildLogicFromLTLNode(Aig_Man_t *, ltlNode *)topNode->right == NULLint isNonTemporalSubformula(ltlNode *)int isWellFormed(ltlNode *)nextNode->right == NULL Variable name "%s" not found in the PO name list topASTNode->left != NULLint checkSignalNameExistence(Abc_Ntk_t *, ltlNode *)topASTNode->right != NULLtopASTNode->right == NULLAig_ObjIsCo( pObj )void populateBoolWithAigNodePtr(Abc_Ntk_t *, Aig_Man_t *, Aig_Man_t *, ltlNode *) faulting PODMANDYO topASTNode->name = %s int checkAllBoolHaveAIGPointer(ltlNode *) Unsupported token type: Exiting execution INVALID situation: aborting...FORBIDDEN node: ABORTING!! Attempting to create circuit with missing AIG pointer in a TEMPORAL node: ABORTING!! Serious ERROR: attempting to create AIG node from a temporal node UNSUPPORTED LTL NODE TYPE:: Aborting execution*pLiveIndex_0 != -1src/proof/live/kliveness.cAig_Man_t *introduceAbsorberLogic(Aig_Man_t *, int *, int *, int)*pLiveIndex_k == -1*pLiveIndex_k != -1kCSpPInpPOutpPOutCo == NULLpPOutCo != NULLAig_ManCheck( pNewAig )*pLiveIndex_k != - 1%s_%d.%skLivesafetyInvariantPOIndex != -1int flipConePdr(Aig_Man_t *, int, int, int, int)Aig_ManCheck( pAig )csSafetyInvar_csLevel1Stabil_vPtrvoid deallocateMasterBarrierDisjunctVecPtrVecInt(Vec_Ptr_t *)%d - int Abc_CommandCS_kLiveness(Abc_Frame_t *, int, char **)cmCghsafetyInvariantPO != -1pre-processing time = %f vMasterBarrierDisjuncts != NULLVec_PtrSize(vMasterBarrierDisjuncts) > 0k = %d, Property proved k = %d, Property DISPROVED Property UNDECIDED with k = %d. usage: kcs [-cmgCh] implements Claessen-Sorensson's k-Liveness algorithm -c : verification with constraints, looks for POs prefixed with csSafetyInvar_ -m : discovers monotone signals -g : verification with user-supplied barriers, looks for POs prefixed with csLevel1Stabil_ -C : verification with discovered monotone signals -h : print usage Enter parameterizedCombK = usage: nck [-cmgCh] generates combinatorial signals for stabilization void Aig_ObjChild0Flip(Aig_Obj_t *) Failed to read integer!newAigPoIndices != NULLsrc/proof/live/monotone.cstruct aigPoIndices *allocAigPoIndices()toBeDeletedAigPoIndices != NULLvoid deallocAigPoIndices(struct aigPoIndices *)newPointersToMonotoneVectors != NULLstruct monotoneVectorsStruct *allocPointersToMonotoneVectors()toBeDeleted != NULLvoid deallocPointersToMonotoneVectors(struct monotoneVectorsStruct *)hint_pendingSignal_monotone nRegCount = %d Aig_Man_t *createMonotoneTester(Aig_Man_t *, struct aigPoIndices *, struct monotoneVectorsStruct *, int *) Processing knownMonotone = %d poCopied = %d, poCreated = %d liCreated++ = %d loCopied + loCreated == liCopied + liCreated Saig_ManPoNum = %d Saig_ManPoNum(pAigNew) = %d, poMarker = %d i = %d, RetValue = %d : %s (Frame %d) Property ProvedPo[%d] = %s No Pending Signal FoundnewStructure != NULLsrc/proof/live/disjunctiveMonotone.cstruct antecedentConsequentVectorsStruct *allocAntecedentConsequentVectorsStruct()void deallocAntecedentConsequentVectorsStruct(struct antecedentConsequentVectorsStruct *)Aig_Man_t *createDisjunctiveMonotoneTester(Aig_Man_t *, struct aigPoIndices *, struct antecedentConsequentVectorsStruct *, int *)vDiffVectorVec_Ptr_t *findNextLevelDisjunctiveMonotone(Aig_Man_t *, struct aigPoIndices *, struct antecedentConsequentVectorsStruct *, Vec_Ptr_t *)hinthintSubStrvoid printAllIntVectors(Vec_Ptr_t *, Abc_Ntk_t *, char *) || INT[%d] : ( csLevel1Stabilvoid printAllIntVectorsStabil(Vec_Ptr_t *, Abc_Ntk_t *, char *)masterVec != NULLvoid appendVecToMasterVecInt(Vec_Ptr_t *, Vec_Ptr_t *)candVec != NULLAig_ObjIsCo(pObjPo)src/proof/live/arenaViolation.cAig_Obj_t *driverToPoNew(Aig_Man_t *, Aig_Obj_t *)!Aig_ObjIsCo(poDriverOld)Vec_IntSize( vIthBarrier ) >= 1Vec_Ptr_t *collectBarrierDisjunctions(Aig_Man_t *, Aig_Man_t *, Vec_Ptr_t *)pObjBarrierVec_PtrSize( vNewBarrierSignals ) == barrierCountvBarrierLiDriver != NULLAig_Obj_t *createArenaViolation(Aig_Man_t *, Aig_Man_t *, Aig_Obj_t *, Aig_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *)vMonotoneDisjunctionNodes != NULLvBarrierSignals != NULLVec_PtrSize( vMonotoneDisjunctionNodes ) == 0Vec_PtrSize( vMonotoneDisjunctionNodes ) == Vec_PtrSize( vMasterBarriers )Aig_Regular(pObj)->pDataAig_Obj_t *createConstrained0LiveConeWithDSC(Aig_Man_t *, Vec_Ptr_t *)csLiveConst_csLiveTarget_pConsequentVec_Ptr_t *collectCSSignalsWithDSC(Abc_Ntk_t *, Aig_Man_t *)windowBegins_withinWindow_0LiveVec_PtrSize(vMonotoneNodes) == Vec_PtrSize(vBarriers)Aig_Man_t *createNewAigWith0LivePoWithDSC(Aig_Man_t *, Vec_Ptr_t *, int *, int, int, int, Vec_Ptr_t *)Vec_PtrSize(vBarrierLiDriver) == Vec_PtrSize(vBarriers)src/proof/live/kLiveConstraints.cAig_Obj_t *createConstrained0LiveCone(Aig_Man_t *, Vec_Ptr_t *)Vec_Ptr_t *collectCSSignals(Abc_Ntk_t *, Aig_Man_t *)Aig_Man_t *createNewAigWith0LivePo(Aig_Man_t *, Vec_Ptr_t *, int *)vSignalVectorAig_Man_t *generateWorkingAig(Aig_Man_t *, Abc_Ntk_t *, int *)n >= ksrc/proof/live/combination.clong countCombination(long, long)Comb-%3d : vC[%d] = %d nCklCombinationCount > 0Aig_Man_t *generateDisjunctiveTester(Abc_Ntk_t *, Aig_Man_t *, int, int)liCopied + liCreated == loCopied + loCreatedAig_Man_t *generateGeneralDisjunctiveTester(Abc_Ntk_t *, Aig_Man_t *, int) Traget Signal Set is Empty: Duplicating given AIGVec_IntSize(vClass) > 0src/proof/ssc/sscClass.cvoid Ssc_GiaSimClassCreate(Gia_Man_t *, Vec_Int_t *)Repr < EntGia_ObjIsHead( p, i )int Ssc_GiaSimClassRefineOneBit(Gia_Man_t *, int)Gia_ObjIsHead(p, i)int Ssc_GiaSimClassRefineOne(Gia_Man_t *, int)!Ssc_GiaSimIsConst0( p, i )void Ssc_GiaSimProcessRefined(Gia_Man_t *, Vec_Int_t *)Gia_ObjRepr(p, i) == 0Gia_ObjNext(p, i) == 0Gia_ObjRepr(p, i) > 0void Ssc_GiaClassesInit(Gia_Man_t *)p->pReprs != NULLint Ssc_GiaClassesRefine(Gia_Man_t *)Pair (%d, %d) are still equivalent. 5 CQdVec_IntSize(&p->pFraig->vHTable) == 0src/proof/ssc/sscCore.cSsc_Man_t *Ssc_ManStart(Gia_Man_t *, Gia_Man_t *, Ssc_Pars_t *)!Gia_ManHasDangling(p->pFraig)Computed reference pattern violates %d constraints (this is a bug!). Parameters: SimWords = %d. SatConfs = %d. SatVarMax = %d. CallsRec = %d. Verbose = %d. SAT calls : Total = %d. Proof = %d. Cex = %d. Undec = %d. SAT solver: Vars = %d. Clauses = %d. Recycles = %d. Sim rounds = %d. Initialization SAT simulation CNF generation SAT solving unsat sat undecided Other int Ssc_GiaSimulatePatternFraig_rec(Ssc_Man_t *, int)iRepr == Gia_ObjRepr(p->pAig, iObj)int Ssc_GiaResimulateOneClass(Ssc_Man_t *, int, int)Gia_ObjIsHead( p->pAig, iRepr )Gia_ObjIsHead(p->pAig, iRepr)iRepr != Gia_ObjRepr(p->pAig, iObj)int Ssc_PerformVerification(Gia_Man_t *, Gia_Man_t *, Gia_Man_t *)Gia_ManRegNum(pCare) == 0Gia_Man_t *Ssc_PerformSweepingInt(Gia_Man_t *, Gia_Man_t *, Ssc_Pars_t *)Gia_ManCiNum(pAig) == Gia_ManCiNum(pCare)Gia_ManIsNormalized(pAig)Gia_ManIsNormalized(pCare)Care set produced %d hits out of %d. Abc_Lit2Var(pRepr->Value) != Abc_Lit2Var(pObj->Value)Reduction in AIG nodes:%8d ->%8d (%6.2f %%). SAT sweeping AIG with %d constraints. careUser AIG: Care AIG: void sat_solver_bookmark(sat_solver *)Conflict limit is reached while trying to find one SAT assignment.Constraints are UNSAT.Constraints are UNSAT after propagation.Verification undecided.There is no equivalences.p->pSat == NULL && p->vId2Var == NULLsrc/proof/ssc/sscSat.cvoid Ssc_ManStartSolver(Ssc_Man_t *)Aig_ManObjNumMax(pMan) == Gia_ManObjNum(p->pFraig)Vec_Int_t *Ssc_ManFindPivotSat(Ssc_Man_t *)iRepr != iNodeint Ssc_ManCheckEquivalence(Ssc_Man_t *, int, int, int)NodeId > 0void Ssc_ManCnfNodeAddToSolver(Ssc_Man_t *, int)Ssc_ObjSatVar(p, Gia_ObjId(p->pFraig, pNode))Vec_IntSize(p->vFanins) > 1void Ssc_ManCnfAddToFrontier(Ssc_Man_t *, int, Vec_Int_t *)!Gia_IsComplement( pNode )void Gia_ManAddClausesMux(Ssc_Man_t *, Gia_Obj_t *)Gia_ObjIsMuxType( pNode )!Gia_IsComplement(pObj)void Ssc_ManCollectSuper(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)void Gia_ManAddClausesSuper(Ssc_Man_t *, Gia_Obj_t *, Vec_Int_t *)Gia_ObjIsAnd( pNode )Vec_WrdSize(p) % nObjs == 0src/proof/ssc/sscSim.cvoid Vec_WrdDoubleSimInfo(Vec_Wrd_t *, int)nWords == Gia_ObjSimWords( p )void Ssc_GiaResetPiPattern(Gia_Man_t *, int)void Ssc_GiaSavePiPattern(Gia_Man_t *, Vec_Int_t *)p->iPatsPi < 64 * Gia_ObjSimWords(p)Vec_WrdSize(p->vSimsPi) % Gia_ManCiNum(p) == 0void Ssc_GiaResetSimInfo(Gia_Man_t *)nWords == Vec_WrdSize(p->vSims) / Gia_ManObjNum(p)void Ssc_GiaSimRound(Gia_Man_t *)pSim == Gia_ObjSimObj( p, pObj )pSim == Gia_ObjSim( p, i )src/proof/ssc/sscUtil.cGia_Man_t *Gia_ManDropContained(Gia_Man_t *)Gia_Man_t *Gia_ManOptimizeRing(Gia_Man_t *)Drop AIG: AIG%3d : src/proof/int/intCheck.cAig_Man_t *Inter_ManUnrollFrames(Aig_Man_t *, int)Aig_ManCiNum(p->pFrames) == nFramesK * Saig_ManPiNum(pTrans) + Saig_ManRegNum(pTrans)Inter_Check_t *Inter_CheckStart(Aig_Man_t *, int)Aig_ManCoNum(p->pFrames) == nFramesK * Saig_ManRegNum(pTrans)void Inter_CheckAddOrGate(Inter_Check_t *, int, int, int)void Inter_CheckAddEqual(Inter_Check_t *, int, int)Aig_ManCoNum(p->pCnf->pMan) == p->nFramesK * nRegsint Inter_CheckPerform(Inter_Check_t *, Cnf_Dat_t *, abctime)Aig_ManCoNum(pCnfInt->pMan) == 1Vec_IntSize(p->vOrLits) == p->nFramesKsrc/proof/int/intContain.cint Inter_ManCheckContainment(Aig_Man_t *, Aig_Man_t *)int Inter_ManCheckEquivalence(Aig_Man_t *, Aig_Man_t *)Aig_Man_t *Inter_ManFramesLatches(Aig_Man_t *, int, Vec_Ptr_t **)Aig_ManCoNum(pOld) == 1void Inter_ManAppendCone(Aig_Man_t *, Aig_Man_t *, Aig_Obj_t **, int)int Inter_ManCheckInductiveContainment(Aig_Man_t *, Aig_Man_t *, int, int)Vec_PtrSize(vMapRegs) == (nSteps + 1) * nRegsint Inter_ManCheckUniqueness(Aig_Man_t *, sat_solver *, Cnf_Dat_t *, int)src/proof/int/intCore.cint Inter_ManPerformInterpolation(Aig_Man_t *, Inter_ManParams_t *, int *)Saig_ManPiNum(pAig) > 0Saig_ManPoNum(pAig)-Saig_ManConstrNum(pAig) == 1Performing interpolation with %d constraints... AIG: PI/PO/Reg = %d/%d/%d. And = %d. Lev = %d. CNF: Var/Cla = %d/%d. Aig_ManCoNum(p->pInter) == 1Step = %2d. Frames = 1 + %d. And = %5d. Lev = %5d. Reached limit (%d) on the number of timeframes. I = %2d. Bmc =%3d. IntAnd =%6d. IntLev =%5d. Conf =%6d. Found a real counterexample in frame %d. p->nConfCur >= p->nConfLimitReached limit (%d) on the number of conflicts. Reached timeout (%d seconds) during rewriting. Proved containment of interpolants.The problem is trivially true for all states.Error: The problem timed out.Error: The problem should be SAT but it is UNSAT.Property trivially fails in the initial state.src/proof/int/intCtrex.cAig_Man_t *Inter_ManFramesBmc(Aig_Man_t *, int)Saig_ManPoNum(pAig) == 1void *Inter_ManGetCounterExample(Aig_Man_t *, int, int)Total ctrex generation timeInter_ManGetCounterExample(): Counter-example verification has FAILED.Counter-example generation in command "int" has failed.Use command "bmc2" to produce a valid counter-example.src/proof/int/intDup.cAig_Man_t *Inter_ManStartInitState(int)Aig_Man_t *Inter_ManStartDuplicated(Aig_Man_t *)Aig_Man_t *Inter_ManStartOneOutput(Aig_Man_t *, int)src/proof/int/intFrames.cAig_Man_t *Inter_ManFramesInter(Aig_Man_t *, int, int, int)Aig_ManCiNum(pInter) <= Aig_ManCiNum(pOther)src/proof/int/intInter.cAig_Man_t *Inter_ManDupExpand(Aig_Man_t *, Aig_Man_t *)Aig_ManCiNum(pInterC) == Aig_ManCiNum(pOther)Im is correct.Ip is correct.Property A => Im fails.Property Im => !B fails.Property A => Ip fails.Property Ip => !B fails.Aig_ManRegNum(pInter) == 0src/proof/int/intM114.csat_solver *Inter_ManDeriveSatSolver(Aig_Man_t *, Cnf_Dat_t *, Aig_Man_t *, Cnf_Dat_t *, Aig_Man_t *, Cnf_Dat_t *, Vec_Int_t *, int)Aig_ManRegNum(pAig) > 0Aig_ManRegNum(pFrames) == 0Aig_ManCoNum(pInter) == 1fUseBackward || Aig_ManCiNum(pInter) == Aig_ManRegNum(pAig)Aig_ManCiNum(pAig) == Aig_ManCiNum(pInter)pCnfFrames->pVarNums[pObj->Id] >= 0Inductive invariant is dumped into file "%s". Interpolants are dumped into file "%s". CNF mappingOther Runtime statistics:p->pCexComb == NULLsrc/proof/cec/cecCec.cvoid Cec_ManTransformPattern(Gia_Man_t *, int, int *)Counter-example verification has failed. Primary output %d has failed, along with other %d incorrect outputsNetworks are NOT EQUIVALENT. Output %d trivially differs (different phase). Networks are NOT EQUIVALENT. Output %d trivially differs (different PIs). Gia_ObjFaninC0(pObj1) == Gia_ObjFaninC0(pObj2)int Cec_ManHandleSpecialCases(Gia_Man_t *, Cec_ParCec_t *)Networks are NOT EQUIVALENT. Output %d trivially differs (PI vs. constant). Gia_ManPoNum(p) % 2 == 0int Cec_ManVerifyNaive(Gia_Man_t *, Cec_ParCec_t *)Timeout (%d sec) is reached. iVar0 >= 0 && iVar1 >= 0Output %d is SAT. UNSAT = %6d. SAT = %6d. UNDEC = %6d. Trivial = %6d. Counter-example simulation has failed. Networks are UNDECIDED after the new CEC engine. Calling the old CEC engine. Gia_ManCoNum(p) == 2int Cec_ManVerifySimple(Gia_Man_t *)src/proof/cec/cecChoice.cGia_Man_t *Cec_ManCombSpecReduce(Gia_Man_t *, Vec_Int_t **, int)Obj = %7d. And = %7d. Conf = %5d. Ring = %d. CSat = %d. Gia_ManRegNum(pSrm) == 0 && Gia_ManCiNum(pSrm) == Gia_ManCiNum(pAig)int Cec_ManChoiceComputation_int(Gia_Man_t *, Cec_ParChc_t *)The refinement was not finished. The result may be incorrect. Srm int Cec_ManCombSpecReal(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *)src/proof/cec/cecClass.cvoid Cec_ManSimClassCreate(Gia_Man_t *, Vec_Int_t *)Gia_ObjIsHead(p->pAig, i)int Cec_ManSimClassRefineOne(Cec_ManSim_t *, int)int Cec_ManSimClassRemoveOne(Cec_ManSim_t *, int)Vec_IntSize( p->vClassNew ) == 1!Gia_ObjIsClass(p->pAig, i)p->pSimInfo[i] == 0unsigned int *Cec_ManSimSimRef(Cec_ManSim_t *, int)p->pMems == NULLp->pSimInfo[i] > 0unsigned int *Cec_ManSimSimDeref(Cec_ManSim_t *, int)!Cec_ManSimCompareConst( pSim, p->nWords )void Cec_ManSimProcessRefined(Cec_ManSim_t *, Vec_Int_t *)Gia_ObjRepr(p->pAig, i) == 0Gia_ObjNext(p->pAig, i) == 0Gia_ObjRepr(p->pAig, i) > 0void Cec_ManSimSavePattern(Cec_ManSim_t *, int)iPat >= 0 && iPat < 32 * p->nWordsp->pBestState->nRegs == Gia_ManRegNum(p->pAig)void Cec_ManSimFindBestPattern(Cec_ManSim_t *)p->vCoSimInfo != NULLint Cec_ManSimAnalyzeOutputs(Cec_ManSim_t *)(Gia_ManPoNum(p->pAig) & 1) == 0Gia_ObjValue(pObj)int Cec_ManSimSimulateRound(Cec_ManSim_t *, Vec_Ptr_t *, Vec_Ptr_t *)Gia_ObjIsHead(p->pAig, Gia_ObjRepr(p->pAig, i))vInfoCis == NULL || iCiId == Gia_ManCiNum(p->pAig)vInfoCos == NULL || iCoId == Gia_ManCoNum(p->pAig)p->nMems == 1vInfoCis && vInfoCosvoid Cec_ManSimCreateInfo(Cec_ManSim_t *, Vec_Ptr_t *, Vec_Ptr_t *)p->pAig->pReprs == NULLint Cec_ManSimClassesPrepare(Cec_ManSim_t *, int) 5 CQdd ddThe number of failed outputs of the miter = %6d. (Words = %4d. Frames = %4d.) Performing rounds of random simulation of %d frames with %d words. nLitsOld == nLitsNewsrc/proof/cec/cecCore.cvoid Cec_ManSimulation(Gia_Man_t *, Cec_ParSim_t *)Random simulation is stopped after %d rounds. Random simulation saturated after %d rounds. The number of POs that are not const-0 candidates = %d. Considered all available candidate equivalences. Switching into reduced mode. Switching into normal mode. %3d : P =%7d. D =%7d. F =%6d. M = %7d. And =%8d. Network after reduction is empty. Exceeded the limit on the number of conflicts (%d). Increasing conflict limit to %d. NBeg = %d. NEnd = %d. (Gain = %6.2f %%). RBeg = %d. REnd = %d. (Gain = %6.2f %%). Sim Sat Pat Disproved at least one output of the miter (zero-based number %d). Disproved %d outputs of the miter. Timed out after %d seconds. src/proof/cec/cecCorr.cGia_Man_t *Gia_ManCorrSpecReduce(Gia_Man_t *, int, int, Vec_Int_t **, int)(!fScorr && nFrames > 1) || (fScorr && nFrames > 0) || nPrefixGia_Man_t *Gia_ManCorrSpecReduceInit(Gia_Man_t *, int, int, int, Vec_Int_t **, int)nFlops <= Vec_PtrSize(vInfo)void Cec_ManStartSimInfo(Vec_Ptr_t *, int)pInfoObj[w] == 0void Gia_ManCorrRemapSimInfo(Gia_Man_t *, Vec_Ptr_t *)Vec_Int_t *Gia_ManCorrCreateRemapping(Gia_Man_t *)void Gia_ManCorrPerformRemapping(Vec_Int_t *, Vec_Ptr_t *)iStart == Vec_IntSize(vCexStore)int Cec_ManResimulateCounterExamples(Cec_ManSim_t *, Vec_Int_t *, int)int Cec_ManResimulateCounterExamplesComb(Cec_ManSim_t *, Vec_Int_t *)2 * Vec_StrSize(vStatus) == Vec_IntSize(vOutputs)int Gia_ManCheckRefinements(Gia_Man_t *, Vec_Str_t *, Vec_Int_t *, Cec_ManSim_t *, int)void Gia_ManCorrReduce_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *)BMC : c =%8d cl =%7d lit =%8d p =%6d d =%6d f =%6d Vec_StrSize(vStatus) * 2 == Vec_IntSize(vEquivs)int Cec_ManLSCorrAnalyzeDependence(Gia_Man_t *, Vec_Int_t *, Vec_Str_t *)iRepr == Gia_ObjRepr(p, iObj)%5d -> %5d (%3d) Cec_ManLatchCorrespondence(): Not a sequential AIG. Obj = %7d. And = %7d. Conf = %5d. Fr = %d. Lcorr = %d. Ring = %d. CSat = %d. Stopped signal correspondence after BMC. Stopped signal correspondence after %d refiment iterations. Gia_ManRegNum(pSrm) == 0 && Gia_ManPiNum(pSrm) == Gia_ManRegNum(pAig)+(pPars->nFrames+!pPars->fLatchCorr)*Gia_ManPiNum(pAig)int Cec_ManLSCorrespondenceClasses(Gia_Man_t *, Cec_ParCor_t *)Iterative refinement is stopped after iteration %d p->vNamesIn != NULLvoid Cec_ManPrintFlopEquivs(Gia_Man_t *)Original flop %s is proved equivalent to internal node %d. The reduced AIG was produced using %d-th invariants and will not verify. Flop output names are not available. Use command "&get -n". int Gia_ManCorrSpecReal(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *, int, int)f && Gia_ObjIsRo(p, pObj)void Gia_ManCorrSpecReduce_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *, int, int)int Gia_ObjHasSameRepr(Gia_Man_t *, int, int)because the property output is no longer a candidate constant.p->pReprs && p->pNexts && p->pIsosrc/proof/cec/cecIso.cvoid Cec_ManTransformClasses(Gia_Man_t *)Gia_ObjColors(p, i) == 0int *Cec_ManDetectIsomorphism(Gia_Man_t *)Gia_ObjColors(p, i)Computed %d pairs of structurally equivalent nodes. Color == 1 || Color == 2void Gia_ManIsoTableAdd(Gia_Man_t *, int, unsigned int *, int, int *, int)pTemp->Value == 0pTemp->fMark0 == 0pIso[IdA] == 0void Gia_ManIsoMatchNodes(int *, unsigned int *, int, Vec_Int_t *, Vec_Int_t *)pIso[IdB] == 0IdA != IdBCO = %8d AND = %8d Conf = %5d MinVar = %5d MinCalls = %5d Unsat calls %6d (%6.2f %%) Ave conf = %8.1f Sat calls %6d (%6.2f %%) Ave conf = %8.1f Undef calls %6d (%6.2f %%) Ave conf = %8.1f Latest: P = %8d. L = %10d. Lm = %10d. Ave = %6.1f. MEM =%6.2f MB Total: P = %8d. L = %10d. Lm = %10d. Ave = %6.1f. MEM =%6.2f MB Finding ShrinkingVerifyingSorting Packing src/proof/cec/cecPat.cint Cec_ManPatComputePattern_rec(Cec_ManSat_t *, Gia_Man_t *, Gia_Obj_t *)void Cec_ManPatComputePattern1_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)(Gia_ObjFanin0(pObj)->fMark1 ^ Gia_ObjFaninC0(pObj)) == 0 || (Gia_ObjFanin1(pObj)->fMark1 ^ Gia_ObjFaninC1(pObj)) == 0void Cec_ManPatComputePattern2_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)int Cec_ManPatComputePattern3_rec(Gia_Man_t *, Gia_Obj_t *)Cec_ManPatVerifyPattern(): Verification failed. Value == GIA_ONEvoid Cec_ManPatVerifyPattern(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)void Cec_ManPatComputePattern4_rec(Gia_Man_t *, Gia_Obj_t *)void Cec_ManPatCleanMark0(Gia_Man_t *, Gia_Obj_t *)void Cec_ManPatSavePattern(Cec_ManPat_t *, Cec_ManSat_t *, Gia_Obj_t *)(Gia_ObjFanin0(pObj)->fMark1 ^ Gia_ObjFaninC0(pObj)) == 1Total = %5d. Max used = %5d. Full = %5d. Series = %d. nRegs <= nInputsVec_Ptr_t *Cec_ManPatPackPatterns(Vec_Int_t *, int, int, int)Vec_IntSize(vPat) > 0void Cec_ManPatStore(Cec_ManPat_t *, Vec_Int_t *)NumberPrev < Numbervoid Cec_ManPatStoreNum(Cec_ManPat_t *, int)Vec_IntSize(vPat) == Sizevoid Cec_ManPatRestore(Cec_ManPat_t *, Vec_Int_t *)  5 CQsrc/proof/cec/cecSat.cvoid Cec2_AddClausesMux(Gia_Man_t *, Gia_Obj_t *, satoko_t *)pNode->fMark0!Gia_IsComplement(pNode)void Cec2_AddClausesSuper(Gia_Man_t *, Gia_Obj_t *, Vec_Ptr_t *, satoko_t *)void Cec2_CollectSuper(Gia_Man_t *, Gia_Obj_t *, int, Vec_Ptr_t *)!Gia_ObjIsCi(pObj)void Cec2_ObjAddToFrontier(Gia_Man_t *, Gia_Obj_t *, Vec_Ptr_t *, satoko_t *)Cec2_ObjSatId(p, pObj) == -1Vec_IntSize(p->vVar2Obj) == iVariObj > 0int Gia_ObjGetCnfVar(Gia_Man_t *, int, Vec_Ptr_t *, Vec_Ptr_t *, satoko_t *)Vec_IntSize(pGia->vVar2Obj) == iVarCec2_ObjSatId(pGia,pNode) >= 0Vec_PtrSize(vFanins) > 1p->vSimsPi != NULLvoid Cec2_ManSaveCis(Gia_Man_t *)void Cec2_ManSimClassRefineOne(Gia_Man_t *, int)Key >= 0 && Key < nTableSizevoid Cec2_ManCreateClasses(Gia_Man_t *, Cec2_Man_t *) fail Rollback int Cec2_ManVerify_rec(Gia_Man_t *, int, satoko_t *)CEX verification FAILED for obj %d and obj %d. Cec2_ObjSatId(p->pNew, pObj) >= 0void Cec2_ManCollect_rec(Cec2_Man_t *, int)iObj0 < iObj1int Cec2_ManSolveTwo(Cec2_Man_t *, int, int, int)p->pPars->fUseCones || satoko_varnum(p->pSat) == 0p->pAig->iPatsPi > 0 && p->pAig->iPatsPi < 64 * p->pAig->nSimWordsint Cec2_ManSweepNode(Cec2_Man_t *, int)status == SATOKO_UNDECS =%5d U =%5d F =%5d !Gia_ObjProved(p, i) && !Gia_ObjFailed(p, i)int Cec2_ManPerformSweeping(Gia_Man_t *, Cec2_Par_t *, Gia_Man_t **)Vec_IntSize(&pMan->pNew->vCopies2) == Gia_ManObjNum(pMan->pNew)(pObj->Value ^ pRepr->Value) == (pObj->fPhase ^ pRepr->fPhase)Failed to resimulate %d times with pattern = %d (total = %d). int Cec2_ObjSetSatId(Gia_Man_t *, Gia_Obj_t *, int)Cec2_ObjSatId(p, pObj) != -1void Cec2_ObjCleanSatId(Gia_Man_t *, Gia_Obj_t *) 5 CQsrc/proof/cec/cecSatG.cvoid Cec3_AddClausesMux(Gia_Man_t *, Gia_Obj_t *, bmcg_sat_solver *)void Cec3_AddClausesSuper(Gia_Man_t *, Gia_Obj_t *, Vec_Ptr_t *, bmcg_sat_solver *)void Cec3_CollectSuper(Gia_Obj_t *, int, Vec_Ptr_t *)void Cec3_ObjAddToFrontier(Gia_Man_t *, Gia_Obj_t *, Vec_Ptr_t *, bmcg_sat_solver *)Cec3_ObjSatId(p, pObj) == -1int Cec3_ObjGetCnfVar(Cec3_Man_t *, int)Cec3_ObjSatId(p->pNew,pNode) >= 0Vec_PtrSize(p->vFanins) > 1void Cec3_ManSaveCis(Gia_Man_t *)void Cec3_ManSimClassRefineOne(Gia_Man_t *, int)void Cec3_ManCreateClasses(Gia_Man_t *, Cec3_Man_t *)int Cec3_ManVerify_rec(Gia_Man_t *, int, bmcg_sat_solver *)Cec3_ObjSatId(p->pNew, pObj) >= 0void Cec3_ManCollect_rec(Cec3_Man_t *, int)int Cec3_ManSolveTwo(Cec3_Man_t *, int, int, int)p->pPars->fUseCones || bmcg_sat_solver_varnum(p->pSat) == 0int Cec3_ManSweepNode(Cec3_Man_t *, int)status == GLUCOSE_UNDECint Cec3_ManPerformSweeping(Gia_Man_t *, Cec3_Par_t *, Gia_Man_t **)int Cec3_ObjSetSatId(Gia_Man_t *, Gia_Obj_t *, int)Cec3_ObjSatId(p, pObj) != -1void Cec3_ObjCleanSatId(Gia_Man_t *, Gia_Obj_t *) 5 CQ88pCex->nBits == pCex->nRegs + pCex->nPis * (pCex->iFrame + 1)src/proof/cec/cecSeq.cvoid Cec_ManSeqDeriveInfoFromCex(Vec_Ptr_t *, Gia_Man_t *, Abc_Cex_t *)pCex->nBits - pCex->nRegs + Gia_ManRegNum(pAig) <= Vec_PtrSize(vInfo)The CEX has flop values different from 0, but they are currently not used by "resim". pCex == NULL || Gia_ManRegNum(pAig) == pCex->nRegsvoid Cec_ManSeqDeriveInfoInitRandom(Vec_Ptr_t *, Gia_Man_t *, Abc_Cex_t *)Vec_PtrSize(vInfo) == Gia_ManRegNum(p->pAig) + Gia_ManPiNum(p->pAig) * p->pPars->nFramesint Cec_ManSeqResimulate(Cec_ManSim_t *, Vec_Ptr_t *)k == Vec_PtrSize(vInfo)(Vec_PtrSize(vSimInfo) - Gia_ManRegNum(pAig)) % Gia_ManPiNum(pAig) == 0int Cec_ManSeqResimulateInfo(Gia_Man_t *, Vec_Ptr_t *, Abc_Cex_t *, int)Cec_ManSeqResimulateCounter(): Counter-example is not available. Cec_ManSeqResimulateCounter(): Equivalence classes are not available. Cec_ManSeqResimulateCounter(): Not a sequential AIG. Cec_ManSeqResimulateCounter(): The number of PIs in the AIG and the counter-example differ. Resimulating %d timeframes. Cec_ManSeqSemiformal(): Equivalence classes are not available. Cec_ManSeqSemiformal(): Not a sequential AIG. Starting: Cec_ManSeqSemiformal: There are only trivial equiv candidates left (PO drivers). Quitting. Quitting refinement because miter could not be unrolled. Gia_ManRegNum(pSrm) == 0 && Gia_ManPiNum(pSrm) == (Gia_ManPiNum(pAig) * nFramesReal)int Cec_ManSeqSemiformal(Gia_Man_t *, Cec_ParSmf_t *)Unrolled for %d frames. pState->iPo >= 0BMC = %3d gore.aigCec_ManSeqSemiformal(): An output of the miter is asserted. Refinement stopped. src/proof/cec/cecSolve.cvoid Cec_AddClausesMux(Cec_ManSat_t *, Gia_Obj_t *)void Cec_AddClausesSuper(Cec_ManSat_t *, Gia_Obj_t *, Vec_Ptr_t *)void Cec_CollectSuper(Gia_Obj_t *, int, Vec_Ptr_t *)void Cec_ObjAddToFrontier(Cec_ManSat_t *, Gia_Obj_t *, Vec_Ptr_t *)void Cec_CnfNodeAddToSolver(Cec_ManSat_t *, Gia_Obj_t *)Cec_ObjSatNum(p,pNode)int Cec_ManSatCheckNode(Cec_ManSat_t *, Gia_Obj_t *)status != 0p->pSat->qtail == p->pSat->qheadint Cec_ManSatCheckNodeTwo(Cec_ManSat_t *, Gia_Obj_t *, Gia_Obj_t *)SAT...OrigId1 >= 0 && OrigId2 >= 0void Cec_ManSatSolve(Cec_ManPat_t *, Gia_Man_t *, Cec_ParSat_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Vec_StrSize(vStatus) == Gia_ManCoNum(pAig)void Cec_ManSatSolveCSat(Cec_ManPat_t *, Gia_Man_t *, Cec_ParSat_t *)void Cec_ManSatSolveSeq_rec(Cec_ManSat_t *, Gia_Man_t *, Gia_Obj_t *, Vec_Ptr_t *, int, int)void Cec_ManSatSolveMiter_rec(Cec_ManSat_t *, Gia_Man_t *, Gia_Obj_t *)Vec_Int_t *Cec_ManSatSolveMiter(Gia_Man_t *, Cec_ParSat_t *, Vec_Str_t **)p->pMuxes == NULLsrc/proof/cec/cecSplit.cvoid Cec_GiaSplitExplore(Gia_Man_t *)%2d %2d %2d %2d iBest >= 0int Gia_SplitCofVar2(Gia_Man_t *, int *, int *)int Gia_SplitCofVar(Gia_Man_t *, int, int *, int *)Depth =%3d SatVar =%7d SatConf =%7d %s UNSAT UNDECIDEDSolved %8.4f %% status == -1int Cec_GiaSplitTest2(Gia_Man_t *, int, int, int, int, int, int, int)Var = %5d. Fanouts = %5d. Cost = %8d. AndBefore = %6d. AndAfter = %6d. Problem is SAT Problem is UNSAT Problem is UNDECIDED after %d case-splits. Processes = %d TimeOut = %d sec MaxIter = %d LookAhead = %d Verbose = %d. nProcs >= 1 && nProcs <= PAR_THR_MAXint Cec_GiaSplitTestInt(Gia_Man_t *, int, int, int, int, int, int, int)ThData[i].p == NULL Solving output %d: The AIG with %d candidate nodes (PI+AND) has %d unique MUX control drivers: %6d : Obj = %6d MUX refs = %5d Level = %5d Cof0 = %7d Cof1 = %7d PI %5d : Refs = %5d The problem is UNSAT without cofactoring.The problem is SAT without cofactoring.Solving CEC problem by cofactoring with the following parameters:dsrc/proof/cec/cecSynth.cGia_Man_t *Gia_ManRegCreatePart(Gia_Man_t *, Vec_Int_t *, int *, int *, int **)Abc_Lit2Var(Gia_ObjValue(pObj)) < Gia_ManObjNum(pNew)int Gia_TransferMappedClasses(Gia_Man_t *, int *, int *)Gia_ObjRepr(pPart, i) < Gia_ManObjNum(pPart)void Gia_ManNormalizeEquivalences(Gia_Man_t *, int *)%3d : Reg = %4d. PI = %4d. (True = %4d. Regs = %4d.) And = %5d. Cl = %5d. void Gia_ObjSetTravIdPrevious(Gia_Man_t *, Gia_Obj_t *)Gia_ObjRepr(p->pAig, i) < isrc/proof/cec/cecSweep.cGia_Man_t *Cec_ManFraSpecReduction(Cec_ManFra_t *)Vec_IntSize(p->vXorNodes) == 2*Gia_ManCoNum(pNew)int Cec_ManFraClassesUpdate(Cec_ManFra_t *, Cec_ManSim_t *, Cec_ManPat_t *, Gia_Man_t *)pObjOld->fMark0 == 1!Gia_ObjProved(p->pAig, iNode)iRepr == Gia_ObjRepr(p->pAig, iNode)Cec_ManFraClassesUpdate(): Error! Node is not refined! !Gia_ObjFailed(p->pAig, iNode)src/proof/acec/acecCl.cvoid Acec_ManDerive_rec(Gia_Man_t *, Gia_Man_t *, int, Vec_Int_t *)Gia_Man_t *Acec_ManDerive(Gia_Man_t *, Vec_Int_t *)%4d <- int Acec_DetectLitPolarity(Gia_Man_t *, int, int)Lit0 == Lit1Problem for leaf %d void Acec_DetectComputeSuppOne_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, Vec_Int_t *)Out %4d : %4d Detected %d top XORs. iStart < Gia_ManCoNum(p)Vec_Int_t *Acec_RewriteTop(Gia_Man_t *, Acec_Box_t *)Vec_IntSize(vLevel) > 0Vec_IntSize(vLevel) <= 3Vec_IntSize(vRes) >= Gia_ManCoNum(p)Added %d adders for replace CLAs. Gia_ManCoNum(p) == Vec_IntSize(vRes)Gia_Man_t *Acec_RewriteReplace(Gia_Man_t *, Vec_Int_t *)Cone:XORs do not form a continuous sequenceBoth inputs of top level XOR have XOR/non-XORCannot find arithmetic boxes.Detected %d oversize support nodes. Rank %d: Lit %d and %d do not pass verification. Total errors in equivalence classes = %d. Gia_ManCiNum(pBase) == Gia_ManCiNum(pAdd)src/proof/acec/acecCore.cGia_Man_t *Acec_CommonStart(Gia_Man_t *, Gia_Man_t *)Finished computing equivalent nodes. Rank %2d : %2d Rank = %4d : Obj = %4d Supp = %d. Vec_IntSize(vLevel1) == Vec_IntSize(vLevel2)void Acec_MoveDuplicates(Vec_Wec_t *, Vec_Wec_t *)Vec_IntSize(Vec_WecEntry(vLits, i+1)) == Vec_IntSize(Vec_WecEntry(vClasses, i+1))Moved %d pairs of PPs to normalize the matrix. pBox0->vShared == NULLint Acec_MatchBoxes(Acec_Box_t *, Acec_Box_t *)pBox1->vShared == NULL*pBeg0 && *pBeg1Vec_IntSize(vShared0) == Vec_IntSize(vShared1)Vec_IntSize(vShared0) + Vec_IntSize(vUnique0) == Vec_IntSize(vLevel0)Vec_IntSize(vShared1) + Vec_IntSize(vUnique1) == Vec_IntSize(vLevel1)Box0: Matched %d entries out of %d. Box1: Matched %d entries out of %d. Matching of adder trees in LHS and RHS succeeded. int Abc_Lit2LitL(int *, int)Vec_Int_t *Vec_WecInsertLevel(Vec_Wec_t *, int)UUUUUUUU33333333""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333Leaf literals and their classes:Shifted one level down.Shifted one level up.Cannot match arithmetic boxes in LHS and RHS. Trying regular CEC.Cannot find arithmetic boxes in both LHS and RHS. Trying regular CEC.Vec_BitEntry(vIsRoot, Entry1)src/proof/acec/acecCo.cVec_Int_t *Gia_PolynCoreOrder_int(Gia_Man_t *, Vec_Int_t *, Vec_Wec_t *, Vec_Int_t *, Vec_Int_t **)Vec_BitEntry(vIsRoot, Entry2)Collected %d boxes. Supp = %3d Cone = %3d Remaining cones: Count = %d. SuppMax = %d. ConeMax = %d. int Gia_PolynCoreDupTreePlus_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *)Gia_Man_t *Gia_PolynCoreDupTree(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, int)Detected %d FAs/HAs. Roots = %d. Leaves = %d. Nodes = %d. Adds = %d. On top of %d COs, created %d new adder outputs. obj = %4d : b0 = %4d b1 = %4d b2 = %4d a0 = %4d a1 = %4d MMMMMMMMMMMMMMMMMMMMMMM*PP"3DUfw"3DUfw PUZ_ 03<?U3@%d = %X %d : %d : pCut[0] == 2src/proof/acec/acecRe.cvoid Ree_ManCutMerge(Gia_Man_t *, int, int *, int *, Vec_Int_t *, Hash_IntMan_t *, Vec_Int_t *, Vec_Int_t *)Value <= nEntriesVec_Int_t *Ree_ManDeriveAdds(Hash_IntMan_t *, Vec_Int_t *, int)n < 8AIG nodes = %d. Cuts = %d. Cuts/Node = %.2f. Ints/Node = %.2f. Adders = %d. Total cuts = %d. Hashed cuts = %d. Hashed/Adders = %.2f. k <= ivoid Ree_ManRemoveTrivial(Gia_Man_t *, Vec_Int_t *)void Ree_ManRemoveContained(Gia_Man_t *, Vec_Int_t *) -> Detected %d FAs and %d HAs. pCut[0] == 2 || pCut[0] == 3int Ree_ManCutMergeOne(int *, int *, int *)pCut[1] < pCut[2]pCut[2] < pCut[3]int Ree_ManCutTruthOne(int *, int *)pCut[1] == pCut0[1] && pCut[2] == pCut0[2]int Ree_ManCutNotFind(int, int, int *)int Ree_ManCutFind(int, int *)int Hsh_Int3ManInsert(Hash_IntMan_t *, int, int, int)int *Hsh_Int3ManLookup(Hash_IntMan_t *, int, int, int)p->nSize < nSizevoid Vec_BitFillExtra(Vec_Bit_t *, int, int)src/proof/acec/acecPa.cint Pas_ManVerifyPhaseOne_rec(Gia_Man_t *, Gia_Obj_t *)!Gia_ObjIsXor(pObj)Fadd %d sum is wrong. Fadd %d carry is wrong. pObj != Gia_ManConst0(p)void Pas_ManPhase_rec(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Gia_Obj_t *, int, Vec_Bit_t *, Vec_Bit_t *)Carry %d participates more than once. Outputs: Inputs: Compl = %d Detected %d FAs and %d HAs. Collected %d adders. Detected %d adder trees. Const == ABC_INFINITYsrc/proof/acec/acecPo.cvoid Acec_ParseSignatureMono(char *, char *, Vec_Int_t *)pTemp == pStop || pTemp[0] == '*'Const != ABC_INFINITYp[0] == '(' && pStop[0] == ')'Vec_Wec_t *Acec_ParseSignatureOne(char *, char *)pNext[0] == '+' || pNext[0] == '-' || pNext[0] == ')'Vec_Wec_t *Acec_ParseSignature(char *)Output signature with %d monomials: %s2^%d(4*o1+2*o2+1*o3)*(4*i4+2*i5+1*i6)+(4*o4+2*o5+1*o6) * i%dPolynomial with %d monomials: Input signature with %d monomials: -2^%d appears %d times +2^%d appears %d times Vec_WecSize(vPolyn) == 2*nNonConstVec_Wec_t *Gia_PolynGetResult(Hsh_VecMan_t *, Hsh_VecMan_t *, Vec_Int_t *)HashC = %d. HashM = %d. Total = %d. Left = %d. Used = %d. Assigning %d outputs from %d to %d rank %d. OutLit == -1Vec_Wec_t *Gia_PolynBuildNew(Gia_Man_t *, Vec_Wec_t *, Vec_Int_t *, int, Vec_Int_t *, Vec_Int_t *, int, int, int)Out %d : Negative Value = %d Out %d : Positive Value = %d Determined the number of extra outputs to be %d. Abc_AbsInt(p->pArray[i-1]) > Abc_AbsInt(p->pArray[i])void Vec_IntCheckUniqueOrderAbs(Vec_Int_t *)p->pArray[i-1] < p->pArray[i]void Vec_IntCheckUniqueOrder(Vec_Int_t *)Vec_IntSize(vTempC) > 0int Gia_PolynBuildAdd(Hsh_VecMan_t *, Hsh_VecMan_t *, Vec_Int_t *, Vec_Wec_t *, Vec_Int_t *, Vec_Int_t *)Vec_IntSize(vTempM) > 0New != 0void Gia_PolynMergeConstOne(Vec_Int_t *, int)Entry != p->pArray[i]void Vec_IntPushOrderAbs(Vec_Int_t *, int)int Gia_PolynHandleOne(Hsh_VecMan_t *, Hsh_VecMan_t *, Vec_Int_t *, Vec_Wec_t *, Vec_Int_t *, Vec_Int_t *, int, int, int, int)QCanont parse the output signatures.iBox >= 0src/proof/acec/acecPool.cint Acec_ManCheckCarryMap(Gia_Man_t *, int, Vec_Int_t *, Vec_Int_t *)Vec_BitEntry(vIsCarryRoot, CarryRoot)Vec_Wec_t *Acec_ManCollectCarryRootSets(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Vec_WecSize(vBoxSets) % 5 == 0Vec_Wec_t *Acec_ManCollectBoxSets(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *)%2d=%2d Detected %d full-adders and %d half-adders. Found %d XOR-cuts. Detected %d adder-tree%s. Tree %3d : Xor = %4d Root = %4d Adder = %4d In = %4d Out = %4d Ins: Outs: Detected %d topmost adder%s. Adder %5d : Tree with %5d nodes. src/proof/acec/acecCover.cvoid Gia_AcecMark_rec(Gia_Man_t *, int, int)p->pMuxes != NULLvoid Gia_AcecExplore(Gia_Man_t *, int)Xor = %d. Fanin0 = %d. Fanin1 = %d. Fan00 = %d. Fan01 = %d. Fan10 = %d. Fan11 = %d. Collected XORs: Node %5d : Supp = %5d. Cone = %5d. Fadds = %d. Hadds = %d. Root nodes found = %d. fComplDiff == (Gia_ObjFaninC0(Gia_ObjFanin1(pObj)) ^ Gia_ObjFaninC1(Gia_ObjFanin1(pObj)))src/proof/acec/acecFadds.cVec_Int_t *Gia_ManDetectHalfAdders(Gia_Man_t *, int)Found %d half-adders with XOR gates: %3d : %5d %5d -> %5d %5d Box %4d [%d x %d] : Input obj IDs = Output obj IDs = curCi == Gia_ManCiNum(p)void Gia_ManIllustrateBoxes(Gia_Man_t *)curCo == Gia_ManCoNum(p)int Dtc_ManCutMergeOne(int *, int *, int *)int Dtc_ObjComputeTruth_rec(Gia_Obj_t *)Value == 3 || Value == 0void Dtc_ManCutMerge(Gia_Man_t *, int, int *, int *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Nodes = %d. Cuts = %d. Cuts/Node = %.2f. Ints/Node = %.2f. Vec_IntSize(vCutsXor) % 4 == 0Vec_Int_t *Dtc_ManFindCommonCuts(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *)Vec_IntSize(vCutsMaj) % 4 == 0Vec_IntSize(vFadds) % 5 == 0XOR3 cuts = %d. MAJ cuts = %d. Full-adders = %d. Vec_IntEntry(vMap, iMaj) >= 0int Gia_ManFindChains_rec(Gia_Man_t *, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Gia_ObjIsAnd(Gia_ManObj(p, iMaj))!Gia_ObjIsTravIdCurrentId(p, Vec_IntEntry(vFadds, 5*iFadd+3))Vec_Wec_t *Gia_ManCollectTopmost(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, int)!Gia_ObjIsTravIdCurrentId(p, Vec_IntEntry(vFadds, 5*iFadd+4))Chain %4d : %4d Total chains = %d. Total full-adders = %d. Vec_IntSize(vChain) > 0Vec_Int_t *Gia_ManFindMapping(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Wec_t *)Vec_IntEntry(vMap2Chain, Vec_IntEntry(vFadds, 5*iFadd+3)) == -1Vec_IntEntry(vMap2Chain, Vec_IntEntry(vFadds, 5*iFadd+4)) == -1Vec_Int_t *Gia_ManCollectTruthTables(Gia_Man_t *, Vec_Int_t *)Type == 2curPi == Tim_ManCiNum(pMan)Tim_Man_t *Gia_ManGenerateTim(int, int, int, int, int)curPo == Tim_ManCoNum(pMan)nIns < 16 && nOuts < 16Gia_Man_t *Gia_ManGenerateExtraAig(int, int, int)pLits[k] >= 0void Gia_ManDupFadd(Gia_Man_t *, Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Wec_t *, Vec_Int_t *, Vec_Int_t *)iMajTruth == 0xE8 || iMajTruth == 0x17iXorTruth == 0x96 || iXorTruth == 0x69iFadd == Vec_IntEntryLast(vChain)void Gia_ManDupWithFaddBoxes_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, Vec_Int_t *, Vec_Wec_t *, Vec_Int_t *, Vec_Int_t *)Gia_Man_t *Gia_ManDupWithNaturalBoxes(Gia_Man_t *, int, int)Carry-chain detection time!Gia_ManHasDangling(pNew)nBoxes == (Gia_ManCoNum(pNew) - Gia_ManCoNum(p)) / 3AIG with boxes construction time!pObj->fMark0 && !pObj->fMark1Gia_Man_t *Gia_ManDupWithArtificalFaddBoxes(Gia_Man_t *, int, int)!pObj->fMark0 || !pObj->fMark1Gia_ObjFanin0(pObj)->fPhase == 0Gia_ObjFanin1(pObj)->fPhase == 0pObj->fMark0 != pObj->fMark1iCiLit >= 0 && iOtherLit >= 0iBox < Gia_ManBoxNum(p)int Gia_ManFindAnnotatedDelay(Gia_Man_t *, int, int *, int)Id < iint Gia_ManFindPath(Gia_Man_t *, int, int, int, Vec_Int_t *)!Gia_ObjIsUsed(pObj)p->vLevels == NULLint Gia_ManIteratePaths(Gia_Man_t *, int, int, int, int, int, int)Running path detection: BoxDelay = %d, PathMin = %d, PathMax = %d, PathLimit = %d. Iter %5d : Paths = %2d. Boxes = %2d. Total boxes = %6d. Max delay = %5d. Skipping other FADDs.Warning: Sequential design is coverted into combinational one by adding white boxes.Currently natural carry-chains cannot be detected when boxes are present.src/proof/acec/acecMult.cword Extra_TruthCanonNPN3(word, int, Vec_Wrd_t *)Members = %d. Skipping %d. Obj = %3d Occurs = %3d Ranks = %3d Leaf = %4d : Supp = %2d %d=%d(%.2f) Collected %d pps. Collected %d pps and %d nodes. """"""""DDDDDDDD 00000000UUUUUUUU33333333""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333Vec_IntSize(vLevel) == 1src/proof/acec/acecNorm.cVec_Int_t *Acec_InsertTree(Gia_Man_t *, Vec_Wec_t *)int Acec_InsertBox_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *)pBox->vShared != NULLGia_Man_t *Acec_InsertBox(Acec_Box_t *, int)pBox->vUnique != NULLCollected %d topmost XORs Vec_IntEntry(vMap, iAnd)src/proof/acec/acecOrder.cVec_Int_t *Gia_PolynFindOrder(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, int, int)Recognizing %d => XXXOR(%d %d) Iteration %d Recognizing (%d %d) => FA(%d %d %d) Recognizing (%d %d) => HA(%d %d) Vec_IntSize(p->vOrder) == Gia_ManObjNum(pGia)src/proof/acec/acecPolyn.cPln_Man_t *Pln_ManAlloc(Gia_Man_t *, Vec_Int_t *)%-6d : * %dHashC = %d. HashM = %d. Total = %d. Used = %d. Vec_IntSize(p->vCoefs) == Hsh_VecSize(p->pHashM)void Gia_PolynBuildOne(Pln_Man_t *, int)Repeating entry %d Line%5d Iter%10d : Obj =%6d. Order =%6d. HashC =%6d. HashM =%10d. Total =%10d. Used =%10d. Q%2d}, // src/proof/acec/acecSt.cvoid Acec_StatsCollect(Gia_Man_t *, int)Gia_ManLutSizeMax(p) < 4iTruth < 15iTruthF < 15fi / fo%6s k < 256 Classes:Internal node %d of rank %d is not part of PPG. Detected %d suspicious leaves. Removing box %d=(%d,%d) of rank %d. src/proof/acec/acecTree.cint Acec_TreeVerifyPhaseOne_rec(Gia_Man_t *, Gia_Obj_t *)Fadd %d sum %d is wrong. Fadd %d carry %d is wrong. Hadd %d sum %d is wrong. Hadd %d carry %d is wrong. Phase of input %d=%d is mismatched in box %d=(%d,%d). The adder tree has %d internal cut points. These %d points have more than one fanout: Node %d(lev %d) has fanout %d. Node != 0void Acec_TreePhases_rec(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, int, int, Vec_Bit_t *)Node == Vec_IntEntry( vAdds, 6*iBox+4 )int Acec_TreeWhichPoint(Vec_Int_t *, int, int)Vec_BitEntry(vFound, In) == Vec_BitEntry(vFound, Out)Vec_Wec_t *Acec_TreeFindTrees(Gia_Man_t *, Vec_Int_t *, Vec_Bit_t *, int, int)Detected %d adders (%d FAs and %d HAs). Collected %d trees with %d adders in them. %4d : %2d { %s%d=(%d,%d)Processing tree %d: Ranks = %d. Adders = %d. Leaves = %d. Roots = %d. %c%dAdders:Inputs:Outputs:There is no internal fanouts.AIG does not have XORs extracted.XHx8h(XHx8h(XHx8h(Xsrc/proof/acec/acec2Mult.cvoid Sdb_StoMergeCuts(Sdb_Sto_t *, int)Vec_Int_t *Sdb_StoIterCuts(Sdb_Sto_t *)pCut[0] == 5Detected %d 5-cuts. RetValue >= 2 && RetValue <= 4pCut[0] == 4Front = %d Back = %d Sign = %d nCutSize < SDB_CUT_NO_LEAFSdb_Sto_t *Sdb_StoAlloc(Gia_Man_t *, int, int, int, int, int)nCutSize > 1 && nCutSize <= SDB_MAX_CUTSIZEnCutNum > 1 && nCutNum < SDB_MAX_CUTNUMvoid Sdb_StoRefObj(Sdb_Sto_t *, int)Running cut computation with CutSize = %d CutNum = %d: int Sdb_CutSetCutIsContainedOrder(Sdb_Cut_t *, Sdb_Cut_t *)int Sdb_CutComputeTruth(Sdb_Sto_t *, Sdb_Cut_t *, Sdb_Cut_t *, int, int, Sdb_Cut_t *, int)int Sdb_CutComputeTruth6(Sdb_Sto_t *, Sdb_Cut_t *, Sdb_Cut_t *, int, int, Sdb_Cut_t *, int)int Sdb_CutSetAddCut(Sdb_Cut_t **, int, int)int Sdb_CutSetCheckArray(Sdb_Cut_t **, int)pCut0->nLeaves <= SDB_MAX_CUTSIZEpCut0->Sign == Sdb_CutGetSign(pCut0)void Sdb_CutAddZero(Sdb_Sto_t *, int)5SψG݈'(H跲`蟎5SψG݈'仠د(H貀ڡ`P<<0ZZxHx(xHx(薎4l`D<< ff&l(4l`薲̖貌&l(j`RjHފF ff"ZZԪj`RFjH\::\t.ψ.t݈NrrN@|(H zn`:\\:.tψt.݈rNNr@|(H zn`<x{x}p%^x{x}p%^xHxHiMiMx(i+i+x(LC>loloC(+HM^%v`q? S_ 5?0Gw"wD_P'>C(+HM^%v`q<Cx{x}p^%>pCx{x}^p%qqL>Clo<LCloM̖MvLl}jo*^%j{*vff ZZ"++jo^*%v*j{:\\:.tt݈.rNNr@|(H zn`:\\:.tt.rNNr@|(H zn` _ ?O|-K/zO|-K/zii2s|9"w0?2;nc2s|93i3i2;ncYTuzeT]nP_DwUiUiYTuzT]ne:\\:.tt.rNNr>C+M^%vq:\\:.tt.rNNr>C+M^%vqP0>Cp!A^%p>Cp!A^%pqq>CLɟ D vLA>CL MMvLA ^%*!v* "++ ^%*v*!0SP5 GD" '|@z n0SP5 GD" '|@z n <<_ ZZ?|OHK(-z/|OHK(-z/ii|2s`c6"<x{x}^>lo<fvl}jo^j{vfZ:\.trN 2"02TTPD:\.trN>^>v^v0P D" < ZHK(-2`c"<0f2(9`eTHYTPfDZد<Z<ffZ\:t.Nr<Z<fΛޚfZ\:t.Nr<Z4R6<fF6VV&fZ< Z 8 X ,#6<"f0d16VJEVbQfPZD(H`\:t.Nr@|(H zn`0P D" ڀ0SP5 GD" '|@z n 0"DPʠ @@ ؠ 0"DP\:Ԅt.ԐNr\:ގ4t.&RFNrʯ,J8bXd 0"DP>(+HM^v`q:\.trN:\.trN>^v0P D̪" ? _0?"wDwP_0P3rrttUNN DU\\..::3" """"""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333UUUUUUUU33333333i < Vec_IntSize(vMove)src/proof/acec/acecXor.cVec_Int_t *Acec_OrderTreeRoots(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Xor node %d belongs to Tree %d and Tree %d. Rank == Vec_IntEntry(vRanks, Fanin)Vec_Wec_t *Acec_FindXorLeaves(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Wec_t **)Rank %2d : Lits = %5d PI = %d Booth = %5d Non-Booth = %5d Vec_WecSize(vAddBoxes) == Vec_WecSize(vXorLeaves)Acec_Box_t *Acec_FindBox(Gia_Man_t *, Vec_Int_t *, Vec_Wec_t *, Vec_Wec_t *, Vec_Int_t *)Vec_WecSize(vAddBoxes) == Vec_IntSize(vXorRoots)*** There no multiple two-input XOR cuts.Vec_PtrSize(vAigs) > 0src/proof/dch/dchAig.cAig_Man_t *Dch_DeriveTotalAig(Vec_Ptr_t *)Aig_ManCiNum(pAig) == Aig_ManCiNum(pAig2)Aig_ManCoNum(pAig) == Aig_ManCoNum(pAig2)src/proof/dch/dchChoice.cint Dch_ObjCountSupp_rec(Aig_Man_t *, Aig_Obj_t *)pRepr->Id < pObj->Idint Dch_DeriveChoiceCountReprs(Aig_Man_t *)pEquiv->Id < pObj->Idint Dch_DeriveChoiceCountEquivs(Aig_Man_t *)int Dch_ObjMarkTfi_rec(Aig_Man_t *, Aig_Obj_t *)Obj %d is not an AND but it has a repr %d. Obj %d has repr %d with a repr %d. node %d and repr %d have diff supports repr %d has final node %d participates in more than one choice class node %d belonging to choice has fanout %d node %d has representative %d and fanout count %d int Aig_ManCheckAcyclic_rec(Aig_Man_t *, Aig_Obj_t *, int)!Aig_ObjIsTravIdPrevious(p, pNode)Node "%d" is encountered twice on the following path to the COs: %d -> (choice of %d) -> CO %d int Dch_ObjCheckTfi(Aig_Man_t *, Aig_Obj_t *, Aig_Obj_t *)!Aig_IsComplement(pRepr)void Dch_DeriveChoiceAigNode(Aig_Man_t *, Aig_Man_t *, Aig_Obj_t *, int)pRepr->pData != NULLAig_ObjIsNode(pRepr)pAig->pReprs != NULLAig_Man_t *Dch_DeriveChoiceAigInt(Aig_Man_t *, int)void Aig_ObjSetRepr(Aig_Man_t *, Aig_Obj_t *, Aig_Obj_t *)Representive verification successful.Representive verification FAILED.Verification of choice AIG succeeded.Verification of choice AIG FAILED.src/proof/dch/dchClass.cDch_Cla_t *Dch_ClassesStart(Aig_Man_t *)p->pId2Class[pRepr->Id] != NULLAig_Obj_t **Dch_ClassesReadClass(Dch_Cla_t *, Aig_Obj_t *, int *)p->pClassSizes[pRepr->Id] > 1Aig_ObjRepr(p->pAig, pObj) == NULLvoid Dch_ClassesCheck(Dch_Cla_t *)Aig_ObjRepr(p->pAig, pObj) == ppClass[0]pPrev->Id < pObj->Idp->nLits == nLitsp->nCands1 == nCands1p->nClasses == nClasses%d(%d,%d) Equivalence classes: Const1 = %5d. Class = %5d. Lit = %5d. Constants { %3d (%3d) : nNodes > 1void Dch_ClassesPrepare(Dch_Cla_t *, int, int)nEntries == nEntries2Vec_PtrSize(p->vClassOld) > 0int Dch_ClassesRefineOneClass(Dch_Cla_t *, Aig_Obj_t *, int)Vec_PtrSize(vRoots) > 1void Dch_ClassesCollectOneClass(Dch_Cla_t *, Aig_Obj_t *, Vec_Ptr_t *)!Dch_ObjIsConst1Cand( pAig, pObj )src/proof/dch/dchInt.hvoid Dch_ObjSetConst1Cand(Aig_Man_t *, Aig_Obj_t *)p->pId2Class[pRepr->Id] == NULLvoid Dch_ObjAddClass(Dch_Cla_t *, Aig_Obj_t *, Aig_Obj_t **, int)p->pClassSizes[pRepr->Id] == 0pClass != NULLAig_Obj_t **Dch_ObjRemoveClass(Dch_Cla_t *, Aig_Obj_t *)!Aig_IsComplement( pNode )src/proof/dch/dchCnf.cvoid Dch_AddClausesMux(Dch_Man_t *, Aig_Obj_t *)Aig_ObjIsMuxType( pNode )!Aig_IsComplement(pNode)void Dch_AddClausesSuper(Dch_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)Aig_ObjIsNode( pNode )void Dch_CollectSuper(Aig_Obj_t *, int, Vec_Ptr_t *)!Aig_ObjIsCi(pObj)void Dch_ObjAddToFrontier(Dch_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)Dch_ObjSatNum(p,pNode)void Dch_CnfNodeAddToSolver(Dch_Man_t *, Aig_Obj_t *)STATS: Ands:%8d ->%8d. Reprs:%7d ->%7d. Choices =%7d. Parameters: Sim words = %d. Conf limit = %d. SAT var max = %d. AIG nodes : Total = %6d. Dangling = %6d. Main = %6d. (%6.2f %%) SAT solver: Vars = %d. Max cone = %d. Recycles = %d. SAT calls : All = %6d. Unsat = %6d. Sat = %6d. Fail = %6d. Choices : Lits = %6d. Reprs = %5d. Equivs = %5d. Choices = %5d. Choicing runtime statistics: Sim init Sim SAT undecidedChoice Synthesis !Aig_IsComplement(pNew)src/proof/dch/dchSat.cint Dch_NodesAreEquiv(Dch_Man_t *, Aig_Obj_t *, Aig_Obj_t *)!Aig_IsComplement(pOld)pNew != pOldEQGyU)] C k 1 g # ]  a  = WCg!i Y 7yEm!k)_=u#{7qQ!QAsE5c/Kg{src/proof/dch/dchSimSat.cvoid Dch_ManCollectTfoCands_rec(Dch_Man_t *, Aig_Obj_t *)p->pAigTotal->pFanData!Aig_IsComplement(pObjFraig)void Dch_ManResimulateSolved_rec(Dch_Man_t *, Aig_Obj_t *)RetValue1void Dch_ManResimulateCex(Dch_Man_t *, Aig_Obj_t *, Aig_Obj_t *)RetValue2void Dch_ManResimulateCex2(Dch_Man_t *, Aig_Obj_t *, Aig_Obj_t *)Aig_Regular(pObjFraig) != Aig_ManConst1(p->pAigFraig)src/proof/dch/dchSweep.cvoid Dch_ManSweepNode(Dch_Man_t *, Aig_Obj_t *)Aig_ObjRepr( p->pAigTotal, pObj ) != pObjReprAig_Obj_t *Dch_ObjChild0Fra(Aig_Obj_t *)i < p->vNodes->nSizesrc/proof/fraig/fraigApi.cFraig_Node_t *Fraig_ManReadIthNode(Fraig_Man_t *, int)!Fraig_IsComplement(p)Fraig_Node_t *Fraig_NodeReadOne(Fraig_Node_t *)Fraig_Node_t *Fraig_NodeReadTwo(Fraig_Node_t *)!Fraig_IsComplement(p1)int Fraig_NodeComparePhase(Fraig_Node_t *, Fraig_Node_t *)!Fraig_IsComplement(p2)Requesting a PI with a negative numberpNodeOld->pRepr == 0src/proof/fraig/fraigCanon.cFraig_Node_t *Fraig_NodeAndCanon(Fraig_Man_t *, Fraig_Node_t *, Fraig_Node_t *)pMan->fDoSparsepNodeNew->pRepr == 0!Fraig_IsComplement(pFanin)src/proof/fraig/fraigFanout.cvoid Fraig_NodeAddFaninFanout(Fraig_Node_t *, Fraig_Node_t *)!Fraig_IsComplement(pFanout)Fraig_Regular(pFanout->p1) == pFanin || Fraig_Regular(pFanout->p2) == pFaninFraig_Regular(pPivot->p2) == pFaninpNodeTo->pFanPivot == NULLvoid Fraig_NodeTransferFanout(Fraig_Node_t *, Fraig_Node_t *)pNodeTo->pFanFanin1 == NULLpNodeTo->pFanFanin2 == NULLp->iWordStart + nWords <= p->nWordsDynasrc/proof/fraig/fraigFeed.cvoid Fraig_FeedBack(Fraig_Man_t *, int *, Msat_IntVec_t *, Fraig_Node_t *, Fraig_Node_t *)p->iWordPerm == FRAIG_NUM_WORDS( p->iPatsPerm )int Fraig_FeedBackCompress(Fraig_Man_t *)Fraig_ManSimulateBitNode( p, pNode, pModel )int *Fraig_ManSaveCounterExample(Fraig_Man_t *, Fraig_Node_t *)Nodes %d and %d have the same D simulation info. uSignOld == pNode->uHashRvoid Fraig_ReallocateSimulationInfo(Fraig_Man_t *)uSignOld == pNode->uHashD@?A@BcFraiging enabled: %s Rewriting enabled: %s BDD construction enabled: %s Verbose output enabled: %s Solver iterations: %d Starting mitering limit: %d Multiplicative coeficient for mitering: %.2f Starting number of rewriting iterations: %d Multiplicative coeficient for rewriting: %.2f Starting number of conflicts in fraiging: %.2f Multiplicative coeficient for fraiging: %.2f BDD size limit for bailing out: %d BDD reordering enabled: %s Last-gasp mitering limit: %d Total conflict limit: %d Total inspection limit: %d p->pSat == NULLsrc/proof/fraig/fraigMan.cvoid Fraig_ManCreateSolver(Fraig_Man_t *)Words: Random = %d. Dynamic = %d. Used = %d. Memory = %0.2f MB. Proof = %d. Counter-example = %d. Fail = %d. FailReal = %d. Zero = %d. Nodes: Final = %d. Total = %d. Mux = %d. (Exor = %d.) ClaVars = %d. AIG simulation %6.2f sec AIG traversal Solver feedback SAT solving Network update TOTAL RUNTIME time4Fraig_NodeVec_t *Fraig_UtilInfoAlloc(int, int, int)i == pNode->NumFraig_NodeVec_t *Fraig_ManGetSimInfo(Fraig_Man_t *)pNode1 != pNode2int Fraig_ManCheckClauseUsingSimInfo(Fraig_Man_t *, Fraig_Node_t *, Fraig_Node_t *)void Fraig_ManAddClause(Fraig_Man_t *, Fraig_Node_t **, int)CEC enging parameters:Parameter dump complete.src/proof/fraig/fraigMem.cchar *Fraig_MemFixedEntryFetch(Fraig_MemFixed_t *)pNodeRes == NULLsrc/proof/fraig/fraigNode.cFraig_Node_t *Fraig_NodeCreatePi(Fraig_Man_t *)!Fraig_IsComplement(pNode)void Fraig_NodeSimulate(Fraig_Node_t *, int, int, int) ףp= ?(%d)(%d,%d):!Fraig_IsComplement(pNew)src/proof/fraig/fraigSat.cint Fraig_NodeIsEquivalent(Fraig_Man_t *, Fraig_Node_t *, Fraig_Node_t *, int, int)!Fraig_IsComplement(pOld)int Fraig_NodeIsImplication(Fraig_Man_t *, Fraig_Node_t *, Fraig_Node_t *, int)pNode1R != pNode2Rint Fraig_ManCheckClauseUsingSat(Fraig_Man_t *, Fraig_Node_t *, Fraig_Node_t *, int)pOld != pNewvoid Fraig_OrderVariables(Fraig_Man_t *, Fraig_Node_t *, Fraig_Node_t *)pNode->fClauses == 0pNode->vFanins->nSize > 1!Fraig_IsComplement( pNode )void Fraig_SupergateAddClausesMux(Fraig_Man_t *, Fraig_Node_t *)Fraig_NodeIsMuxType( pNode )Fraig_NodeIsAnd( pNode )void Fraig_SupergateAddClauses(Fraig_Man_t *, Fraig_Node_t *, Fraig_NodeVec_t *)Var1 < nVars!Fraig_IsComplement(pNode1)src/proof/fraig/fraigTable.cint Fraig_CompareSimInfo(Fraig_Node_t *, Fraig_Node_t *, int, int)!Fraig_IsComplement(pNode2)int Fraig_FindFirstDiff(Fraig_Node_t *, Fraig_Node_t *, int, int, int)int Fraig_CompareSimInfoUnderMask(Fraig_Node_t *, Fraig_Node_t *, int, int, unsigned int *)void Fraig_CollectXors(Fraig_Node_t *, Fraig_Node_t *, int, int, unsigned int *)Structural table. Table size = %d. Number of entries = %d. {%d} Functional table. Table size = %d. Number of entries = %d. Zero-node table. Table size = %d. Number of entries = %d. Counter == pT->nEntriesint Fraig_TableRehashF0(Fraig_Man_t *, int)void Fraig_TableResizeS(Fraig_HashTable_t *)void Fraig_TableResizeF(Fraig_HashTable_t *, int)src/proof/fraig/fraigUtil.cint Fraig_CheckTfi(Fraig_Man_t *, Fraig_Node_t *, Fraig_Node_t *)Internal node %d has first fanin %d that is a secondary node. Internal node %d has second fanin %d that is a secondary node. %3d : PI %3d : %c%3d %c%3d int Fraig_MappingUpdateLevel_rec(Fraig_Man_t *, Fraig_Node_t *, int)pNode1->Num < pNode2->Numint Fraig_NodeIsExorType(Fraig_Node_t *)int Fraig_NodeIsMuxType(Fraig_Node_t *)int Fraig_NodeIsExor(Fraig_Node_t *)Fraig_NodeIsExorType(pNode)Fraig_IsComplement(pNode->p1)Fraig_Node_t *Fraig_NodeRecognizeMux(Fraig_Node_t *, Fraig_Node_t **, Fraig_Node_t **)Fraig_NodeIsMuxType(pNode)Total nodes = %d. Referenced nodes = %d. Number of candidate pairs = %d. Proved = %d. void Fraig_Dfs_rec(Fraig_Man_t *, Fraig_Node_t *, Fraig_NodeVec_t *, int)src/proof/fraig/fraigVec.cvoid Fraig_NodeVecShrink(Fraig_NodeVec_t *, int)void Fraig_NodeVecRemove(Fraig_NodeVec_t *, Fraig_Node_t *)void Fraig_NodeVecWriteEntry(Fraig_NodeVec_t *, int, Fraig_Node_t *)Fraig_Node_t *Fraig_NodeVecReadEntry(Fraig_NodeVec_t *, int)p->nFramesAll == 1src/proof/fra/fraBmc.cvoid Fra_BmcFilterImplications(Fra_Man_t *, Fra_Bmc_t *)p->pManAig == pBmc->pAigFramesk == Aig_ManRegNum(p->pAig)Aig_Man_t *Fra_BmcFrames(Fra_Bmc_t *, int)p->pBmc == NULLvoid Fra_BmcPerform(Fra_Man_t *, int, int)Original AIG = %d. Init %d frames = %d. Fraig = %d. Before BMC: Const = %5d. Class = %5d. Lit = %5d. Imp = %5d. After BMC: Fraiged init frames: Node = %6d. Lev = %5d. Aig_Obj_t *Bmc_ObjChild0Frames(Aig_Obj_t *, int)Aig_ManRegNum(pMan) == 0src/proof/fra/fraCec.cint Fra_FraigSat(Aig_Man_t *, ABC_INT64_T, ABC_INT64_T, int, int, int, int, int, int, int)Created SAT problem with %d variable and %d clauses. Original miter: Nodes = %6d. Initial SAT: Nodes = %6d. Rewriting: Nodes = %6d. Balance-X: Nodes = %6d. Fraiging (i=%d): Nodes = %6d. Final SAT: Nodes = %6d. Timed out after verifying %d partitions (out of %d). int Fra_FraigCecTop(Aig_Man_t *, Aig_Man_t *, int, int, int, int)Aig_ManNodeNum(pMan1) >= Aig_ManNodeNum(pMan2)p->pAig->pReprs[i] == NULLsrc/proof/fra/fraClass.cvoid Fra_ClassesCopyReprs(Fra_Cla_t *, Vec_Ptr_t *)int Fra_ClassesCountLits(Fra_Cla_t *)int Fra_ClassesCountPairs(Fra_Cla_t *)Fra_ClassObjRepr(pTemp) == pClass[0]void Fra_PrintClass(Fra_Cla_t *, Aig_Obj_t **)Fra_ClassObjRepr(pObj) == Aig_ManConst1(p->pAig)void Fra_ClassesPrint(Fra_Cla_t *, int)void Fra_ClassesPrepare(Fra_Cla_t *, int, int)ppTable[i]->fMarkA == 0ppClass[0] != NULL && ppClass[1] != NULLAig_Obj_t **Fra_RefineClassOne(Fra_Cla_t *, Aig_Obj_t **)pClass2[0] != NULLint Fra_RefineClassLastIter(Fra_Cla_t *, Vec_Ptr_t *)int Fra_ClassesRefine(Fra_Cla_t *)Vec_PtrEntry(p->vClasses1,0) != Aig_ManConst1(p->pAig)int Fra_ClassesRefine1(Fra_Cla_t *, int, int *)ppClass[0] != NULLId1 < Id2void Fra_ClassesTest(Fra_Cla_t *, int, int)Before: Const = %6d. Class = %6d. After: Const = %6d. Class = %6d. Aig_ManRegNum(p->pAig) > 0Aig_Man_t *Fra_ClassesDeriveAig(Fra_Cla_t *, int)Aig_ManRegNum(p->pAig) < Aig_ManCiNum(p->pAig)Aig_ManCoNum(pManFraig) % nFramesAll == 0Assert miters = %6d. Output miters = %6d. pObjRepr->Id < pObj->Idvoid Fra_ClassesDeriveNode(Aig_Man_t *, Aig_Obj_t *, Aig_Obj_t **)Classes are not cleared!Vec_IntSize(vSatVarsFrom) == Vec_IntSize(vSatVarsTo)src/proof/fra/fraClau.cint *Fra_ClauCreateMapping(Vec_Int_t *, Vec_Int_t *, int)Aig_ManCoNum(pMan) - Aig_ManRegNum(pMan) == 1Cla_Man_t *Fra_ClauStart(Aig_Man_t *)Aig_ManCoNum(pFramesMain) == 2Aig_ManCoNum(pFramesTest) == Aig_ManRegNum(pMan)Aig_ManCoNum(pFramesBmc) == Aig_ManRegNum(pMan)Vec_IntSize(p->vSatVarsTestCs) == Vec_IntSize(p->vSatVarsMainCs)Vec_IntSize(p->vSatVarsTestCs) == Vec_IntSize(p->vSatVarsBmcNs)RetValue == l_Trueint Fra_ClauCheckProperty(Cla_Man_t *, Vec_Int_t *)int Fra_ClauCheckBmc(Cla_Man_t *, Vec_Int_t *)pMap[lit_var(iLit)] >= 0void Fra_ClauRemapClause(int *, Vec_Int_t *, Vec_Int_t *, int)int Fra_ClauCheckClause(Cla_Man_t *, Vec_Int_t *, Vec_Int_t *)Vec_IntSize(vMain) <= Vec_IntSize(vNew)void Fra_ClauReduceClause(Vec_Int_t *, Vec_Int_t *)i == Vec_IntSize(vMain)Vec_IntSize(vCex) <= Vec_IntSize(vSatCsVars)void Fra_ClauPrintClause(Vec_Int_t *, Vec_Int_t *)i == Vec_IntSize(vCex)int Fra_Clau(Aig_Man_t *, int, int, int) Property is proved after %d iterations. Reducing failed after %d iterations (BMC failed). Reducing failed after %d iterations (nothing left). LitsInd = %3d. Vec_IntSize(p->vCexMain) > 0 LitsRed = %3d. p->pSatMain->qtail == p->pSatMain->qheadProperty is not proved after %d iterations. void sat_solver_act_var_clear(sat_solver *)Vec_IntSize(vVec) > 1Vec_Int_t *Vec_IntSplitHalf(Vec_Int_t *)The property is trivially inductive.@ @ >src/proof/fra/fraClaus.cint Fra_ClausRunSat(Clu_Man_t *)pCut->nLeaves > 1 && pCut->nLeaves < 5int Fra_ClausProcessClausesCut(Clu_Man_t *, Fra_Sml_t *, Dar_Cut_t *, int *)nWordsForSim % 8 == 0int Fra_ClausProcessClausesCut2(Clu_Man_t *, Fra_Sml_t *, Dar_Cut_t *, int *)pCut->nFanins > 1 && pCut->nFanins < 17void Fra_ClausProcessClausesCut3(Clu_Man_t *, Fra_Sml_t *, Aig_Cut_t *, int *)Vec_IntSize(p->vClauses) > p->nClausesMaxint Fra_ClausSelectClauses(Clu_Man_t *)Cost < CostMaxpCostCount[0] == 0pCostCount[c] >= 0Selected %d clauses. Cost range: [%d < %d < %d] Collected %d register constants and %d one-hotness implications. Sim-seqLat-claCuts InfoseqSim-cmbInfocmbNode = %5d. Non-triv cuts = %7d. Clauses = %6d. Clause per cut = %6.2f. p->nLutSize < 13int Fra_ClausProcessClauses2(Clu_Man_t *, int)Node = %5d. Cuts = %7d. Clauses = %6d. Clause/cut = %6.2f. Processing sim-info to find candidate clauses (unoptimized)p->nClauses == 0End - Beg <= p->nLutSizeEnd == Vec_IntSize(p->vLitsProven)Vec_IntEntry( p->vCosts, i ) >= 0End == Vec_IntSize(p->vLits)Already proved clauses filtered out %d candidate clauses (out of %d). Vec_IntEntry( p->vCosts, i ) > 0int Fra_ClausBmcClauses(Clu_Man_t *)p->pSatBmc->qtail == p->pSatBmc->qheadp->pCnf->nVars <= Vec_PtrSize(p->vCexes)void Fra_ClausSimInfoClean(Clu_Man_t *)p->nCexes == p->nCexesAllocvoid Fra_ClausSimInfoRealloc(Clu_Man_t *)p->nCexes < p->nCexesAllocvoid Fra_ClausSimInfoRecord(Clu_Man_t *, int *)Abc_InfoHasBit( (unsigned *)Vec_PtrEntry(p->vCexes, i), p->nCexes ) == 0iVar > 0 && iVar < p->pCnf->nVarsint Fra_ClausSimInfoCheck(Clu_Man_t *, int *, int)int Fra_ClausInductiveClauses(Clu_Man_t *) Property holds. Property fails. void Fra_ClausAddToStorage(Clu_Man_t *)Added to storage %d proved clauses (including %d one-hot clauses) SUMMARY: Total proved clauses = %d. Clause per lit: >7=%d Aig_Obj_t *Fra_ClausGetLiteral(Clu_Man_t *, int *, int)p->pCnf->pVarNums[i] < p->pCnf->nVarsvoid Fra_ClausWriteIndClauses(Clu_Man_t *)_care.aigCare one-hotness clauses will be written into file "%s". void Fra_ClausEstimateCoverage(Clu_Man_t *)Aig_ManCoNum(p->pAig) > 2Care states ratio = %f. (%d out of %d patterns) PARAMETERS: Frames = %d. Pref = %d. Clauses max = %d. Cut size = %d. Level max = %d. Cuts max = %d. Batches = %d. Increment cut size = %s. !p->fTarget || Aig_ManCoNum(pAig) - Aig_ManRegNum(pAig) == 1int Fra_Claus(Aig_Man_t *, int, int, int, int, int, int, int, int, int, int, int, int, int)Problem fails the base case after %d frame expansion. *** BATCH %d: Using %d-cuts. BMC disproved %d clauses. Iter %3d : Begin = %5d. End = %5d. Exs = %5d. Fra_Claus(): Internal error. Property FAILS during refinement. Property HOLDS inductively after strengthening. Time Finished proving inductive clauses. Property failed after sequential simulation!Error: Solver is UNSAT after adding assumption clauses.Problem is inductive without strengthening.Error: Main solver is unsat.Error: BMC solver is unsat.src/proof/fra/fraCnf.cvoid Fra_AddClausesMux(Fra_Man_t *, Aig_Obj_t *)void Fra_AddClausesSuper(Fra_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)Vec_Ptr_t *Fra_CollectSuper(Aig_Obj_t *, int)void Fra_ObjAddToFrontier(Fra_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)Fra_ObjFaninVec(pObj) == NULLpOld || pNewvoid Fra_CnfNodeAddToSolver(Fra_Man_t *, Aig_Obj_t *, Aig_Obj_t *)Fra_ObjSatNum(pNode)Fra_ObjFaninVec(pNode) == NULLAig_ManCiNum(p->pManAig) == Vec_IntSize(vCex)src/proof/fra/fraCore.cvoid Fra_FraigVerifyCounterEx(Fra_Man_t *, Vec_Int_t *)The node %d is not constant under cex! The nodes %d and %d are not equal under cex! void Fra_FraigNode(Fra_Man_t *, Aig_Obj_t *)p->pPars->nFramesK || Aig_Regular(pObjFraig) != Aig_ManConst1(p->pManFraig)p->pPars->nFramesK || Fra_ClassObjRepr(pObj) != pObjReprsrc/proof/fra/fra.hAig_Obj_t *Fra_ObjChild0Fra(Aig_Obj_t *, int)Fra_FraigNode(): Error in class refinement!>src/proof/fra/fraHot.cint Fra_OneHotNodesAreClause(Fra_Sml_t *, Aig_Obj_t *, Aig_Obj_t *, int, int)pSim->pAig == p->pManAigVec_Int_t *Fra_OneHotCompute(Fra_Man_t *, Fra_Sml_t *)i-nTruePis >= 0k-nTruePis >= 0p->pPars->nFramesK == 1void Fra_OneHotAssume(Fra_Man_t *, Vec_Int_t *)Vec_IntEntry(vOneHots, i) == 0void Fra_OneHotCheck(Fra_Man_t *, Vec_Int_t *)p->pSml->pAig == p->pManAigint Fra_OneHotRefineUsingCex(Fra_Man_t *, Vec_Int_t *)void Fra_OneHotEstimateCoverage(Fra_Man_t *, Vec_Int_t *)Fra_OneHotAssume(): Adding clause makes SAT solver unsat.Fra_OneHotCheck(): Clause is not refined!Fra_OneHotAddKnownConstraint(): Adding clause makes SAT solver unsat.p->nWordsTotal > 0src/proof/fra/fraImp.cVec_Ptr_t *Fra_SmlSortUsingOnes(Fra_Sml_t *, int)pnBits[i] <= nBitsnTotal == nNodes + nBits + 1Vec_IntSize(vImps) >= nImpLimitVec_Int_t *Fra_SmlSelectMaxCost(Vec_Int_t *, int *, int, int, int *)pCosts[i] <= nCostMaxAig_ManObjNumMax(p->pManAig) < (1 << 15)Vec_Int_t *Fra_ImpDerive(Fra_Man_t *, int, int, int)nImpMaxLimit > 0 && nImpUseLimit > 0 && nImpUseLimit <= nImpMaxLimitImplications: All = %d. Try = %d. NonSeq = %d. Comb = %d. Res = %d. Implication weight: Min = %d. Pivot = %d. Max = %d. Left > 0 && Left < p->nSatVarsvoid Fra_ImpAddToSolver(Fra_Man_t *, Vec_Int_t *, int *)Right > 0 && Right < p->nSatVarsMax >= pNode->Idint Fra_ImpCheckForNode(Fra_Man_t *, Vec_Int_t *, Aig_Obj_t *, int)Vec_IntEntry(vImps, i) == 0pResult[0] == 0double Fra_ImpComputeStateSpaceRatio(Fra_Man_t *)Fra_ImpCheckForNode(): Implication is not refined!p->pManFraig->nRegs == pTemp->nRegssrc/proof/fra/fraInd.cvoid Fra_FraigInductionRewrite(Fra_Man_t *)p->pManFraig->nAsserts == pTemp->nAssertsAig_ManRegNum(p->pManAig) == Aig_ManCoNum(pTemp) - pTemp->nAssertsp->pManFraig == NULLAig_Man_t *Fra_FramesWithClasses(Fra_Man_t *)Aig_ManRegNum(p->pManAig) > 0Aig_ManRegNum(p->pManAig) < Aig_ManCiNum(p->pManAig)%3d : Reg = %4d. PI = %4d. (True = %4d. Regs = %4d.) And = %5d. It = %3d. Cl = %5d. Aig_ManRegNum(pManAig) > 0Aig_Man_t *Fra_FraigInduction(Aig_Man_t *, Fra_Ssw_t *)pParams->nFramesK > 0!(pPars->nFramesP > 0 && pPars->fUse1Hot)!(pPars->nFramesK > 1 && pPars->fUse1Hot)Simulating %d AIG nodes for %d cycles ... p->pSat != NULL%3d : C = %6d. Cl = %6d. L = %6d. LR = %6d. I = %6d. 1h = %6d. NR = %6d. p->vTimeouts == NULLOriginal AIG: Reduced AIG: .pairs%d %d %c Result: %d pairs of seq equiv nodes are written into file "%s". void Fra_FramesConstrainNode(Aig_Man_t *, Aig_Obj_t *, int)Aig_ObjPhaseReal(pMiter) == 1Fra_FraigInduction(): Internal error. The result may not verify.Fra_FraigInduction(): Adding implicationsn to CNF led to a conflict.Fra_FraigInduction(): Runtime limit exceeded.Partitioning was disabled to allow implication writing.pSat->size == 2 * pCnf->nVarssrc/proof/fra/fraIndVer.cint Fra_InvariantVerify(Aig_Man_t *, int, Vec_Int_t *, Vec_Int_t *)pSat->qtail == pSat->qheadInvariant verification: %d clauses (out of %d) FAILED the base case. Invariant verification: %d clauses (out of %d) FAILED the inductive case. Invariant verification: %d clauses verified correctly. Invariant verification: SAT solver is unsat after adding a clause.Invariant verification: Can only verify for K = 1Iterations = %d. LitBeg = %d. LitEnd = %d. (%6.2f %%). AIG partitioningAIG rebuiding FRAIGing AIG updating Aig_ObjIsCi(pObj0)src/proof/fra/fraLcr.cint Fra_LcrNodesAreEqual(Aig_Obj_t *, Aig_Obj_t *)Aig_ObjIsCi(pObj1)int Fra_LcrNodeIsConst(Aig_Obj_t *)Aig_ObjIsCi(ppClass[c])Aig_Man_t *Fra_LcrDeriveAigForPartitioning(Fra_Lcr_t *)Aig_Obj_t *Fra_LcrCreatePart_rec(Fra_Cla_t *, Aig_Man_t *, Aig_Man_t *, Aig_Obj_t *)Aig_Man_t *Fra_FraigLatchCorrespondence(Aig_Man_t *, int, int, int, int, int *, float)Simulating AIG with %d nodes for %d cycles ... Partitioning AIG ... %3d : Const = %6d. Class = %6d. L = %6d. Part = %3d. Fra_FraigLatchCorrespondence(): Runtime limit exceeded.333333?$@d  src/proof/fra/fraMan.cAig_Man_t *Fra_ManPrepareComb(Fra_Man_t *)SimWord = %d. Round = %d. Mem = %0.2f MB. LitBeg = %d. LitEnd = %d. (%6.2f %%). Proof = %d. Cex = %d. Fail = %d. FailReal = %d. C-lim = %d. ImpRatio = %6.2f %% AIG rewriting Unsat Sat Fail Class refining time1 Speculations = %d. Inverse S = %5d. SNew = %5d. R = %7.2f. Over = %5d. Quant = %5d. ScanningPIs = %6d. POs = %6d. Lim = %3d. AveS = %3d. SN = %3d. R = %4.2f Max = %5d. Extension ffffff?src/proof/fra/fraSat.cint Fra_NodesAreEquiv(Fra_Man_t *, Aig_Obj_t *, Aig_Obj_t *)int Fra_NodesAreImp(Fra_Man_t *, Aig_Obj_t *, Aig_Obj_t *, int, int)int Fra_NodesAreClause(Fra_Man_t *, Aig_Obj_t *, Aig_Obj_t *, int, int)int Fra_NodeIsConst(Fra_Man_t *, Aig_Obj_t *)pNew != p->pManFraig->pConst1int Fra_SetActivityFactors_rec(Fra_Man_t *, Aig_Obj_t *, int, int)Fra_ObjSatNum(pObj)int Fra_SetActivityFactors(Fra_Man_t *, Aig_Obj_t *, Aig_Obj_t *)p->pPars->dActConeRatio > 0 && p->pPars->dActConeRatio < 1@KL'POriginal miter: Latches = %5d. Nodes = %6d. Sequential cleanup: Latches = %5d. Nodes = %6d. Phase abstraction: Latches = %5d. Nodes = %6d. Forward retiming: Latches = %5d. Nodes = %6d. Networks are NOT EQUIVALENT after simulation. Latch-corr (I=%3d): Latches = %5d. Nodes = %6d. Fraiging: Latches = %5d. Nodes = %6d. Min-reg retiming: Latches = %5d. Nodes = %6d. Global conflict limit (%d) exceeded. K-step (K=%2d,I=%3d): Latches = %5d. Nodes = %6d. Rewriting: Latches = %5d. Nodes = %6d. Seq simulation : Latches = %5d. Nodes = %6d. Property proved using interpolation. Property DISPROVED in frame %d using interpolation. Property UNDECIDED after interpolation. src/proof/fra/fraSec.cint Fra_FraigSec(Aig_Man_t *, Fra_Sec_t *, Aig_Man_t **)Networks are UNDECIDED. SOLUTION: UNDECIDED The unsolved reduced miter is written into file "%s". Fra_FraigSec(): Counter-example verification has FAILED.The counter-example is invalid because of phase abstraction.EQGyU)] C k 1 g # ]  a  = WCg!i Y 7yEm!k)_=u#{7qQ!QAsE5c/Kg{i < p->pSml->nWordsTotalsrc/proof/fra/fraSim.cvoid Fra_SmlCheckOutputSavePattern(Fra_Man_t *, Aig_Obj_t *)k < 32p->pManFraig->pData == NULLAig_ObjFanin0(pObj)->fPhase == (unsigned)Aig_ObjFaninC0(pObj)int Fra_SmlCheckOutput(Fra_Man_t *)void Fra_SmlAssignRandom(Fra_Sml_t *, Aig_Obj_t *)void Fra_SmlAssignConst(Fra_Sml_t *, Aig_Obj_t *, int, int)void Fra_SmlInitialize(Fra_Sml_t *, int)p->nFrames > 0void Fra_SmlAssignDist1(Fra_Sml_t *, unsigned int *)void Fra_SmlNodeSimulate(Fra_Sml_t *, Aig_Obj_t *, int)iFrame == 0 || p->nWordsFrame < p->nWordsTotal!Aig_IsComplement(pObj0)int Fra_SmlNodesCompareInFrame(Fra_Sml_t *, Aig_Obj_t *, Aig_Obj_t *, int, int)!Aig_IsComplement(pObj1)iFrame0 == 0 || p->nWordsFrame < p->nWordsTotaliFrame1 == 0 || p->nWordsFrame < p->nWordsTotalvoid Fra_SmlNodeCopyFanin(Fra_Sml_t *, Aig_Obj_t *, int)!Aig_IsComplement(pOut)void Fra_SmlNodeTransferNext(Fra_Sml_t *, Aig_Obj_t *, Aig_Obj_t *, int)!Aig_IsComplement(pIn)Aig_ObjIsCo(pOut)Aig_ObjIsCi(pIn)!fInit || Aig_ManRegNum(p->pManAig)void Fra_SmlSimulate(Fra_Man_t *, int)Cannot open file "%s" with simulation patterns. File "%s" contains symbol (%c) other than '0' or '1'. Aig_ManRegNum(p->pAig) == 0void Fra_SmlInitializeGiven(Fra_Sml_t *, Vec_Str_t *)Vec_StrSize(vSimInfo) % Aig_ManCiNum(p->pAig) == 0nPats <= nPatsPaddedFra_Sml_t *Fra_SmlSimulateCombGiven(Aig_Man_t *, char *, int, int)File "%s": The number of binary digits (%d) is not divisible by the number of primary inputs (%d). p->fNonConstOutAbc_Cex_t *Fra_SmlGetCounterExample(Fra_Sml_t *)iPo < Aig_ManCoNum(p->pAig)-Aig_ManRegNum(p->pAig)iFrame < p->nFramesiBit < 32 * p->nWordsFrameAbc_Cex_t *Fra_SmlCopyCounterExample(Aig_Man_t *, Aig_Man_t *, int *)nTruePis * nFrames == Aig_ManCiNum(pFrames)nTruePos * nFrames == Aig_ManCoNum(pFrames)Error: A counter-example did not refine classes!Fra_SmlGetCounterExample(): Counter-example is invalid.p->pFrames == NULLsrc/proof/ssw/sswAig.cAig_Man_t *Ssw_FramesWithClasses(Ssw_Man_t *)p->vInits == NULL || Vec_IntSize(p->vInits) == iLits + Saig_ManPiNum(p->pAig)pFrames->pData == NULLAig_Man_t *Ssw_SpeculativeReduction(Ssw_Man_t *)void Ssw_FramesConstrainNode(Ssw_Man_t *, Aig_Man_t *, Aig_Man_t *, Aig_Obj_t *, int, int)pObjNew != Aig_Not(pObjReprNew)pObjNew != pObjReprNewsrc/proof/ssw/sswInt.hAig_Obj_t *Ssw_ObjChild0Fra(Ssw_Man_t *, Aig_Obj_t *, int)src/proof/ssw/sswBmc.cAig_Obj_t *Ssw_BmcUnroll_rec(Ssw_Frm_t *, Aig_Obj_t *, int)Saig_ManRegNum(pFrm->pAig) > 0Abc_Cex_t *Ssw_BmcGetCounterExample(Ssw_Frm_t *, Ssw_Sat_t *, int, int)int Ssw_BmcDynamic(Aig_Man_t *, int, int, int, int *)Conf =%8.0f. Var =%8d. AIG=%9d. src/proof/ssw/sswClass.cAig_Obj_t **Ssw_ClassesReadClass(Ssw_Cla_t *, Aig_Obj_t *, int *)void Ssw_ClassesCollectClass(Ssw_Cla_t *, Aig_Obj_t *, Vec_Ptr_t *)p->pClassSizes[ppClass[0]->Id] >= 2void Ssw_ClassesCheck(Ssw_Cla_t *)%d(%d,%d,%d) Equiv classes: Const1 = %5d. Class = %5d. Lit = %5d. p->pClassSizes[pObj->Id] == 0void Ssw_ClassesRemoveNode(Ssw_Cla_t *, Aig_Obj_t *)p->pId2Class[pObj->Id] == NULLpRepr != NULLp->pId2Class[pRepr->Id][0] == pReprp->pClassSizes[pRepr->Id] >= 2k + 1 == p->pClassSizes[pRepr->Id]int Ssw_ClassesPrepareRehash(Ssw_Cla_t *, Vec_Ptr_t *, int)Allocated %.2f MB to store simulation information. Initial simulation of %d frames with %d words. Collecting candidate equivalence classes. Vec_PtrSize(vCands) == p->nCands1Ssw_Cla_t *Ssw_ClassesPrepare(Aig_Man_t *, int, int, int, int, int, int)Simulation of %d frames with %d words (%2d rounds). memcmp(pClassSizes, p->pClassSizes, sizeof(int)*Aig_ManObjNumMax(pAig)) == 0Ssw_Cla_t *Ssw_ClassesPrepareFromReprs(Aig_Man_t *)(i == 0) == (Entry == 0)Ssw_Cla_t *Ssw_ClassesPreparePairs(Aig_Man_t *, Vec_Int_t **)Aig_ObjId(pRepr) < Aig_ObjId(pObj)Ssw_Cla_t *Ssw_ClassesPreparePairsSimple(Aig_Man_t *, Vec_Int_t *)int Ssw_ClassesRefineOneClass(Ssw_Cla_t *, Aig_Obj_t *, int)!Ssw_ObjIsConst1Cand( pAig, pObj )void Ssw_ObjSetConst1Cand(Aig_Man_t *, Aig_Obj_t *)void Ssw_ObjAddClass(Ssw_Cla_t *, Aig_Obj_t *, Aig_Obj_t **, int)pClass[0] == pReprAig_Obj_t **Ssw_ObjRemoveClass(Ssw_Cla_t *, Aig_Obj_t *)src/proof/ssw/sswCnf.cvoid Ssw_AddClausesMux(Ssw_Sat_t *, Aig_Obj_t *)void Ssw_AddClausesSuper(Ssw_Sat_t *, Aig_Obj_t *, Vec_Ptr_t *)void Ssw_CollectSuper(Aig_Obj_t *, int, Vec_Ptr_t *)void Ssw_ObjAddToFrontier(Ssw_Sat_t *, Aig_Obj_t *, Vec_Ptr_t *)Ssw_ObjSatNum(p,pObj) == 0Ssw_ObjSatNum(p,pNode)void Ssw_CnfNodeAddToSolver(Ssw_Sat_t *, Aig_Obj_t *)int Ssw_CnfGetNodeValue(Ssw_Sat_t *, Aig_Obj_t *)src/proof/ssw/sswConstr.cAig_Man_t *Ssw_FramesWithConstraints(Aig_Man_t *, int)Aig_ManRegNum(p) < Aig_ManCiNum(p)p->nConstrs > 0int Ssw_ManSetConstrPhases_(Aig_Man_t *, int, Vec_Int_t **)pSat->size == nFrames * pCnf->nVarspCnf->pVarNums[Aig_ObjId(pObj)] >= 0Vec_IntSize(p->vInits) % Saig_ManPiNum(p->pAig) == 0void Ssw_ManRefineByConstrSim(Ssw_Man_t *)output %d failed in frame %d. constraint %d failed in frame %d. iLits == Vec_IntSize(p->vInits)pObjFraig != NULL && pObjReprFraig != NULLint Ssw_ManSweepNodeConstr(Ssw_Man_t *, Aig_Obj_t *, int, int)(pObj->fPhase == pObjRepr->fPhase) == (Aig_ObjPhaseReal(pObjFraig) == Aig_ObjPhaseReal(pObjReprFraig))Aig_ObjRepr( p->pAig, pObj ) != pObjReprSsw_ManSweepNodeConstr(): Failed to refine representative. !Saig_ObjIsPi(p->pAig, pObj)Aig_Obj_t *Ssw_ManSweepBmcConstr_rec(Ssw_Man_t *, Aig_Obj_t *, int)pObjNew != NULLint Ssw_ManSweepBmcConstr_old(Ssw_Man_t *)int Ssw_ManSweepBmcConstr(Ssw_Man_t *)Aig_Obj_t *Ssw_FramesWithClasses_rec(Ssw_Man_t *, Aig_Obj_t *, int)(nConstrPairs & 1) == 0int Ssw_ManSweepConstr(Ssw_Man_t *)Vec_IntSize(p->vInits) == iLitsSsw_ObjChild0Fra(p,pObj,f) != Aig_ManConst1(p->pFrames)Polarity violation. void Aig_ObjSetCopy(Aig_Obj_t *, Aig_Obj_t *)Aig_Obj_t *Aig_ObjCopy(Aig_Obj_t *)@KLd2srm.blifIterative refinement is stopped before iteration %d. The network is reduced using candidate equivalences. Speculatively reduced miter is saved in file "%s". If the miter is SAT, the reduced result is incorrect. %3d : C =%7d. Cl =%7d. Pr =%6d. Cex =%5d. R =%4d. F =%4d. %3d : C =%7d. Cl =%7d. LR =%6d. NR =%6d. Cex =%5d. R =%4d. F =%5d. %s src/proof/ssw/sswCore.cAig_Man_t *Ssw_SignalCorrespondence(Aig_Man_t *, Ssw_Pars_t *)pPars->nFramesK > 0Ssw_SignalCorrespondence(): The init state does not satisfy the constraints! Aig_ObjIsCi(pObjFrames)src/proof/ssw/sswDyn.cvoid Ssw_ManLabelPiNodes(Ssw_Man_t *)pObjFrames->fMarkB == 0void Ssw_ManCollectPis_rec(Aig_Obj_t *, Vec_Ptr_t *)void Ssw_ManCollectPos_rec(Ssw_Man_t *, Aig_Obj_t *, Vec_Int_t *)p->pFrames->pFanData != NULLpRepr != pObjvoid Ssw_ManLoadSolver(Ssw_Man_t *, Aig_Obj_t *, Aig_Obj_t *)pReprFrames != pObjFramesvoid Ssw_ManSweepTransferDyn(Ssw_Man_t *)Aig_ObjIsCi(pObjFraig)p->vSimInfo == NULLint Ssw_ManSweepDyn(Ssw_Man_t *)p->nPatterns == 0src/proof/ssw/sswFilter.cvoid Ssw_ManRefineByFilterSim(Ssw_Man_t *, int)void Ssw_ManRollForward(Ssw_Man_t *, int)void Ssw_ManFindStartingState(Ssw_Man_t *, Abc_Cex_t *)int Ssw_ManSweepNodeFilter(Ssw_Man_t *, Aig_Obj_t *, int)Ssw_ManSweepNodeFilter(): Failed to refine representative. Aig_Obj_t *Ssw_ManSweepBmcFilter_rec(Ssw_Man_t *, Aig_Obj_t *, int)Exceeded the resource limits (%d conflicts). Quitting... Exceeded the time frame limit (%d time frames). Quitting... void Ssw_SignalFilter(Aig_Man_t *, int, int, int, int, int, Abc_Cex_t *, int, int)Aig_ManConstrNum(pAig) == 0p->vInits == NULLRound %3d: All equivalences are refined away. Initial : pObj0->pData == NULLsrc/proof/ssw/sswIslands.cvoid Ssw_MatchingStart(Aig_Man_t *, Aig_Man_t *, Vec_Int_t *)pObj1->pData == NULLpObj0->pData == pObj1pObj1->pData == pObj0Mismatch between LO pairs. void Ssw_MatchingExtendOne(Aig_Man_t *, Vec_Ptr_t *)Extending islands by %d steps: %2d : Total = %6d. Unmatched = %6d. Ratio = %6.2f %% pNext1->pData == pNext0void Ssw_MatchingExtend(Aig_Man_t *, Aig_Man_t *, int, int)Aig_ManCiNum(p0) == Aig_ManCiNum(p1)Vec_Int_t *Ssw_MatchingPairs(Aig_Man_t *, Aig_Man_t *)Aig_ManCoNum(p0) == Aig_ManCoNum(p1)Aig_ManRegNum(p0) == Aig_ManRegNum(p1)Aig_ManObjNum(p0) == Aig_ManObjNum(p1)pObj0->pData != NULLVec_Int_t *Ssw_MatchingMiter(Aig_Man_t *, Aig_Man_t *, Aig_Man_t *, Vec_Int_t *)pObj1->pData != NULLAig_ObjType(pObj0) == Aig_ObjType(pObj1)Aig_ObjIsNode(pObj0) || Saig_ObjIsLo(pMiter, pObj0)Aig_ObjIsNode(pObj1) || Saig_ObjIsLo(pMiter, pObj1)pObj0->Id < pObj1->Idsrm_part.blifDumping speculative miter is possible only for partial signal correspondence (switch "-c"). Verification successful. Verification failed with a counter-example. Verification UNDECIDED. The number of remaining regs = %d (total = %d). Performing sequential verification using structural similarity. Aig_ManRegNum(pPart0) > 0int Ssw_SecWithSimilarity(Aig_Man_t *, Aig_Man_t *, Ssw_Pars_t *)Aig_ManRegNum(pPart1) > 0Saig_ManPiNum(pPart0) == Saig_ManPiNum(pPart1)Saig_ManPoNum(pPart0) == Saig_ManPoNum(pPart1)src/proof/ssw/sswLcorr.cvoid Ssw_ManSweepTransfer(Ssw_Man_t *)nVarNum > 0void Ssw_SmlAddPattern(Ssw_Man_t *, Aig_Obj_t *, Aig_Obj_t *)void Ssw_ManBuildCone_rec(Ssw_Man_t *, Aig_Obj_t *)void Ssw_ManSweepLatchOne(Ssw_Man_t *, Aig_Obj_t *, Aig_Obj_t *)Aig_ObjIsCi(pObjRepr) || Aig_ObjIsConst1(pObjRepr)int Ssw_ManSweepLatch(Ssw_Man_t *)8@src/proof/ssw/sswMan.cSsw_Man_t *Ssw_ManCreate(Aig_Man_t *, Ssw_Pars_t *)Parameters: F = %d. AddF = %d. C-lim = %d. Constr = %d. MaxLev = %d. Mem = %0.2f MB. AIG : PI = %d. PO = %d. Latch = %d. Node = %d. Ave SAT vars = %d. SAT calls : Proof = %d. Cex = %d. Fail = %d. Lits proved = %d. SAT solver: Vars max = %d. Calls max = %d. Recycles = %d. Sim rounds = %d. BMC Spec reduceMark cones Statistics reflecting the use of constraints: Total cones = %6d. Constraint cones = %6d. (%6.2f %%) Total equivs = %6d. Removed equivs = %6d. (%6.2f %%) p->pMSat == NULLvoid Ssw_ManCleanup(Ssw_Man_t *)Cannot use partitioned computation with constraints. Miter has %d outputs. NonConst0 = %d. Undecided = %d. pObj1m && pObj2msrc/proof/ssw/sswPairs.cVec_Int_t *Ssw_TransferSignalPairs(Aig_Man_t *, Aig_Man_t *, Aig_Man_t *, Vec_Int_t *, Vec_Int_t *)idObj > 0Vec_Int_t **Ssw_TransformPairsIntoTempClasses(Vec_Int_t *, int)(pReprs[idRepr] == -1) || (pvClasses[pReprs[idRepr]] != NULL)(pReprs[idObj] == -1) || (pvClasses[pReprs[idObj] ] != NULL)idReprObj != idReprVec_IntSize(vIds1) == Vec_IntSize(vIds2)Aig_Man_t *Ssw_SignalCorrespondenceWithPairs(Aig_Man_t *, Aig_Man_t *, Vec_Int_t *, Vec_Int_t *, Ssw_Pars_t *)Recorded %d pairs (before: %d after: %d). Verification failed with the counter-example. Verification UNDECIDED. Remaining registers %d (total %d). vIds1 != NULL && vIds2 != NULLint Ssw_SecWithPairs(Aig_Man_t *, Aig_Man_t *, Vec_Int_t *, Vec_Int_t *, Ssw_Pars_t *)Performing specialized verification with node pairs. Performing general verification without node pairs. esrc/proof/ssw/sswRarity.cAbc_Cex_t *Ssw_RarDeriveCex(Ssw_RarMan_t *, int, int, int, int)Ssw_RarDeriveCex(): Counter-example is invalid. Mismatch Vec_IntSize(vInit) == Saig_ManRegNum(p->pAig) * p->pPars->nWordsvoid Ssw_RarManInitialize(Ssw_RarMan_t *, Vec_Int_t *)i < 64int Ssw_RarManObjWhichOne(Ssw_RarMan_t *, Aig_Obj_t *)Vec_PtrEntry(p->vCexes, i) == NULLint Ssw_RarManCheckNonConstOutputs(Ssw_RarMan_t *, int, abctime)Output %*d was asserted in frame %4d (solved %*d out of %*d outputs). Vec_PtrSize(vCands) == Ssw_ClassesCand1Num(p->ppClasses)void Ssw_RarManSimulate(Ssw_RarMan_t *, Vec_Int_t *, int, int)Output %d is trivally SAT in frame 0. int Ssw_RarSimulate(Aig_Man_t *, Ssw_RarPars_t *)Rarity simulation with %d words, %d frames, %d rounds, %d restart, %d seed, and %d sec timeout. Simulated %d frames for %d rounds with %d restarts. Simulated %d frames for %d rounds with %d restarts and solved %d outputs. Reached timeout (%d sec). Reached gap timeout (%d sec). Starts =%6d Rounds =%6d Frames =%6d CEX =%6d (%6.2f %%) Vec_IntSize(p->vInits) % Aig_ManRegNum(pAig) == 0Simulation of %d frames for %d rounds with %d restarts did not assert POs. Generating random permutation of %d flops. Randomly adding %d unused flops. int Ssw_RarSignalFilter(Aig_Man_t *, Ssw_RarPars_t *)Rarity equiv filtering with %d words, %d frames, %d rounds, %d seed, and %d sec timeout. Beginning simulation from the state derived using the counter-example. Vec_IntSize(p->vInits) == Aig_ManRegNum(pAig) * pPars->nWordsInitial : Simulated %d frames for %d rounds with %d restarts. Round %3d: Id < Aig_ManObjNumMax(p->pAig)word *Ssw_RarObjSim(Ssw_RarMan_t *, int)Id < 64 * p->pPars->nWordsword *Ssw_RarPatSim(Ssw_RarMan_t *, int)void Ssw_RarTransferPatterns(Ssw_RarMan_t *, Vec_Int_t *)iPatBest >= 0Vec_IntSize(vInits) == Aig_ManRegNum(p->pAig) * p->pPars->nWordsiBin >= 0 && iBin < Aig_ManRegNum(p->pAig) / p->pPars->nBinSizevoid Ssw_RarAddToBinPat(Ssw_RarMan_t *, int, int)iPat >= 0 && iPat < (1 << p->pPars->nBinSize)int Ssw_RarGetBinPat(Ssw_RarMan_t *, int, int)void Ssw_RarManStop(Ssw_RarMan_t *)Vec_Int_t *Ssw_RarFindStartingState(Aig_Man_t *, Abc_Cex_t *)EQGyU)] C k 1 g # ]  a  = WCg!i Y 7yEm!k)_=u#{7qQ!QAsE5c/Kg{src/proof/ssw/sswSat.cint Ssw_NodesAreEquiv(Ssw_Man_t *, Aig_Obj_t *, Aig_Obj_t *)p->pMSat != NULLAig_Regular(pOld) != Aig_Regular(pNew)int Ssw_NodesAreConstrained(Ssw_Man_t *, Aig_Obj_t *, Aig_Obj_t *)p->pPars->fConstrs || Aig_ObjPhaseReal(pOld) == Aig_ObjPhaseReal(pNew)int Ssw_NodeIsConstrained(Ssw_Man_t *, Aig_Obj_t *)src/proof/ssw/sswSemi.cSsw_Sem_t *Ssw_SemManStart(Ssw_Man_t *, int, int)EQGyU)] C k 1 g # ]  a  = WCg!i Y 7yEm!k)_=u#{7qQ!QAsE5c/Kg{pObjLo->fPhase == 0src/proof/ssw/sswSim.cint Ssw_SmlCheckXorImplication(Ssw_Sml_t *, Aig_Obj_t *, Aig_Obj_t *, Aig_Obj_t *)int Ssw_SmlCountXorImplication(Ssw_Sml_t *, Aig_Obj_t *, Aig_Obj_t *, Aig_Obj_t *)int Ssw_SmlCountEqual(Ssw_Sml_t *, Aig_Obj_t *, Aig_Obj_t *)i < p->nWordsTotalint *Ssw_SmlCheckOutputSavePattern(Ssw_Sml_t *, Aig_Obj_t *)int *Ssw_SmlCheckOutput(Ssw_Sml_t *)void Ssw_SmlAssignRandom(Ssw_Sml_t *, Aig_Obj_t *)p->nWordsFrame * p->nFrames == p->nWordsTotalvoid Ssw_SmlAssignRandomFrame(Ssw_Sml_t *, Aig_Obj_t *, int)void Ssw_SmlObjAssignConst(Ssw_Sml_t *, Aig_Obj_t *, int, int)void Ssw_SmlObjAssignConstWord(Ssw_Sml_t *, Aig_Obj_t *, int, int, int)iWord < p->nWordsFramevoid Ssw_SmlObjSetWord(Ssw_Sml_t *, Aig_Obj_t *, unsigned int, int, int)void Ssw_SmlAssignDist1(Ssw_Sml_t *, unsigned int *)void Ssw_SmlAssignDist1Plus(Ssw_Sml_t *, unsigned int *)void Ssw_SmlNodeSimulate(Ssw_Sml_t *, Aig_Obj_t *, int)iFrame0 < p->nFramesint Ssw_SmlNodesCompareInFrame(Ssw_Sml_t *, Aig_Obj_t *, Aig_Obj_t *, int, int)iFrame1 < p->nFramesvoid Ssw_SmlNodeCopyFanin(Ssw_Sml_t *, Aig_Obj_t *, int)void Ssw_SmlNodeTransferNext(Ssw_Sml_t *, Aig_Obj_t *, Aig_Obj_t *, int)void Ssw_SmlNodeTransferFirst(Ssw_Sml_t *, Aig_Obj_t *, Aig_Obj_t *)void Ssw_SmlInitialize(Ssw_Sml_t *, int)Aig_ManRegNum(p->pAig) <= Aig_ManCiNum(p->pAig)void Ssw_SmlInitializeSpecial(Ssw_Sml_t *, Vec_Int_t *)nRegs <= Aig_ManCiNum(p->pAig)Vec_IntSize(vInit) == nRegs * p->nWordsFramevoid Ssw_SmlReinitialize(Ssw_Sml_t *)void Ssw_SmlSimulateOneDyn_rec(Ssw_Sml_t *, Aig_Obj_t *, int, int *, int)unsigned int *Ssw_SmlSimInfo(Ssw_Sml_t *, Aig_Obj_t *)Abc_Cex_t *Ssw_SmlGetCounterExample(Ssw_Sml_t *)Ssw_SmlGetCounterExample(): Counter-example is invalid. src/proof/ssw/sswSimSat.cvoid Ssw_ManResimulateBit(Ssw_Man_t *, Aig_Obj_t *, Aig_Obj_t *)void Ssw_ManResimulateWord(Ssw_Man_t *, Aig_Obj_t *, Aig_Obj_t *, int)src/proof/ssw/sswSweep.cvoid Ssw_CheckConstraints(Ssw_Man_t *)Total constraints = %d. Added constraints = %d. void Ssw_SmlAddPatternDyn(Ssw_Man_t *)int Ssw_ManSweepNode(Ssw_Man_t *, Aig_Obj_t *, int, int, Vec_Int_t *)Ssw_ManSweepNode(): Failed to refine representative. equiv%03d.aigAIG with %4d disproved equivs is dumped into file "%s". int Ssw_ManSweep(Ssw_Man_t *)src/proof/ssw/sswUnique.cvoid Ssw_UniqueRegisterPairInfo(Ssw_Man_t *)p->pPars->nFramesK > 1int Ssw_ManUniqueOne(Ssw_Man_t *, Aig_Obj_t *, Aig_Obj_t *, int)p->vDiffPairs && Vec_IntSize(p->vDiffPairs) == Saig_ManRegNum(p->pAig)Aig_ObjIsCi(pTemp)Aig_ObjCioId(pTemp) > 0Node = %5d : Supp = %3d. Regs = %3d. Feasible = %s. Vec_PtrSize(vCommon) > 0int Ssw_ManUniqueAddConstraint(Ssw_Man_t *, Vec_Ptr_t *, int, int)Saig_ObjIsLo(p->pAig, pObj)p->iOutputLit == -1Aig_ManCheck: The PI node "%p" has fanins. Aig_ManCheck: The PO node "%p" has NULL fanin. Aig_ManCheck: The PO node "%p" has second fanin. Aig_ManCheck: The AIG has internal node "%p" with a NULL fanin. Aig_ManCheck: The AIG has node "%p" with a wrong ordering of fanins. Aig_ManCheck: Node "%p" is not in the structural hashing table. C1 = %d. Pi = %d. Po = %d. Buf = %d. And = %d. Xor = %d. Total = %d. Created = %d. Deleted = %d. Existing = %d. Entries = %d. And = %d. Xor = %d. Total = %d. src/aig/aig/aigCheck.cvoid Aig_ManCheckMarkA(Aig_Man_t *)(int)pObj->fPhase == 0void Aig_ManCheckPhase(Aig_Man_t *)(int)pObj->fPhase == (Aig_ObjPhaseReal(Aig_ObjChild0(pObj)) & Aig_ObjPhaseReal(Aig_ObjChild1(pObj)))Aig_ManCheck: The number of nodes in the structural hashing table is wrong.Aig_ManCheck: The number of created nodes is wrong. CQ 5 CQsrc/aig/aig/aigCanon.cvoid Aig_RManTableResize(Aig_RMan_t *)*ppPlace == NULLTotal funcs = %10d Full DSD funcs = %10d Part DSD funcs = %10d Non- DSD funcs = %10d Uniq-var funcs = %10d Unique funcs = %10d %2d = %8d aiglib%02d.aig%2d/%2d Distribution of functions:Decomposition failed.The number of variables in too large.src/aig/aig/aigCuts.cAig_ManCut_t *Aig_ManCutStart(Aig_Man_t *, int, int, int, int)int Aig_CutSupportMinimize(Aig_ManCut_t *, Aig_Cut_t *)int Aig_CutMerge(Aig_ManCut_t *, Aig_Cut_t *, Aig_Cut_t *, Aig_Cut_t *)void Aig_ObjComputeCuts(Aig_ManCut_t *, Aig_Obj_t *, int)Aig_ObjCuts(p, pObj) == NULLpAig->pManCuts == NULLAig_ManCut_t *Aig_ComputeCuts(Aig_Man_t *, int, int, int, int)Nodes = %6d. Total cuts = %6d. %d-input cuts = %6d. unsigned int Aig_CutTruthPhase(Aig_Cut_t *, Aig_Cut_t *)int Aig_CutMergeOrdered(Aig_ManCut_t *, Aig_Cut_t *, Aig_Cut_t *, Aig_Cut_t *)Aig_Cut_t *Aig_CutFindFree(Aig_ManCut_t *, Aig_Obj_t *)int Aig_CutFindCost(Aig_ManCut_t *, Aig_Cut_t *)Tim_ManBoxForCo( (Tim_Man_t *)p->pManTime, Aig_ObjCioId(pNext) ) == iBoxsrc/aig/aig/aigDfs.cint Aig_ManVerifyTopoOrder(Aig_Man_t *)void Aig_ManDfs_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)Vec_PtrSize(vNodes) == Aig_ManNodeNum(p)Vec_Ptr_t *Aig_ManDfs(Aig_Man_t *, int)Vec_PtrSize(vNodes) == Aig_ManObjNum(p)void Aig_ManDfsAll_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)Vec_Ptr_t *Aig_ManDfsAll(Aig_Man_t *)void Aig_ManDfsPreorder_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)Vec_Ptr_t *Aig_ManDfsPreorder(Aig_Man_t *, int)Vec_Vec_t *Aig_ManLevelize(Aig_Man_t *)void Aig_ManDfsChoices_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)!Aig_ObjIsTravIdCurrent(p, pObj)p->pEquivs != NULLVec_Ptr_t *Aig_ManDfsChoices(Aig_Man_t *)void Aig_ManDfsReverse_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)Aig_ObjIsNode(pObj) || Aig_ObjIsBuf(pObj)void Aig_ManChoiceLevel_rec(Aig_Man_t *, Aig_Obj_t *)void Aig_ConeMark_rec(Aig_Obj_t *)!Aig_ObjIsMarkA(pObj)void Aig_ConeCleanAndMark_rec(Aig_Obj_t *)int Aig_ConeCountAndMark_rec(Aig_Obj_t *)void Aig_ConeUnmark_rec(Aig_Obj_t *)void Aig_SupportSize_rec(Aig_Man_t *, Aig_Obj_t *, int *)int Aig_SupportSize(Aig_Man_t *, Aig_Obj_t *)!Aig_ObjIsCo(pObj)void Aig_Support_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)Vec_Ptr_t *Aig_Support(Aig_Man_t *, Aig_Obj_t *)!Aig_IsComplement(ppObjs[i])void Aig_SupportNodes(Aig_Man_t *, Aig_Obj_t **, int, Vec_Ptr_t *)void Aig_Transfer_rec(Aig_Man_t *, Aig_Obj_t *)void Aig_Compose_rec(Aig_Man_t *, Aig_Obj_t *, Aig_Obj_t *, Aig_Obj_t *)Aig_Compose(): The PI variable %d is not defined. void Aig_ObjCollectCut_rec(Aig_Obj_t *, Vec_Ptr_t *)void Aig_ObjCollectCut(Aig_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *)int Aig_ObjCollectSuper_rec(Aig_Obj_t *, Aig_Obj_t *, Vec_Ptr_t *)int Aig_ObjCollectSuper(Aig_Obj_t *, Vec_Ptr_t *)Vec_PtrSize(vSuper) > 10<101p->pManTime == NULLsrc/aig/aig/aigDup.cAig_Man_t *Aig_ManDupSimple(Aig_Man_t *)p->nAsserts == 0 || p->nConstrs == 0Aig_Man_t *Aig_ManDupSimpleWithHints(Aig_Man_t *, Vec_Int_t *)Aig_Man_t *Aig_ManDupSimpleDfs(Aig_Man_t *)pObj->Level == ((Aig_Obj_t*)pObj->pData)->LevelAig_Man_t *Aig_ManDupOrdered(Aig_Man_t *)Aig_ManDupOrdered(): Cleanup after AIG duplication removed %d nodes. Aig_Man_t *Aig_ManDupCof(Aig_Man_t *, int, int)Aig_Man_t *Aig_ManDupTrim(Aig_Man_t *)Aig_ManDupTrim(): Cleanup after AIG duplication removed %d nodes. Aig_Man_t *Aig_ManDupExor(Aig_Man_t *)Aig_Regular(pEquivNew)->Id < Aig_Regular(pObjNew)->IdAig_Obj_t *Aig_ManDupDfs_rec(Aig_Man_t *, Aig_Man_t *, Aig_Obj_t *)p->pEquivs != NULL || Aig_ManBufNum(p) != 0 || Aig_ManNodeNum(p) == Aig_ManNodeNum(pNew)Aig_Man_t *Aig_ManDupDfs(Aig_Man_t *)Aig_ManDupDfs(): Cleanup after AIG duplication removed %d nodes. Aig_ManCiNum(p) == Aig_ManCiNum(pOrder)Vec_Ptr_t *Aig_ManOrderPios(Aig_Man_t *, Aig_Man_t *)Aig_ManCoNum(p) == Aig_ManCoNum(pOrder)Aig_Man_t *Aig_ManDupLevelized(Aig_Man_t *)!Aig_ObjIsBuf(pObj)Aig_Man_t *Aig_ManDupWithoutPos(Aig_Man_t *)Aig_Man_t *Aig_ManDupRepres(Aig_Man_t *)Aig_Man_t *Aig_ManDupRepresDfs(Aig_Man_t *)Aig_ManRegNum(p1) == 0Aig_Man_t *Aig_ManCreateMiter(Aig_Man_t *, Aig_Man_t *, int)Aig_ManRegNum(p2) == 0Aig_ManCoNum(p1) == 1Aig_ManCoNum(p2) == 1Aig_Man_t *Aig_ManDupOrpos(Aig_Man_t *, int)Aig_Man_t *Aig_ManDupOneOutput(Aig_Man_t *, int, int)iPoNum < Aig_ManCoNum(p)-Aig_ManRegNum(p)Aig_Man_t *Aig_ManDupUnsolvedOutputs(Aig_Man_t *, int)Aig_ManRegNum(pNew) == 0Aig_Man_t *Aig_ManDupArray(Vec_Ptr_t *)Aig_ManCiNum(pNew) == Aig_ManCiNum(p)Llb_ManDeriveAigWithHints(): The check has failed.Aig_ManDupOrdered(): The check has failed.Aig_ManDupTrim(): The check has failed.Aig_ManDupExor(): The check has failed.Aig_ManDupDfs(): The check has failed.Aig_ManDupLevelized(): The check has failed.Aig_ManDupFlopsOnly(): The check has failed.Aig_ManDupRepres: Check has failed.Aig_ManDupRepresDfs: Check has failed.The AIG manager should have no constraints.Aig_ManDupSimple(): The check has failed.Aig_ManBufNum(p) == 0src/aig/aig/aigFanout.cvoid Aig_ManFanoutStart(Aig_Man_t *)p->pFanData == NULLp->pFanData != NULLvoid Aig_ManFanoutStop(Aig_Man_t *)void Aig_ObjAddFanout(Aig_Man_t *, Aig_Obj_t *, Aig_Obj_t *)!Aig_IsComplement(pObj) && !Aig_IsComplement(pFanout)pFanout->Id > 0*pNext == *pFirstp->pFanData && pObj->Id < p->nFansAlloc && pFanout->Id < p->nFansAllocvoid Aig_ObjRemoveFanout(Aig_Man_t *, Aig_Obj_t *, Aig_Obj_t *)*pPrev == iFan*pNext == iFan*pFirst > 0int Aig_ObjWhatFanin(Aig_Obj_t *, Aig_Obj_t *)Aig_ManCiNum(pManOn) == Aig_ManCiNum(pManOff)src/aig/aig/aigInter.cvoid Aig_ManInterFast(Aig_Man_t *, Aig_Man_t *, int)Aig_ManCoNum(pManOn) == Aig_ManCoNum(pManOff)Aig_Man_t *Aig_ManInter(Aig_Man_t *, Aig_Man_t *, int, int)The incremental SAT problem is not UNSAT.The SAT problem is not unsat.src/aig/aig/aigJust.cint Aig_NtkFindSatAssign_rec(Aig_Man_t *, Aig_Obj_t *, int, Vec_Int_t *, int)int Aig_ObjTerSimulate_rec(Aig_Man_t *, Aig_Obj_t *)PO =%6d. C0 =%6d. C0f =%6d. C1 =%6d. C1f =%6d. (%6.2f %%) Ave =%4.1f int Aig_ObjSetTerValue(Aig_Obj_t *, int)!pObj->fMarkA && !pObj->fMarkBsrc/aig/aig/aigMan.cvoid Aig_ManStop(Aig_Man_t *)lat = %5d and = %7d xor = %5d ch = %5d buf = %5d lev = %3dREG: Beg = %5d. End = %5d. (R =%5.1f %%) AND: Beg = %6d. End = %6d. (R =%5.1f %%)Aig_ManExtractMiter(): The check has failed.src/aig/aig/aigMem.cchar *Aig_MmFixedEntryFetch(Aig_MmFixed_t *)char *Aig_MmFlexEntryFetch(Aig_MmFlex_t *, int)pFanin->nRefs > 0src/aig/aig/aigMffc.cint Aig_NodeDeref_rec(Aig_Obj_t *, unsigned int, float *, float *)int Aig_NodeRef_rec(Aig_Obj_t *, unsigned int)int Aig_NodeRefLabel_rec(Aig_Man_t *, Aig_Obj_t *, unsigned int)void Aig_NodeMffcSupp_rec(Aig_Man_t *, Aig_Obj_t *, unsigned int, Vec_Ptr_t *, int, Aig_Obj_t *)int Aig_NodeMffcSupp(Aig_Man_t *, Aig_Obj_t *, int, Vec_Ptr_t *)ConeSize1 == ConeSize2(pPower != NULL) == (p->vProbs != NULL)int Aig_NodeMffcLabel(Aig_Man_t *, Aig_Obj_t *, float *)int Aig_NodeMffcLabelCut(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)ConeCur1 == ConeCur2int Aig_NodeMffcExtendCut(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *)pLeafBest != NULLAig_ObjIsNode(pLeafBest)!Aig_IsComplement(pGhost)src/aig/aig/aigObj.cAig_Obj_t *Aig_ObjCreate(Aig_Man_t *, Aig_Obj_t *)Aig_ObjIsHash(pGhost)void Aig_ObjConnect(Aig_Man_t *, Aig_Obj_t *, Aig_Obj_t *, Aig_Obj_t *)Aig_ObjFanin0(pObj)->Type > 0Aig_ObjFanin1(pObj)->Type > 0!Aig_ObjIsNode(pObj) || pObj->Level > 0void Aig_ObjDisconnect(Aig_Man_t *, Aig_Obj_t *)void Aig_ObjDelete(Aig_Man_t *, Aig_Obj_t *)!Aig_ObjIsTerm(pObj)Aig_ObjRefs(pObj) == 0void Aig_ObjDelete_rec(Aig_Man_t *, Aig_Obj_t *, int)void Aig_ObjDeletePo(Aig_Man_t *, Aig_Obj_t *)void Aig_ObjPatchFanin0(Aig_Man_t *, Aig_Obj_t *, Aig_Obj_t *)Compl void Aig_ObjPrint(Aig_Man_t *, Aig_Obj_t *)Node %4d : BUF( %d%s ) { %4d %4d%s class of %dAig_ObjIsBuf(Aig_ObjFanin0(pObj))void Aig_NodeFixBufferFanins(Aig_Man_t *, Aig_Obj_t *, int)Aig_ObjPhaseReal(Aig_ObjChild0(pObj)) == Aig_ObjPhaseReal(pFanReal0)Aig_ObjIsBuf(Aig_ObjFanin0(pObj)) || Aig_ObjIsBuf(Aig_ObjFanin1(pObj))int Aig_ManPropagateBuffers(Aig_Man_t *, int)void Aig_ObjReplace(Aig_Man_t *, Aig_Obj_t *, Aig_Obj_t *, int)!Aig_ObjIsCi(pObjOld) && !Aig_ObjIsCo(pObjOld)!Aig_ObjIsBuf(pObjNewR) && !Aig_ObjIsCo(pObjNewR)pObjOld != pObjNewRpObjOld != Aig_ObjFanin0(pObjNewR)pObjOld != Aig_ObjFanin1(pObjNewR)void Aig_ObjDeref(Aig_Obj_t *)pEntry->nRefs == 0void Aig_ManRecycleMemory(Aig_Man_t *, Aig_Obj_t *)p->pFanData && pObj->Id < p->nFansAllocAig_Obj_t *Aig_ObjFanout0(Aig_Man_t *, Aig_Obj_t *)Error: A cycle is encountered while propagating buffers.i < Vec_PtrSize(p->vCis)src/aig/aig/aigOper.cAig_Obj_t *Aig_IthVar(Aig_Man_t *, int)Aig_Obj_t *Aig_Oper(Aig_Man_t *, Aig_Obj_t *, Aig_Obj_t *, Aig_Type_t)Type == AIG_OBJ_AND || Type == AIG_OBJ_EXORAig_Obj_t *Aig_Multi(Aig_Man_t *, Aig_Obj_t **, int, Aig_Type_t)nArgs > 0vPairs->nSize > 0Aig_Obj_t *Aig_Miter(Aig_Man_t *, Vec_Ptr_t *)vNodes1->nSize > 0 && vNodes1->nSize > 0Aig_Obj_t *Aig_MiterTwo(Aig_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *)vNodes1->nSize == vNodes2->nSizeNumber of nodes = %6d. Type == AIG_OBJ_CI || Aig_Regular(p0) != Aig_Regular(p1)src/aig/aig/aigOrder.cvoid Aig_ManOrderStart(Aig_Man_t *)p->pOrderData == NULLp->pOrderDatavoid Aig_ManOrderStop(Aig_Man_t *)ObjId != 0void Aig_ObjOrderInsert(Aig_Man_t *, int)Aig_ObjIsNode( Aig_ManObj(p, ObjId) )p->pOrderData[2*ObjId] == 0xFFFFFFFFp->pOrderData[2*ObjId+1] == 0xFFFFFFFFp->pOrderData[2*iPrev+1] == (unsigned)p->iNextvoid Aig_ObjOrderRemove(Aig_Man_t *, int)void Aig_ObjOrderAdvance(Aig_Man_t *)p->pOrderData[2*p->iPrev+1] == (unsigned)p->iNext?Patterns: Total = %6d. Skipped = %6d. Cares = %6.2f %% %6.1f %%src/aig/aig/aigPart.cchar *Part_ManFetch(Part_Man_t *, int)Part_One_t *Part_ManMergeEntry(Part_Man_t *, Part_One_t *, Part_One_t *, int)Vec_Ptr_t *Aig_ManSupports(Aig_Man_t *)iIn < Aig_ManRegNum(p)Vec_Ptr_t *Aig_ManSupportsRegisters(Aig_Man_t *)iOut < Aig_ManRegNum(p)vSupp != NULLunsigned int *Aig_ManSuppCharStart(Vec_Int_t *, int)void Aig_ManSuppCharAdd(unsigned int *, Vec_Int_t *, int)Counter == Aig_ManCoNum(p)void Aig_ManPartitionPrint(Aig_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *)void Aig_ManPartitionCompact(Vec_Ptr_t *, Vec_Ptr_t *, int)Vec_PtrSize(vSupports) == Aig_ManRegNum(pAig)Vec_Ptr_t *Aig_ManPartitionSmartRegisters(Aig_Man_t *, int, int)Aig_Obj_t *Aig_ManDupPart_rec(Aig_Man_t *, Aig_Man_t *, Aig_Obj_t *, Vec_Int_t *)Vec_IntSize(vSuppMap) == Aig_ManCiNum(pNew)void Aig_ManDupPartAll_rec(Aig_Man_t *, Aig_Man_t *, Aig_Obj_t *)Vec_PtrSize(vAigs) > 1Aig_Man_t *Aig_ManChoicePartitioned(Vec_Ptr_t *, int, int, int, int)Vec_PtrEntry( vOutsTotal, Vec_IntEntry(vPart,k) ) == NULLPart %4d (out of %4d) PI = %5d. PO = %5d. And = %6d. Lev = %4d. Aig_ManCiNum(pNew) == Aig_ManCiNum(pPrev)void Aig_ManChoiceConstructiveOne(Aig_Man_t *, Aig_Man_t *, Aig_Man_t *)Aig_ManCiNum(pNew) == Aig_ManCiNum(pThis)Aig_ManCoNum(pNew) == Aig_ManCoNum(pPrev)Aig_ManCoNum(pNew) == Aig_ManCoNum(pThis)Aig_Regular((Aig_Obj_t *)pObj->pData)->fMarkBChoice node = %5d. Level = %2d. Choices = %d. { S=%d N=%d L=%d pNew->pReprs == NULLAig_Man_t *Aig_ManChoiceConstructive(Vec_Ptr_t *, int)void Part_ManRecycleEntry(Part_Man_t *, Part_One_t *)void Aig_ObjSetRepr_(Aig_Man_t *, Aig_Obj_t *, Aig_Obj_t *)pNode1->Id < p->nReprsAllocpNode2->Id < p->nReprsAllocsrc/aig/aig/aigPartReg.cvoid Aig_ManRegPartitionAdd(Aig_ManPre_t *, int)!p->pfPartVars[iReg]Partition contains %d groups of 1-hot registers: { Part %3d SUMMARY: Free = %4d. Total = %4d. Ratio = %6.2f. Unique = %4d. Overlap size (%d) is more or equal than the partition size (%d). nOverSize < nPartSizeVec_Ptr_t *Aig_ManRegPartitionSimple(Aig_Man_t *, int, int)nPartSize && Vec_IntSize(vDomain) > nPartSizevoid Aig_ManPartDivide(Vec_Ptr_t *, Vec_Int_t *, int, int)Latch %d: %d=%d Total collected = %d. Total regs = %d. Adjusting it to be equal to half of the partition size.\s]\]`]Aig_ObjRefs((Aig_Obj_t *)pObj->pData) < Aig_ObjRefs(pObj)src/aig/aig/aigPartSat.cAig_Man_t *Aig_ManPartSplitOne(Aig_Man_t *, Vec_Ptr_t *, Vec_Int_t **)Aig_ManNodeNum(pNew) == Vec_PtrSize(vNodes)Vec_Ptr_t *Aig_ManPartSplit(Aig_Man_t *, Vec_Int_t *, Vec_Ptr_t **, Vec_Ptr_t **)Aig_ManPartSplit(): Skipping partition # %d without nodes (warning). pObj->fPhase == pObjInit->fPhasevoid Aig_ManPartSetNodePolarity(Aig_Man_t *, Aig_Man_t *, Vec_Int_t *)int Aig_ManAddNewCnfToSolver(sat_solver *, Aig_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Ptr_t *, int)iSatVarOld != 0Partitioning derived %d partitions. Partions were transformed into AIGs. %4d : Aig = %6d. Vs = %7d. RootCs = %7d. LearnCs = %6d. Exceeded the limit on the total number of conflicts (%d). Unknown partitioning algorithm.src/aig/aig/aigRepr.cvoid Aig_ManReprStart(Aig_Man_t *, int)void Aig_ManReprStop(Aig_Man_t *)void Aig_ObjCreateRepr(Aig_Man_t *, Aig_Obj_t *, Aig_Obj_t *)!Aig_IsComplement(pNode1)!Aig_IsComplement(pNode2)pNode1->Id < pNode2->IdpNew->pReprs != NULLvoid Aig_ManTransferRepr(Aig_Man_t *, Aig_Man_t *)Aig_Man_t *Aig_ManDupReprBasic(Aig_Man_t *)int Aig_ManRemapRepr(Aig_Man_t *)int Aig_ObjCheckTfi(Aig_Man_t *, Aig_Obj_t *, Aig_Obj_t *)Aig_Man_t *Aig_ManRehash(Aig_Man_t *)void Aig_ManMarkValidChoices(Aig_Man_t *)p->pEquivs == NULLAig_Obj_t *Aig_ObjFindRepr(Aig_Man_t *, Aig_Obj_t *)pNode->Id < p->nReprsAllocvoid Aig_ObjClearRepr(Aig_Man_t *, Aig_Obj_t *)Aig_ManDupRepr: Check has failed.src/aig/aig/aigRet.cvoid Rtm_ObjAddFanin(Rtm_Obj_t *, Rtm_Obj_t *, int)pObj->nFanins <= pObj->NumpFanin->nFanouts <= pFanin->TempRtm_ObjCheckRetimeFwd(pObj)void Rtm_ObjRetimeFwd(Rtm_Man_t *, Rtm_Obj_t *)Rtm_ObjCheckRetimeBwd(pObj)void Rtm_ObjRetimeBwd(Rtm_Man_t *, Rtm_Obj_t *)Rtm_Man_t *Rtm_ManFromAig(Aig_Man_t *)Val == RTM_VAL_ZERO || Val == RTM_VAL_ONE || Val == RTM_VAL_VOIDAig_Man_t *Rtm_ManToAig(Rtm_Man_t *)Detected %d autonomous objects. pObj->nFanins == pObj->NumAig_Man_t *Rtm_ManRetime(Aig_Man_t *, int, int, int)pObj->nFanouts == pObj->TempPerformed %d %s latch moves of max depth %d and max latch count %d. bwdMemory usage = %d. Register sharing timeVal != 0Rtm_Init_t Rtm_ObjRemFirst2(Rtm_Man_t *, Rtm_Edg_t *)pEdge->nLats > 0Rtm_Init_t Rtm_ObjRemFirst1(Rtm_Edg_t *)pEdge->nLats == 10Rtm_Init_t Rtm_InitNot(Rtm_Init_t)Rtm_Init_t Rtm_InitAnd(Rtm_Init_t, Rtm_Init_t)void Rtm_ObjTransferToBig(Rtm_Man_t *, Rtm_Edg_t *)(pEdge->nLats & 15) == 15void Rtm_ObjTransferToBigger(Rtm_Man_t *, Rtm_Edg_t *)Val > 0Rtm_Init_t Rtm_ObjRemLast1(Rtm_Edg_t *)void Rtm_ObjAddFirst2(Rtm_Man_t *, Rtm_Edg_t *, Rtm_Init_t)void Rtm_ObjAddFirst1(Rtm_Edg_t *, Rtm_Init_t)Rtm_ManToAig: The network check has failed.src/aig/aig/aigRetF.cint Aig_ManRetimeMark_rec(Aig_Man_t *, Aig_Obj_t *)void Aig_ManRetimeMark(Aig_Man_t *)pObjLo->pNext == NULLpObjLi->pNext == NULLAig_Man_t *Aig_ManRetimeFrontier(Aig_Man_t *, int)p->vFlopNums == NULL || Vec_IntSize(p->vFlopNums) == p->nRegssrc/aig/aig/aigScl.cAig_Man_t *Aig_ManRemap(Aig_Man_t *, Vec_Ptr_t *)!Aig_IsComplement(pObjMapped)Aig_ObjIsCi(pObjMapped)Aig_ObjCioId(pObj) != Aig_ObjCioId(pObjMapped)Aig_ManNodeNum(p) >= Aig_ManNodeNum(pNew)void Aig_ManSeqCleanup_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)Vec_PtrSize(vNodes) <= Aig_ManCoNum(p)int Aig_ManSeqCleanup(Aig_Man_t *)k == Vec_PtrSize(vNodes) - nTruePosVec_PtrSize(vCis) == nTruePis + p->nRegsVec_PtrSize(vCos) == nTruePos + p->nRegsint Aig_ManSeqCleanupBasic(Aig_Man_t *)Regs = %d. Fanins = %d. Const0 = %d. Const1 = %d. int Aig_ManReduceLachesCount(Aig_Man_t *)void Aig_ManComputeSccs(Aig_Man_t *)SCC #%d contains %5d registers. %3d : Reg = %4d. PI = %4d. (True = %4d. Regs = %4d.) And = %5d. It = %3d. Cl = %5d pAig->vFlopNums == NULLAig_Man_t *Aig_ManScl(Aig_Man_t *, int, int, int, int, int, int, int)pFlop1 != pFlop2Aig_ManRemap(): The check has failed.Performing combinational register sweep:There is only one SCC of registers in this network.The network is combinational.Cannot visualize AIG with more than 200 nodes. AIG structure generated by IVY packagedigraph AIG { AIG structure visualized by ABC Node%d [label = "%d"src/aig/aig/aigSplit.cAig_Obj_t *Aig_NodeBddToMuxes_rec(DdManager *, DdNode *, Aig_Man_t *, st__table *)DdNode *Aig_ManBuildPoBdd_rec(Aig_Man_t *, Aig_Obj_t *, DdManager *)Saig_ManPoNum(p) == 1DdManager *Aig_ManBuildPoBdd(Aig_Man_t *, DdNode **)Support =%5d. BDD size =%6d. Created %d cofactors (out of %d). Aig_ManConvertBddsToAigs(): The check has failed.Property output function is a constant.The number of cofactoring variables should be less than 17.The number of cofactoring variables should be a positive number.Currently works only for one primary output.src/aig/aig/aigTable.cvoid Aig_TableResize(Aig_Man_t *)Counter == Aig_ManNodeNum(p)Aig_Obj_t *Aig_TableLookup(Aig_Man_t *, Aig_Obj_t *)Aig_ObjIsNode(pGhost)Aig_ObjChild0(pGhost) && Aig_ObjChild1(pGhost)Aig_ObjFanin0(pGhost)->Id < Aig_ObjFanin1(pGhost)->Idvoid Aig_TableInsert(Aig_Man_t *, Aig_Obj_t *)Aig_TableLookup(p, pObj) == NULLvoid Aig_TableDelete(Aig_Man_t *, Aig_Obj_t *)*ppPlace == pObjTable size = %d. Entries = %d. Aig_ObjChild0(pObj) && Aig_ObjChild1(pObj)Aig_Obj_t **Aig_TableFind(Aig_Man_t *, Aig_Obj_t *)Aig_ObjFanin0(pObj)->Id < Aig_ObjFanin1(pObj)->Idp->vLevelRsrc/aig/aig/aigTiming.cint Aig_ObjRequiredLevel(Aig_Man_t *, Aig_Obj_t *)int Aig_ObjReverseLevelNew(Aig_Man_t *, Aig_Obj_t *)void Aig_ManStartReverseLevels(Aig_Man_t *, int)p->vLevelR == NULLp->vLevelR != NULLvoid Aig_ManStopReverseLevels(Aig_Man_t *)void Aig_ManUpdateLevel(Aig_Man_t *, Aig_Obj_t *)Aig_ObjIsNode(pObjNew)Aig_ObjLevel(pTemp) == LevAig_ObjLevel(pFanout) >= Levvoid Aig_ManUpdateReverseLevel(Aig_Man_t *, Aig_Obj_t *)void Aig_ManVerifyLevel(Aig_Man_t *)Level of node %6d should be %4d instead of %4d. Levels of %d nodes are incorrect. void Aig_ManVerifyReverseLevel(Aig_Man_t *)Reverse level of node %6d should be %4d instead of %4d. Reverse levels of %d nodes are incorrect. void Aig_ObjSetReverseLevel(Aig_Man_t *, Aig_Obj_t *, int)int Aig_ObjReverseLevel(Aig_Man_t *, Aig_Obj_t *)Vec_PtrSize(vLeaves) <= Vec_PtrSize(vTruthElem)src/aig/aig/aigTruth.cunsigned int *Aig_ManCutTruth(Aig_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *)Vec_PtrSize(vNodes) <= Vec_PtrSize(vTruthStore)Vec_PtrSize(vNodes) == 0 || pRoot == Vec_PtrEntryLast(vNodes)EQGyU)] C k 1 g # ]  a  = WCg!i Y 7yEm!k)_=u#{7qQ!QAsE5c/Kg{!Aig_TsiStateLookup( p, pState, nWords )src/aig/aig/aigTsim.cvoid Aig_TsiStateInsert(Aig_Tsi_t *, unsigned int *, int)void Aig_TsiStatePrint(Aig_Tsi_t *, unsigned int *) (0=%5d, 1=%5d, x=%5d) Aig_ManTernarySimulate(): Did not reach a fixed point after %d iterations (not a bug). Detected 0 constants after %d iterations of ternary simulation. Vec_Ptr_t *Aig_ManTernarySimulate(Aig_Man_t *, int, int)Detected %d constants after %d iterations of ternary simulation. Value0 == AIG_XVS1 && Value1 == AIG_XVS1int Aig_XsimAnd(int, int)Value == AIG_XVSXint Aig_XsimInv(int)src/aig/aig/aigUtil.cvoid Aig_ObjCleanData_rec(Aig_Obj_t *)void Aig_ObjCollectMulti(Aig_Obj_t *, Vec_Ptr_t *)int Aig_ObjIsMuxType(Aig_Obj_t *)int Aig_ObjRecognizeExor(Aig_Obj_t *, Aig_Obj_t **, Aig_Obj_t **)Aig_Obj_t *Aig_ObjRecognizeMux(Aig_Obj_t *, Aig_Obj_t **, Aig_Obj_t **)Aig_ObjIsMuxType(pNode) ^ void Aig_ObjPrintVerbose(Aig_Obj_t *, int)Node %d : CICO( AND( %d%s, %d%s ) %paigbug\%03d.blifIntermediate AIG with %d nodes was written into file "%s". # BLIF file written by procedure Aig_ManDumpBlif() .names n%0*d 1 // Verilog file written by procedure Aig_ManDumpVerilog() module %s ( clockmodule %s (%s n%0*d, n%0*dinput clock; input n%0*d; output n%0*d; reg n%0*d; wire n%0*d; assign n%0*d = 1'b1; assign n%0*d = %sn%0*d & %sn%0*d; assign n%0*d = %sn%0*d; always @ (posedge clock) begin n%0*d <= n%0*d; end initial begin n%0*d <= 1'b0; end pObj != pCtrlvoid Aig_ManPrintControlFanouts(Aig_Man_t *)rand.txt%10d : %10d void Aig_NodeUnionLists(Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *)void Aig_NodeIntersectLists(Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *)vArr->nSize <= vArr1->nSizevArr->nSize <= vArr2->nSizevoid Aig_ManCounterExampleValueStart(Aig_Man_t *, Abc_Cex_t *)pAig->pData2 == NULLAbc_InfoHasBit(pCex->pData, iBit++) == 0Abc_InfoHasBit( (unsigned *)pAig->pData2, nObjs * pCex->iFrame + Aig_ObjId(Aig_ManCo(pAig, pCex->iPo)) )pAig->pData2 != NULLvoid Aig_ManCounterExampleValueStop(Aig_Man_t *)Id >= 0 && Id < Aig_ManObjNumMax(pAig)int Aig_ManCounterExampleValueLookup(Aig_Man_t *, int, int) Using counter-example, which asserts output %d in frame %d. Value of object %d in frame %d is %d. Control signal:Aig_ManDumpBlif(): AIG manager does not have POs.src/aig/aig/aigWin.cint Aig_ManFindCut_int(Vec_Ptr_t *, Vec_Ptr_t *, int, int)Aig_ObjIsNode(pFaninBest)Vec_PtrSize(vFront) <= nSizeLimitvoid Aig_ManFindCut(Aig_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *, int, int)Aig_ObjIsNode(pRoot)Aig_ObjChild0(pRoot)Aig_ObjChild1(pRoot)!pRoot->fMarkA!Aig_ObjFanin0(pRoot)->fMarkA!Aig_ObjFanin1(pRoot)->fMarkAint Aig_NodeGetLeafCostOne(Aig_Obj_t *, int)src/aig/saig/saigCone.cvoid Saig_ManSupport_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)Vec_Ptr_t *Saig_ManSupport(Aig_Man_t *, Vec_Ptr_t *)Saig_ObjIsPo(p, pObj)void Saig_ManPrintConeOne(Aig_Man_t *, Aig_Obj_t *) PO %3d nCurNew + nCurPrev + nCurOld == Vec_PtrSize(vCur)%d:%d %d=%d+%d+%d The format of this print-out: For each PO, x:a b=c+d+e, where - x is the time-frame counting back from the PO- a is the total number of registers in the COI of the PO so far- b is the number of registers in the COI of the PO in this time-frame- c is the number of registers in b that are new (appear for the first time)- d is the number of registers in b in common with the previous time-frame- e is the number of registers in b in common with other time-framessrc/aig/saig/saigConstr.cVec_Ptr_t *Saig_DetectConstrCollectSuper(Aig_Obj_t *)iOut >= 0 && iOut < Saig_ManPoNum(p)int Saig_ManDetectConstr(Aig_Man_t *, int, Vec_Ptr_t **, Vec_Ptr_t **)Vec_PtrSize(vSuper) >= 2Output %d : Structural analysis found %d original properties and %d constraints. Aig_Man_t *Saig_ManDupFoldConstrs(Aig_Man_t *, Vec_Int_t *)Entry > 0 && Entry < Saig_ManPoNum(pAig)The output is not an AND.There is no structural constraints.Cannot find special flop about the inputs of OR gate.Special flop input is complemented.There is no flop outputs.Collected constraints are not compatible.Simulating %d nodes and %d flops for %d frames with %d words... Primary output %d fails on some input patterns. Primary output : Constraint %3d : ProbOne = %f ProbOneC = %f AllZeroValue = %d src/aig/saig/saigConstr2.cint Saig_ManFilterUsingIndOne_new(Aig_Man_t *, Aig_Man_t *, sat_solver *, Cnf_Dat_t *, int, int, int)Aig_ManCoNum(pFrames) == Vec_VecSizeSize(vCands)void Saig_ManFilterUsingInd(Aig_Man_t *, Vec_Vec_t *, int, int, int)%d:%s%d p->pObjCopies == NULLAig_Man_t *Saig_ManUnrollCOI_(Aig_Man_t *, int)pAig->pObjCopies == NULLAig_Man_t *Saig_ManUnrollCOI(Aig_Man_t *, int)pCnf->pVarNums[i] > 0void Saig_CollectSatValues(sat_solver *, Cnf_Dat_t *, Vec_Ptr_t *, int *)int Saig_DetectTryPolarity(sat_solver *, int, int, Cnf_Dat_t *, Aig_Obj_t *, int, Vec_Ptr_t *, int *, int)Aig_ManCoNum(pFrames) == 1Vec_Vec_t *Ssw_ManFindDirectImplications(Aig_Man_t *, int, int, int, int)Found %3d candidates. Level %d. Cands =%d Found %3d constraints after filtering. Level %d. Constr =%d Vec_Vec_t *Saig_ManDetectConstrFunc(Aig_Man_t *, int, int, int, int)Detecting constraints with %d frames, %d conflicts, and %d propagations. Frames: The problem is trivially UNSAT (inductive with k=%d). Found %3d classes of candidates. nNewFlops == Vec_PtrSize(vNewFlops)Aig_Man_t *Saig_ManDupUnfoldConstrsFunc(Aig_Man_t *, int, int, int, int, int)Aig_ManConstrNum(pAig) < Saig_ManPoNum(pAig)Aig_Man_t *Saig_ManDupFoldConstrsFunc(Aig_Man_t *, int, int)src/aig/saig/saigUnfold2.cint Saig_ManFilterUsingIndOne2(Aig_Man_t *, Aig_Man_t *, sat_solver *, Cnf_Dat_t *, int, int, int, int)Aig_ManCoNum(pFrames) == Vec_VecSizeSize(vCands)*3void Saig_ManFilterUsingInd2(Aig_Man_t *, Vec_Vec_t *, int, int, int)i==0 type I : %d:%s%d type II: %d:%s%d nFrames == 1Vec_Vec_t *Ssw_ManFindDirectImplications2(Aig_Man_t *, int, int, int, int)#reg after unfold2: %d Aig_Man_t *Saig_ManDupFoldConstrsFunc2(Aig_Man_t *, int, int, int)#reg after fold2: %d Warning: Reached the limit on the number of patterns.Solver could not solve the original problem.Solver returned undecided.Filtered cands: Saig_ManPoNum(pAig) > 0src/aig/saig/saigDual.cAig_Man_t *Saig_ManDupDual(Aig_Man_t *, Vec_Int_t *, int, int, int, int, int, int)nDualPis >= 0 && nDualPis <= Saig_ManPiNum(pAig)vDcFlops == NULL || Vec_IntSize(vDcFlops) == Aig_ManRegNum(pAig)nCycles > 0void Saig_ManBlockPo(Aig_Man_t *, int)src/aig/saig/saigDup.cAig_Man_t *Saig_ManCreateEquivMiter(Aig_Man_t *, Vec_Int_t *, int)pObjLi->fMarkA == 0Aig_Man_t *Saig_ManDupAbstraction(Aig_Man_t *, Vec_Int_t *)pObjLo->fMarkA == 0p->vCiNumsOrig == NULLint Saig_ManVerifyCex(Aig_Man_t *, Abc_Cex_t *)int Saig_ManVerifyCexNoClear(Aig_Man_t *, Abc_Cex_t *)Abc_Cex_t *Saig_ManExtendCex(Aig_Man_t *, Abc_Cex_t *)int Saig_ManFindFailedPoCex(Aig_Man_t *, Abc_Cex_t *)Aig_ManRegNum(pAig) <= Vec_IntSize(vInit)Aig_Man_t *Saig_ManDupWithPhase(Aig_Man_t *, Vec_Int_t *)void Saig_ManDupCones_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *)CEX does fail the given sequential miter.Saig_ManExtendCex(): The counter-example is invalid!!!i && k && i < ksrc/aig/saig/saigInd.cint Saig_ManStatesAreEqual(sat_solver *, Vec_Int_t *, int, int, int)nRegs * k <= Vec_IntSize(vState)int Saig_ManAddUniqueness(sat_solver *, Vec_Int_t *, int, int, int, int *, int *, int)iVars <= nRegsfUnique == 0 || fUniqueAll == 0int Saig_ManInduction(Aig_Man_t *, int, int, int, int, int, int, int, int)Induction parameters: FramesMax = %5d. ConflictMax = %6d. Aig_ObjIsCi(pObjPiCopy)Aig_ManCoNum(pAigPart)-1 == Vec_IntSize(vTopVarNums)Aig_ObjIsCi(pObjPi)pObjPiCopy != NULLiReg >= 0 && iReg < Aig_ManRegNum(p)Vec_IntSize(vState)%Aig_ManRegNum(p) == 0Adding constaint for state %2d and state %2d. Frame %4d : PI =%5d. PO =%5d. AIG =%5d. Var =%7d. Clau =%7d. Conf =%7d. State %3d : Timeout (%d sec) was reached during iteration %d. Conflict limit (%d) was reached during iteration %d. Completed %d iterations and added %d uniqueness constraints. Completed %d iterations. SAT solver became UNSAT after adding a uniqueness constraint.Cannot constrain an incomplete state.pi%0*dpo%0*dlo%0*dsrc/aig/saig/saigIoa.cchar *Saig_ObjName(Aig_Man_t *, Aig_Obj_t *)# BLIF file written by procedure Saig_ManDumpBlif() # If unedited, this file can be read by Saig_ManReadBlif() # AIG stats: pi=%d po=%d reg=%d and=%d obj=%d maxid=%d .names %s 1 int Saig_ManReadNumber(Aig_Man_t *, char *)Aig_Obj_t *Saig_ManReadNode(Aig_Man_t *, int *, char *)Saig_ManDumpBlif(): Cannot open file for writing.Saig_ManReadBlif(): Check has failed.Saig_ManReadBlif(): Error 20.Saig_ManReadBlif(): Error 19.Saig_ManReadBlif(): Error 18.Saig_ManReadBlif(): Error 17.Saig_ManReadBlif(): Error 16.Saig_ManReadBlif(): Error 15.Saig_ManReadBlif(): Error 14.Saig_ManReadBlif(): Error 13.Saig_ManReadBlif(): Error 12.Saig_ManReadBlif(): Error 11.Saig_ManReadBlif(): Error 10.Saig_ManReadBlif(): Error 9.Saig_ManReadBlif(): Error 8.Saig_ManReadBlif(): Error 7.Saig_ManReadBlif(): Error 6.Saig_ManReadBlif(): Error 5.Saig_ManReadBlif(): Error 4.Saig_ManReadBlif(): Error 3.Saig_ManReadBlif(): Error 2.Saig_ManReadBlif(): Error 1.Saig_ManReadBlif(): Cannot open file for reading.Vec_IntSize(vPermCis) == Aig_ManCiNum(pAig)src/aig/saig/saigIso.cVec_Int_t *Saig_ManFindIsoPermCos(Aig_Man_t *, Vec_Int_t *)Aig_ObjIsConst1(pFanin) || pFanin->iData > 0void Saig_ManDupIsoCanonical_rec(Aig_Man_t *, Aig_Man_t *, Aig_Obj_t *)Aig_ObjFanin0(pObj)->iData != Aig_ObjFanin1(pObj)->iDataAig_ManCiNum(pAig1) == Aig_ManCiNum(pAig2)int Iso_ManCheckMapping(Aig_Man_t *, Aig_Man_t *, Vec_Int_t *, int)Aig_ManCoNum(pAig1) == Aig_ManCoNum(pAig2)Aig_ManRegNum(pAig1) == Aig_ManRegNum(pAig2)Aig_ManNodeNum(pAig1) == Aig_ManNodeNum(pAig2)Structural equivalence failed at node %d. Vec_IntSize(vPerm1_) == Aig_ManCiNum(pAig1)Vec_Int_t *Iso_ManFindMapping(Aig_Man_t *, Aig_Man_t *, Vec_Int_t *, Vec_Int_t *, int)Vec_IntSize(vPerm2_) == Aig_ManCiNum(pAig2)Entry >= 0 && Entry < Aig_ManCiNum(pAig1)%6d finished... Duplicate timeIsomorph timeAIGER timeSorting timeReduced %d outputs to %d outputs. int Vec_VecLevelSize(Vec_Vec_t *, int)AIG1:Structural equivalence failed at primary output 0.Nontrivial classes:Mapping of AIGs is NOT found.Mapping of AIGs is found.Aig_ObjIsCi(pObj) || Aig_ObjIsNode(pObj)src/aig/saig/saigIsoFast.cvoid Iso_StoCollectInfo_rec(Aig_Man_t *, Aig_Obj_t *, int, Vec_Int_t *, Iso_Dat_t *, Vec_Ptr_t *)*((int *)pThis) == 0pThis->nFoNeg + pThis->nFoPosAig_ObjIsCo(pPo)Vec_Int_t *Iso_StoCollectInfo(Iso_Sto_t *, Aig_Obj_t *)p->pCounters[Entry]Vec_IntEntry(p->vVisited, pPerm[0]) <= Vec_IntEntry(p->vVisited, pPerm[Vec_IntSize(p->vVisited)-1])Info computation timeSorting timeDevided %d outputs into %d cand equiv classes. Unique = %d nSize >= (1<<10)src/aig/saig/saigIsoSlow.cvoid Iso_ReadPrimes(char *)0x%08x,void Iso_ManObjCount(Aig_Man_t *, Aig_Obj_t *, int *, int *)Building Hashing Aig_ObjIsCi(pIso1) || Aig_ObjIsCo(pIso1)int Iso_ObjCompareByData(Aig_Obj_t **, Aig_Obj_t **)Aig_ObjIsCi(pIso2) || Aig_ObjIsCo(pIso2)void Iso_ManCollectClasses(Iso_Man_t *)Vec_PtrSize(p->vSingles) == p->nSinglesVec_PtrSize(p->vClasses) == p->nClassespIso->FaninSig == 0Iso_Man_t *Iso_ManCreate(Aig_Man_t *)pIso->FanoutSig == 0!Aig_ObjIsCo(pObj) || pIso->Id == 0void Iso_ManAssignAdjacency(Iso_Man_t *)Total objects =%7d. Entries =%7d. Classes =%7d. Singles =%7d. %5d : { %d{%s%d(%d),%s%d(%d)}pTemp->Id == 0void Iso_ManRehashClassNodes(Iso_Man_t *)pTemp->Id != 0Iso_Obj_t *Iso_ManFindBestObj(Iso_Man_t *, Iso_Obj_t *)Best level %d void Iso_ManBreakTies(Iso_Man_t *, int)p->nClasses == 0Vec_Int_t *Iso_ManFinalize(Iso_Man_t *)Vec_PtrSize(p->vClasses) == 0pObj->iData > 0p->nClasses > 0void Iso_ManDumpOneClass(Iso_Man_t *)p->nObjIds == 1+Aig_ManCiNum(p->pAig)+Aig_ManNodeNum(p->pAig)Vec_Int_t *Saig_ManFindIsoPerm(Aig_Man_t *, int)Iso_Obj_t *Iso_ManObj(Iso_Man_t *, int)int Iso_ObjId(Iso_Man_t *, Iso_Obj_t *)87%м޾{~~0?`tN9k *| M}o t3[8T6o?JF:Sޭ#<Pt~5EϖZkhIړϔBBR!2XjKS"bGݾ#&*UY4З.67ks"f܋.{]|tUʊtkP/#>W4hN^ Q'*9>(|7pQ|z{}.^jI}[UKIUj5XH;8K.*廌i; Vb %Kk=2dv7?7DwK+.1^#[Ɣz!52WdO_ncN{T}"[EyCQU弔!/og:Iy%7dʯt|P>t WPeo<_º2!p`&(OeR V&rj)ľU/Len4O_3(&H}=RW(:qQtޙzMRDoZF{Əi49>42yLl(yۣ8KT 5U*B5QX  ~V>qS$!tBJyt K9z 2.%-i_HE7{UJ2Q#y*M8A(r"7K ,QWڄw>>G,E( d8FmG <$e5tyNJm[ ̄u[2)rnZ4f^1+Ǎ,Ȩ-P؜hf8.t^CM*Ŏ<ܮXA>zZ;ZHoY Z:k 0PD\i%^: t+O⁏rM.tG/݂OfižԢުGɤTpI@ ,uј,\],Y7[?8/Ebr\4֦,CwBPd(C)1!թ9ޥ;gJ; DUٙ#u(YYi&1\lc߻A=ƪL )^Lg",Lb/FwO"\ mXGM!z`aBÿQYwDLu j~J>ËHM}@y :)l {r1#Hi O~9xGEZ'R &$0ox@C>)D R%]o O Oị 9&V4A]ey}]/{FޒofuBk6iȯlL~7\eunrK:K/4smqq;I0DѿeF]֞`gU`/ Ȗj-OmqY&usL$j%d@XDJ"W4VpתK @<40OA45& .pzaK.B=ȹɜ /-&StQ佧}m;^!fYs)̫fn 32׮7au'fKd2a/w7KU{lVY%ۇ.8NXRx9 ;2Z?{:^1?F^RʘJ̆Ipu*X!8.)Q>=WOiÚqy@e?#n3&l[i)*E5u@UfzɨSi{śIIXgYHUHza!E!b6.ˆueK r80F{dhؾiڽސz c#.QVswX 8/ ^%0ܜh`Db'd}4=L&h@'B,<]H$GJ("'IaJ-Sy]W(}mż 6s7rbSf]]AZks 6{}#h8p V "E)DMdz3 45 mg̠}Z-n-Z2,N_q,p sAK$CQk*ƧVQ8YTR"tTVuBN@ݝĆM?o;1 ]t=dI29 °[)s5@*ys 3ggڸB|f @4pAU~~%mN1+`E@Q3+/l KX mT$wO 4eo fq݇ glrC!ջRBJ[]њDU>iOHe[H c^`}X @DF#"jo6mшT ]U'Djc:.h83W#ɵ4&/n<#'X5 Fߵ0w IANGc Hq!@ h6M>k0ɗ6/x9s#Yf1f֩rD-89)_)X3yn-#[ba|)'>z $%%H꘽&]<-a*`QKЇáU V.0POݖ x:ݝXdV|g#<~w_al@oԆeXy}( ^&q6kȈg"9aSXǓc < -/7>ɂM=T',S"]اgSA4r会VHLNEY,KU7^cYUO{bNPhs|׏,]00KlY`FWǿnL̇ock[d1EcY$!(ˊ+Aaק~?%'M/,&^.׼%>Z:\a97-hO 5e|N5'PȴcIF`l:PqQo.K.e,'SB8-ufJ%7**TLM\JeQ2 Ni33 1'vБмnT0=QRcn#/k`!G!|އ9Ba9T~+/M-Ri@WhJ4& K⭚<"ˑ#]2?Y9D c@oDoƺ(qQ6R5 |9LRZf3'[5Ld&m\8BPמ!M1J$S.47I'kyM00F4tw Zc퍥E8%f o< ?^aDq.SYxo9R+R b p^z,C4M 8b(wkaBb{ƨRΆF6~;@5yB%{jv;rHr0WR3 "tp"Ht@ͻ}\)oθчUNon-trivial classes:Saig_ManRegNum(p0) > 0 || Saig_ManRegNum(p1) > 0src/aig/saig/saigMiter.cAig_Man_t *Saig_ManCreateMiter(Aig_Man_t *, Aig_Man_t *, int)Saig_ManPiNum(p0) == Saig_ManPiNum(p1)Saig_ManPoNum(p0) == Saig_ManPoNum(p1)Aig_Man_t *Saig_ManCreateMiterComb(Aig_Man_t *, Aig_Man_t *, int)Saig_ManPiNum(pBot) == Saig_ManPiNum(pTop)Aig_Man_t *Saig_ManUnrollTwo(Aig_Man_t *, Aig_Man_t *, int)Saig_ManPoNum(pBot) == Saig_ManPoNum(pTop)Saig_ManRegNum(pBot) == Saig_ManRegNum(pTop)Saig_ManRegNum(pBot) > 0 || Saig_ManRegNum(pTop) > 0Aig_Regular(pObj)->pData != NULLAig_Man_t *Aig_ManDupNodesHalf(Aig_Man_t *, Vec_Ptr_t *, int)Saig_ManRegNum(p) % 2 == 0int Saig_ManDemiterSimple(Aig_Man_t *, Aig_Man_t **, Aig_Man_t **)The output number %d of the miter is constant 1. int Saig_ManDemiterCheckPo(Aig_Man_t *, Aig_Obj_t *, Aig_Obj_t **, Aig_Obj_t **)The output number %d cannot be demitered. void Saig_ManDemiterLabel_rec(Aig_Man_t *, Aig_Obj_t *, int)Aig_Obj_t *Saig_ManGetLabeledRegister_rec(Aig_Man_t *, Aig_Obj_t *)Saig_ManRegNum(p) > 0int Saig_ManDemiter(Aig_Man_t *, Aig_Man_t **, Aig_Man_t **)Ouput pair %4d: Difficult case... The miters contains %d flops reachable from both AIGs. Primary output %d has failed in frame %d. Flop input %d has failed in the last frame. The counter-example detected %d incorrect POs or flop inputs. int Ssw_SecSpecialMiter(Aig_Man_t *, Aig_Man_t *, int, int)Aig_ManRegNum(pPart0) == Aig_ManRegNum(pPart1)Output %3d : AND Yes NoOR with %d inputs TerminalThe miter cannot be demitered.Counter-example is not available.Demitering has failed.After demitering AIGs have different number of flops. Quitting.Performing sequential verification using combinational A/B miter.nLits == 1 || nLits == 2src/aig/saig/saigOutDec.cVec_Ptr_t *Saig_ManFindPrimes(Aig_Man_t *, int, int)Adding prime %d%c Adding prime %d%c %d%c Property cone size = %6d 1-lit primes = %5d 2-lit primes = %5d EQGyU)] C k 1 g # ]  a  = WCg!i Y 7yEm!k)_=u#{7qQ!QAsE5c/Kg{p->vNonXRegs == NULLsrc/aig/saig/saigPhase.cint Saig_TsiCountNonXValuedRegisters(Saig_Tsim_t *, int)ValueThis != 0Vec_Int_t *Saig_TsiComputeTransient(Saig_Tsim_t *, int)void Saig_TsiPrintTraces(Saig_Tsim_t *, int, int, int)int Saig_TsiComputePrefix(Saig_Tsim_t *, unsigned int *, int)!Saig_TsiStateLookup( p, pState, nWords )void Saig_TsiStateInsert(Saig_Tsim_t *, unsigned int *, int)void Saig_TsiStatePrint(Saig_Tsim_t *, unsigned int *)Ternary simulation converged after %d iterations. Saig_ManReachableTernary(): Did not reach a fixed point after %d iterations (not a bug). pReg->Id < pCtrl->Idvoid Saig_ManAnalizeControl(Aig_Man_t *, int)nFrames <= 256int Saig_ManFindRegisters(Saig_Tsim_t *, int, int, int)Value == SAIG_XVS0 || Value == SAIG_XVS1Register %5d has generator: [Found %3d useful registers. Vec_IntSize(pTsi->vNonXRegs) > 0Aig_Man_t *Saig_ManPerformAbstraction(Saig_Tsim_t *, int, int)int Saig_ManPhaseFrameNum(Aig_Man_t *, Vec_Int_t *)int Saig_ManPhasePrefixLength(Aig_Man_t *, int, int, Vec_Int_t **)Lead = %5d. Loop = %5d. Total flops = %5d. Binary flops = %5d. Aig_Man_t *Saig_ManPhaseAbstract(Aig_Man_t *, Vec_Int_t *, int, int, int, int, int)The cycle (%d) is not modulo the number of frames (%d). Phase abstraction cannot be done. There is no registers to abstract with %d frames. Aig_Man_t *Saig_ManPhaseAbstractAuto(Aig_Man_t *, int)pNew->nBits == pNew->nPis * (iFrame + 1) + pNew->nRegsAbc_Cex_t *Saig_PhaseTranslateCex(Aig_Man_t *, Abc_Cex_t *)i <= pCex->nBitsValue0 == SAIG_XVS1 && Value1 == SAIG_XVS1int Saig_XsimAnd(int, int)Value == SAIG_XVSXint Saig_XsimInv(int)void Saig_XsimPrint(FILE *, int)Their fanout: Ternary traces for each flop:Clock-like register: Control register: Fanouts of the fanout: Register is not found.All registers have X-valued states. Phase abstraction cannot be done.The cycle of ternary states is trivial. Phase abstraction cannot be done.The number of frames is more than 256. Phase assignment is not performed.The number of frames is less than 2. Phase assignment is not performed.Print-out finished. Phase assignment is not performed.The PI count in the AIG and in the CEX do not match.nFanouts < nFanoutsAllocsrc/aig/saig/saigRetFwd.cAig_Obj_t **Aig_ManStaticFanoutStart(Aig_Man_t *)pObjLo->pFanin0 && pObjLi->nRefs == 1void Saig_ManMarkAutonomous(Aig_Man_t *)%2d : And = %6d. Reg = %5d. Unret = %5d. Move = %6d. RetValue != l_Undefsrc/aig/saig/saigRetMin.cVec_Int_t *Saig_ManRetimeInitState(Aig_Man_t *)int Saig_ManRetimeUnsatCore(Aig_Man_t *, int)UNSAT core: %d clauses, %d variables, %d POs. void Saig_ManRetimeDup_rec(Aig_Man_t *, Aig_Obj_t *)Vec_Ptr_t *Saig_ManGetRegistersToExclude(Aig_Man_t *)Vec_PtrSize(vNodes) == DiffsnTruePi == p->nTruePisint Saig_ManHideBadRegs(Aig_Man_t *, Vec_Ptr_t *)nTruePo == p->nTruePosnTruePi == Aig_ManCiNum(p)nTruePo == Aig_ManCoNum(p)Excluding %d registers that cannot be backward retimed. Excluding register %d. Assuming const-0 init-state after backward retiming. Result will not verify.Backward retiming cannot reduce registers.Forward retiming cannot reduce registers.src/aig/saig/saigRetStep.cAig_Obj_t *Saig_ManRetimeNodeFwd(Aig_Man_t *, Aig_Obj_t *, int)Aig_ObjCioId(pFanin0) > 0Aig_ObjCioId(pFanin1) > 0Aig_Obj_t *Saig_ManRetimeNodeBwd(Aig_Man_t *, Aig_Obj_t *)Aig_ObjCioId(pObjLo) > 0Saig_ObjIsLo(p, pObjLo)int Saig_ManRetimeSteps(Aig_Man_t *, int, int, int)Introducing bug during retiming.Network has %d (out of %d) registers driving POs. Network has %d (out of %d) registers driven by PIs. src/aig/saig/saigScl.cint Saig_ManReportComplements(Aig_Man_t *)!pObj->fMarkAiWord == p->nWordssrc/aig/saig/saigSimFast.cFaig_Man_t *Faig_ManCreate(Aig_Man_t *)seqsimframesThe total number of frames (%d) should exceed prefix (%d). Setting the total number of frames to be %d. Counter == pAig->nObjsVec_Int_t *Faig_ManComputeSwitchProbs4(Aig_Man_t *, int, int, int)Faig_CheckIdLo(p,i)int Faig_ObjLoToLi(Faig_Man_t *, int)Faig_CheckIdNo(p,i)int Faig_ObjIdToNumNo(Faig_Man_t *, int)Faig_CheckIdCo(p,i)int Faig_ObjIdToNumCo(Faig_Man_t *, int) :|KUΧUn`Y0  ` 0  `Y0  ` 0  src/aig/saig/saigSimMv.cSaig_MvObj_t *Saig_ManCreateReducedAig(Aig_Man_t *, Vec_Ptr_t **)Saig_MvMan_t *Saig_MvManStart(Aig_Man_t *, int) *void Saig_MvSimulateFrame(Saig_MvMan_t *, int, int)The number of registers that never became undef = %d. (Total = %d.) FLOP %5d : (%3d) Saig_MvIsConst0( Vec_IntEntry(vValues,0) )int Saig_MvManCheckOscilator(Saig_MvMan_t *, int)Saig_MvIsConst0( Vec_IntEntry(vValues,Per) )Detected %d const0 flops and %d pairs of equiv binary flops. nFramesSymb >= 1 && nFramesSymb <= nFramesSaturVec_Ptr_t *Saig_MvManSimulate(Aig_Man_t *, int, int, int, int)Constructing the problemBegining to saturate simulation after %d frames Agressively saturating simulation after %d frames Converged after %d frames with lasso in state %d. Cycle = %d. Multi-valued simulationint Saig_MvHash(int, int, int)src/aig/saig/saigSimSeq.cint Raig_ManCreate_rec(Raig_Man_t *, Aig_Obj_t *)Vec_IntSize(p->vCis2Ids) == Aig_ManCiNum(pAig)Raig_Man_t *Raig_ManCreate(Aig_Man_t *)p->nObjs == nObjsp->pRefs[ pObj->iData ] == 0i > 1unsigned int *Raig_ManSimRef(Raig_Man_t *, int)p->pSims[i] == 0unsigned int *Raig_ManSimDeref(Raig_Man_t *, int)p->pSims[i] > 0Vec_IntEntry(p->vLos, iPioNum-p->nPis) == iint Raig_ManSimulateRound(Raig_Man_t *, int, int, int *)pRes[0] == 1pRes[0] > 0nCis == p->nCisnCos == p->nCosp->nMems == 1 + Vec_IntSize(p->vLis)int Raig_ManSimulate(Aig_Man_t *, int, int, int, int, int)Miter is trivially satisfiable (output %d). Frame %4d out of %4d and timeout %3d sec. Time = %7.2f sec Miter is satisfiable after simulation (output %d). No bug detected after %d frames with time limit %d seconds. Maxcut = %8d. AigMem = %7.2f MB. SimMem = %7.2f MB. Miter is trivially unsatisfiable.i < SAIG_WORDS - 1src/aig/saig/saigStrSim.cvoid Saig_StrSimTransferNext(Aig_Obj_t *, Aig_Obj_t *, int)Aig_ObjRepr(p1, pObj1) == pObj0void Saig_StrSimulateRound(Aig_Man_t *, Aig_Man_t *)pObj0 == Aig_ObjRepr( p1, pObj1 )void Saig_StrSimSetFinalMatching(Aig_Man_t *, Aig_Man_t *)Aig_ObjIsNode(pObj1)Saig_ObjIsLo(p1, pObj1)Total matches = %6d. Wrong matches = %6d. Ratio = %5.2f %% void Saig_StrSimSetContiguousMatching_rec(Aig_Man_t *, Aig_Obj_t *)void Saig_StrSimSetContiguousMatching(Aig_Man_t *, Aig_Man_t *)void Ssw_StrSimMatchingExtendOne(Aig_Man_t *, Vec_Ptr_t *)pNext0 == Aig_ObjRepr( p1, pNext1 )void Ssw_StrSimMatchingExtend(Aig_Man_t *, Aig_Man_t *, int, int)pNext1 == Aig_ObjRepr( p0, pNext0 )Allocated %6.2f MB to simulate the first AIG. Allocated %6.2f MB to simulate the second AIG. %3d : Match =%6d. FF =%6d. (%6.2f %%) Node =%6d. (%6.2f %%) pObj0 == Aig_ObjRepr(pPart1, pObj1)Vec_Int_t *Saig_StrSimPerformMatching(Aig_Man_t *, Aig_Man_t *, int, int, Aig_Man_t **)1   src/aig/saig/saigSwitch.cSaig_SimObj_t *Saig_ManCreateMan(Aig_Man_t *)void Saig_ManSimulateFrames(Saig_SimObj_t *, int, int)p->iNode == 1 + p->nIns + p->nNodes + p->nOutsvoid Aig_CManRestart(Aig_CMan_t *)p->pCur - p->Data < p->nBytes - 10void Aig_CManStoreNum(Aig_CMan_t *, unsigned int)void Aig_CManAddNode(Aig_CMan_t *, int, int)iFan1 < (p->iNode << 1) Bytes alloc = %5d. Bytes used = %7d. Ave per node = %4.2f. iPat < 16 * nWordssrc/aig/saig/saigSynch.cint Saig_SynchSavePattern(Aig_Man_t *, Vec_Ptr_t *, int, int, Vec_Str_t *)Vec_StrSize(vSequence) % Saig_ManPiNum(pAig) == 0int Saig_SynchSequenceRun(Aig_Man_t *, Vec_Ptr_t *, Vec_Str_t *, int)Value != 2Vec_Str_t *Saig_SynchSequence(Aig_Man_t *, int)nTerCur == nTerCur2Count not initialize %d registers. Aig_ManNodeNum(pNew) == Aig_ManNodeNum(p)Aig_Man_t *Saig_ManDupInitZero(Aig_Man_t *)Design 1: Synchronizing sequence is not found. Design 1: Synchronizing sequence of length %4d is found. Aig_Man_t *Saig_SynchSequenceApply(Aig_Man_t *, int, int)Design 1: Design 2: Design 2: Synchronizing sequence is not found. Design 2: Synchronizing sequence of length %4d is found. Aig_Man_t *Saig_Synchronize(Aig_Man_t *, Aig_Man_t *, int, int)Miter of the synchronized designs is constructed. v == 0 || v == 1 || v == 3unsigned int Saig_SynchTernary(int)Quitting synchronization.Aig_ManCoNum(pFrames) == Aig_ManRegNum(pAig)src/aig/saig/saigTempor.cAig_Man_t *Saig_ManTemporDecompose(Aig_Man_t *, int)nFrames >= 0Aig_Man_t *Saig_ManTempor(Aig_Man_t *, int, int, int, int, int, int, int)Reducing frame count from %d to %d to fit the last transient. Using computed frame number (%d). Using user-given frame number (%d). A cex found in the first %d frames. BMC for %d frames could not be completed. A cex may exist! iLastBefore < nFramesFinishedBMC succeeded to frame %d. Adjusting frame count to be (%d) based on the last transient signal. The leading sequence has length 1. Temporal decomposition is not performed.The leading sequence has length 0. Temporal decomposition is not performed.pFrames->pReprs != NULLsrc/aig/saig/saigTrans.cvoid Saig_ManCreateMapping(Aig_Man_t *, Aig_Man_t *, int)Aig_Man_t *Saig_ManFramesNonInitial(Aig_Man_t *, int)nFrames <= nFramesMaxAig_Man_t *Saig_ManFramesInitialMapped(Aig_Man_t *, int, int, int)iNum2 != -1f >= iFrame2Aig_Man_t *Saig_ManTimeframeSimplify(Aig_Man_t *, int, int, int, int)MappedNormal!Saig_ManHasMap1(pAig)!Saig_ManHasMap2(pAig)p->pData2 == NULLvoid Saig_ManStartMap2(Aig_Man_t *, int)void Saig_ManSetMap2(Aig_Man_t *, Aig_Obj_t *, int, Aig_Obj_t *, int)p->pData2 != NULLvoid Saig_ManStopMap2(Aig_Man_t *)p->pData == NULLvoid Saig_ManStartMap1(Aig_Man_t *, int)void Saig_ManSetMap1(Aig_Man_t *, Aig_Obj_t *, int, Aig_Obj_t *)void Saig_ManStopMap1(Aig_Man_t *)src/aig/saig/saigWnd.cvoid Saig_ManWindowOutline_rec(Aig_Man_t *, Aig_Obj_t *, int, Vec_Ptr_t *, int *)Aig_ObjIsTravIdCurrent(p, pObjLi) == Aig_ObjIsTravIdCurrent(p, pObjLo)Vec_Ptr_t *Saig_ManWindowOutline(Aig_Man_t *, Aig_Obj_t *, int)Aig_Obj_t *Saig_ObjHasUnlabeledFanout(Aig_Man_t *, Aig_Obj_t *)Vec_Ptr_t *Saig_ManWindowCollectPis(Aig_Man_t *, Vec_Ptr_t *)Aig_ObjIsNode(pObjBig)void Saig_ManWindowInsertBig_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *)i == Saig_ManPiNum(pWnd)Aig_Man_t *Saig_ManWindowInsertNodes(Aig_Man_t *, Vec_Ptr_t *, Aig_Man_t *)i == Saig_ManPoNum(pWnd)Aig_ManCiNum(pNew) - Aig_ManCiNum(p) == Aig_ManCoNum(pNew) - Aig_ManCoNum(p)Aig_ManNodeNum(p) > 1Aig_Obj_t *Saig_ManFindPivot(Aig_Man_t *)Aig_Man_t *Saig_ManWindowTest(Aig_Man_t *)Vec_Ptr_t *Saig_ManCollectedDiffNodes(Aig_Man_t *, Aig_Man_t *)Aig_ObjIsTravIdCurrent(p0, pObj0) == Aig_ObjIsTravIdCurrent(p0, pObj1)pFanin == Aig_ObjRepr( p1, pMatch )void Saig_ManWindowCreatePis(Aig_Man_t *, Aig_Man_t *, Aig_Man_t *, Vec_Ptr_t *)void Saig_ManWindowCreatePos(Aig_Man_t *, Aig_Man_t *, Aig_Man_t *)Aig_ObjIsTravIdCurrent(p0, pFanin0) == Aig_ObjIsTravIdCurrent(p1, pFanin1)Aig_ObjIsNode(pObj0)pMatch0 == Aig_ObjRepr( p1, pMatch1 )Aig_Man_t *Saig_ManWindowExtractMiter(Aig_Man_t *, Aig_Man_t *)Aig_ObjIsNode(pObjSmall)void Saig_ManWindowInsertSmall_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *)The window cannot be reinserted because PI/PO counts do not match.src/aig/gia/giaAig.cvoid Gia_ManFromAig_rec(Gia_Man_t *, Aig_Man_t *, Aig_Obj_t *)void Gia_ManFromAigChoices_rec(Gia_Man_t *, Aig_Man_t *, Aig_Obj_t *)iObjNew > iNextNewGia_ObjIsAnd(Gia_ManObj(pNew, iNextNew))Gia_Man_t *Gia_ManFromAigChoices(Aig_Man_t *)Gia_Man_t *Gia_ManFromAigSimple(Aig_Man_t *)void Gia_ManToAig_rec(Aig_Man_t *, Aig_Obj_t **, Gia_Man_t *, Gia_Obj_t *)!fChoices || (p->pNexts && p->pReprs)Aig_Man_t *Gia_ManToAig(Gia_Man_t *, int)p->pNexts == NULL && p->pReprs == NULLAig_Man_t *Gia_ManToAigSkip(Gia_Man_t *, int)nOutDelta > 0 && Gia_ManCoNum(p) % nOutDelta == 0Aig_Man_t *Gia_ManToAigSimple(Gia_Man_t *)i == 0 || Aig_ObjId(ppNodes[i]) == ivoid Gia_ManReprToAigRepr(Aig_Man_t *, Gia_Man_t *)pGia->pReprs != NULLi == 0 || !Abc_LitIsCompl(pObj->iData)void Gia_ManReprToAigRepr2(Aig_Man_t *, Gia_Man_t *)void Gia_ManReprFromAigRepr(Aig_Man_t *, Gia_Man_t *)pGia->pReprs == NULLGia_ManObjNum(pGia) - Gia_ManCoNum(pGia) == Aig_ManObjNum(pAig) - Aig_ManCoNum(pAig)i == 0 || !Abc_LitIsCompl(Gia_ObjValue(pObjGia))void Gia_ManReprFromAigRepr2(Aig_Man_t *, Gia_Man_t *)Counter-example verification has failed. src/aig/gia/giaAgi.cAgi_Man_t *Agi_ManFromGia(Gia_Man_t *)Agi_ObjIsAnd(p, i)int Agi_ManSuppSize_rec(Agi_Man_t *, int)int Agi_ManAppendAnd(Agi_Man_t *, int, int)p->nObjs < p->nCapint Agi_ManAppendObj(Agi_Man_t *)hhw0*V3 E 5[\X%Vec_IntSize(vNodes) == i + 1 + nInputs + nLatchessrc/aig/gia/giaAiger.cGia_Man_t *Gia_AigerReadFromMemory(char *, int, int, int, int)Wrong name format. The output number (%d) is out of range. The output number (%d) is listed twice. constraint:invariant:Recognized and added %d constraints. Recognized and skipped %d invariants. Gia_AigerReadInt(pCur) == 4pCur == pCurTempGia_AigerReadInt(pCur) == 4*Gia_ManRegNum(pNew)Gia_AigerReadInt(pCur) == 4*Gia_ManObjNum(pNew)nSize % 4 == 0!Gia_ManHasChoices(pNew)Vec_IntSize(vInits) == Gia_ManRegNum(pNew)Vec_IntEntry(vInits, i) == Abc_Var2Lit(Gia_ObjId(pNew, pObj), 0)Structural hashing enabled while reading AIGER invalidated the mapping. Consider using "&r -s". pNew->pSpec == NULLGia_Man_t *Gia_AigerRead(char *, int, int, int)aig Vec_Str_t *Gia_AigerWriteIntoMemoryStr(Gia_Man_t *)Vec_Str_t *Gia_AigerWriteIntoMemoryStrPart(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, int)pInit->nXors == 0 && pInit->nMuxes == 0void Gia_AigerWrite(Gia_Man_t *, char *, int, int, int)Gia_AigerWrite(): Cannot open the output file "%s". p->fGiaSimple || Gia_ManBufNum(p) || uLit0 < uLit1Vec_PtrSize(p->vNamesIn) == Gia_ManCiNum(p)Vec_PtrSize(p->vNamesOut) == Gia_ManCoNum(p)Vec_IntSize(p->vFlopClasses) == Gia_ManRegNum(p)Vec_IntSize(p->vGateClasses) == Gia_ManObjNum(p)i > Gia_ObjSibl(p, i)Vec_IntSize(p->vObjClasses) == Gia_ManObjNum(p) This file was produced by the GIA package in ABC on %s %s%0*d.aigGia_AigerWriteSimple(): Cannot open the output file "%s". Gia_FileSize(): The file is unavailable (absent or open).Warning: Creating unit-delay box delay tables because box library is not available.Cleanup removed objects after reading. Old gate/object abstraction maps are invalid!Cannot read extension "w" because AIG is rehashed. Use "&r -s ".Gia_AigerWrite(): AIGER generation has failed because the allocated buffer is too small.AIG cannot be written because it has no POs.Gia_AigerWriteSimple(): AIG cannot be written because it has no POs.src/aig/gia/giaAigerExt.cGia_Rpr_t *Gia_AigerReadEquivClasses(unsigned char **, int)p->pReprs && p->pNextsunsigned char *Gia_WriteEquivClassesInt(Gia_Man_t *, int *)iOffset <= nAllocint *Gia_AigerReadMapping(unsigned char **, int)unsigned char *Gia_AigerWriteMappingInt(Gia_Man_t *, int *)int *Gia_AigerReadMappingSimple(unsigned char **, int)Vec_IntSize(p->vMapping) >= Gia_ManObjNum(p)Vec_Str_t *Gia_AigerWriteMappingSimple(Gia_Man_t *)nSize2 == nSizeVec_Str_t *Gia_AigerWriteMappingDoc(Gia_Man_t *)Vec_Int_t *Gia_AigerReadPacking(unsigned char **, int)@{Gzt?src/aig/gia/giaBalAig.cvoid Gia_ManSuperCollectXor_rec(Gia_Man_t *, Gia_Obj_t *, int)!Gia_ObjFaninC0(pObj) && !Gia_ObjFaninC1(pObj)void Gia_ManSuperCollect(Gia_Man_t *, Gia_Obj_t *, int)Vec_IntSize(p->vSuper) > 0nSize > 2void Gia_ManPrepareLastTwo(Gia_Man_t *, Vec_Int_t *)int Gia_ManBalanceGate(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, int *, int)Vec_IntSize(vSuper) == 1void Gia_ManBalance_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *, int)Vec_IntSize(p->vStore) == iEnd!fStrict || Gia_ManObjNum(pNew) <= Gia_ManObjNum(p)Gia_Man_t *Gia_ManBalanceInt(Gia_Man_t *, int)!Abc_LitIsCompl(pSet[k])void Dam_ManCreateMultiRefs(Dam_Man_t *, Vec_Int_t **, Vec_Int_t **)void Dam_ManCreatePairs(Dam_Man_t *, int)Num == Hash_IntManEntryNum(p->vHash)Num == Vec_FltSize(p->vCounts)Num == Vec_IntSize(p->vDiv2Nod)Vec_FltSize(p->vCounts) == Hash_IntManEntryNum(p->vHash)+1Vec_IntSize(p->vDiv2Nod) == nDivsUsed+1Pairs: Total =%9d (%6.2f %%) Tried =%9d (%6.2f %%) Used =%9d (%6.2f %%) Xor =%9d (%6.2f %%)Div: void Dam_ManMultiAig_rec(Dam_Man_t *, Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *)Gia_ObjIsXor(pObj) || Gia_ObjIsAndReal(p, pObj)Final statistics after extracting %6d divisors: Div%5d : D%-8d = %8s Weight %9.2f Ands =%8d F = %c%c %c%c pNods[0] >= 2void Dam_ManUpdate(Dam_Man_t *, int)Dam_DivSet(p, i)[0] == Hash_IntObjData2(p->vHash, i) Total =%9d (%6.2f %%) Gain =%6d (%6.2f %%) GainX = %d Divisor queue: ??pCutsR[nCutsR]->Delay == Targetsrc/aig/gia/giaBalLut.cint Bal_ManDeriveCuts(Bal_Man_t *, int, int, int, int, int, int, int, int, int, int, int, int)nCutsR > 0 && nCutsR < p->nCutNumVec_PtrSize(p->vCutSets) == Gia_ManObjNum(p->pNew)Vec_IntSize(p->vCosts) == Gia_ManObjNum(p->pNew)int Bal_ManSetGateLevel(Bal_Man_t *, Gia_Obj_t *, int)int Bal_SetCutIsContainedOrder(Bal_Cut_t *, Bal_Cut_t *)int Bal_SetCheckArray(Bal_Cut_t **, int)pCut0->nLeaves <= BAL_LEAF_MAXpCut0->Sign == Bal_CutGetSign(pCut0->pLeaves, pCut0->nLeaves)Best delay = %d void Gia_ManBalance_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *)void Gia_ManSuperCollect(Gia_Man_t *, Gia_Obj_t *)void Gia_ManSuperCollectXor_rec(Gia_Man_t *, Gia_Obj_t *)iBeg <= iEndint Bal_ManFindBestPair(Bal_Man_t *, Vec_Int_t *, Gia_Obj_t *)int Vec_IntFindFirstSameDelayAsLast(Bal_Man_t *, Vec_Int_t *)DelayCur >= Delay{GzThe maximum mapped level (%d) is less than the target level (%d). The maximum AIG level (%d) is less than the target level (%d). !LevelMax != !nTimeWindowsrc/aig/gia/giaBalMap.cGia_Man_t *Gia_ManExtractWindow(Gia_Man_t *, int, int, int)Collected %d outputs to extract. Gia_Man_t *Gia_ManPerformSopBalanceWin(Gia_Man_t *, int, int, int, int, int)Gia_Man_t *Gia_ManPerformDsdBalanceWin(Gia_Man_t *, int, int, int, int, int, int)src/aig/gia/giaBidec.cunsigned int *Gia_ManConvertAigToTruth_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, int, Vec_Int_t *)int Gia_ObjPerformBidec(Bdc_Man_t *, Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Gia_ManPerformBidec() node count before and after: %6d and %6d. Resynthesis is not performed when nodes have more than 15 inputs.Resynthesis is not performed when nodes have less than 2 inputs.nFrameMax > 0src/aig/gia/giaCCof.cCcf_Man_t *Ccf_ManStart(Gia_Man_t *, int, int, int, int)void Gia_ManCofOneDerive_rec(Ccf_Man_t *, int)int Gia_ManCofGetReachable(Ccf_Man_t *, int)%3d : AIG =%7d Conf =%7d. Gia_Man_t *Gia_ManCofTest(Gia_Man_t *, int, int, int, int)ITER %3d : Property failed in frame %d. Runtime limit (%d sec) is reached after %d frames. Completed %d frames without converging. Backward reachability converged after %d iterations. Conflict limit or timeout is reached after %d frames. Property holds.Property is undecided.src/aig/gia/giaCex.cint Gia_ManVerifyCex(Gia_Man_t *, Abc_Cex_t *, int)Gia_ManPiNum(pAig) == p->nPisint Gia_ManFindFailedPoCex(Gia_Man_t *, Abc_Cex_t *, int)int Gia_ManSetFailedPoCex(Gia_Man_t *, Abc_Cex_t *)void Gia_ManCounterExampleValueStart(Gia_Man_t *, Abc_Cex_t *)pGia->pData2 == NULLAbc_InfoHasBit( (unsigned *)pGia->pData2, nObjs * pCex->iFrame + Gia_ObjId(pGia, Gia_ManCo(pGia, pCex->iPo)) )pGia->pData2 != NULLvoid Gia_ManCounterExampleValueStop(Gia_Man_t *)Id >= 0 && Id < Gia_ManObjNum(pGia)int Gia_ManCounterExampleValueLookup(Gia_Man_t *, int, int)Abc_Cex_t *Gia_ManCexExtendToIncludeCurrentStates(Gia_Man_t *, Abc_Cex_t *)iBit == pCex->nRegsAbc_Cex_t *Gia_ManCexExtendToIncludeAllObjects(Gia_Man_t *, Abc_Cex_t *)Gia_Man_t *Gia_ManFramesForCexMin(Gia_Man_t *, int)Care bits = %d. void Gia_ManMinCex(Gia_Man_t *, Abc_Cex_t *)Status %d. Selected %d assumptions out of %d. Analyze_finalLEXUNSATPiNum >= 0 && PiNum < pCex->nBits - pCex->nRegsAbc_Cex_t *Bmc_CexCareDeriveCex(Abc_Cex_t *, int, int *, int)Non-SAT-based CEX minimizationAbc_Cex_t *Bmc_CexCareSatBasedMinimizeAig(Gia_Man_t *, Abc_Cex_t *, int, int)Constructing SAT solverStatus %s Selected %5d assumptions out of %5d. BUGLEXUNSAT پCھؾپپsrc/aig/gia/giaClp.cint Gia_ManRebuildNode(Dsd_Manager_t *, Dsd_Node_t *, Gia_Man_t *, DdManager *, Vec_Int_t *, Vec_Str_t *, Vec_Str_t *)Vec_PtrSize(vFuncs) == Vec_PtrCountZero(vFuncs) + Gia_ManCoNum(p)Vec_Ptr_t *Gia_ManCollapse(Gia_Man_t *, DdManager *, int, int)Ins = %d. Outs = %d. Shared BDD nodes = %d. Peak live nodes = %d. Peak nodes = %d. iHandle == p->nObjDatasrc/aig/gia/giaCof.cCof_Man_t *Cof_ManCreateLogicSimple(Gia_Man_t *)pObjLog->nFanouts == pObjLog->ValueCof_ObjIsCi(pObj) || Cof_ObjIsNode(pObj)int Cof_ManTfoSize_rec(Cof_Man_t *, Cof_Obj_t *)int Cof_ManTfiSize_rec(Cof_Man_t *, Cof_Obj_t *)int Cof_ManSuppSize_rec(Cof_Man_t *, Cof_Obj_t *)p->pLevels[LevelStart] == 0int Cof_ManCountRemoved(Cof_Man_t *, Cof_Obj_t *, int)pTemp->Id != Abc_Lit2Var(pTemp->iLit)pFanin0 == pTemp || pFanin1 == pTempLevelNext > i && LevelNext < p->nLevelsi/o/c =%2d %5d %5d l =%4d TFI =%7d TFO =%7d C0 =%6d C1 =%6d%11d %12d Fanins: Max = %d. Ave = %.2f. Fanouts: Max = %d. Ave = %.2f. MFFCs: Max = %d. Ave = %.2f. Memory for logic network%10.3f MB Gia_ManDupCof(): Variable %d is out of range (%d; %d). Gia_ManDupCof(): Variable %d should be a CI or an AND node. iCofVar > 0Gia_Man_t *Gia_ManDupCofInt(Gia_Man_t *, int)Vec_Int_t *Gia_ManTransfer(Gia_Man_t *, Gia_Man_t *, Gia_Man_t *, Vec_Int_t *)Cofactoring %d signals. Cofactored variable %d. int Cof_ObjMffcSize(Cof_Obj_t *)The distribution of fanins, fanouts. and MFFCs in the network: Number Nodes with fanin Nodes with fanout Nodes with MFFCToo many signals to cofactor.p->pId2Part[ iObj ] >= 0src/aig/gia/giaCone.cvoid Opa_ManMoveOne(Opa_Man_t *, Gia_Obj_t *, Gia_Obj_t *)Gia_ObjIsCi(pFanin) || Gia_ObjIsAnd(pFanin)p->pId2Part[ iFanin ] == -1Vec_IntSize(vPartObj) > 0%6d : %6d -> %6d void Opa_ManPerform(Gia_Man_t *)int Gia_ManConeMark_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, int)Selected %d pivots with more than one fanout (out of %d CIs and ANDs). %2d : Pivot =%7d Fanout =%7d Signature propagation: pObj->Value >= 0 && pObj->Value < 64Vec_Wrd_t *Gia_ManDeriveSigns(Gia_Man_t *, Vec_Int_t *, int)Computed %d partitions: Vec_IntSize(vBin) > 0Vec_Ptr_t *Gia_ManHashOutputs(Gia_Man_t *, Vec_Wrd_t *, int)PO =%7d FF =%7dThe algorithm divided %d POs into %d partitions. Groups %d: Listing partitions with more than 100 outputs:!Cbs0_QueIsEmpty(&p->pProp)src/aig/gia/giaCSatOld.cint Cbs0_ManSolve_rec(Cbs0_Man_t *)Cbs0_VarIsJust( pVar )!p->pProp.iHead && !p->pProp.iTailint Cbs0_ManSolve(Cbs0_Man_t *, Gia_Obj_t *)!p->pJust.iHead && !p->pJust.iTailJustMax = %5d Gia_ManRegNum(pAig) == 0Vec_Int_t *Cbs_ManSolveMiter(Gia_Man_t *, int, Vec_Str_t **, int)!Gia_IsComplement(pVar)int Cbs0_ManPropagateOne(Cbs0_Man_t *, Gia_Obj_t *)Cbs0_VarIsAssigned(pVar)Gia_ObjIsAnd(pVar)Cbs0_VarIsJust(pVar)!Cbs0_QueHasNode( &p->pJust, pVar )pVar->fMark0int Cbs0_VarValue(Gia_Obj_t *)int Cbs0_ManPropagateTwo(Cbs0_Man_t *, Gia_Obj_t *)!Cbs0_VarValue(pVar)Value0 == 1 || Value1 == 1p->pAig->pRefs != NULLGia_Obj_t *Cbs0_ManDecideMaxFF(Cbs0_Man_t *)iCurFF > 0int Cbs0_VarFaninFanoutMax(Cbs0_Man_t *, Gia_Obj_t *)Gia_ObjIsCand(pObjR)void Cbs0_ManAssign(Cbs0_Man_t *, Gia_Obj_t *)!Cbs0_VarIsAssigned(pObjR)iBound <= p->pProp.iTailvoid Cbs0_ManCancelUntil(Cbs0_Man_t *, int)void Cbs0_VarUnassign(Gia_Obj_t *)Constant 1 output of SRM!!!!Cbs_QueIsEmpty(&p->pProp)src/aig/gia/giaCSat.cint Cbs_ManSolve_rec(Cbs_Man_t *, int)Cbs_VarIsJust( pVar )int Cbs_ManSolve(Cbs_Man_t *, Gia_Obj_t *)p->pClauses.iHead == 1 && p->pClauses.iTail == 1int Cbs_ManSolve2(Cbs_Man_t *, Gia_Obj_t *, Gia_Obj_t *)Vec_Int_t *Cbs_ManSolveMiterNc(Gia_Man_t *, int, Vec_Str_t **, int)int Cbs_ManPropagateOne(Cbs_Man_t *, Gia_Obj_t *, int)Cbs_VarIsAssigned(pVar)Value0 == 0 && Value1 == 0Cbs_VarIsJust(pVar)!Cbs_QueHasNode( &p->pJust, pVar )int Cbs_VarValue(Gia_Obj_t *)int Cbs_ManAnalyze(Cbs_Man_t *, int, Gia_Obj_t *, Gia_Obj_t *, Gia_Obj_t *)Cbs_VarIsAssigned(pFan0)pFan1 == NULL || Cbs_VarIsAssigned(pFan1)Cbs_QueIsEmpty( pQue )pQue->pData[pQue->iHead] == NULLvoid Cbs_ManDeriveReason(Cbs_Man_t *, int)pQue->iHead + 1 < pQue->iTailiLitLevel == LevelpQue->pData[pQue->iHead] != NULLpVar->Value != ~0int Cbs_VarDecLevel(Cbs_Man_t *, Gia_Obj_t *)Gia_Obj_t *Cbs_VarReason1(Cbs_Man_t *, Gia_Obj_t *)p->iHead < p->iTailint Cbs_QueFinish(Cbs_Que_t *)void Cbs_QuePush(Cbs_Que_t *, Gia_Obj_t *)int Cbs_ManPropagateTwo(Cbs_Man_t *, Gia_Obj_t *, int)!Cbs_VarValue(pVar)Gia_Obj_t *Cbs_ManDecideMaxFF(Cbs_Man_t *)int Cbs_VarFaninFanoutMax(Cbs_Man_t *, Gia_Obj_t *)void Cbs_ManAssign(Cbs_Man_t *, Gia_Obj_t *, int, Gia_Obj_t *, Gia_Obj_t *)!Cbs_VarIsAssigned(pObjR)pObjR->Value == ~0Vec_IntSize(p->vLevReas) == 3 * p->pProp.iTailvoid Cbs_ManCancelUntil(Cbs_Man_t *, int)void Cbs_VarUnassign(Gia_Obj_t *)pQue->pData[hClause0] != NULLint Cbs_ManResolve(Cbs_Man_t *, int, int, int)pQue->pData[hClause0] == pQue->pData[hClause1]src/aig/gia/giaCSat2.cint Cbs2_ManUpdateFrontier(Cbs2_Man_t *, int, int *)!Cbs2_QueIsEmpty(&p->pProp)int Cbs2_ManSolve1_rec(Cbs2_Man_t *, int)p->Pars.fUseHighestCbs2_VarIsJust(p, pVar, iVar)int Cbs2_ManSolve2_rec(Cbs2_Man_t *, int)int Cbs2_ManSolve(Cbs2_Man_t *, int)int Cbs2_ManSolve2(Cbs2_Man_t *, int, int)Fanouts of node %d: void Cbs2_ManCreateFanout_rec(Cbs2_Man_t *, int)void Cbs2_ManDeleteFanout_rec(Cbs2_Man_t *, int)Vec_IntEntry(&p->vFanout0, iObj) == 0void Cbs2_ManCheckFanouts(Cbs2_Man_t *)Vec_IntEntry(&p->vFanoutN, Abc_Var2Lit(iObj, 0)) == 0Vec_IntEntry(&p->vFanoutN, Abc_Var2Lit(iObj, 1)) == 0Vec_Int_t *Cbs2_ManSolveMiterNc(Gia_Man_t *, int, Vec_Str_t **, int)Prop1 = %d. Prop2 = %d. Prop3 = %d. ClaConf = %d. FailJ = %d. FailC = %d. JFrontint Cbs2_ManPropagateOne(Cbs2_Man_t *, int, int)Cbs2_VarIsAssigned(p, iVar)int Cbs2_ManAnalyze(Cbs2_Man_t *, int, int, int, int)Cbs2_QueIsEmpty( pQue )Cbs2_VarIsAssigned(p, iFan0)iFan1 == 0 || Cbs2_VarIsAssigned(p, iFan1)iVar == Abc_Lit2Var(pLits[0])Cbs2_VarValue(p, iVar) == Abc_LitIsCompl(pLits[0])p->iTail + Plus <= p->nSizevoid Cbs2_QueGrow(Cbs2_Que_t *, int)pQue->pData[pQue->iHead] == 0int Cbs2_ManDeriveReason(Cbs2_Man_t *, int)pQue->pData[pQue->iHead+1] == 0pQue->iHead + 2 < pQue->iTailiObj == Abc_Lit2Var(pLits[0])pQue->pData[pQue->iHead+1] != 0!Cbs2_VarUnused(p, iVar)int Cbs2_VarDecLevel(Cbs2_Man_t *, int)pQue->iHead+1 < pQue->iTailint Cbs2_QueFinish(Cbs2_Man_t *, int)Lit == pLits[0] || Lit == pLits[1]void Cbs2_ManWatchClause(Cbs2_Man_t *, int, int)int Cbs2_ManPropagateTwo(Cbs2_Man_t *, int, int)Cbs2_VarValue(p, iVar) == 0int Cbs2_ManPropagateClauses(Cbs2_Man_t *, int, int)void Cbs2_ManPropagateUnassigned(Cbs2_Man_t *, int, int)Cbs2_VarUnused(p, iObj)void Cbs2_ManAssign(Cbs2_Man_t *, int, int, int, int)!Cbs2_VarIsAssigned(p, iObj)void Cbs2_ManCancelUntil(Cbs2_Man_t *, int)void Cbs2_VarUnassign(Cbs2_Man_t *, int)pQue->pData[hClause0+1] != 0int Cbs2_ManResolve(Cbs2_Man_t *, int, int, int)pQue->pData[hClause0+1] == pQue->pData[hClause1+1]Cbs2_QueIsEmpty( &p->pClauses )void Cbs2_ManBumpClause(Cbs2_Man_t *, int)!Tas_QueIsEmpty(&p->pProp)src/aig/gia/giaCTas.cint Tas_ManSolve_rec(Tas_Man_t *, int)Tas_VarIsJust( pVar )int Tas_ManSolve(Tas_Man_t *, Gia_Obj_t *, Gia_Obj_t *)int Tas_ManSolveArray(Tas_Man_t *, Vec_Ptr_t *)Vec_Int_t *Tas_ManSolveMiterNc(Gia_Man_t *, int, Vec_Str_t **, int)void Tas_ManSolveMiterNc2(Gia_Man_t *, int, Gia_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *)!Gia_ObjIsConst0(Gia_ObjFanin0(pRoot))!Gia_ObjProved( pAigOld, Gia_ObjId(pAigOld, pOldRoot) )Tried = %d Stored = %d int Tas_ManPropagateOne(Tas_Man_t *, Gia_Obj_t *, int)Tas_VarIsAssigned(pVar)Tas_VarIsJust(pVar)!Tas_QueHasNode( &p->pJust, pVar )int Tas_ManPropagateWatch(Tas_Man_t *, int, int)!Tas_LitIsTrue( pObj, pCur->pLits[0] )Tas_VarIsAssigned(pObj)Abc_Lit2Var(Lit) < Gia_ManObjNum(p->pAig)void Tas_ManWatchClause(Tas_Man_t *, Tas_Cls_t *, int)pClause->nLits >= 2pClause->pLits[0] == Lit || pClause->pLits[1] == LitTas_QueIsEmpty( pQue )int Tas_ManCreateFromCls(Tas_Man_t *, Tas_Cls_t *, int)!Tas_LitIsTrue( pObj, pCls->pLits[i] )void Tas_ManDeriveReason(Tas_Man_t *, int)pReason == pObjTas_VarIsAssigned( pReason )!Tas_LitIsTrue( pReason, pCls->pLits[j] )pQue->pData[pQue->iHead] == NULL || Level == 0int Tas_VarDecLevel(Tas_Man_t *, Gia_Obj_t *)Gia_Obj_t *Tas_VarReason1(Tas_Man_t *, Gia_Obj_t *)int Tas_QueFinish(Tas_Que_t *)int Tas_VarValue(Gia_Obj_t *)int Tas_ManAnalyze(Tas_Man_t *, int, Gia_Obj_t *, Gia_Obj_t *, Gia_Obj_t *)Tas_VarIsAssigned(pFan0)pFan1 == NULL || Tas_VarIsAssigned(pFan1)int Tas_ManPropagateTwo(Tas_Man_t *, Gia_Obj_t *, int)!Tas_VarValue(pVar)Tas_Cls_t *Tas_ManCreateCls(Tas_Man_t *, int)pQue->pData[hClause] != NULLTas_VarIsAssigned( pObj )Gia_Obj_t *Tas_ManFindActive(Tas_Man_t *)Gia_Obj_t *Tas_ManDecideMaxFF(Tas_Man_t *)int Tas_VarFaninFanoutMax(Tas_Man_t *, Gia_Obj_t *)void Tas_ManAssign(Tas_Man_t *, Gia_Obj_t *, int, Gia_Obj_t *, Gia_Obj_t *)!Tas_VarIsAssigned(pObjR)void Tas_ManCancelUntil(Tas_Man_t *, int)void Tas_VarUnassign(Gia_Obj_t *)int Tas_ManResolve(Tas_Man_t *, int, int, int)0hH(`@x X8pP0hH( ` !@!src/aig/gia/giaCut.cvoid Gia_StoMergeCuts(Gia_Sto_t *, int)nCutSize < GIA_CUT_NO_LEAFGia_Sto_t *Gia_StoAlloc(Gia_Man_t *, int, int, int, int, int)nCutSize > 1 && nCutSize <= GIA_MAX_CUTSIZEnCutNum > 1 && nCutNum < GIA_MAX_CUTNUMvoid Gia_StoRefObj(Gia_Sto_t *, int)Running cut computation with CutSize = %d CutNum = %d CutMin = %s TruthMin = %s The number of nodes with cut count over the limit (%d cuts) = %d nodes (out of %d). int Gia_CutSetCutIsContainedOrder(Gia_Cut_t *, Gia_Cut_t *)int Gia_CutComputeTruth(Gia_Sto_t *, Gia_Cut_t *, Gia_Cut_t *, int, int, Gia_Cut_t *, int)int Gia_CutComputeTruth6(Gia_Sto_t *, Gia_Cut_t *, Gia_Cut_t *, int, int, Gia_Cut_t *, int)int Gia_CutSetAddCut(Gia_Cut_t **, int, int)int Gia_CutSetCheckArray(Gia_Cut_t **, int)pCut0->nLeaves <= GIA_MAX_CUTSIZEpCut0->Sign == Gia_CutGetSign(pCut0)void Gia_CutAddZero(Gia_Sto_t *, int)""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333UUUUUUUU33333333src/aig/gia/giaDfs.cvoid Gia_ManCollectCis_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)void Gia_ManCollectAnds_rec(Gia_Man_t *, int, Vec_Int_t *)void Gia_ManCollectNodesCis_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)DFS from each outputint Gia_ManSuppSize_rec(Gia_Man_t *, Gia_Obj_t *)int Gia_ManConeSize_rec(Gia_Man_t *, Gia_Obj_t *)Vec_Vec_t *Gia_ManLevelize(Gia_Man_t *)Gia_ObjLevel(p, pObj) > 0Vec_Int_t *Gia_ManOrderReverse(Gia_Man_t *)void Gia_ManCollectSeq_rec(Gia_Man_t *, int, Vec_Int_t *, Vec_Int_t *)%8d finished... void Gia_ManCollectTfi_rec(Gia_Man_t *, int, Vec_Int_t *)void Gia_ManCollectTfo_rec(Gia_Man_t *, int, Vec_Int_t *)pNew->pReprs == NULL && pNew->pNexts == NULLsrc/aig/gia/giaDup.cvoid Gia_ManDupRemapEquiv(Gia_Man_t *, Gia_Man_t *)Vec_IntSize( vClass ) > 1iPrev < iNodeVec_IntSize(p->vCis) == Vec_IntSize(pNew->vCis)void Gia_ManDupRemapCis(Gia_Man_t *, Gia_Man_t *)Gia_ObjCioId(pObj) == i!Gia_IsComplement(pObjNew)Vec_IntSize(p->vCos) == Vec_IntSize(pNew->vCos)void Gia_ManDupRemapCos(Gia_Man_t *, Gia_Man_t *)Gia_ManCiNum(pNew) == Gia_ManCiNum(p)Gia_Man_t *Gia_ManDupOrderDfs(Gia_Man_t *)Vec_IntSize(vMapFf2Ppi) == Vec_IntSize(vMapPpi2Ff) + Vec_IntCountEntry(vMapFf2Ppi, -1)Gia_Man_t *Gia_ManDupAbs(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *)pObj->Value != ~0Gia_ManPiNum(pNew) == Gia_ManPiNum(p) + Vec_IntSize(vMapPpi2Ff)Gia_ManPoNum(pNew) == Gia_ManPoNum(p)Gia_ManCoNum(pNew) == Gia_ManCoNum(p) - Vec_IntSize(vMapPpi2Ff)Gia_Man_t *Gia_ManDupOutputVec(Gia_Man_t *, Vec_Int_t *)Gia_ManPoNum(p) == Vec_IntSize(vOutPres)Gia_Man_t *Gia_ManDupSelectedOutputs(Gia_Man_t *, Vec_Int_t *)Gia_ManPoNum(p) >= Vec_IntSize(vOutsLeft)void Gia_ManDupOrderDfsChoices_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *)Abc_Lit2Var(pObj->Value) > Abc_Lit2Var(pNext->Value)Gia_Man_t *Gia_ManDupOrderDfsChoices(Gia_Man_t *)Gia_Man_t *Gia_ManDupOrderDfsReverse(Gia_Man_t *)Gia_ManIsNormalized(pNew)Gia_Man_t *Gia_ManDupOrderAiger(Gia_Man_t *)Gia_Man_t *Gia_ManDupLastPis(Gia_Man_t *, int)pCex == NULL || nFrames <= pCex->iFramevoid Gia_ManCycle(Gia_Man_t *, Abc_Cex_t *, int)Gia_ManCiNum(p1) == Gia_ManCiNum(p2)Gia_Man_t *Gia_ManDup2(Gia_Man_t *, Gia_Man_t *)Gia_ManCoNum(p1) == Gia_ManCoNum(p2)Vec_IntSize(vPiPerm) == Gia_ManPiNum(p)Gia_Man_t *Gia_ManDupPerm(Gia_Man_t *, Vec_Int_t *)Vec_IntSize(vFfPerm) == Gia_ManRegNum(p)Gia_Man_t *Gia_ManDupPermFlop(Gia_Man_t *, Vec_Int_t *)Vec_IntSize(vFfMask) >= Gia_ManRegNum(p)Gia_Man_t *Gia_ManDupSpreadFlop(Gia_Man_t *, Vec_Int_t *)k == Gia_ManRegNum(p)Gia_ManCiNum(pNew) == Gia_ManCiNum(pTwo)void Gia_ManDupAppendShare(Gia_Man_t *, Gia_Man_t *)Gia_Man_t *Gia_ManDupInvMiter(Gia_Man_t *, Gia_Man_t *)Gia_ManRegNum(pInv) == 0Gia_ManCoNum(pInv) == 1Gia_ManRegNum(p) == Gia_ManCiNum(pInv)Gia_ManPoNum(pOne) == 1Gia_Man_t *Gia_ManDupAppendCones(Gia_Man_t *, Gia_Man_t **, int, int)Gia_ManRegNum(pOne) == 0Gia_ManPiNum(pOne) == Gia_ManRegNum(p)Gia_ManPiNum(pOne) == Gia_ManCiNum(p)p->vFlopClasses != NULLGia_Man_t *Gia_ManDupFlopClass(Gia_Man_t *, int)Counter1 == Counter2Gia_Man_t *Gia_ManDupMarked(Gia_Man_t *)pNew->nObjsAlloc == pNew->nObjsnRos == nRisAbc_Lit2Var(pObj->Value) > Abc_Lit2Var(pSibl->Value)Gia_Man_t *Gia_ManDupTimes(Gia_Man_t *, int)Gia_Man_t *Gia_ManDupDfs2(Gia_Man_t *)void Gia_ManDupDfs_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *)iPo >= 0 && iPo < Gia_ManPoNum(p)Gia_Man_t *Gia_ManDupDfsOnePo(Gia_Man_t *, int)void Gia_ManDupCofactorVar_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *)iVar >= 0 && iVar < Gia_ManPiNum(p)Gia_Man_t *Gia_ManDupCofactorVar(Gia_Man_t *, int, int)Value == 0 || Value == 1Gia_ManRegNum(pCof0) == 0Gia_Man_t *Gia_ManDupMux(int, Gia_Man_t *, Gia_Man_t *)Gia_ManRegNum(pCof1) == 0Gia_ManCoNum(pCof0) == 1Gia_ManCoNum(pCof1) == 1Gia_ManCiNum(pCof1) == Gia_ManCiNum(pCof0)iVar >= 0 && iVar < Gia_ManCiNum(pCof1)Gia_Man_t *Gia_ManDupCofactorObj(Gia_Man_t *, int, int)iObj > 0 && iObj < Gia_ManObjNum(p)Gia_ObjIsCand(Gia_ManObj(p, iObj))Gia_ManCiNum(p) % nBlock == 0Gia_Man_t *Gia_ManDupBlock(Gia_Man_t *, int)Gia_ManCoNum(p) % nBlock == 0Gia_Man_t *Gia_ManDupExist(Gia_Man_t *, int)Gia_Man_t *Gia_ManDupUniv(Gia_Man_t *, int)Gia_Man_t *Gia_ManDupExist2(Gia_Man_t *, int)Gia_ObjIsCo(pRoot)Gia_Man_t *Gia_ManDupDfsCone(Gia_Man_t *, Gia_Obj_t *)void Gia_ManDupConeSupp_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)void Gia_ManDupConeBack_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *)Gia_ManCiNum(pNew) == Vec_IntSize(vCiIds)int Gia_ManDupConeBack(Gia_Man_t *, Gia_Man_t *, Vec_Int_t *)Gia_ManCiNum(pNew) == Vec_IntSize(vObjs)int Gia_ManDupConeBackObjs(Gia_Man_t *, Gia_Man_t *, Vec_Int_t *)void Gia_ManDupDfs3_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *)Gia_Man_t *Gia_ManDupDfsNode(Gia_Man_t *, Gia_Obj_t *)(Gia_ManPoNum(p) & 1) == 0Vec_Int_t *Gia_ManDupTrimmedNonZero(Gia_Man_t *)Gia_ManPiNum(pNonDual) > 02 * Gia_ManPoNum(pNonDual) == Gia_ManPoNum(p)int Gia_ManPoIsToRemove(Gia_Man_t *, Gia_Obj_t *, int)!Gia_ManHasDangling( pNew )Gia_Man_t *Gia_ManDupTrimmed(Gia_Man_t *, int, int, int, int)Gia_Man_t *Gia_ManDupTrimmed2(Gia_Man_t *)Gia_ManPoNum(p) == Gia_ManPiNum(p2)Gia_Man_t *Gia_ManDupOntop(Gia_Man_t *, Gia_Man_t *)Gia_ManRegNum(p2) == 0Gia_Man_t *Gia_ManDupWithNewPo(Gia_Man_t *, Gia_Man_t *)Gia_ManPiNum(p2) == Gia_ManRegNum(p1)%d->%d Gia_Man_t *Gia_ManPermuteInputs(Gia_Man_t *, int, int)p->pReprsOld != NULLGia_Man_t *Gia_ManDupDfsClasses(Gia_Man_t *)Gia_Man_t *Gia_ManDupTopAnd_iter(Gia_Man_t *, int)Detected %6d AND leaves and %6d CI leaves. int Gia_ManMiter_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *)Gia_Man_t *Gia_ManDupAndOr(Gia_Man_t *, int, int, int)nOuts % 2 == 0Vec_Ptr_t *Gia_ManMiterNames(Vec_Ptr_t *, int)nOuts <= Vec_PtrSize(p)Gia_Man_t *Gia_ManTransformMiter(Gia_Man_t *)Gia_Man_t *Gia_ManTransformMiter2(Gia_Man_t *)Gia_Man_t *Gia_ManTransformTwoWord2DualOutput(Gia_Man_t *)Gia_Man_t *Gia_ManTransformDualOutput(Gia_Man_t *)Vec_IntSize(vNodes0) <= Vec_IntSize(vNodes1)(int)strlen(pInit) == Gia_ManRegNum(p)Gia_Man_t *Gia_ManDupZeroUndc(Gia_Man_t *, char *, int, int, int)Converted %d 1-valued FFs and %d DC-valued FFs. pInit[i] == 'x' || pInit[i] == 'X'Gia_Man_t *Gia_ManMiter2(Gia_Man_t *, char *, int)k == Gia_ManPiNum(pUndc)Vec_PtrSize(vGias) > 0Gia_Man_t *Gia_ManChoiceMiter(Vec_Ptr_t *)Gia_ManCiNum(pGia) == Gia_ManCiNum(pGia0)Gia_ManCoNum(pGia) == Gia_ManCoNum(pGia0)Gia_ManRegNum(pGia) == Gia_ManRegNum(pGia0)Gia_Man_t *Gia_ManDupWithConstraints(Gia_Man_t *, Vec_Int_t *)void Gia_ManDupCones_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *)Gia_ManObjNum(p) <= nSkips + 4 * nVars + 1Gia_Man_t *Gia_ManOneHot(int, int)Appending 1-hotness constraints to the PIs. Gia_Man_t *Gia_ManDupWithConstr(Gia_Man_t *)Vec_IntSize(vSuper) > 1iLitBest != -1Gia_Man_t *Gia_ManDupOuts(Gia_Man_t *)int Gia_ManDupHashDfs_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *)void Gia_ManDupCleanDfs_rec(Gia_Obj_t *)Gia_Man_t *Gia_ManDupStrashReduce(Gia_Man_t *, Vec_Wec_t *, Vec_Int_t **)Gia_ObjFanin0Copy(pObj) < 2 * Gia_ManObjNum(pNew)Vec_IntSize(vCoMapLit) == Gia_ManCoNum(p)int Gia_ManIsoStrashReduceOne(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)Gia_Man_t *Gia_ManDupDemiter(Gia_Man_t *, int)The miter is %s-decomposable into %d parts. Index >= 0 && Index < Vec_IntSize(vXors)void Gia_ManDupDemiterOrderXors(Gia_Man_t *, Vec_Int_t *)!Vec_IntEntry( vTakenOuts, Index )Vec_IntSize(vPart[0]) == Vec_IntSize(vPart[1])int Gia_ManDecideWhereToAdd(Gia_Man_t *, Vec_Int_t **, Gia_Obj_t **)Vec_IntSize(vOrder) % 2 == 0Gia_Man_t *Gia_ManDemiterToDual(Gia_Man_t *)int Gia_ManDemiterDual(Gia_Man_t *, Gia_Man_t **, Gia_Man_t **)Gia_ManCoNum(p) % 2 == 0int Gia_ManDemiterTwoWords(Gia_Man_t *, Gia_Man_t **, Gia_Man_t **)p->pReprs == NULL && p->pNexts == NULLvoid Gia_ManSeqEquivMerge(Gia_Man_t *, Gia_Man_t **)pPart[n]->pReprs != NULL && pPart[n]->pNexts != NULLConst0:void Gia_ManPrintEquivs(Gia_Man_t *)void Gia_ObjSetCioId(Gia_Obj_t *, int)Gia_Obj_t *Gia_ManRo(Gia_Man_t *, int)int Gia_ManAppendMuxReal(Gia_Man_t *, int, int, int)iLitC >= 0 && Abc_Lit2Var(iLitC) < Gia_ManObjNum(p)Abc_Lit2Var(iLitC) != Abc_Lit2Var(iLit0)Abc_Lit2Var(iLitC) != Abc_Lit2Var(iLit1)!Vec_IntSize(&p->vHTable) || !Abc_LitIsCompl(iLit1)Problem is trivially UNSAT.The AIG cannot be decomposed using AND-decomposition.Gia_ManMiter(): Designs have different number of COs.Gia_ManMiter(): Designs have different number of CIs.Gia_ManMiter(): At least one of the designs has no registers.Gia_ManMiter(): Designs have different number of POs.Gia_ManMiter(): Designs have different number of PIs.The miter's output is a constant.The miter's output is not AND-decomposable.Cannot demiter because the top-most gate is an AND-gate.iObj1 < iObj2src/aig/gia/giaEdge.cvoid Gia_ManEdgeFromArray(Gia_Man_t *, Vec_Int_t *)Found %d violations during edge conversion. p->vEdge1 && p->vEdge2Vec_Int_t *Gia_ManEdgeToArray(Gia_Man_t *)Vec_IntSize(p->vEdge1) == Gia_ManObjNum(p)Vec_IntSize(p->vEdge2) == Gia_ManObjNum(p)Entry > 0 && Entry < 4void Gia_ManConvertPackingToEdges(Gia_Man_t *)Skipped %d illegal edges. int Gia_ManEvalEdgeDelay(Gia_Man_t *)Gia_ObjLutSize(p, iObj) <= 4int Gia_ObjComputeEdgeDelay(Gia_Man_t *, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, int)Gia_ObjLutSize2(p, iObj) <= 4nCountMax > 0int Gia_ManComputeEdgeDelay(Gia_Man_t *, int)int Gia_ObjComputeEdgeDelay2(Gia_Man_t *, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)int Gia_ManComputeEdgeDelay2(Gia_Man_t *)Vec_IntSize(vNodes) == Vec_WecSize(vWin)int Gia_ManEvalWindowInc(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Wec_t *, Vec_Int_t *, int)int Gia_ManEvalWindow(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Wec_t *, Vec_Int_t *, int)void Edg_ManToMapping(Gia_Man_t *)int Edg_ManEvalEdgeDelay(Gia_Man_t *)int Edg_ManEvalEdgeDelayR(Gia_Man_t *)void Edg_ManCollectCritEdges(Gia_Man_t *, Vec_Wec_t *, int)Delay1 + Delay2 <= DelayMaxint Edg_ObjImprove(Gia_Man_t *, int, int, int, int)Delay1 + Delay2 + 1 <= DelayMaxGia_ObjIsAnd(Gia_ManObj(p, iNext))Edges = %d Fanins (all %d EC %d ENC %d C %d) Fanouts (all %d EC %d ENC %d C %d) nEdges <= nEdgeLimitFixed %d critical fanins Fixed %d critical fanouts Running edge assignment with E = %d. DelayD == DelayR + DelayNoEdgeint Edg_ManAssignEdgeNew(Gia_Man_t *, int, int) Iter %4d : Delay = %4d int Gia_ObjEvalEdgeDelay(Gia_Man_t *, int, Vec_Int_t *)Cannot fixFullWrong number of edges.+?@F(knN(knN(knN(knNpObj->iFanin < pObj->nFaninssrc/aig/gia/giaEmbed.cvoid Emb_ObjAddFanin(Emb_Obj_t *, Emb_Obj_t *)pFanin->iFanout < pFanin->nFanoutsGia_ObjRefNum( pGia, pObj ) > 0Emb_Man_t *Emb_ManStartSimple(Gia_Man_t *)nNodes == Emb_ManNodeNum(p)hHandle == p->nObjDatap->nObjs == Gia_ManObjNum(pGia)pObjLog->nFanins == pObjLog->iFanin || Gia_ObjIsConst0(pObj)pObjLog->nFanouts == pObjLog->iFanout || Gia_ObjIsCo(pObj)void Emb_ManCollectSuper_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, Vec_Int_t *)void Emb_ManCollectSuper(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, Vec_Int_t *)p->pRefs == NULLvoid Emb_ManCreateRefsSpecial(Gia_Man_t *)Gia_ObjRefNum(p, pObj) > 0p->pRefs != NULLvoid Emb_ManTransformRefs(Gia_Man_t *, int *, int *)pFanin->fMark0Gia_ObjRefNum( pGia, pObj ) == 0Emb_Man_t *Emb_ManStart(Gia_Man_t *)i/o =%7d/%7d ff =%7d node =%8d obj =%8d From inputs: From outputs: From nodes: Vec_IntSize(vThis) > 0Emb_Obj_t *Emb_ManPerformBfs(Emb_Man_t *, Vec_Int_t *, Vec_Int_t *, Emb_Dat_t *)Vec_IntSize(vNext) > 0pDist == NULL || pDist[pResult->Value] == p->nDistMax - 1Emb_ObjIsTravIdCurrent(p, pNext)void Emb_DumpGraphIntoFile(Emb_Man_t *)Emb_ObjIsCo(pFanin)void Emb_ManComputeDimensions(Emb_Man_t *, int)p->pVecs == NULLnReached == p->nReachedp->pMatr == NULLvoid Emb_ManComputeCovariance(Emb_Man_t *, int)p->pEigen == NULLnSols < nDimsvoid Emb_ManComputeEigenvectors(Emb_Man_t *, int, int)p->pSols == NULLvoid Emb_ManComputeSolutions(Emb_Man_t *, int, int)%2d : HPWL = %e placeX < nCols && placeY < nRowsVec_Int_t *Emb_ManDumpGnuplotPrepare(Emb_Man_t *)fStart == 0# This Gnuplot file was produced by ABC on %s set nokey set terminal gif font 'arial' 10 size 800,600 xffffff x000000 x000000 x000000 set output '%s' .gifset title "%s : PI = %d PO = %d FF = %d Node = %d Obj = %d HPWL = %.2e\n(image generated by ABC and Gnuplot on %s)"font "Times, 12" plot [:] '-' w l void Emb_ManDumpGnuplot(Emb_Man_t *, char *, int, int)EOF # pause -1 "Close window" # reset Clustered: Setup DimensionsMatrix Eigenvecs RefinementImage dumpEmb_ManDumpGnuplot(): Placement is not available.src/aig/gia/giaEnable.cvoid Gia_CollectSuper_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)void Gia_CollectSuper(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)%s (total = %d driven = %d) %3d : Obj = %6d Refs = %6d Freq = %6d void Gia_ManDetectSeqSignals(Gia_Man_t *, int, int)Flops with set/reset = %6d. Flops with enable = %6d. Set signalsReset signalsEnable signalsVec_Int_t *Gia_ManDetectSeqSignalsWithFanout(Gia_Man_t *, int, int)Adding set signal %d related to %d flops. Adding reset signal %d related to %d flops. Adding enable signal %d related to %d flops. Vec_Int_t *Gia_ManTransferFrames(Gia_Man_t *, Gia_Man_t *, int, Gia_Man_t *, Vec_Int_t *)Cannot recognize enable of flop %d. Cannot recognize self-loop of enable flop %d. The flop driver %d is not a node. The flop driver %d is not an OR gate. The flop driver fanin %d is not a node. The flop %d does not have a self-loop. Gia_Man_t *Gia_ManRemoveEnables(Gia_Man_t *)Vec_PtrSize( vDatas ) == Gia_ManRegNum(p)Vec_IntSize( vFlopClasses ) == Gia_ManRegNum(p)Detected %d classes. Vec_IntEntry(pNew->vIdsOrig, i) >= 0src/aig/gia/giaEquiv.cvoid Gia_ManOrigIdsRemap(Gia_Man_t *, Gia_Man_t *)Smo != Bigvoid Gia_ManOrigIdsRemapPairsInsert(Vec_Int_t *, int, int)!p->pReprs && !p->pNextsGia_Man_t *Gia_ManOrigIdsReduce(Gia_Man_t *, Vec_Int_t *)int Gia_ManCheckTopoOrder_rec(Gia_Man_t *, Gia_Obj_t *)int *Gia_ManDeriveNexts(Gia_Man_t *)void Gia_ManDeriveReprs(Gia_Man_t *)Detected a mismatch in counting equivalence classes (%d). cst =%3d cls =%6d lit =%8d int Gia_ManEquivCountOne(Gia_Man_t *, int)Gia_ObjRepr(p, Ent) == iClass %4d : Num = %2d {void Gia_ManEquivPrintOne(Gia_Man_t *, int, int) <%d%d>cst =%8d cls =%7d lit =%8d unused =%8d proof =%6d mem =%5.2f MB Const0 (%d) = int Gia_ManChoiceMinLevel_rec(Gia_Man_t *, int, int, Vec_Int_t *)LevMin > 0Gia_ObjIsAnd(pPivot)void Gia_ManEquivReduce_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *, int, int)Gia_ManEquivReduce(): Equivalence classes are not available. Gia_ManEquivReduce(): Dual-output miter should have even number of POs. void Gia_ManEquivReduce2_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, int)~pRepr->Value~pRepr2->Valuevoid Gia_ManEquivFixOutputPairs(Gia_Man_t *)void Gia_ManEquivDeriveReprs(Gia_Man_t *, Gia_Man_t *, Gia_Man_t *)Gia_Man_t *Gia_ManEquivRemapDfs(Gia_Man_t *)int Gia_ManEquivSetColor_rec(Gia_Man_t *, Gia_Obj_t *, int)int Gia_ManEquivSetColors(Gia_Man_t *, int)CI+AND = %7d A = %7d B = %7d Ad = %7d Bd = %7d AB = %7d. void Gia_ManSpecReduce_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, int, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Gia_ManSpecReduce(): Equivalence classes are not available. Speculatively reduced model has no primary outputs. Gia_ManSpecReduce(): Dual-output miter should have even number of POs. Vec_IntSize(vGuide) == Gia_ManEquivCountLitsAll(p)Gia_Man_t *Gia_ManSpecReduce(Gia_Man_t *, int, int, int, int, int)Gia_ManPoNum(pNew) == Gia_ManPoNum(p) + nAddPosvoid Gia_ManSpecReduceInit_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, int, int)Gia_ManSpecReduceInit(): Equivalence classes are not available. Gia_ManSpecReduceInit(): Circuit is not sequential. Gia_ManSpecReduceInit(): Mismatch in the number of registers. Gia_ManSpecReduceInit(): Dual-output miter should have even number of POs. pInit->nRegs == Gia_ManRegNum(p) && pInit->nPis == 0Gia_Man_t *Gia_ManSpecReduceInit(Gia_Man_t *, Abc_Cex_t *, int, int)Stopped unrolling after %d frames. void Gia_ManEquivTransform(Gia_Man_t *, int)Gia_ObjColors(p, iNode)Removed classes = %6d (out of %6d). Removed literals = %6d (out of %6d). Gia_ManEquivMark(): Current AIG does not have equivalences. Gia_ManEquivMark(): Input file %s could not be read. Vec_IntSize(vTrace) == nLitsAllvoid Gia_ManEquivMark(Gia_Man_t *, char *, int, int)Gia_ManEquivMark(): The number of POs is not correct: MiterPONum(%d) != AIGPONum(%d) + AIGFilteredEquivNum(%d). nLits == nLitsAlliLit == nAddPosGia_ManEquivMark(): The number of POs is not correct: MiterPONum(%d) != AIGPONum(%d) + AIGEquivNum(%d). Set %d equivalences as proved. Gia_ManEquivFilter(): Equivalence classes are not defined. Gia_ManEquivFilter(): Array of disproved POs is not available. Gia_ManPoNum(pSrm) == Gia_ManPoNum(p) + Vec_IntSize(vMap)void Gia_ManEquivFilter(Gia_Man_t *, Vec_Int_t *, int)Design POs = %d. SRM POs = %d. Spec POs = %d. Disproved POs = %d. Gia_ManEquivFilter(): Array of disproved POs contains PO index (%d), which does not fit into the range of available PO indexes of the SRM: [%d; %d]. Gia_ManEquivFilter(): One of the original POs (%d) have failed. Gia_ManEquivFilter(): Array of disproved POs contains at least one duplicate entry (%d), p->pReprs != NULL && p->pNexts != NULLvoid Gia_ManEquivImprove(Gia_Man_t *)iReprBest > 0!Gia_IsComplement(pOld)int Gia_ObjCheckTfi(Gia_Man_t *, Gia_Obj_t *, Gia_Obj_t *)void Gia_ManEquivToChoices_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *)(int)pObj->Value == Abc_LitNotCond( pRepr->Value, Gia_ObjPhaseReal(pRepr) ^ Gia_ObjPhaseReal(pObj) )pRepr->Value < pObj->ValueGia_ObjNext(pNew, Gia_ObjId(pNew, pObjNew)) == 0(Gia_ManCoNum(p) % nSnapshots) == 0Gia_Man_t *Gia_ManEquivToChoices(Gia_Man_t *, int)Gia_ObjIsConst0(pRepr) || Gia_ObjIsRo(p, pRepr)Gia_CommandSpecI(): Equivalence classes are not defined. Gia_CommandSpecI: No equivalences left. ITER %3d : Gia_CommandSpecI: There are only trivial equiv candidates left (PO drivers). Quitting. Gia_CommandSpecI(): Internal BMC could not find a counter-example. Cannot read first file %s. Cannot read second file %s. Cannot create sequential miter. The number of objects in different. The AIG structure of the miter does not match. pGia->pNexts[i] == 0int Gia_ManFilterEquivsForSpeculation(Gia_Man_t *, char *, char *, int, int)!Gia_ObjIsHead(pGia, i)ClassA < ClassBGia_ObjIsHead(pGia, ClassA)The number of two-node classes after filtering = %d. int Gia_ManFilterEquivsUsingParts(Gia_Man_t *, char *, char *)pObj->fMark0 || pObj->fMark1Gia_ObjNext(pGia, iPrev) == 0The number of literals: Before = %d. After = %d. fFlopsOnly ^ fFlopsWithvoid Gia_ManFilterEquivsUsingLatches(Gia_Man_t *, int, int, int)EQGyU)] C k 1 g # ]  a  = WCg!i Y 7yEm!k)_=u#{7qQ!QAsE5c/Kg{src/aig/gia/giaEra.cvoid Gia_ManEraHashResize(Gia_ManEra_t *)pThis->NumCounter == Vec_PtrSize( p->vStates ) - 1int Gia_ManAnalyzeResult(Gia_ManEra_t *, Gia_ObjEra_t *, int, int)Gia_ManPiNum(pAig) <= 12int Gia_ManCollectReachable(Gia_Man_t *, int, int, int, int)Gia_ManRegNum(pAig) > 0Reached the limit on states traversed (%d). Miter failed in state %d after %d transitions. States =%10d. Reached =%10d. R = %5.3f. Depth =%6d. Mem =%9.2f MB. Reachability analysis traversed %d states with depth %d. test.stgExtracted STG was written into file "%s". i@@0Asrc/aig/gia/giaEra2.cint Gia_ManDeriveCiTfo_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)pPivot->fMark0 == 0Vec_Int_t *Gia_ManDeriveCiTfoOne(Gia_Man_t *, Gia_Obj_t *)%4d %4d : Prev %4d %p 0 =%3d 1 =%3d - =%3dint Gia_ManAreFindBestVar(Gia_ManAre_t *, Gia_PtrAre_t)p->fTreeint Gia_ManAreCubeCheckTree(Gia_ManAre_t *, Gia_StaAre_t *)!Gia_StaHasValue0(pSta, iVar) && !Gia_StaHasValue1(pSta, iVar)Gia_StaHasValue0(pCube, iVar) ^ Gia_StaHasValue1(pCube, iVar)void Gia_ManAreMostUsedPi_rec(Gia_Man_t *, Gia_Obj_t *)int Gia_ManCheckPOs_rec(Gia_Man_t *, Gia_Obj_t *)p->pTarget == NULLint Gia_ManAreDeriveNexts_rec(Gia_ManAre_t *, Gia_PtrAre_t)Vec_IntSize(vTfos) == Vec_IntSize(vLits)Exceeded the limit on the number of transitions from a state cube (%d). Currently can only handle circuit with up to %d registers. %s after finding %d state cubes (%d not contained) with depth %d. StoppedCompletedCofactoringThe number of unique state minterms in computed state cubes is %d. void Gia_ManAreDeriveCexSatStart(Gia_ManAre_t *)void Gia_ManAreDeriveCexSatStop(Gia_ManAre_t *)p->pTarget != NULLiOutFailed < Gia_ManPoNum(p->pAig)void Gia_ManAreDeriveCexSat(Gia_ManAre_t *, Gia_StaAre_t *, Gia_StaAre_t *, int)sat_solver_var_value( (sat_solver *)p->pSat, Vec_IntEntry(p->vSatNumCis, Gia_ManPiNum(p->pAig)+i) ) == 0sat_solver_var_value( (sat_solver *)p->pSat, Vec_IntEntry(p->vSatNumCis, Gia_ManPiNum(p->pAig)+i) ) == 1p->iOutFail >= 0Abc_Cex_t *Gia_ManAreDeriveCex(Gia_ManAre_t *, Gia_StaAre_t *)Vec_PtrSize(vStates) >= 1Var < Gia_ManPiNum(p->pAig)int Gia_ManAreCubeCheckList(Gia_ManAre_t *, Gia_PtrAre_t *, Gia_StaAre_t *)pSta == Gia_ManAreSta(p, *pRoot)void Gia_ManAreCubeAddToList(Gia_ManAre_t *, Gia_PtrAre_t *, Gia_StaAre_t *)pRoot->nItem || pRoot->nPagevoid Gia_ManAreCompress(Gia_ManAre_t *, Gia_PtrAre_t *)void Gia_ManAreRebalance(Gia_ManAre_t *, Gia_PtrAre_t *)pNode == Gia_ManAreObj(p, *pRoot)Error: Best variable not found!!!Generated counter-example is INVALID. Generated counter-example verified correctly. SAT problem is not satisfiable. Failure...ERA manager has run out of memory after allocating 2B internal nodes.ERA manager has run out of memory after allocating 2B state cubes.Vec_IntSize(vEsop) > 0src/aig/gia/giaEsop.cvoid Eso_ManCoverPrint(Eso_Man_t *, Vec_Int_t *)Vec_IntSize(vLevel) == 0void Eso_ManMinimizeAdd(Eso_Man_t *, int)Vec_IntSize(Eso_ManCube(p, Cube)) == ivoid Eso_ManMinimizeCopy(Eso_Man_t *, Vec_Int_t *)vCube->nSize <= vCube->nCapint Eso_ManComputeAnd(Eso_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)vCube->nSize >= vCube1->nSizevCube->nSize >= vCube2->nSizeOutput %3d: ESOP has %5d cubes Outs = %d. Cubes = %d. Used = %d. Hashed = %d. iCube >= 0Vec_Int_t *Eso_ManCube(Eso_Man_t *, int)Const 0QGia_ObjIsAnd(Gia_ManObj(p, iObj))src/aig/gia/giaExist.cvoid Gia_ManQuantVerify(Gia_Man_t *, int)Mismatch at node %d related to CI %d (%d). Gia_ManObjNum(p) == 1void Gia_ManQuantSetSuppStart(Gia_Man_t *)p->vSuppWords == NULLVec_IntSize(&p->vSuppVars) == 0Vec_WrdSize(p->vSuppWords) == p->nSuppWords * Gia_ManObjNum(p)void Gia_ManQuantSetSuppZero(Gia_Man_t *)void Gia_ManQuantSetSuppCi(Gia_Man_t *, Gia_Obj_t *)p->vSuppWords != NULLp->iSuppPi == Vec_IntSize(&p->vSuppVars)void Gia_ManQuantSetSuppAnd(Gia_Man_t *, Gia_Obj_t *)!Abc_TtIsConst0( Gia_ManQuantInfoId(p, iObj), p->nSuppWords )void Gia_ManQuantUpdateCiSupp(Gia_Man_t *, int)Abc_TtIsConst0(pInfo, p->nSuppWords)void Gia_ManQuantMarkUsedCis(Gia_Man_t *, int (*)(void *, int), void *)void Gia_ManQuantDupConeSupp_rec(Gia_Man_t *, Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, Vec_Int_t *, int (*)(void *, int), void *)Gia_Man_t *Gia_ManQuantDupConeSupp(Gia_Man_t *, int, int (*)(void *, int), void *, Vec_Int_t **, int *)int Gia_ManQuantExist2(Gia_Man_t *, int, int (*)(void *, int), void *)pNew->iSuppPi > 0 && pNew->iSuppPi <= 64 * pNew->nSuppWordsOutLit > 1Vec_IntSize(vOuts) > 0Gia_ObjIsCi( Gia_ManObj(p0, Abc_Lit2Var(iLit)) )int Gia_ManQuantExistInt(Gia_Man_t *, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)pNew->iSuppPi == Gia_ManCiNum(pNew) - Vec_IntSize(vSide)pNew->iSuppPi == 0src/aig/gia/giaFalse.cvoid Gia_ManFalseRebuildOne(Gia_Man_t *, Gia_Man_t *, Vec_Int_t *, int, int)Eliminated path: Path %d : Gia_ObjIsCo(pPivot)void Gia_ManCheckFalseOne(Gia_Man_t *, int, int, Vec_Wec_t *, int, int)PO %6d : Level = %3d Timeout reached after %d seconds. There is no false path. False path contains %d nodes (out of %d): top = %d Collected %d non-overlapping false paths. Gia_Man_t *Gia_ManCheckOne(Gia_Man_t *, int, int, int, int, int)Performed %d attempts and %d changes. src/aig/gia/giaFanout.cvoid Gia_ManFanoutStart(Gia_Man_t *)void Gia_ManFanoutStop(Gia_Man_t *)void Gia_ObjAddFanout(Gia_Man_t *, Gia_Obj_t *, Gia_Obj_t *)!Gia_IsComplement(pObj) && !Gia_IsComplement(pFanout)Gia_ObjId(p, pFanout) > 0p->pFanData && Gia_ObjId(p, pObj) < p->nFansAlloc && Gia_ObjId(p, pFanout) < p->nFansAllocvoid Gia_ObjRemoveFanout(Gia_Man_t *, Gia_Obj_t *, Gia_Obj_t *)iOffset <= Vec_IntSize(vEdgeMap)Vec_Int_t *Gia_ManStartFanoutMap(Gia_Man_t *, Vec_Int_t *)p->vFanoutNums == NULLvoid Gia_ManStaticFanoutStart(Gia_Man_t *)p->vFanout == NULLVec_IntEntry(vCounts, i) == Gia_ObjFanoutNum(p, pObj)Num < 2int Gia_FanoutCreate(int, int)int Gia_ObjWhatFanin(Gia_Man_t *, Gia_Obj_t *, Gia_Obj_t *)src/aig/gia/giaForce.cvoid Frc_ObjAddFanin(Frc_Obj_t *, Frc_Obj_t *)Frc_Man_t *Frc_ManStartSimple(Gia_Man_t *)nNodes == Frc_ManNodeNum(p)pObjLog->nFanins == pObjLog->iFaninpObjLog->nFanouts == pObjLog->iFanoutvoid Frc_ManCollectSuper_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, Vec_Int_t *)void Frc_ManCollectSuper(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, Vec_Int_t *)void Frc_ManCreateRefsSpecial(Gia_Man_t *)void Frc_ManTransformRefs(Gia_Man_t *, int *, int *)Frc_Man_t *Frc_ManStart(Gia_Man_t *)pObj->iFanout > 0int Frc_ManCrossCut_rec(Frc_Man_t *, Frc_Obj_t *)int Frc_ManCrossCut2_rec(Frc_Man_t *, Frc_Obj_t *)Vec_IntSize(vOrder) == Frc_ManCoNum(p)int Frc_ManCrossCut(Frc_Man_t *, Vec_Int_t *, int)Frc_ObjIsCo(pObj)p->nCutCur == 0CrossCut = %6d void Frc_ManPlaceDfs_rec(Frc_Man_t *, Frc_Obj_t *, int *)void Frc_ManPlaceDfs(Frc_Man_t *, Vec_Int_t *)nPlaces == p->nObjsCounter == Frc_ManObjNum(p)void Frc_ManPlacementRefine(Frc_Man_t *, int, int)pPermX == pHandles%2d : Span = %e Cut = %6d (%5.2f %%) CutR = %6d Sortx\large\aig\dg1.g2^%d machine words (%d bytes). FillupRead Write src/aig/gia/giaFrames.cvoid Gia_ManUnrollDup_rec(Gia_Man_t *, Gia_Obj_t *, int)Vec_IntSize(vLimit) == 0Gia_Man_t *Gia_ManUnrollDup(Gia_Man_t *, Vec_Int_t *)Vec_Ptr_t *Gia_ManUnrollAbs(Gia_Man_t *, int)Gia_ManObj(pNew, k)->Value > 0Vec_IntSize(vOne) <= Size - 1iRank == Vec_IntSize(p->vLimit)-1Gia_ManUnr_t *Gia_ManUnrStart(Gia_Man_t *, Gia_ParFra_t *)Vec_IntSize(p->vRank) == Gia_ManObjNum(p->pOrder)Shift == Vec_IntSize(p->vStore)Convergence = %d. Dangling objects = %d. Average degree = %.3f p->pNew == NULLvoid *Gia_ManUnrollStart(Gia_Man_t *, Gia_ParFra_t *)void *Gia_ManUnrollAdd(void *, int)Gia_ManPoNum(p->pNew) == p->pPars->nFrames * Gia_ManPoNum(p->pAig)Gia_Man_t *Gia_ManUnroll(Gia_Man_t *, Gia_ParFra_t *)Frame %3d : CI = %6d. AND = %6d. CO = %6d. Gia_Man_t *Gia_ManFramesInit(Gia_Man_t *, Gia_ParFra_t *)Before cleanup = %d nodes. After cleanup = %d nodes. Gia_Man_t *Gia_ManFrames(Gia_Man_t *, Gia_ParFra_t *)pPars->nFrames > 0Gia_Man_t *Gia_ManFramesInitSpecial(Gia_Man_t *, int, int)Computing specialized unrolling with %d frames... Computed prefix of %d frames. Degree >= 0 && Degree < pArray[0]int Gia_ObjUnrRead(Gia_ManUnr_t *, int, int)Gia_ObjIsCi(pObjReal)int Gia_ObjUnrReadCi(Gia_ManUnr_t *, int, int, Gia_Man_t *)̌?p->nFront > 0src/aig/gia/giaFront.cvoid Gia_ManFrontTransform(Gia_Man_t *)pObj->Value == GIA_NONE(int)pObj->Value < p->nFrontGia_ObjId(pNew, pObjNew) == Gia_ObjId(p, pObj)Gia_Man_t *Gia_ManFront(Gia_Man_t *)Gia_ObjValue(pObj) == 0pFanin0New->Value != GIA_NONEpFanin1New->Value != GIA_NONEpNew->nObjs == p->nObjsnCrossCut == 0 || nCrossCutMax == nCrossCutMaxInitpFront[i] == 0iFront < nFrontint Gia_ManFrontFindNext(char *, int, int)Vec_IntEntry(vLeaves, i) >= 0src/aig/gia/giaFx.cint Gia_ManSopToAig(Gia_Man_t *, char *, Vec_Int_t *)Value == '-'int Gia_ManFactorGraph(Gia_Man_t *, Dec_Graph_t *, Vec_Int_t *)Kit_PlaGetVarNum(pSop) == Vec_IntSize(vLeaves)int Gia_ManFactorNode(Gia_Man_t *, char *, Vec_Int_t *)Vec_IntCheckUniqueSmall(&vLeaves)Vec_Wrd_t *Gia_ManComputeTruths(Gia_Man_t *, int, int, int)Vec_WrdCap(vTruths) == 16 || Vec_WrdSize(vTruths) == Vec_WrdCap(vTruths)Vec_Wec_t *Gia_ManFxRetrieve(Gia_Man_t *, Vec_Str_t **, int)Counter * nWords == Vec_WrdSize(vTruths)!Vec_IntEntry( vVisit, iObj )void Gia_ManFxTopoOrder_rec(Vec_Wec_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, int)Vec_IntEntry(vCube, 0) == iObjiFanin >= nInputsVec_Int_t *Gia_ManFxTopoOrder(Vec_Wec_t *, int, int, Vec_Int_t **, Vec_Int_t **)Vec_IntSize(vOrder) == nNodeMaxVec_IntSize(vOrder) > Vec_StrSize(vCompls)Gia_Man_t *Gia_ManFxInsert(Gia_Man_t *, Vec_Wec_t *, Vec_Str_t *)Lit >= 0 && Abc_Lit2Var(Lit) < Vec_IntSize(vFanins)Vec_IntEntry(vCopies, iItem) == -1Gia_Man_t *Gia_ManPerformFx(Gia_Man_t *, int, int, int, int, int)src/aig/gia/giaGen.cint Gia_ManSimulateWords(Gia_Man_t *, int)Vec_WrdSize(vSimsIn) == nWords * Gia_ManCiNum(p)int Gia_ManSimulateWordsInit(Gia_Man_t *, Vec_Wrd_t *)%s_x.train.data%s_y.train.data%s_x.test.data%s_y.test.dataVec_BitSize(vBitX) <= Vec_BitCap(vBitX)void Gia_ManDumpFiles(Gia_Man_t *, int, int, int, char *)Vec_BitSize(vBitY) <= Vec_BitCap(vBitY)Value == 4nSize[n] * Gia_ManCiNum(p) % 8 == 0Value == nBytesnSize[n] * Gia_ManCoNum(p) % 8 == 0Finished dumping files "%s" and "%s". %s.flistFinished dumping file list "%s". %s.train.pla%s.valid.pla%s.test.plaFinished dumping files: "%s.{train, valid, test}.pla". "name" : "%s", "input" : %d, "output" : %d, "and" : %d, "level" : %d, "total" : %d, "correct" : %d, "guess" : %d The number of symbols (%d) does not match other lines (%d). The number of lines (%d) is not divisible by 64. Vec_WrdSize(vSimsIn) % nWords == 0void Gia_ManSimFileRead(char *, int, int, Vec_Wrd_t *, Vec_Int_t *)nPats == 64*nWordsFinished reading %d simulation patterns for %d inputs. Probability of 1 at the output is %6.2f %%. Vec_IntSize(vValues) == nWords * 64void Gia_ManCompareValues(Gia_Man_t *, Vec_Wrd_t *, Vec_Int_t *, char *)p->nSimWords == nWordsTotal = %6d. Errors = %6d. Correct = %6d. (%6.2f %%) Naive guess = %6d. (%6.2f %%) Finished dumping statistics into file "%s". The number of inputs in the file "%s" (%d) does not match the AIG (%d). &ˬˬˬˬˬˬˬˬˬˬˬˬˬˬˬˬˬˬˬˬˬˬˬˬˬˬˬˬˬˬˬˬˬJˬrˬˬˬˬˬˬˬˬˬˬūˬˬ\|N~R~Q+fa1X` GO!HPLLysrc/aig/gia/giaGig.cVec_Str_t *Gls_ManCount(FILE *, int *)int Gls_ManParseOne(char **)int Gls_ManParse(FILE *, Gls_Man_t *)*pLine == ')'k == 4k == 4 || k == 5Index == Vec_IntEntry(p->vIndexes, iObj)Gia_Man_t *Gls_ManConstruct(Gls_Man_t *, char *)Cannot read file "%s". %s=%d BarSeqSelLut4Lut6Del7Node %d Fanouts: p->iObjData == p->nObjDatasrc/aig/gia/giaGlitch.cvoid Gli_ManFinalize(Gli_Man_t *)pObj->iFanin == (int)pObj->nFaninspObj->iFanout == (int)pObj->nFanoutspObj->iFanin < (int)pObj->nFaninsvoid Gli_ObjAddFanin(Gli_Obj_t *, Gli_Obj_t *)pFanin->iFanout < (int)pFanin->nFanoutsVec_IntSize(vFanins) <= 16int Gli_ManCreateNode(Gli_Man_t *, Vec_Int_t *, int, word *)0.0 < PiTransProb && PiTransProb < 1.0void Gli_ManSetPiRandom(Gli_Man_t *, float)pObj->fPhase == pObj->fPhase2void Gli_ManVerify(Gli_Man_t *)pObj->nGlitches >= pObj->nSwitchesvoid Gli_ManSetPiRandomSeq(Gli_Man_t *, float)Simulated %d patterns. Input transition probability %.2f. MemoryVec_IntSize(&p->vHTable) == 0src/aig/gia/giaHash.cvoid Gia_ManHashAlloc(Gia_Man_t *)void Gia_ManHashStart(Gia_Man_t *)Vec_IntSize(&vOld) > 0void Gia_ManHashResize(Gia_Man_t *)Table size = %d. Entries = %d. Hits = %d. Misses = %d. p->fAddStrash == 0int Gia_ManHashXorReal(Gia_Man_t *, int, int)int Gia_ManHashMuxReal(Gia_Man_t *, int, int, int)int Gia_ManHashAnd(Gia_Man_t *, int, int)Vec_IntSize(vLits) == 1int Gia_ManHashAndMulti(Gia_Man_t *, Vec_Int_t *)Vec_IntSize(&p->vHash) == Gia_ManObjNum(p)int *Gia_ManHashFind(Gia_Man_t *, int, int, int)p->pMuxes || iLit0 < iLit1iLit0 < iLit1 || (!Abc_LitIsCompl(iLit0) && !Abc_LitIsCompl(iLit1))iLitC == -1 || !Abc_LitIsCompl(iLit1)UTTThUUUUUUUU33333333""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333""""""""DDDDDDDD 00000000src/aig/gia/giaIf.cint Gia_ManComputeOverlap2One_rec(Gia_Man_t *, int, Vec_Str_t *, Vec_Int_t *)int Gia_ManComputeOverlap2(Gia_Man_t *)int Gia_ManComputeOverlapOne_rec(Gia_Man_t *, int)int Gia_ManComputeOverlap(Gia_Man_t *)int Gia_ManCountDupLut(Gia_Man_t *)Dup fanins = %d. CI fanins = %d. MUX fanins = %d. Total = %d. (%.2f %%) Mapping (K=%d) : %slut =%7d%s %sedge =%8d%s %slev =%5d%s %s(%.2f)%s %slevB =%5d%s void Gia_ManPrintPackingStats(Gia_Man_t *)Packing (N=%d) : %d x LUT = %d Total = %d Total LUT = %dLUT = %d : %d=%d %.1f %% Ave = %.2f The max LUT size (%d) is too large. void Gia_ManChoiceLevel_rec(Gia_Man_t *, Gia_Obj_t *)int Gia_ManChoiceLevel(Gia_Man_t *)If_Man_t *Gia_ManToIf(Gia_Man_t *, If_Par_t *)i == If_ObjId(pIfObj)int Gia_ManBuildFromMiniInt(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, int)Vec_IntSize(vLeaves) == 1pIfMan->pPars->pLutStruct == NULLGia_Man_t *Gia_ManFromIfAig(If_Man_t *)pIfMan->pPars->fDelayOpt || pIfMan->pPars->fDsdBalance || pIfMan->pPars->fUserRecLib || pIfMan->pPars->fUserSesLib54Node %d is not decomposable. Deriving LUT structures has failed. int Gia_ManNodeIfToGia(Gia_Man_t *, If_Man_t *, If_Obj_t *, Vec_Int_t *, int)Gia_ManNodeIfToGia(): Computing local AIG has failed. If_DsdManSuppSize(pIfMan->pIfDsdMan, If_CutDsdLit(pIfMan, pCutBest)) == (int)pCutBest->nLeavesint Gia_ManFromIfLogicFindLut(If_Man_t *, Gia_Man_t *, If_Cut_t *, sat_solver *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)nPermBitNum % nVarNum == 0void Gia_ManFromIfGetConfig(Vec_Int_t *, If_Man_t *, If_Cut_t *, int, Vec_Str_t *)Var < (int)pCutBest->nLeavesAbc_Lit2Var(Lit) < (int)pCutBest->nLeavesnTtBitNum + nPermBitNum < 32 * nIntNumint Gia_ManFromIfLogicFindCell(If_Man_t *, Gia_Man_t *, Gia_Man_t *, If_Cut_t *, Ifn_Ntk_t *, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)iVar >= 0 && iVar < nLeaves && pIfMan->pPars->nLutSize <= 13int Gia_ManFromIfLogicCofVars(Gia_Man_t *, If_Man_t *, If_Cut_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Gia_ObjIsAnd(Gia_ManObj(pNew, Abc_Lit2Var(iLitCofs[c])))iLitCofs[0] > 1 || iLitCofs[1] > 1Vec_IntSize(vLeaves2) == 2Mask > 0 && nLeaves <= 2 * (pIfMan->pPars->nLutSize/2) && pIfMan->pPars->nLutSize <= 13int Gia_ManFromIfLogicAndVars(Gia_Man_t *, If_Man_t *, If_Cut_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Vec_IntSize(vLeaves2) >= 1!pIfMan->pPars->fDeriveLuts || pIfMan->pPars->fTruthGia_Man_t *Gia_ManFromIfLogic(If_Man_t *)Abc_Lit2Var(Entry) < Abc_Lit2Var(pIfObj->iCopy)pNew->vConfigs == NULLpNew->pCellStr == NULL!vConfigs || Vec_IntSize(vConfigs) == 2 + Vec_IntEntry(vConfigs, 0) * Vec_IntEntry(vConfigs, 1)!Gia_ObjIsAnd(pFanin) || Gia_ObjIsLut(pNew, Gia_ObjId(pNew, pFanin))!Gia_ObjIsLut(pNew, Gia_ObjId(pNew, pObj))%s_configs.txtFinished dumping configs into file "%s". Gia_ManMappingVerify: Internal node %d does not have mapping. void Gia_ManMappingVerify(Gia_Man_t *)Gia_ManMappingVerify: CO driver %d does not have mapping. !Abc_LitIsCompl(Gia_ObjValue(Gia_ManObj(pGia, i)))void Gia_ManTransferMapping(Gia_Man_t *, Gia_Man_t *)void Gia_ManTransferPacking(Gia_Man_t *, Gia_Man_t *)Gia_ObjIsLut(pGia, Gia_ObjId(pGia, pObj))Gia_ObjIsLut(p, Gia_ObjId(p, pObjNew))p->vPacking == NULLpPars->pTimesArr == NULLGia_Man_t *Gia_ManPerformMappingInt(Gia_Man_t *, If_Par_t *)pPars->pTimesReq == NULLVec_IntSize(p->vCiArrs) == Gia_ManCiNum(p)Vec_IntSize(p->vCoReqs) == Gia_ManCoNum(p)Switching activity computation for designs with boxes is disabled. If_ManCoNum(pIfMan) == Vec_IntSize(p->vCoAttrs)pNew->pName == NULLGia_Man_t *Gia_ManPerformMapping(Gia_Man_t *, void *)Gia_Man_t *Gia_ManPerformSopBalance(Gia_Man_t *, int, int, int)Gia_Man_t *Gia_ManPerformDsdBalance(Gia_Man_t *, int, int, int, int)nFanins <= 7void Gia_ManTestStruct(Gia_Man_t *)LUT5 = %d LUT6 = %d NonDec = %d (%.2f %%) LUT7 = %d NonDec = %d (%.2f %%) Gia_Man_t *Gia_ManDupHashMapping(Gia_Man_t *)p->pLutRefsint Gia_ObjLutRefIncId(Gia_Man_t *, int)Abc_TtBitCount16(This) <= nSuppLimvoid Abc_TtDeriveBiDec(word *, int, int, int, int, word *, word *)Abc_TtBitCount16(That) <= nSuppLimint Abc_TtVerifyBiDec(word *, int, int, int, int, word, word)k == nThisk == nThatBi-decomposition verification failed.Arrival times are not given.ABC framework is not initialized by calling Abc_Start().Required times are not given.Current network in ABC framework has no CO arrival times.i == Gia_ObjLutSize(p->pGia, iObj)src/aig/gia/giaIff.cfloat Gia_IffObjTimeOne(Iff_Man_t *, int, int, int)DelayMax >= 0nSize <= p->pLib->LutMaxfloat Gia_IffObjTimeTwo(Iff_Man_t *, int, int *, float)float Gia_IffObjTimeThree(Iff_Man_t *, int, int *, int *, float)nDegree == 2 || nDegree == 3Iff_Man_t *Gia_ManIffPerform(Gia_Man_t *, If_LibLut_t *, Tim_Man_t *, int, int)arrTime3 < arrTime2Max delay = %.2f. Count1 = %d. Count2 = %d. Count3 = %d. Gia_ObjIsLut(p->pGia, iObj)void Gia_ManIffSelect_rec(Iff_Man_t *, int, Vec_Int_t *)iFaninSkip3 == -1iFaninSkip2 > 0iFaninSkip2 > 0 && iFaninSkip3 > 0Performing %d-clustering with %d-LUTs: The LUT size is more than 6.LUT library for packing 6-LUTs should have 11 or 16 inputs.LUT library for packing 4-LUTs should have 7 or 10 inputs.The total of %d classes: %5d : (%3d,%3d) Iter %4d : Entries =%8d. Uniques =%8d. Singles =%8d. pLevSizes[i] > 0src/aig/gia/giaIso.cvoid Gia_IsoPrepare(Gia_IsoMan_t *)pLevBegins[MaxLev+1] == p->nObjsp->pUniques[Gia_IsoGetItem(p, iBegin)] == 0void Gia_IsoAssignUnique(Gia_IsoMan_t *)int Gia_IsoSort(Gia_IsoMan_t *)p->pUniques[Gia_IsoGetItem(p, iBeginOld)] == 0Vec_IntSize(p->vClasses) > 0void Gia_IsoAssignOneClass2(Gia_IsoMan_t *)p->pUniques[Gia_IsoGetItem(p, iBegin+1)] == 0Broke ties in class %d of size %d at level %d. void Gia_IsoAssignOneClass3(Gia_IsoMan_t *)Broke ties in last class of size %d at level %d. void Gia_IsoAssignOneClass(Gia_IsoMan_t *, int)p->pUniques[Gia_IsoGetItem(p, iBegin+k)] == 0Broke ties in class of size %d at level %d. Obj %6d : Level = %4d. iBegin = %4d. Size = %4d. Gia_ManCiNum(pGia) > 0Vec_Ptr_t *Gia_IsoDeriveEquivPos(Gia_Man_t *, int, int)Gia_ManPoNum(pGia) > 0Start Simulate Sort void Gia_ManFindCaninicalOrder_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)Gia_ObjFanin0(pObj)->Value != Gia_ObjFanin1(pObj)->ValueGia_Man_t *Gia_ManIsoCanonicize(Gia_Man_t *, int)Gia_ManObjNum(p) == 2Gia_ManPoNum(pPart) == 1Vec_Str_t *Gia_ManIsoFindString(Gia_Man_t *, int, int, Vec_Int_t **)Gia_ManObjNum(pPart) == 2(Gia_ManPoNum(pInit) & 1) == 0Gia_Man_t *Gia_ManIsoReduce(Gia_Man_t *, Vec_Ptr_t **, Vec_Ptr_t **, int, int, int, int)Reduced %d outputs to %d candidate classes (%d outputs are in %d non-trivial classes). %6d %6d %6d : pvPiPerms == NULL || Vec_PtrArray(*pvPiPerms)[iPo] == NULLCounter == Gia_ManPoNum(p)Reduced %d outputs to %d equivalence classes (%d outputs are in %d non-trivial classes). Reduced %d dual outputs to %d dual outputs. Reduced %d outputs to %d. void Gia_IsoTest(Gia_Man_t *, Abc_Cex_t *, int)jKS"bGݾ#&*UY4З.67ks"f܋.{]|tUʊtkP/#>W4hN^ Q'*9>(|7pQ|z{}.^jI}[UKIUj5XH;8K.*廌i; Vb %Kk=2dv7?7DwK+.1^#[Ɣz!52WdO_ncN{T}"[EyCQU弔!/og:Iy%7dʯt|P>t WPeo<_º2!p`&(OeR V&rj)ľU/Len4O_3(&H}=RW(:qQtޙzMRDoZF{Əi49>42yLl(yۣ8KT 5U*B5QX  ~V>qS$!tBJyt K9z 2.%-i_HE7{UJ2Q#y*M8A(r"7K ,QWڄw>>G,E( d8FmG <$e5tyNJm[ ̄u[2)rnZ4f^1+Ǎ,Ȩ-P؜hf8.t^CM*Ŏ<ܮXA>zZ;ZHoY Z:k 0PD\i%^: t+O⁏rM.tG/݂OfižԢުGɤTpI@ ,uј,\],Y7[?8/Ebr\4֦,CwBPd(C)1!թ9ޥ;gJ; DUٙ#u(YYi&1\lc߻A=ƪL )^Lg",Lb/FwO"\ mXGConsidering random permutation of the primary inputs of the AIG:CEX for the init AIG is not valid.CEX for the perm AIG is not valid.CEX for the perm AIG is valid.CEX for the init AIG is valid.jKS"bGݾ#&*UY4З.67ks"f܋.{]|tUʊtkP/#>W4hN^ Q'*9>(|7pQ|z{}.^jI}[UKIUj5XH;8K.*廌i; Vb %Kk=2dv7?7DwK+.1^#[Ɣz!52WdO_ncN{T}"[EyCQU弔!/og:Iy%7dʯt|P>t WPeo<_º2!p`&(OeR V&rj)ľU/Len4O_3(&H}=RW(:qQtޙzMRDoZF{Əi49>42yLl(yۣ8KT 5U*B5QX  ~V>qS$!tBJyt K9z 2.%-i_HE7{UJ2Q#y*M8A(r"7K ,QWڄw>>G,E( d8FmG <$e5tyNJm[ ̄u[2)rnZ4f^1+Ǎ,Ȩ-P؜hf8.t^CM*Ŏ<ܮXA>zZ;ZHoY Z:k 0PD\i%^: t+O⁏rM.tG/݂OfižԢުGɤTpI@ ,uј,\],Y7[?8/Ebr\4֦,CwBPd(C)1!թ9ޥ;gJ; DUٙ#u(YYi&1\lc߻A=ƪL )^Lg",Lb/FwO"\ mXGsrc/aig/gia/giaIso2.cunsigned int Gia_Iso2ManCone_rec(Gia_Man_t *, int, int)int Gia_Iso2ManUniqify(Gia_Iso2Man_t *)Vec_IntEntry(p->vUniques, Gia_ObjId(p->pGia, pObj)) == -1void Gia_Iso2ManCollectOrder2_rec(Gia_Man_t *, int, Vec_Int_t *)void Gia_Iso2ManCollectOrder_rec(Gia_Man_t *, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Vec_IntSize(vClass) > 1int Gia_Iso2ManCheckIsoClassOneSkip(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)Finished %8d outputs (out of %8d)... P>Iter %3d : %6d out of %6d .}=R.6d&1߻jKS"bGݾ#&*UY4З.67ks"f܋.{]|tUʊ{Gzt?Vec_IntSize(vLeaves) > 0src/aig/gia/giaJf.cvoid Jf_ManGenCnf(word, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)pCnf->pObj2Count[iOut] > 0Cnf_Dat_t *Jf_ManCreateCnf(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *)float *Jf_ManInitRefs(Jf_Man_t *)DSD classes that appear in more than %.1f %% of mapped nodes: iFunc < 595void Jf_ManProfileClasses(Jf_Man_t *)%5.1f %% Other : pPars->nLutSize <= JF_LEAF_MAXJf_Man_t *Jf_ManAlloc(Gia_Man_t *, Jf_Par_t *)pPars->nCutNum <= JF_CUT_MAXUnique truth tables = %d. Memory = %.2f MB last <= cint Jf_ObjCutFilterBoth(Jf_Man_t *, Jf_Cut_t **, int)int Jf_TtComputeForCut(Jf_Man_t *, int, int, int *, int *, int *)pSto[c]->pCut[0] <= nOldSuppvoid Jf_ObjComputeCuts(Jf_Man_t *, Gia_Obj_t *, int)c <= CutNumJf_ObjIsUnit(Gia_ObjFanin0(pObj)) && Jf_ObjIsUnit(Gia_ObjFanin1(pObj))pSto[0]->Cost >= 0pSto[0]->Flow >= 0Aig: CI = %d CO = %d AND = %d LutSize = %d CutMax = %d Rounds = %d Computing cuts... CutPair = %lu Merge = %lu Eval = %lu Cut = %lu Memory: Gia = %.2f MB Man = %.2f MB Cuts = %.2f MB Coarse = %d (%.1f %%)Gia_ObjRefNum(p->pGia, pObj) > 0int Jf_ManComputeDelay(Jf_Man_t *, int)p->pGia->pRefs != NULLint Jf_ManComputeRefs(Jf_Man_t *)Jf_ObjIsUnit(pObj)pFlow[i] >= 0void Jf_ManPropagateEla(Jf_Man_t *, int)Gia_Man_t *Jf_ManDeriveMappingGia(Jf_Man_t *)Class == 0Class == 1p->pDsd == NULL || Sdm_ManReadDsdVarNum(p->pDsd, Class) == Jf_CutSize(pCut)!p->pPars->fCutMinvoid Jf_ManDeriveMapping(Jf_Man_t *)!p->pPars->fCutMin || Jf_CutSize(pCut) <= 6Vec_IntCap(vMapping) == 16 || Vec_IntSize(vMapping) == Vec_IntCap(vMapping)Gia_Man_t *Jf_ManDeriveGia(Jf_Man_t *)%s : Level =%6lu Area =%9lu Edge =%9lu Cnf =%9lu !Gia_ManBufNum(pGia)Gia_Man_t *Jf_ManPerformMapping(Gia_Man_t *, Jf_Par_t *)!pPars->fCutMin || !pPars->fFuncDsd || pPars->nLutSize <= 6Flow Edge test.cnf%d : %d %d Jf_ObjIsUnit(p)void Jf_ObjCleanUnit(Gia_Obj_t *)int Jf_CutIsContainedOrder(int *, int *)float Jf_CutFlow(Jf_Man_t *, int *)c <= cMaxint Jf_ObjAddCutToStore(Jf_Man_t *, Jf_Cut_t **, int, int)Gia_ObjIsCi(pObj) || Gia_ObjIsBuf(pObj)void Jf_ObjAssignCut(Jf_Man_t *, Gia_Obj_t *)void Jf_ObjPropagateBuf(Jf_Man_t *, Gia_Obj_t *, int)pCuts < pCutvoid Jf_ObjSetBestCut(int *, int *, Vec_Int_t *)""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333UUUUUUUU33333333Hard limit on the number of different Boolean functions (2^23) is reached. Quitting...Z@ src/aig/gia/giaKf.cint Kf_ManComputeDelay(Kf_Man_t *, int)int Kf_ManComputeRefs(Kf_Man_t *)void *Kf_WorkerThread(void *)Vec_Int_t *Kf_ManCreateFaninCounts(Gia_Man_t *)void Kf_ManComputeCuts(Kf_Man_t *)Vec_IntSum(vFanins) == 0LutSize = %d CutMax = %d Threads = %d Vec_IntSize(p->vTemp) == 1 + KF_ADD_ON1 + KF_ADD_ON2void Kf_ManComputeMapping(Kf_Man_t *)Cuts = %.2f MB Set = %.2f KB pPars->nLutSize <= KF_LEAF_MAXKf_Man_t *Kf_ManAlloc(Gia_Man_t *, Jf_Par_t *)pPars->nCutNum <= KF_CUT_MAXpPars->nProcNum <= KF_PROC_MAXGia_Man_t *Kf_ManDerive(Kf_Man_t *)void Kf_SetMergeOrder(Kf_Set_t *, int *, int *, int, int)pCutR->nLeaves > 1int Kf_SetCutIsContainedOrder(Kf_Cut_t *, Kf_Cut_t *)p->nCuts > 0void Kf_SetFilterOrder(Kf_Set_t *)nCuts > 0 && nCuts < p->nCutNumvoid Kf_SetSelectBest(Kf_Set_t *, int, int)p->nCuts == nCutsnCuts > 0 && nCuts < KF_CUT_MAXvoid Kf_ManSaveResults(Kf_Cut_t **, int, Kf_Cut_t *, Vec_Int_t *)Vec_IntEntry(vTemp, 1) > 0p->nTEntries == 0void Kf_HashPopulate(Kf_Set_t *, Kf_Cut_t *)p->nTEntries == pCut->nLeavesint Kf_HashLookup(Kf_Set_t *, int)void Kf_SetFilter(Kf_Set_t *)void Kf_SetMergeSimple(Kf_Set_t *, int *, int *, int, int)nSizeB >= nSizeCint Kf_SetCutIsContainedSimple(Kf_Cut_t *, Kf_Cut_t *)void Kf_SetFilterSimple(Kf_Set_t *) @Index < 2 || Gia_ObjIsMux(p->pGia, pDriver)src/aig/gia/giaLf.cint Lf_ObjCoArrival2_rec(Lf_Man_t *, Gia_Obj_t *)int Lf_ManComputeCrossCut(Gia_Man_t *)pObj->Value == 0CutMax = %d Vec_FltCap(vSwitches) == 0void Lf_ManComputeSwitching(Gia_Man_t *, Vec_Flt_t *)void Lf_ObjMergeOrder(Lf_Man_t *, int)pCutSave->nLeaves == 1pCutSave->pLeaves[0] == Gia_ObjFaninId2(p->pGia, iObj)(int)pCut0->nLeaves + (int)pCut1->nLeaves + 1 <= p->pPars->nLutSizenCutsR == 1 || pCutsR[0]->Delay <= pCutsR[1]->Delay!pCut0->fMux7The number of used cutsets = %d. void Lf_ManSetCutRefs(Lf_Man_t *)Lf_ObjMapRefNum(p, iObj) > 0void Lf_ManSetMapRefsOne(Lf_Man_t *, int)!pBest->Cut[0].fUsed && !pBest->Cut[1].fUsed!pCut->fMux7 || pCut->nLeaves == 3Relaxing user-specified delay target from %d to %d. !Gia_ManBufNum(p->pGia)int Lf_ManSetMapRefs(Lf_Man_t *)Vec_IntSize(&p->vMapRefs) == Gia_ManAndNotBufNum(p->pGia)Vec_FltSize(&p->vFlowRefs) == Gia_ManAndNotBufNum(p->pGia)void Lf_ManCountMapRefsOne(Lf_Man_t *, int)Lf_BestIsMapped(pBest)!pCut->fMux7void Lf_ManCountMapRefs(Lf_Man_t *)!p->pPars->fCutMin && p->pGia->vMapping == NULLGia_Man_t *Lf_ManDeriveMapping(Lf_Man_t *)!Gia_ObjIsBuf(Gia_ManObj(p->pGia,i))!p->pPars->fCutMin && pGia->pMuxesGia_Man_t *Lf_ManDeriveMappingCoarse(Lf_Man_t *)Vec_IntCap(pNew->vMapping) == 16 || Vec_IntSize(pNew->vMapping) == Vec_IntCap(pNew->vMapping)Gia_Man_t *Lf_ManDeriveMappingGia(Lf_Man_t *)pCut->iFunc >= 0Abc_Lit2Var(pCut->iFunc) == 0Abc_Lit2Var(pCut->iFunc) == 1pPars->nCutNum > 1 && pPars->nCutNum <= LF_CUT_MAXLf_Man_t *Lf_ManAlloc(Gia_Man_t *, Jf_Par_t *)pPars->nLutSize > 1 && pPars->nLutSize <= LF_LEAF_MAXk == Gia_ManAndNotBufNum(pGia)LUT =%9lu Swt =%8.1f Mux7 =%7lu LutSize = %d CutNum = %d Iter = %d Ratio = %d Edge = %d Delay = %d CutMin = %d Coarse = %d Cut/Set = %d/%d BytesCreated %d regular %d-LUTs and %d dual %d-LUTs. The total of %d %d-LUTs. Best = %.2f MB Front = %.2f MB Map = %.2f MB TT = %.2f MB Total = %.2f MB%d:%d Equal = %d (%.0f %%) TT = %d (%.2f %%) MuxTT = %d (%.0f %%) CoDrvs = %d (%.2f %%) CoInvs = %d (%.2f %%) Front = %d (%.2f %%) TimeFails = %d p->vStoreNew.iCur == 0void Lf_ManComputeMapping(Lf_Man_t *)Ela Initial Derived Gia_Man_t *Lf_ManPerformMapping(Gia_Man_t *, Jf_Par_t *)!pPars->fCutGroup || pPars->nLutSize == 9 || pPars->nLutSize == 11 || pPars->nLutSize == 13Gia_Man_t *Gia_ManPerformLfMapping(Gia_Man_t *, Jf_Par_t *, int)Lf_Cut_t *Lf_MemLoadMuxCut(Lf_Man_t *, int, Lf_Cut_t *)Page < Vec_PtrSize(&p->vPages)Lf_Cut_t *Lf_MemLoadCut(Lf_Mem_t *, int, int, Lf_Cut_t *, int, int)pCut->nLeaves <= LF_LEAF_MAXpCut->nLeaves >= 2 || pCut->iFunc <= 3!pCut->fMux7 || Gia_ObjIsMux(p->pGia, pMux)void Lf_CutParams(Lf_Man_t *, Lf_Cut_t *, int, float, Gia_Obj_t *)pCut->nLeaves < LF_NO_LEAFpBest->Delay[0] <= pBest->Delay[1]pBest->Flow[0] >= pBest->Flow[1]nCuts >= 1int Lf_SetAddCut(Lf_Cut_t **, int, int)int Lf_SetCutIsContainedOrder(Lf_Cut_t *, Lf_Cut_t *)int Lf_CutComputeTruthMux(Lf_Man_t *, Lf_Cut_t *, Lf_Cut_t *, Lf_Cut_t *, int, int, int, Lf_Cut_t *)int Lf_CutComputeTruthMux6(Lf_Man_t *, Lf_Cut_t *, Lf_Cut_t *, Lf_Cut_t *, int, int, int, Lf_Cut_t *)int Lf_CutComputeTruth(Lf_Man_t *, Lf_Cut_t *, Lf_Cut_t *, int, int, Lf_Cut_t *, int)int Lf_CutComputeTruth6(Lf_Man_t *, Lf_Cut_t *, Lf_Cut_t *, int, int, Lf_Cut_t *, int)int Lf_MemSaveCut(Lf_Mem_t *, Lf_Cut_t *, int)p->MaskPage - (p->iCur & p->MaskPage) >= 4 * (LF_LEAF_MAX + 2)Gia_ObjIsAndNotBuf(pObj)Lf_Cut_t *Lf_ManFetchSet(Lf_Man_t *, int)iVar >= 0 && iVar < (int)pCut->nLeavesint Lf_ManDerivePart(Lf_Man_t *, Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Lf_Cut_t *, Vec_Int_t *, Vec_Int_t *, Gia_Obj_t *)void Vec_MemAddMuxTT(Vec_Mem_t *, int)""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333UUUUUUUU33333333A TT = %d (%.2f %%) src/aig/gia/giaMf.cVec_Wrd_t *Mf_ManTruthCollect(int)Original = %d. Unique = %d. Unique = %d. Occur = %4d CNF size = %2d p->pPars->nLutSize <= 8Vec_Int_t *Mf_ManDeriveCnfs(Mf_Man_t *, int *, int *, int *)nCubes == Vec_IntEntry(&p->vCnfSizes, iFunc)Cnf_Dat_t *Mf_ManDeriveCnf(Mf_Man_t *, int, int)pCnf->vMapping == NULLMf_CubeLit(pCubes[c], k)pCnfIds[Id] >= 0 && pCnfIds[Id] < nVarsiCla == nClasiLit == nLitspCnf->pObj2Count[Id] > 0void Mf_ObjMergeOrder(Mf_Man_t *, int)Gia_Man_t *Mf_ManDeriveMapping(Mf_Man_t *)Gia_Man_t *Mf_ManDeriveMappingCoarse(Mf_Man_t *)Gia_Man_t *Mf_ManDeriveMappingGia(Mf_Man_t *)Abc_Lit2Var(Mf_CutFunc(pCut)) == 0Abc_Lit2Var(Mf_CutFunc(pCut)) == 1pPars->nCutNum > 1 && pPars->nCutNum <= MF_CUT_MAXMf_Man_t *Mf_ManAlloc(Gia_Man_t *, Jf_Par_t *)pPars->nLutSize > 1 && pPars->nLutSize <= MF_LEAF_MAX!p->pPars->fGenCnf || Vec_IntSize(&p->vCnfSizes) == Vec_MemEntryNum(p->vTtMem)void Mf_ManFree(Mf_Man_t *)CNF =%9lu CNF = %d Cut = %.2f MB %d = %d nLutSize >= 3 && nLutSize <= 8void *Mf_ManGenerateCnf(Gia_Man_t *, int, int, int, int, int)Ent == iVec_Int_t *Vec_IntUniqifyHash(Vec_Int_t *, int)Vec_IntSize(vUnique) == nUnique * nIntSizenCubes <= 64int Abc_Tt6Cnf(word, int, int *)word Abc_Tt6IsopCover(word, word, int, int *, int *)nCubes <= 256int Abc_Tt8Cnf(word *, int, int *)void Abc_Tt8IsopCover(word *, word *, int, word *, int *, int *)(uOn[0] & ~uRes[0]) == 0 && (uOn[1] & ~uRes[1]) == 0 && (uOn[2] & ~uRes[2]) == 0 && (uOn[3] & ~uRes[3]) == 0(uRes[0] & ~uOnDc[0])==0 && (uRes[1] & ~uOnDc[1])==0 && (uRes[2] & ~uOnDc[2])==0 && (uRes[3] & ~uOnDc[3])==0void Abc_Tt7IsopCover(word *, word *, int, word *, int *, int *)(uOn[0] & ~uRes[0]) == 0 && (uOn[1] & ~uRes[1]) == 0(uRes[0] & ~uOnDc[0])==0 && (uRes[1] & ~uOnDc[1])==0nLeaves <= p->pPars->nLutSizevoid Mf_CutParams(Mf_Man_t *, Mf_Cut_t *, float)int Mf_SetCutIsContainedOrder(Mf_Cut_t *, Mf_Cut_t *)int Mf_CutComputeTruthMux(Mf_Man_t *, Mf_Cut_t *, Mf_Cut_t *, Mf_Cut_t *, int, int, int, Mf_Cut_t *)int Mf_CutComputeTruthMux6(Mf_Man_t *, Mf_Cut_t *, Mf_Cut_t *, Mf_Cut_t *, int, int, int, Mf_Cut_t *)int Abc_Tt6CnfSize(word, int)int Abc_Tt8CnfSize(word *, int)int Abc_Tt8Isop(word *, word *, int, word *)int Abc_Tt7Isop(word *, word *, int, word *)int Mf_CutComputeTruth(Mf_Man_t *, Mf_Cut_t *, Mf_Cut_t *, int, int, Mf_Cut_t *, int)int Mf_CutComputeTruth6(Mf_Man_t *, Mf_Cut_t *, Mf_Cut_t *, int, int, Mf_Cut_t *, int)!Mf_CutIsTriv(pCut, iObj)void Mf_ObjComputeBestCut(Mf_Man_t *, int)Mf_CutSize(pCut) <= p->pPars->nLutSizevoid Mf_ObjSetBestCut(int *, int *)""""""""DDDDDDDD 00000000jKS"bGݾ#&*UY4З.67ks"f܋.{]|tUʊUUUUUUUU33333333""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333jjjjjjnObjsMax > 0src/aig/gia/giaMan.cGia_Man_t *Gia_ManStart(int)void Gia_ManStop(Gia_Man_t *)dom1.aigdom2.aigPlacement: Objects = %8d. Fixed = %8d. Undef = %8d. void Gia_ManPrintTents(Gia_Man_t *)Tents: %d=%d(%d) Unused=%d B = %d Q = %d void Gia_ManPrintInitClasses(Vec_Int_t *)!Gia_ObjSiblObj(p, i)->fMark0void Gia_ManPrintChoiceStats(Gia_Man_t *)Gia_ObjIsAnd(Gia_ObjSiblObj(p, i))Choice stats: Equivs =%7d. Choices =%7d. Edges (Q=2) : edge =%8d lev =%5.1f "level" : %d %-8s : %s%-8s%s : i/o =%7d/%7d ff =%7d boxff =%d(%d) %s =%8dnod lev =%5d (%.2f) %s%s =%8d%s %slev =%5d%s %s(%.2f)%s cut = %d(%d) ch =%5d box = %d bb = %d xor = %d XOR/MUX power =%8.1f %6.2f %%and =%8d lev =%5d Outputs = %7d. Unsat = %7d. Sat = %7d. Undec = %7d. Level = %5d Supp = %5d Cone = %5d Mffc = %5d Prob = %8.4f void Gia_ManSetRegNum(Gia_Man_t *, int)void Gia_ManPrintNpnClasses(Gia_Man_t *)Gia_ManLutSizeMax( p ) <= 4NPN CLASS STATISTICS (for %d LUT4 present in the current mapping): %3d: Class %3d : Count = %6d (%7.2f %%) %s Other : Count = %6d (%7.2f %%) Approximate number of 4:1 MUX structures: All = %6d (%7.2f %%) MFFC = %6d (%7.2f %%) Gia_ObjIsLut(p, iObj)void Gia_ManDfsCollect_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)Vec_Int_t *Gia_ManDfsArrivals(Gia_Man_t *, Vec_Int_t *)Time0 >= 0Gia_ObjIsLut(p, Entry)Time0 >= 0 && Time1 >= 0Vec_Int_t *Gia_ManDfsRequireds(Gia_Man_t *, Vec_Int_t *, int)Req >= 0Arr <= ReqVec_Int_t *Gia_ManDfsSlacks(Gia_Man_t *)nTotal > 0void Gia_ManDfsSlacksPrint(Gia_Man_t *)Slack range %3d = [%4d, %4d) Nodes = %5d int Gia_ManNameIsLegalInVerilog(char *)%c%0*d%c, ); buf( %s, not( %s, and( %s, buf( %s, 1'b%d ); Statistics for each outputs of the miter:Network contains no internal objects.Currently cannot write sequential AIG.src/aig/gia/giaMem.cchar *Gia_MmFixedEntryFetch(Gia_MmFixed_t *)char *Gia_MmFlexEntryFetch(Gia_MmFlex_t *, int)nLutSizeMax < 16src/aig/gia/giaMfs.cSfm_Ntk_t *Gia_ManExtractMfs(Gia_Man_t *)Gia_ObjCopyArray(p, iFan) >= 0Vec_IntSize(vLeaves) < 16Vec_IntSize(vLeaves) == Gia_ObjLutSize(p, Id)Counter == nMfsVarsGia_ManCiNum(p->pAigExtra) < 16Vec_IntSize(vArray) == 0curCi - nRealPis == Gia_ManCoNum(p->pAigExtra)iBbIn == nBbInsiBbOut == nBbOutsiMfsId > 0Gia_Man_t *Gia_ManInsertMfs(Gia_Man_t *, Sfm_Ntk_t *, int)Vec_IntSize(vBoxesLeft) <= nBoxesVec_IntSize(vMfsTopo) > 0Abc_LitIsCompl(iGroup)iLitNew >= 0Sfm_NodeReadUsed(pNtk, iMfsId)Vec_IntEntryLast(vMapping2) == Abc_Lit2Var(iLitNew)pTruth[0] == uTruthVar || pTruth[0] == ~uTruthVarGia_Man_t *Gia_ManPerformMfs(Gia_Man_t *, Sfm_Par_t *)p->vMapping != NULLTiming manager is given but there is no GIA of boxes. Currently "&mfs" cannot process the network containing white-boxes with more than 15 inputs. Currently "&mfs" cannot process the network containing nodes with more than 15 fanins. The network is not changed by "&mfs". The network has %d nodes changed by "&mfs". int Abc_TtSimplify(word *, int *, int, int *)int Abc_TtMinimumBase(word *, int *, int, int *)UUUUUUUU33333333""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333""""""""DDDDDDDD 00000000src/aig/gia/giaMini.cGia_Man_t *Gia_ManFromMiniAig(Mini_Aig_t *, Vec_Int_t **)Gia_Man_t *Gia_ManFromMiniLut(Mini_Lut_t *, Vec_Int_t **)Gia_ManHasMapping(pGia)Mini_Lut_t *Gia_ManToMiniLut(Gia_Man_t *)LutSize >= 2Vec_IntSize(vLeaves) == Gia_ObjLutSize(pGia, i)pRes[i] == -1int *Gia_ManMapMiniLut2MiniAig(Gia_Man_t *, Gia_Man_t *, Gia_Man_t *, Vec_Int_t *, Vec_Int_t *)Found functional mismatch for LutId %d and AigId %d. Found phase mismatch for LutId %d and AigId %d. iReprMini < iVec_Int_t *Gia_ManMapEquivAfterScorr(Gia_Man_t *, Vec_Int_t *)Gia_Man_t *Gia_MiniAigReduce(Mini_Aig_t *, int *)Gia_Man_t *Gia_MiniAigMiter(Mini_Aig_t *, int *)nPos > Mini_AigRegNum(p)iPos == nPosMini_AigRegNum(p) == Gia_ManCoNum(pGia) - Tempmini_aig_miter.aigmini_aig_reduced.aig&ps; &scorr; &psDumped miter AIG in file "%s". Dumped reduced AIG in file "%s". ./src/aig/miniaig/minilut.hId >= 0 && Id < p->nSizeint Mini_LutNodeFanin(Mini_Lut_t *, int, int)LutSize >= 2 && LutSize <= 16Mini_Lut_t *Mini_LutStart(int)p->LutSize*p->nSize < MINI_LUT_NULL/2void Mini_LutPush(Mini_Lut_t *, int, int *, unsigned int *)pVars[i] >= 0 && pVars[i] < p->nSizevoid Mini_LutGrow(Mini_Lut_t *, int)p->pTruthsnVars >= 0 && nVars <= p->LutSizeint Mini_LutCreateNode(Mini_Lut_t *, int, int *, unsigned int *)Var0 >= 0 && Var0 < p->nSizeint Mini_LutCreatePo(Mini_Lut_t *, int)GIA derived from MiniLut is not available.Internal GIA with equivalence classes is not directly derived from MiniAig.Equivalence classes of internal GIA are not available.Internal GIA with equivalence classes is not available.Mapping of MiniAig nodes is not available.GIA derived from MiniAig is not available.K(Węș͙әٙޙQxor =%8d %6.2f %% mux =%8d %6.2f %% and =%8d %6.2f %% src/aig/gia/giaMuxes.cGia_Man_t *Gia_ManDupMuxes(Gia_Man_t *, int)p->pMuxes != NULL || Gia_ManXorNum(p)Gia_Man_t *Gia_ManDupNoMuxes(Gia_Man_t *, int)!Gia_ManHasChoices(p)Gia_Man_t *Gia_ManMuxRestructure(Gia_Man_t *)!Gia_ManHasMapping(p)Gia_ObjIsMuxId(p, iObj)int Gia_MuxRef(Gia_Man_t *, int)int Gia_MuxDeref(Gia_Man_t *, int)int Gia_MuxMffcSize(Gia_Man_t *, int)<%02d> [(void Gia_MuxStructPrint(Gia_Man_t *, int)int Gia_MuxStructDump(Gia_Man_t *, int, Vec_Str_t *, int, int)The distribution of MUX tree %s: widthssizes %d=%d Summary: Max = %d Ave = %.2fAbc_NamObjNumMax(pMan->pNames) == Vec_WecSize(pMan->vTops)void Gia_ManMuxProfiling(Gia_Man_t *)MUX structure profile for AIG "%s": Total MUXes = %d. Total trees = %d. Unique trees = %d. Memory = %.2f MB The first %d structures: Occur = %4d Size = %4d For example, structure %d has %d MUXes and bit-width %d: %d = %s !Gia_ObjIsRi(p, pObj)int Gia_ManEncodeObj(Gia_Man_t *, int)int Gia_ManEncodeFanin(Gia_Man_t *, int)Gia_ObjType_t Gia_ManEncodeFanout(Gia_Man_t *, Gia_Obj_t *, int) %5s -> %d x %sVec_IntSize(vRes) == Gia_ManObjNum(p)Vec_Int_t *Gia_ManProfileHash(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *)void Gia_ManProfileStructuresInt(Gia_Man_t *, int, int)Vec_IntSize(vCodeOffsets) == Gia_ManObjNum(p)Showing TFI/node/TFO structures that appear more than %d times. Weight =%6d First obj =Vec_IntSize(vRes) < Gia_ManCiNum(p)Vec_Wec_t *Gia_ManFindCofs(Gia_Man_t *, Vec_Int_t *, Gia_Man_t **)Vec_IntSize(vLayer) == Gia_ManCoNum(p)Vec_IntSize(vMap) == Vec_WecSize(vCofs)Vec_Int_t *Gia_ManFindEquivClasses(Vec_Wec_t *)nBits < Vec_IntSize(vIns)void Gia_ManFindDerive(Gia_Man_t *, int, Vec_Int_t *, Vec_Wec_t *, Vec_Int_t *)Vec_IntSize(vMap) == (1 << Vec_IntSize(vIns))Cof >= 0 && Cof < Vec_WecSize(vCofs)Vec_IntSize(vData) == (1 << nBits)Vec_IntSize(vBits) == nBitsiC0iC1iPIiFFiXORiMUXiANDiANDniANDpoPOoFFoXORoMUXcoMUXdoANDoANDnoANDpGIA_ENDShowing TFI/node/TFO structures for all nodes:????   nFans == (int)pCell->nFaninssrc/aig/gia/giaNf.cvoid Nf_StoCreateGateAdd(Vec_Mem_t *, Vec_Wec_t *, Mio_Cell2_t *, word, int *, int, Vec_Wec_t *, Vec_Int_t *, int, int, int)Vec_WecSize(vTt2Match) == Vec_WecSize(vProfs)Vec_IntSize(vArray) == 2 * Vec_IntSize(vArrayProfs)pCell->nFanins <= 6void Nf_StoCreateGateMaches(Vec_Mem_t *, Vec_Wec_t *, Mio_Cell2_t *, int **, int **, int *, Vec_Wec_t *, Vec_Int_t *, int, int, int)Gate %16s Area =%8.2f In = %d compl Gates = %d. Truths = %d. Matches = %d. pPars->nCutNum > 1 && pPars->nCutNum <= NF_CUT_MAXNf_Man_t *Nf_StoCreate(Gia_Man_t *, Jf_Par_t *)pPars->nLutSize > 1 && pPars->nLutSize <= NF_LEAF_MAXvoid Nf_ObjMergeOrder(Nf_Man_t *, int)Delay =%8.2f Area =%12.2f Gate =%6d Inv =%6d Edge =%7d Coarse = %d Cells = %d Funcs = %d Matches = %d And = %d Choices = %d Merge = %.0f (%.1f) Eval = %.0f (%.1f) Cut = %.0f (%.1f) Use = %.0f (%.1f) Mat = %.0f (%.1f) Total = %.2f MB %5d %s : D =%6.2f C = %d Cut = {iFuncLit == 0 || iFuncLit == 1void Nf_ManCutMatchOne(Nf_Man_t *, int, int *, int *)nFans == (int)pC->nFanins!Nf_CutIsTriv(pCut, iObj)void Nf_ManCutMatch(Nf_Man_t *, int)Nf_CutSize(pCut) <= p->pPars->nLutSizepDp->D < SCL_INFINITY || pDn->D < SCL_INFINITYp->Iter > 0Object %d has pDp unassigned. Object %d has pDn unassigned. Object %d has pAp unassigned. Object %d has pAn unassigned. pDp->D < SCL_INFINITYpAp->D < SCL_INFINITYpAn->D < SCL_INFINITYpDp->F < FLT_MAXpDn->F < FLT_MAXpAp->F < FLT_MAXpAn->F < FLT_MAX******** Critical delay violation %.2f -> %.2f ******** Relaxing user-specified delay target from %.2f to %.2f. Nf_CutSize(pCut) == (int)pCell->nFaninsvoid Nf_ManSetMapRefsGate(Nf_Man_t *, int, int, Nf_Mat_t *)pM->fBest == 0Dp = %6.2f Dn = %6.2f Ap = %6.2f An = %6.2f Dp = %8s Dn = %8s Ap = %8s An = %8s !p->fUseElaint Nf_ManSetMapRefs(Nf_Man_t *)!pMs[0]->fCompl || !pMs[1]->fComplpMs[c]->fCompl && !pMs[!c]->fCompl!pM->fComplnRefs[c] && !nRefs[!c]pM->fBestword Nf_MatchDeref_rec(Nf_Man_t *, int, int, Nf_Mat_t *)Nf_ObjMapRefNum(p, i, !c) > 0Nf_ObjMapRefNum(p, iVar, fCompl) > 0word Nf_MatchRef_rec(Nf_Man_t *, int, int, Nf_Mat_t *, int, Vec_Int_t *)pM->D <= RequiredNf_ObjMapRefNum(p, i, !c) >= 0Nf_ObjMapRefNum(p, iVar, fCompl) >= 0Nf_ObjMapRefNum(p, Abc_Lit2Var(iLit), Abc_LitIsCompl(iLit)) > 0word Nf_MatchRefArea(Nf_Man_t *, int, int, Nf_Mat_t *, int)void Nf_ManElaBestMatchOne(Nf_Man_t *, int, int, int *, int *, Nf_Mat_t *, int)pMd->fBestint Nf_ManComputeArrival(Nf_Man_t *, Nf_Mat_t *, int *)pDc->fBestvoid Nf_ManResetMatches(Nf_Man_t *, int)!pAc->fBestc==0 || pDc->fComplpDc->fBest != pAc->fBestRound > 0 || (!pDc->fBest && !pAc->fBest)pM[0]->fBest && pM[1]->fBest!pM[c]->fComplpM[!c]->fComplvoid Nf_ManComputeMappingEla(Nf_Man_t *)pMb->fBestpMb->D <= RequiredpM->D <= Required - pCell->iDelays[k]pM->D <= Required - pCell->iDelays[k] - p->InvDelayIp->pGia->vCellMapping == NULLGia_Man_t *Nf_ManDeriveMapping(Nf_Man_t *)void Nf_ManUpdateStats(Nf_Man_t *)The number of variables is too large: 2*%d + %d = %d > %d. !Gia_ObjIsCi(Gia_ObjFanin0(pObj))int Nf_ManExtractWindow(void *, Vec_Int_t *, Vec_Wec_t *, Vec_Wec_t *, Vec_Int_t *, Vec_Int_t *, Vec_Wrd_t *, word *, int, int)iCutInv[c] == -1Vec_WecSize(vObjCuts) == 2*iObj-LitShiftiCutInv[0] == -1 || iCutInv[1] == -1Vec_WecSize(vCuts) == Vec_IntSize(vCutGates)Vec_WecSize(vCuts) == Vec_WrdSize(vCutAreas)Vec_WecSize(vObjCuts) == 2*Gia_ManAndNum(p->pGia)void Nf_CutParams(Nf_Man_t *, Nf_Cut_t *, float)int Nf_SetCutIsContainedOrder(Nf_Cut_t *, Nf_Cut_t *)int Nf_CutComputeTruthMux6(Nf_Man_t *, Nf_Cut_t *, Nf_Cut_t *, Nf_Cut_t *, int, int, int, Nf_Cut_t *)int Nf_CutComputeTruth6(Nf_Man_t *, Nf_Cut_t *, Nf_Cut_t *, int, int, Nf_Cut_t *, int)int *Nf_CutFromHandle(int *, int)pCut > pCutSetint Nf_CutHandle(int *, int *)pD->fBest != pA->fBestNf_Mat_t *Nf_ObjMatchBest(Nf_Man_t *, int, int)Unassigned""""""""DDDDDDDD 00000000UUUUUUUU33333333""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333  Ap->pGia->pRefs == NULLsrc/aig/gia/giaOf.cvoid Of_ManAreaFlow(Of_Man_t *)pPars->nCutNum > 1 && pPars->nCutNum <= OF_CUT_MAXOf_Man_t *Of_StoCreate(Gia_Man_t *, Jf_Par_t *)pPars->nLutSize > 1 && pPars->nLutSize <= OF_LEAF_MAXvoid Of_ObjMergeOrder(Of_Man_t *, int)Delay =%8.2f Area =%8d Edge =%9d pCutMin != NULLvoid Of_ManComputeBackward1(Of_Man_t *)void Of_ManComputeBackward3(Of_Man_t *)AreaAft <= AreaBefnSize < 2 || Delays[0] >= Delays[nSize-1]void Of_ManComputeForwardDirconCut(Of_Man_t *, int, int *, int *, int *)Delays[0] >= 0 && Delays[nSize-1] >= 0Delays[k] == Of_ObjDelay1(p, iVar) + DelayLut1*pDelay1 <= *pDelay2Of_ObjDelay2(p, iVar) + DelayLut2 <= *pDelay1Of_ObjDelay1(p, iVar) + DelayLut1 <= *pDelay1Of_ObjDelay1(p, iVar) + DelayLut1 <= *pDelay2Global delay =%8.2f void Of_ManComputeBackwardDircon1(Of_Man_t *)void Of_ManCreateSat(Of_Man_t *, int, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)nCutCount == nCutsAllProblem clauses = %d. Cardinality clauses = %d. Undecided. Satisfiable. Unsatisfiable. Nodes = %d LUTs = %d nAndsAll == Shiftvoid Of_ManPrintCuts(Of_Man_t *)Total: Ands = %d. Luts = %d. Cuts = %d. Gia_Man_t *Of_ManDeriveMapping(Of_Man_t *)void Of_CutParams(Of_Man_t *, Of_Cut_t *, int)int Of_SetCutIsContainedOrder(Of_Cut_t *, Of_Cut_t *)int Of_CutComputeTruthMux6(Of_Man_t *, Of_Cut_t *, Of_Cut_t *, Of_Cut_t *, int, int, int, Of_Cut_t *)int Of_CutComputeTruth6(Of_Man_t *, Of_Cut_t *, Of_Cut_t *, int, int, Of_Cut_t *, int)Of_ObjHasCuts(p, iObj)void Of_ManLiftCuts(Of_Man_t *, int)iObj>0 && iObjpGia)int *Of_ObjCutBestP(Of_Man_t *, int)void Of_ManComputeForwardObj2(Of_Man_t *, int)Delay <= Requiredint Of_CutHandle(int *, int *)Vec_IntSize(&p->vCutRefs) == 0int Of_CutAreaDerefed2(Of_Man_t *, int *)""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333UUUUUUUU33333333Error: Delay violation.Gia_ObjIsLut(p, Id)src/aig/gia/giaPack.cVec_Int_t *Gia_ManLutCollect2(Gia_Man_t *)Gia_ObjIsLut(p, iFan)Vec_IntCap(vOrder) == 16 || Vec_IntSize(vOrder) == Vec_IntCap(vOrder)nSize <= 32void Gia_ManLutPacking(Gia_Man_t *, int, int, int, int)Vec_IntSum(vBSize) == Vec_IntSize(vOrder)Vec_IntCap(vPacking) == 16 || Vec_IntSize(vPacking) == Vec_IntCap(vPacking)Vec_IntEntry(vPacking, Start) == -1Vec_IntCountEntry(vPacking, -1) == 0Global delay = %d. Sat_ObjXValue(pObj) == 0src/aig/gia/giaPat.cvoid Gia_SatCollectCone_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)void Gia_SatCollectCone(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)void Gia_SatVerifyPattern(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, Vec_Int_t *)Gia_SatVerifyPattern(): Verification FAILED.F@nFans < 7src/aig/gia/giaPf.cvoid Pf_StoCreateGateAdd(Pf_Man_t *, word, int *, int, int)void Pf_StoCreateGate(Pf_Man_t *, Mio_Cell_t *, int **, int **, int *)pPars->nCutNum > 1 && pPars->nCutNum <= PF_CUT_MAXPf_Man_t *Pf_StoCreate(Gia_Man_t *, Jf_Par_t *)pPars->nLutSize > 1 && pPars->nLutSize <= PF_LEAF_MAXVec_WecSize(p->vTt2Match) == Vec_MemEntryNum(p->vTtMem)void Pf_ObjMergeOrder(Pf_Man_t *, int)void Pf_CutParams(Pf_Man_t *, Pf_Cut_t *, int)int Pf_SetCutIsContainedOrder(Pf_Cut_t *, Pf_Cut_t *)int Pf_CutComputeTruthMux6(Pf_Man_t *, Pf_Cut_t *, Pf_Cut_t *, Pf_Cut_t *, int, int, int, Pf_Cut_t *)int Pf_CutComputeTruth6(Pf_Man_t *, Pf_Cut_t *, Pf_Cut_t *, int, int, Pf_Cut_t *, int)""""""""DDDDDDDD 00000000UUUUUUUU33333333""""""""DDDDDDDD PPPPPPPPUUUUUUUUUUUUUUUUUUUUUUUU 00000000333333333333333333333333nLutSize * nLutNum <= nFlopssrc/aig/gia/giaQbf.cVec_Int_t *Gia_GenCollectFlopIndexes(char *, int, int, int)Flop index (%d) exceeds the number of flops (%d). Gia_GenCollectFlopIndexes: Expecting %d flop indexes (instead of %d). Gia_GenCollectFlopIndexes: There are %d duplicated flops in the list. Vec_IntSize(vFlops) == nLutNum * nLutSizeVec_Int_t *Gia_GenCreateMuxes(Gia_Man_t *, Gia_Man_t *, Vec_Int_t *, int, int, Vec_Int_t *, int)iFlop >= 0 && iFlop < Gia_ManRegNum(p)Vec_IntSize(vPLits) == nLutNum * (1 << nLutSize)Vec_Int_t *Gia_Gen2CreateMuxes(Gia_Man_t *, int, int, Vec_Int_t *, Vec_Int_t *)Vec_IntSize(vXLits) == nLutSizeGenerated QBF miter with %d parameters, %d functional variables, and %d AIG nodes. %d-input %d-output code table: --> Simulation of the encoding with %d random pairs: x =%3d y =%3d nand =%3d c(x) = c(y) = c(nand) = nand(c(x),c(y)) = Enumerated %d assignments when timeout (%d sec) was reached. Enumerated %d assignments when conflict limit (%d) was reached. Enumerated the complete set of %d assignments. Gia_ManPiNum(p) == nPars + Vec_IntSize(vValues)Gia_Man_t *Gia_QbfCofactor(Gia_Man_t *, int, Vec_Int_t *, Vec_Int_t *)Gia_ManPiNum(pNew) == nParsVec_IntSize(vValues) == p->nVarsvoid Gia_QbfPrint(Qbf_Man_t *, Vec_Int_t *, int)Cla =%7d Vec_IntSize(vValues) == p->nParsint Gia_QbfVerify(Qbf_Man_t *, Vec_Int_t *)Vec_IntEntry(p->vParMap, i) == -1void Gia_QbfAddSpecialConstr(Qbf_Man_t *)void Gia_QbfLearnConstraint(Qbf_Man_t *, Vec_Int_t *) Pattern Var =%4d Solving QBF for "%s" with %d parameters, %d variables and %d AIG nodes. Gia_ManRegNum(pGia) == 0int Gia_QbfSolve(Gia_Man_t *, int, int, int, int, int, int, int)Vec_IntSize(p->vValues) == p->nVarsVec_IntSize(p->vValues) == p->nParsVec_IntSize(p->vValues) == nParsVec_IntSize(p->vValues) == (1 << nEncVars) * nBitsThe problem timed out after %d sec. The problem aborted after %d conflicts. The problem aborted after %d iterations. src/aig/gia/giaResub.cint Gia_ObjCheckMffc_rec(Gia_Man_t *, Gia_Obj_t *, int, Vec_Int_t *)Vec_Wec_t *Gia_ManComputeMffcs(Gia_Man_t *, int, int, int, int)iPivot <= Vec_WecSize(vMffcs)Collected %d (%.1f %%) MFFCs and %d (%.1f %%) have no divisors (div ave for others is %.2f). Using %.2f MB for MFFCs and %.2f MB for pivots. Vec_IntSize(vMffc) == 3 + Vec_IntEntry(vMffc, 1)void Gia_ManAddDivisors(Gia_Man_t *, Vec_Wec_t *)iMffc != -1src/aig/gia/giaRetime.cint Gia_ManMarkAutonomous_rec(Gia_Man_t *, Gia_Obj_t *)void Gia_ManRetimeDup_rec(Gia_Man_t *, Gia_Obj_t *)vFlopClasses == NULL || Vec_IntSize(vFlopClasses) == Vec_PtrSize(vCut)Gia_Man_t *Gia_ManRetimeForwardOne(Gia_Man_t *, int *, int *)int Gia_ObjIsTravIdPrevious(Gia_Man_t *, Gia_Obj_t *)0Gia_ManPiNum(p) == nInputssrc/aig/gia/giaRex.cvoid Gia_ManAutomSimulate(Gia_Man_t *, Vec_Int_t *, char *)Simulating string "%s": Frame %d : %c %d Vec_IntSize(vLits) > 0int Gia_ManBuild1Hot(Gia_Man_t *, Vec_Int_t *)-> %d '%c' Reached from state %d '%c': %d '%c' iState == 0 || !Gia_SymbSpecial(pStr[iState])void Gia_ManCollectReached(char *, Vec_Int_t *, int, Vec_Int_t *, Vec_Int_t *, int)Vec_IntEntry(vVisited, iState) != TravIdInput variable order: Vec_IntSize(vStack) == 0Gia_Man_t *Gia_ManRex2Gia(char *, int, int)Init state = %s word Gia_ManAutomStep(Gia_Man_t *, word, word *, Vec_Wrd_t *)Vec_WrdSize(vTemp) >= Gia_ManObjNum(p)CountMin < ABC_INFINITYvoid Gia_ManAutomWalkOne(Gia_Man_t *, int, Vec_Wrd_t *, Vec_Int_t *, Vec_Wrd_t *, word)CountMin == 0Cannot simulate an automaton with more than 63 states.Cannot simulate an automaton with more than 64 inputs.AIG should have one primary output.src/aig/gia/giaSatEdge.cVec_Int_t *Seg_ManCountIntEdges(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, int)Gia_ObjIsCi(pObj) || Gia_ObjIsLut(p->pGia, iLut)int Seg_ManCountIntLevels(Seg_Man_t *, int)void Seg_ManCreateCnf(Seg_Man_t *, int, int)nVars <= nVarsLutnVars != 1 && nVars < nVarsLutCount == p->nVarsDelay constraints = %d. Edge constraints = %d. Running SatEdge with starting delay %d and edge %d (edge vars %d, total vars %d) Proved UNSAT for delay %d. Solution with delay %2d and %5d edges exists. Conf = %8d. Resource limit reached for delay %d. int Gia_ObjLutRefNumId(Gia_Man_t *, int)src/aig/gia/giaSatLE.cVec_Int_t *Sle_ManComputeCuts(Gia_Man_t *, int, int)Nodes = %d. Cuts = %d. Cuts/Node = %.2f. Ints/Node = %.2f. Mem = %.2f MB. Obj %3d void Sle_ManCollectCutFaninsOne(Gia_Man_t *, int, Vec_Int_t *, Vec_Bit_t *, Vec_Int_t *, Vec_Bit_t *)Cannot find the following cut at node %d: {iFound >= 0void Sle_ManDeriveInit(Sle_Man_t *)iFanin < iObjGia_ObjIsLut(p->pGia, iFanin)Gia_ObjIsAnd(Gia_ManObj(p->pGia, iFanin))Gia_ObjIsAnd(Gia_ManObj(p->pGia, iObj))void Sle_ManDeriveCnf(Sle_Man_t *, int, int)iCutVar0 > 0 && iEdgeVar0 > 0nEdges == Vec_IntSize(vCutFans)nEdges == 1 || nEdges == 2int Sle_ManAddEdgeConstraints(Sle_Man_t *, int)pCutThis == NULLvoid Sle_ManDeriveResult(Sle_Man_t *, Vec_Int_t *, Vec_Int_t *)pCutThis != NULLRunning solver with %d conflicts, %d initial delay, and %d edges. Dynamic constraints = %s. Vars: Total = %d. Node = %d. Cut = %d. Edge = %d. Delay = %d. Clas: Total = %d. Cut = %d. Edge = %d. EdgeEx = %d. Delay = %d. Solution with delay %2d, node count %5d, and edge count %5d exists. Conf = %8d. Proved UNSAT for delay %d. Conf = %8d. Resource limit reached for delay %d. Conf = %8d. Clas: Total = %d. Cut = %d. Edge = %d. EdgeEx = %d. Delay = %d. Calls = %d. int Sle_SetCutIsContainedOrder(int *, int *)Vec_IntSize(p->vSolCur) > 0src/aig/gia/giaSatLut.cvoid Sbl_ManGetCurrentMapping(Sbl_Man_t *)int Sbl_ManCreateTiming(Sbl_Man_t *, int)iAnd >= 0int Sbl_ManEvaluateMapping(Sbl_Man_t *, int)iAnd == Vec_IntEntry(p->vRootVars, i)iLut > 0Vec_IntSize(p->vSolBest) < Vec_IntSize(p->vSolInit)void Sbl_ManUpdateMapping(Sbl_Man_t *)Vec_IntSize(p->vLeaves) <= 128 && Vec_IntSize(p->vAnds) <= p->nVarsint Sbl_ManComputeCuts(Sbl_Man_t *)~Gia_ObjFanin1(pObj)->ValueVec_IntSize(p->vCutsStart) == nObjsVec_IntSize(p->vCutsNum) == nObjsVec_WrdSize(p->vCutsI1) == Vec_WrdSize(p->vCutsN1)Vec_WrdSize(p->vCutsI2) == Vec_WrdSize(p->vCutsN2)Vec_WrdSize(p->vCutsI1) == Vec_IntSize(p->vCutsObj)Gia_ObjIsLut2(p->pGia, Obj)(int)pObj->Value == Vec_IntSize(p->vLeaves) + i(int)pFanin->Value < Vec_IntSize(p->vLeaves) || Gia_ObjIsLut2(p->pGia, Fanin)p->FirstVar == sat_solver_nvars(p->pSat)int Sbl_ManCreateCnf(Sbl_Man_t *)Obj %d: Window with less than %d nodes does not exist. Obj %d: This window was already tried. Obj = %6d : Leaf = %2d. AND = %2d. Root = %2d. LUT = %2d. Obj %d: Encountered window with %d inputs and %d internal nodes. All clauses = %d. Multi clauses = %d. Binary clauses = %d. Other clauses = %d. Trying to find mapping with %d LUTs. Cut %3d : Node = %3d %6d Critical path of length (%d) is detected: int Sbl_ManTestSat(Sbl_Man_t *, int)SAT UNDEC confl =%8d. Total LitCount = %d. Object %5d : Saved %2d nodes (Conf =%8d) Iter =%3d Delay = %d Edges = %4d Cut UndecParameters: WinSize = %d AIG nodes. Conf = %d. DelayMax = %d. Tried = %d. Used = %d. HashWin = %d. SmallWin = %d. LargeWin = %d. IterOut = %d. SAT runs = %d. int Gia_ObjLutRefDecId(Gia_Man_t *, int)Obj >= 0 && Obj < 128void Sbl_ManComputeCutsOne(Sbl_Man_t *, int, int, int)int Sbl_CutIsFeasible(word, word, word, word, int)vCutsI1->nSize == vCutsN1->nSizeint Sbl_CutPushUncontained(Vec_Wrd_t *, Vec_Wrd_t *, Vec_Wrd_t *, Vec_Wrd_t *, word, word, word, word)vCutsI2->nSize == vCutsN2->nSizei%d n%d Skipping.QOutput literal %d has no cut. Abc_LitIsCompl(Lit)src/aig/gia/giaSatMap.cint Sbm_ManCheckSol(Sbm_Man_t *, Vec_Int_t *)Inverter of input %d of cut %d is not mapped. Internal literal %d of cut %d is not mapped. int Sbm_ManCreateCnf(Sbm_Man_t *)Vec_IntSize(vLits) >= 2nVarsReal == nVarsAllocsat_solver *Sbm_AddCardinSolver(int, Vec_Int_t **)LogN = %d. N = %3d. Vars = %5d. Clauses = %6d. Comb = %d. Vec_WecSize(p->vObjCuts) + p->nInputs <= nVarsint Sbm_ManTestSat(void *)All clauses = %d. Multi clauses = %d. Binary clauses = %d. Other clauses = %d. Trying to find mapping with %d gates. AND Lits = %d. Inputs = %d. Vars = %d. All vars = %d. %2d : Cut %3d (Gate %2d) Area = %7.2f int sat_solver_add_half_sorter(sat_solver *, int, int, int, int)void Sbm_AddCardinConstrMerge(sat_solver *, int *, int, int, int, int *)Vec_IntEntry(vMapping, Root)src/aig/gia/giaSatoko.cVec_Int_t *Gia_ManCollectVars(int, Vec_Int_t *, int)Output %6d : Total: Cone has %6d vars (out of %6d). src/aig/gia/giaScl.cint Gia_ManCombMarkUsed_rec(Gia_Man_t *, Gia_Obj_t *)Gia_Man_t *Gia_ManCleanupOutputs(Gia_Man_t *, int)nOutputs < Gia_ManCoNum(p)int Gia_ManSeqMarkUsed_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)Merging combinationally equivalent flops.Performing sequential cleanup.Aig_ManCiNum(p) == Gia_ManCiNum(pOrder)src/aig/gia/giaScript.cVec_Ptr_t *Gia_ManOrderPios(Aig_Man_t *, Gia_Man_t *)Aig_ManCoNum(p) == Gia_ManCoNum(pOrder)Gia_ManBufNum(p) > 0Gia_Man_t *Gia_ManDupFromBarBufs(Gia_Man_t *)k == Gia_ManBufNum(p)Gia_ManBufNum(p) == 0Gia_Man_t *Gia_ManDupToBarBufs(Gia_Man_t *, int)k == nBarBufsGia_ManBufNum(pNew) == nBarBufsGia_ManCiNum(pNew) == nPiRealGia_ManCoNum(pNew) == nPoRealGia_Man_t *Gia_ManAigSynch2(Gia_Man_t *, void *, int, int)Gia_ManBufNum(pInit) == Gia_ManBufNum(pGia1)Gia_ManBufNum(pInit) == Gia_ManBufNum(pGia2)Gia_ManBufNum(pInit) == Gia_ManBufNum(pGia3)&unmap; &lf -K %d -C %d -k %s; &save-t&unmap; &lf -K %d -C %d %s; &save&unmap; &if -sz -S %d%d -K %d -C %d %sMapping with &if -sz -S %d%d -K %d -C %d %s: &put; mfs2 -W 4 -M 500 -C 7000; &get -m&dsdb; &dch -C 500; &if -K %d -C %d %s; &saveMapping with &dch -C 500; &if -K %d -C %d %s: &syn2 -m -R 10; &dsdb&blut -a -K %d&st; &sopb&synch2 -K 6 -C 500; &if -m%s -C %d; %s &save&put; mfs2 -W 4 -M 500 -C 7000; &get -m;&dch -C 500; &if -m%s -C %d; %s &save&synch2 -K 6 -C 500; &lf -m%s -E 5 -C %d; %s &save&dch -C 500; &lf -m%sk -E 5 -C %d; %s &save&synch2 -K %d -C 500; &if -m%s -K %d -C %d; %s &save&dch -C 500; &if -m%s -K %d -C %d; %s &save&synch2 -K %d -C 500; &lf -m%s -E 5 -K %d -C %d; %s &save&dch -C 500; &lf -m%sk -E 5 -K %d -C %d; %s &save&st; &sopb -R 10 -C 4&st; &sopb -R 10&st; &if -C %d; &save; &st; &syn2; &if -C %d; &save; &load&st; &if -C %d -K %d; &save; &st; &syn2; &if -C %d -K %d; &save; &load&st; &if -%s -K 6; &dch -f; &if -C %d; %s&save; &load&mfs; &st; &if -%s -K 6; &dch -f; &if -C %d -K %d; %s&save; &load&st; &if -%s -K 6; &synch2; &if -C %d; %s&save; &load&st; &if -%s -K 6; &synch2; &if -C %d -K %d; %s&save; &loadTrying simple synthesis with %s... LMSSOP balancingMapping final:MAPPING:Final result...Mapping with &lf:Mapping with &lf -k:Trying SOP balancing...Trying synthesis...Trying harder synthesis...Trying medium synthesis...src/aig/gia/giaShow.cvoid Gia_ShowPath(Gia_Man_t *, char *)Cannot visualize AIG with more than %d critical nodes. AIG structure generated by GIA packageThe critical path contains %d LUTs with %d critical edges and spans %d levels.Gia_ObjLevel(p, Gia_ObjFanin0(pNode)) == nLevels Node%d [label = "%d:%d"Cannot visualize AIG with more than %d nodes. The AIG contains %d nodes and spans %d levels. Node%d [label = "Const0"The AIG contains %d nodes, %d full-adders, and %d half-adders, and spans %d levels. Node%d [label = "%d_%d", shape = octagon, shape = doubleoctagon!Gia_ObjIsMux(p, pObj)int Gia_ShowCollectObjs_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *, Vec_Int_t *)src/aig/gia/giaShrink.cGia_Man_t *Gia_ManMapShrink4(Gia_Man_t *, int, int)Gia_ManMapShrink4() node reduction after sweep %6d -> %6d. Resynthesis is not performed when nodes have more than 4 inputs.Node reduction after sweep %6d -> %6d. uTruth1 != 0 && uTruthC != 0src/aig/gia/giaShrink6.cint Shr_ObjPerformBidec(Shr_Man_t *, Bdc_Man_t *, Gia_Man_t *, Vec_Int_t *, word, word)iLast + 1 == Gia_ManObjNum(pNew)Gia_ManObjNum(pNew) < p->nNewSizeword Shr_ManComputeTruth6_rec(Gia_Man_t *, int, Vec_Wrd_t *)word Shr_ManComputeTruth6(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, Vec_Wrd_t *)Gia_Man_t *Gia_ManMapShrink6(Gia_Man_t *, int, int, int)Vec_IntSize(pMan->vLeaves) <= 6nDivs <= pMan->nDivMaxPerformed %d resubs and %d decomps. Gain in AIG nodes = %d. Limit > 6int Shr_ManCollectDivisors(Shr_Man_t *, Vec_Int_t *, int, int)Gia_ObjIsTravIdCurrentId(p->pNew, iDiv)Gia_ObjIsAnd(pFan)Gia_ObjLevel(p->pNew, Gia_ManObj(p->pNew, iDiv)) < Gia_ObjLevel(p->pNew, pFan)i < iPlace%3d : %7d %7.2f %% Pairs: Total = %8d Init = %8d %7.2f %% Final = %8d %7.2f %% Real = %8d %7.2f %% Num == Hash_IntManEntryNum(pHash)src/aig/gia/giaShrink7.cVec_Int_t *Unm_ManComputePairs(Unm_Man_t *, int)Num == Vec_IntSize(vNum2Obj)Num < Vec_IntSize(vNum2Obj)The number of used nodes = %d Vec_Wrd_t *Unm_ManComputeTruths(Unm_Man_t *)Vec_IntSize(p->vLeaves) <= 6Hash_IntManEntryNum(p->pHash) == 0Vec_Int_t *Unm_ManCollectDecomp(Unm_Man_t *, Vec_Int_t *, int)FanK < FanJNum == Hash_IntManEntryNum(p->pHash)UUUUUUUU33333333Statistics for pairs appearing less than 20 times: <src/aig/gia/giaSim.cvoid Gia_ManSimCollect_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)Logic0 = %d (%d). Logic1 = %d (%d). Simulator could not allocate %.2f GB for simulation info. AIG = %7.2f MB. Front mem = %7.2f MB. Other mem = %7.2f MB. p->pAig->nFront > 0void Gia_ManSimulateRound(Gia_ManSim_t *)Gia_ManConst0(p->pAig)->Value == 0Gia_ObjValue(pObj) < p->pAig->nFrontGia_ObjValue(pObj) == GIA_NONEGia_ManCiNum(p->pAig) == iCisGia_ManCoNum(p->pAig) == iCos Generated counter-example is INVALID. No bug detected after simulating %d frames with %d words. Vec_IntSize(vPat) % nOuts == 0int Gia_ManSimWriteFile(char *, Vec_Int_t *, int)Vec_IntSize(vPat) % Gia_ManPiNum(p) == 0Vec_Int_t *Gia_ManSimSimulateOne(Gia_Man_t *, Vec_Int_t *)k == Vec_IntSize(vPat)The number of 0s and 1s in the input file (%d) does not evenly divide by the number of primary inputs (%d). Output patterns are written into file "%s". !p->fBuiltInSimvoid Gia_ManBuiltInSimStart(Gia_Man_t *, int, int)Gia_ManAndNum(p) == 0p->fBuiltInSim || p->fIncrSimvoid Gia_ManBuiltInSimPerformInt(Gia_Man_t *, int)Vec_WrdSize(p->vSims) == Gia_ManObjNum(p) * p->nSimWordsvoid Gia_ManBuiltInSimResimulateCone_rec(Gia_Man_t *, int)int Gia_ManBuiltInSimCheckOver(Gia_Man_t *, int, int)int Gia_ManBuiltInSimCheckEqual(Gia_Man_t *, int, int)int Gia_ManBuiltInSimPack(Gia_Man_t *, Vec_Int_t *)iObj == Gia_ManObjNum(p)int Gia_ManBuiltInSimAddPat(Gia_Man_t *, Vec_Int_t *)Vec_WrdSize(p->vSims) == p->nSimWords * Gia_ManObjNum(p)Vec_WrdSize(p->vSimsPi) == p->nSimWords * Gia_ManCiNum(p)iPat >= 0 && iPat < p->iPatsPiAbc_TtGetBit(Gia_ManBuiltInData(p, 1+Abc_Lit2Var(iLit)), iPat) != Abc_LitIsCompl(iLit)Vec_IntSize(p->vTimeStamps) <= Gia_ManObjNum(p)void Gia_ManIncrSimUpdate(Gia_Man_t *)Vec_WrdSize(p->vSims) <= Gia_ManObjNum(p) * p->nSimWordsp->iNextPi <= Gia_ManCiNum(p)!p->fIncrSimvoid Gia_ManIncrSimStart(Gia_Man_t *, int, int)void Gia_ManIncrSimStop(Gia_Man_t *)Vec_IntSize(vObjLits) > 0void Gia_ManIncrSimSet(Gia_Man_t *, Vec_Int_t *)Vec_IntEntry(p->vTimeStamps, iObj) < p->iTimeStampvoid Gia_ManIncrSimCone_rec(Gia_Man_t *, int)iLit0 > 1 && iLit1 > 1int Gia_ManIncrSimCheckOver(Gia_Man_t *, int, int)int Gia_ManIncrSimCheckEqual(Gia_Man_t *, int, int)Memory: AIG = %7.2f MB. SimInfo = %7.2f MB. src/aig/gia/giaSim2.cvoid Gia_Sim2ClassCreate(Gia_Man_t *, Vec_Int_t *)int Gia_Sim2ClassRefineOne(Gia_Sim2_t *, int)void Gia_Sim2ProcessRefined(Gia_Sim2_t *, Vec_Int_t *)pAig->pReprs && pAig->pNextsint Gia_ManSimSimulateEquiv(Gia_Man_t *, Gia_ParSim_t *)Lits = %4d. void Gia_Sim2SimulateRound(Gia_Sim2_t *)Gia_ObjValue(pObj) == i 5 CQ'8Vec_WrdSize(vSims) == nWords * Gia_ManObjNum(p)src/aig/gia/giaSimBase.cvoid Gia_ManSimPatAssignInputs(Gia_Man_t *, int, Vec_Wrd_t *, Vec_Wrd_t *)Vec_WrdSize(pGia->vSimsPi) % Gia_ManCiNum(pGia) == 0Vec_Wrd_t *Gia_ManSimPatSim(Gia_Man_t *)void Gia_ManSimPatValuesDerive(Gia_Man_t *, int, Vec_Wrd_t *, Vec_Wrd_t *)Vec_WrdSize(vValues) == nWords * Gia_ManCoNum(p)Vec_WrdSize(p->vSimsPi) == nWords * Gia_ManCiNum(p)Vec_Wrd_t *Gia_ManSimPatValues(Gia_Man_t *)Vec_WrdSize(vBase) % nInputs == 0Vec_Wrd_t *Gia_ManSimCombine(int, Vec_Wrd_t *, Vec_Wrd_t *, int)Vec_WrdSize(vAddOn) % nInputs == 0nWordsUse <= nWordsAddOnVec_WrdSize(vSimsIn) == Vec_WrdCap(vSimsIn) || Vec_WrdSize(vSimsIn) < 16Abc_TtGetBit(pSimsC, i) && (Abc_TtGetBit(pSimsI, i) != Abc_LitIsCompl(pLits[k]))int Gia_ManSimBitPackOne(int, Vec_Wrd_t *, Vec_Wrd_t *, int, int *, int)iPat <= nCexes + nUnDecsVec_Wrd_t *Gia_ManSimBitPacking(Gia_Man_t *, Vec_Int_t *, int, int)iCur == Vec_IntSize(vCexStore)Compressed %d CEXes into %d patterns and added %d words to available %d words. void Gia_ManSimPatWrite(char *, Vec_Wrd_t *, int)Written %d words of simulation data into file "%s". int Gia_ManSimPatReadOne(char)Vec_Wrd_t *Gia_ManSimPatRead(char *)Read %d words of simulation data. Simulating %d patterns leads to %d unique objects (%.2f %% out of %d), Const0 = %d. Const1 = %d. Status >= -1 && Status <= 1void Gia_ManPatSatImprove(Gia_Man_t *, int, int)Total = %d : SAT = %d. UNSAT = %d. UNDEC = %d. Gia_SimRsbMan_t *Gia_SimRsbAlloc(Gia_Man_t *)p->nWords == Vec_WrdSize(p->vSimsObj) / Gia_ManObjNum(pGia)Vec_Int_t *Gia_SimRsbTfo(Gia_SimRsbMan_t *, int, int)Vec_IntEntryLast(p->vTfo) == iObjword *Gia_SimRsbFunc(Gia_SimRsbMan_t *, int, Vec_Int_t *, int)word *Gia_SimRsbCareSet(Gia_SimRsbMan_t *, int, Vec_Int_t *)Vec_IntSize(p->vFanins) > 0void Gia_ObjSimCollect(Gia_SimRsbMan_t *)Vec_Int_t *Gia_ObjSimCands(Gia_SimRsbMan_t *, int, int)Vec_IntSize(p->vFanins) == 0 || Vec_IntSize(p->vCands) >= nCandsLevel %3d : %d = buf(%d) Level %3d : %d = inv(%d) pGia->vSimsPi != NULLint Gia_ManSimRsb(Gia_Man_t *, int, int)Can resubstitute %d nodes (%.2f %% out of %d) (Bufs = %d Invs = %d) void Gia_ManSimRelAssignInputs(Gia_Man_t *, int, Vec_Wrd_t *, int, Vec_Wrd_t *)Vec_WrdSize(vSimsIn) == nWordsIn * Gia_ManCiNum(p)int Gia_ManSimRelCollectOutputs(Gia_Man_t *, int, Vec_Wrd_t *, int, Vec_Wrd_t *, Vec_Wrd_t *)Vec_WrdSize(vSimsOut) == nWordsOut * Gia_ManCoNum(p)Vec_WrdSize(vRel) == nWordsOut * nMintsThe relation is not well-defined for %d (out of %d) patterns. Vec_WrdSize(vFuncs) == 2 * nOuts * nWordsvoid Gia_ManSimRelCheckFuncs(Gia_Man_t *, Vec_Wrd_t *, int, Vec_Wrd_t *)nOuts <= 32For pattern %d, minterm %d produced by function is not in the relation. Total number of similar errors = %d. Vec_WrdSize(vRel) % nMints == 0Vec_Wrd_t *Gia_ManSimRelDeriveFuncs(Gia_Man_t *, Vec_Wrd_t *, int)The relation was successfully determized without don't-cares for %d patterns. Vec_Wrd_t *Gia_ManSimRelDeriveFuncs2(Gia_Man_t *, Vec_Wrd_t *, int)The relation was successfully determized with don't-cares for %d patterns. %4d : Off = %6d On = %6d Dc = %6d (%6.2f %%) Count = %2d void Gia_ManSimRelTest(Gia_Man_t *)Vec_WrdSize(vSims) % nWords == 0Gia_SimAbsMan_t *Gia_SimAbsAlloc(Gia_Man_t *, word *, word *, Vec_Wrd_t *, int, Vec_Int_t *, int)Vec_WrdSize(p->vCoverTable) == p->nWordsTable * (p->nCands+1)void Gia_SimAbsCheckSolution(Gia_SimAbsMan_t *)Found solution { %d } Found solution { %d %d } Found solution { %d %d %d } Vec_IntEntry(p->vValues, iPat) == 0void Gia_SimAbsSolve(Gia_SimAbsMan_t *)Vec_IntEntry(p->vValues, iPat2) == 1k == Vec_IntSize(p->vPatPairs)Solution %2d for covering problem [%5d x %5d]: Vec_IntSize(p->vResub) > 0int Gia_SimAbsRefine(Gia_SimAbsMan_t *)Abc_TtGetBit(p->pSet[Value], i)Abc_TtGetBit(p->pSet[!Value], iPat)There are %d offset and %d onset minterms (%d pairs) and %d divisors. Vec_IntSize(vValue0) > 0void Gia_SimAbsInit(Gia_SimAbsMan_t *)Vec_IntSize(vValue1) > 0Resubstitution timeGia_RsbMan_t *Gia_RsbAlloc(Gia_Man_t *, word *, word *, Vec_Wrd_t *, int, Vec_Wrd_t *, int, Vec_Int_t *)Vec_WrdSize(vSims) == 64 * nWords * nWordsTVec_WrdSize(vSims) == Vec_WrdSize(vSimsT)iObj < nWordsT * 64!Value0 || !Value1Vec_WecSize(p->vSets[0]) == 1Vec_WecSize(p->vSets[1]) == 1Vec_WecSize(p->vSets[0]) == nLeavesvoid Gia_RsbPrint(Gia_RsbMan_t *)Vec_WecSize(p->vSets[1]) == nLeavesDatabase for %d objects and cost %d: void Gia_RsbUpdateAdd(Gia_RsbMan_t *, int)Vec_WecSize(p->vSets[0]) == 2*nLeavesVec_WecSize(p->vSets[1]) == 2*nLeavesIndex < Vec_IntSize(p->vObjs)void Gia_RsbUpdateRemove(Gia_RsbMan_t *, int)k == nLeaves/2Vec_WecSize(p->vSets[0]) == (1 << Vec_IntSize(p->vObjs))int Gia_RsbRemovalCost(Gia_RsbMan_t *, int)Vec_WecSize(p->vSets[1]) == (1 << Vec_IntSize(p->vObjs))Abc_TtGetBit(p->pSet[1], iObj)int Gia_RsbFindNode(Gia_RsbMan_t *)nNodesNew <= nNodesVec_WecSize(p->vSets[0]) == Vec_WecSize(p->vSets[1])int Gia_RsbCollectValid(Gia_RsbMan_t *)Vec_Int_t *Gia_SimQualityOne(Gia_Man_t *, Vec_Int_t *, int)Vec_IntSize(vRes) == Gia_ManCoNum(p)Gia_ManCiNum(p) <= 10void Gia_SimQualityTest(Gia_Man_t *)Vec_Int_t *Gia_SimGenerateStats(Gia_Man_t *)Vec_IntSize(vTotal) == Vec_IntSize(vThis)double Gia_SimComputeScore(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *)Iter %5d : Init = %6.3f Final = %6.3f Ratio = %4.2f Tries = %5d Choosing %5d MaxIn >= 0 && MaxIn < Gia_ManCiNum(p)void Gia_ManPatDistImprove(Gia_Man_t *, int)Pat %5d : Tries = %5d InitValue = %6.3f FinalValue = %6.3f Ratio = %4.2f Improved %d patterns with average init value %.2f and average final value %.2f. Vec_WrdSize(vPatterns) % Gia_ManCiNum(p) == 0Vec_Int_t *Gia_SimCollectRare(Gia_Man_t *, Vec_Wrd_t *, int)CountRare <= TotalBits/2Vec_Flt_t *Gia_SimQualityImpact(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *)Vec_WrdSize(vSims) == Gia_ManObjNum(p)float Gia_ManPatGetQuo(Gia_Man_t *, Vec_Int_t *, Vec_Wrd_t *, int, int)Pat %5d : Rare = %4d Cands = %3d Value = %8.3f Change = %8.3f Improved %d out of %d patterns using %d rare nodes: %.2f -> %.2f. There are no counter-examples. No need for more simulation.The function agrees with the relation.src/aig/gia/giaSort.cvoid Gia_SortVerifySorted(int *, int)Sorting %d integers qsort minisat with inlined comparisonsrc/aig/gia/giaSpeedup.cvoid Gia_LutDelayTraceSortPins(Gia_Man_t *, int, int *, float *)Gia_ObjLutSize(p, iObj) == 0 || pPinPerm[0] < Gia_ObjLutSize(p, iObj)pPinPerm[i] < Gia_ObjLutSize(p, iObj)float Gia_ObjComputeArrival(Gia_Man_t *, int, int)float Gia_ObjPropagateRequired(Gia_Man_t *, int, int)float Gia_ManDelayTraceLut(Gia_Man_t *)float Gia_ManDelayTraceLutPrint(Gia_Man_t *, int)int Gia_ManSpeedupObj_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)Gia_Man_t *Gia_ManSpeedup(Gia_Man_t *, int, int, int, int)p->vTiming == NULLvoid Gia_ManTimeStart(Gia_Man_t *)p->vTiming != NULLvoid Gia_ManTimeClean(Gia_Man_t *)void Gia_ManTimeStop(Gia_Man_t *)Bad node!!!Speedup stopped adding choices because there was too many to add.src/aig/gia/giaSplit.cVec_Wec_t *Spl_ManToWecMapping(Gia_Man_t *)Gia_ManHasMapping2(p)Vec_Int_t *Spl_ManFromWecMapping(Gia_Man_t *, Vec_Wec_t *)Vec_IntSize(vMapping) < 16 || Vec_IntSize(vMapping) == Vec_IntCap(vMapping)Spl_Man_t *Spl_ManAlloc(Gia_Man_t *, int, int)!Gia_ManHasMapping2(pGia)!Gia_ManHasMapping(p->pGia)void Spl_ManStop(Spl_Man_t *)Gia_ManHasMapping2(p->pGia)Vec_BitEntry(p->vMarksAnd, iObj)void Spl_ManWinFindLeavesRoots(Spl_Man_t *)Gia_ObjIsLut2(p->pGia, iFan) || Vec_BitEntry(p->vMarksCIO, iFan)Gia_ObjIsLut2(p, iObj)int Spl_ManLutFanouts(Gia_Man_t *, int, Vec_Int_t *, Vec_Bit_t *, Vec_Bit_t *)Gia_ObjLutRefNumId(p->pGia, iObj) > 0int Spl_ManFindOne(Spl_Man_t *)int Spl_ManLutMffcSize(Gia_Man_t *, int, Vec_Int_t *, Vec_Bit_t *)Gia_ObjIsLut2(p->pGia, iPivot)int Spl_ManComputeOne(Spl_Man_t *, int)Gia_ObjIsLut2(p->pGia, iObj)!Vec_BitEntry(p->vMarksNo, iObj)int Gia_ManComputeOneWin(Gia_Man_t *, int, Vec_Int_t **, Vec_Int_t **, Vec_Int_t **, Vec_Int_t **)pGia->pSatlutWinman == NULLvoid Gia_ManComputeOneWinStart(Gia_Man_t *, int, int)Obj = %6d : Leaf = %2d. Node = %2d. Root = %2d. AND = %3d. src/aig/gia/giaStg.cvoid Gia_ManPrintStateEncoding(Vec_Vec_t *, int)int Gia_ManCreateOrGate(Gia_Man_t *, Vec_Int_t *)nStates > 0Vec_Vec_t *Gia_ManAssignCodes(int, int, int *)kHot >= 1 && kHot <= 5Vec_IntSize(vLines) % 4 == 0Gia_Man_t *Gia_ManStgKHot(Vec_Int_t *, int, int, int, int, int)Vec_VecSize(vCodes) == nStatesb >= 0 && b < nBitsiMint >= 0 && iMint < (1<= 0 && iCur < nStatesiNext >= 0 && iNext < nStatesiOut >= 0 && iOut < (1<pMuxes == NULLsrc/aig/gia/giaStr.cGia_Man_t *Str_NtkToGia(Gia_Man_t *, Str_Ntk_t *)Gia_Man_t *Gia_ManDupMuxesNoHash(Gia_Man_t *)!pObj->fMark0void Str_MuxInputsCollect(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)void Str_MuxStructCollect(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)void Str_MuxStructDump(Gia_Man_t *, Gia_Obj_t *, Vec_Str_t *)Vec_Wec_t *Str_ManDeriveTrees(Gia_Man_t *)Abc_NamObjNumMax(pNames) == Vec_WecSize(vGroups)void Str_ManNormalize_rec(Str_Ntk_t *, Gia_Man_t *, Gia_Obj_t *, Vec_Wec_t *, Vec_Int_t *)~pRoot->ValueStr_Ntk_t *Str_ManNormalizeInt(Gia_Man_t *, Vec_Wec_t *, Vec_Int_t *)pNtk->nObjs <= Gia_ManObjNum(p)int Str_ManVectorAffinity(Gia_Man_t *, Vec_Int_t *, Vec_Int_t *, word *, int)Matrix[i]int Str_NtkBalanceTwo(Gia_Man_t *, Str_Ntk_t *, Str_Obj_t *, int, int, Vec_Int_t *, int *, int *, word *, int, int, int)Limit <= Vec_IntCap(vSuper)void Str_NtkBalanceMulti(Gia_Man_t *, Str_Ntk_t *, Str_Obj_t *, Vec_Int_t *, int)Limit <= Vec_IntCap(vCosts)Vec_IntSize(vSuper) > 0Vec_IntSize(vSuper) <= 64iBest > 0 && iBest < Vec_IntSize(vSuper)iBest > 0iBest2 > 0nLutSize < 16Gia_Man_t *Str_NtkBalance(Gia_Man_t *, Str_Ntk_t *, int, int, int, int, int)nGroups * nMuxes >= 2Max delay = %d. Old objs = %d. New objs = %d. Gia_Man_t *Gia_ManLutBalance(Gia_Man_t *, int, int, int, int, int){%d}void Str_MuxCreate(Str_Mux_t *, Str_Ntk_t *, int, int, Vec_Int_t *, int)pObj->Type == STR_MUXpFanin->Edge[2].Fan <= 0int Str_MuxToGia_rec(Gia_Man_t *, Str_Mux_t *, int, Vec_Int_t *)pFanin->Edge[2].fCompl == 0i + 1 < kvoid Str_MuxChangeOnce(Str_Mux_t *, int *, int, int, Str_Mux_t *, Gia_Man_t *, Vec_Int_t *)pSpots[0]->Edge[pInds[0]].Fan > 0pSpots[1]->Edge[pInds[1]].Fan > 0pTree[Abc_Lit2Var(pPath[c])].Edge[2].fCompl == 0int Str_MuxFindPath_rec(Str_Mux_t *, int *, int *)Trying node %d with path of length %d. %2d %2d -> %3d (%3d) Node %6d (%3d %3d) : Checks = %d. Delay: %d -> %d. pMux->Copy == -1int Str_MuxRestructAreaThree(Gia_Man_t *, Str_Mux_t *, Vec_Int_t *, int)Str_MuxHasFanin(pFanin0, 0) != Str_MuxHasFanin(pFanin0, 1)int Str_MuxRestructArea_rec(Gia_Man_t *, Str_Mux_t *, Str_Mux_t *, int, Vec_Int_t *, int)nMuxes0 + nMuxes1 == 3 || nMuxes0 + nMuxes1 == 4nMuxes0 == 2 || nMuxes1 == 2int Str_MuxRestructureArea(Gia_Man_t *, Str_Ntk_t *, int, int, Vec_Int_t *, int, int)Result >= 0 && Result <= 2int Str_ObjCreate(Str_Ntk_t *, int, int, int *)pFanins[i] >= 0Str_Obj_t *Str_NtkObj(Str_Ntk_t *, int)Network contains %d ands, %d xors, %d muxes (%d trees in %d groups). Did not find!nVarsMax <= 20src/aig/gia/giaSupMin.cGia_ManSup_t *Gia_ManSupStart(int)Enable is not an AND. DataSupp = %6d. DataCone = %6d. CareSupp = %6d. CareCone = %6d.void Gia_ManSupExperiment(Gia_Man_t *, Vec_Int_t *)Refs = %d. bFunc != NULLsrc/aig/gia/giaSupp.cint Gia_ManFindRemoved(Gia_ManMin_t *)p->iLits[n] >= 2int Gia_ManRebuildOne(Gia_ManMin_t *, int)Vec_IntSize(p->vCleared) > 0Abc_Lit2Var(p->iLits[n]) == iObjn || !Overlapint Gia_ManGatherSupp(Gia_ManMin_t *)Gia_Man_t *Gia_ManSupportAndTest(Gia_Man_t *)void Gia_Min2AddClausesMux(Gia_Man_t *, Gia_Obj_t *, satoko_t *)void Gia_Min2AddClausesSuper(Gia_Man_t *, Gia_Obj_t *, Vec_Ptr_t *, satoko_t *)void Gia_Min2CollectSuper(Gia_Obj_t *, int, Vec_Ptr_t *)void Gia_Min2ObjAddToFrontier(Gia_Man_t *, Gia_Obj_t *, Vec_Ptr_t *, satoko_t *, Vec_Int_t *)Gia_Min2ObjSatId(p, pObj) == -1int Gia_Min2ObjGetCnfVar(Gia_Man2Min_t *, int)Gia_Min2ObjSatId(p->pGia,pNode) >= 0iObj0 > 0 && iObj1 > 0int Gia_Min2ManSolve(Gia_Man2Min_t *)Gia_Min2ManSimulate(p) == 1int Gia_Min2ManGatherSupp(Gia_Man2Min_t *)Gia_Man_t *Gia_Man2SupportAndTest(Gia_Man_t *)int Gia_ManGatherSupp_rec(Gia_Man_t *, int, Vec_Int_t *, Vec_Int_t *)int Gia_ObjIsTravIdPreviousId(Gia_Man_t *, int)int Gia_Min2ObjSetSatId(Gia_Man_t *, Gia_Obj_t *, int)iPattern > 0 && iPattern < 64void Gia_Min2SimSetInputBit(Gia_Man2Min_t *, int, int, int)Gia_Min2ObjSatId(p, pObj) != -1void Gia_Min2ObjCleanSatId(Gia_Man_t *, Gia_Obj_t *)int Gia_Min2ManGatherSupp_rec(Gia_Man_t *, int, Vec_Int_t *, Vec_Int_t *)src/aig/gia/giaSweep.cvoid Gia_ManMarkSeqGiaWithBoxes_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)iFlop >= 0 && iFlop < nRegsvoid Gia_ManMarkSeqGiaWithBoxes(Gia_Man_t *, int)Gia_ManBoxNum(p) > 0Gia_Man_t *Gia_ManDupWithBoxes(Gia_Man_t *, int)nMarked == 0 || nMarked == nBoxIns + nBoxOutsp->pAigExtra != NULLpNew->pAigExtra == NULLGia_ManCiNum(pNew) == Tim_ManPiNum((Tim_Man_t*)pNew->pManTime) + Gia_ManCoNum(pNew->pAigExtra)int Gia_ManFraigCheckCis(Gia_Man_t *, Gia_Obj_t *)Gia_Obj_t *Gia_ManFraigMarkCis(Gia_Man_t *, Gia_Obj_t *, int)Gia_Obj_t *Gia_ManFraigMarkCos(Gia_Man_t *, Gia_Obj_t *, int)Gia_Obj_t *Gia_ManFraigMarkAnd(Gia_Man_t *, Gia_Obj_t *)p->pManTime != NULLGia_Man_t *Gia_ManFraigCreateGia(Gia_Man_t *)Abc_Lit2Var(pReprs[fanId]) < Gia_ObjId(p, pObj)int Gia_ObjFanin0CopyRepr(Gia_Man_t *, Gia_Obj_t *, int *)int Gia_ObjFanin1CopyRepr(Gia_Man_t *, Gia_Obj_t *, int *)Gia_Man_t *Gia_ManFraigReduceGia(Gia_Man_t *, int *)Vec_Int_t *Gia_ManComputeCarryOuts(Gia_Man_t *)void Gia_ManCheckIntegrityWithBoxes(Gia_Man_t *)Warning: AIG with boxes has internal fanout in %d complex flops and %d carries. int *Gia_ManFraigSelectReprs(Gia_Man_t *, Gia_Man_t *, int, int *)Computed %d const objects and %d other objects. Fixed %d flop inputs and %d box/box connections (out of %d non-flop boxes). Gia_ObjReprSelf(pClp, Abc_Lit2Var(iLitClp)) == Gia_ObjReprSelf(pClp, Abc_Lit2Var(iLitClp2))Abc_Lit2Var(pReprs[i]) < iFound %d const objects and %d other objects. Gia_ManObjNum(p) == Aig_ManObjNum(pNew)void Gia_ManFraigSweepPerform(Gia_Man_t *, void *)p->pManTime == NULL || Gia_ManBoxNum(p) == 0Gia_Man_t *Gia_ManFraigSweepSimple(Gia_Man_t *, void *)iDom >= 1 && iDom <= nDomsvoid Gia_ManSweepComputeOneDomainEquivs(Gia_Man_t *, Vec_Int_t *, int, void *, int, int, int)Vec_IntSize(vPerm) == Gia_ManRegNum(p)Gia_ManObjNum(pNew) == Gia_ManObjNum(p)Gia_Man_t *Gia_ManSweepWithBoxesAndDomains(Gia_Man_t *, void *, int, int, int, int)nDoms > 1Domain %2d : %5d -> %5d : EqConst =%4d. EqFlop =%4d. Dangling =%4d. Unused =%4d. Gia_Man_t *Gia_ManSweepWithBoxes(Gia_Man_t *, void *, void *, int, int, int, int)Sweeper AIG manager SAT solver TOTAL CNF construction Undecided GIA: SAT calls = %d. Sat = %d. Unsat = %d. Undecided = %d. Proofs = %d. pSwp->vCexUser == NULL || Vec_IntSize(pSwp->vCexUser) == Gia_ManPiNum(p)src/aig/gia/giaSweeper.cVec_Int_t *Gia_SweeperGetCex(Gia_Man_t *)int Gia_SweeperProbeCreate(Gia_Man_t *, int)int Gia_SweeperProbeDelete(Gia_Man_t *, int)int Gia_SweeperProbeUpdate(Gia_Man_t *, int, int)int Gia_SweeperProbeLit(Gia_Man_t *, int)vInNames == NULL || Gia_ManPiNum(p) == Vec_PtrSize(vInNames)Gia_Man_t *Gia_SweeperExtractUserLogic(Gia_Man_t *, Vec_Int_t *, Vec_Ptr_t *, Vec_Ptr_t *)vOutNames == NULL || Vec_IntSize(vProbeIds) == Vec_PtrSize(vOutNames)Dumping logic cones and conditionsint Gia_SweeperCheckEquiv(Gia_Man_t *, int, int)iLitOld > iLitNewint Gia_SweeperCondCheckUnsat(Gia_Man_t *)Vec_IntSize(p->vCondProbes) > 0Gia_SweeperIsRunning(pDst)Vec_Int_t *Gia_SweeperGraft(Gia_Man_t *, Vec_Int_t *, Gia_Man_t *)Vec_IntSize(vProbes) == Gia_ManPiNum(pSrc)Gia_ManPiNum(pDst) == Gia_ManPiNum(pSrc)Gia_SweeperIsRunning(p)Gia_Man_t *Gia_SweeperSweep(Gia_Man_t *, Vec_Int_t *, int, int, int, int)int Gia_SweeperFraig(Gia_Man_t *, Vec_Int_t *, char *, int, int, int, int)int Gia_SweeperRun(Gia_Man_t *, Vec_Int_t *, char *, int)GIA manager statistics before and after applying "%s": Vec_IntSize(&pGia->vHTable)Swp_Man_t *Swp_ManStart(Gia_Man_t *)void Swp_ManSetObj2Lit(Swp_Man_t *, int, int)Swp_ManObj2Lit(p, Gia_ObjId(p->pGia, pNode))void Gia_ManCnfNodeAddToSolver(Swp_Man_t *, int)void Gia_ManAddClausesMux(Swp_Man_t *, Gia_Obj_t *)void Gia_ManCollectSuper(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)void Gia_ManAddClausesSuper(Swp_Man_t *, Gia_Obj_t *, Vec_Int_t *)Vec_IntEntry(p->vId2Lit, Abc_Lit2Var(Lit))int Swp_ManLit2Lit(Swp_Man_t *, int)LitSat > 0Vec_Int_t *Gia_ManGetCex(Gia_Man_t *, Vec_Int_t *, sat_solver *, Vec_Int_t *)Memory usage:Runtime usage:SAT sweeper statistics: 0CObj = %8d (%8d). F = %6d. AIG = %7.2f MB. F-mem = %7.2f MB. Other = %7.2f MB. Simulated %d frames with %d words. Simulation timep->pSwitchingsrc/aig/gia/giaSwitch.cfloat Gia_ManEvaluateSwitching(Gia_Man_t *)Gia_ManObjNum(pDfs) == Gia_ManObjNum(p)Vec_Flt_t *Gia_ManPrintOutputProb(Gia_Man_t *)void Gia_ManSwiSimInfoRandom(Gia_ManSwi_t *, unsigned int *, int)void Gia_ManSwiSimulateRound(Gia_ManSwi_t *, int)void Gia_ManSwiSimInfoRandomShift(Gia_ManSwi_t *, unsigned int *, int)Conflict of options: Can either compute probability of 1, or probability of switching by observing transitions.Vec_IntCountEntry(p->vRegClasses, 0) == 0src/aig/gia/giaTim.cint Gia_ManClockDomainNum(Gia_Man_t *)nAll == Gia_ManCiNum(p)Gia_Man_t *Gia_ManDupNormalize(Gia_Man_t *, int)nPis > 0Gia_ManIsNormalized(p)Gia_Man_t *Gia_ManDupUnshuffleInputs(Gia_Man_t *)Gia_ManIsSeqWithBoxes(p)int Gia_ManOrderWithBoxes_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)Vec_Int_t *Gia_ManOrderWithBoxes(Gia_Man_t *)Gia_ManIsNormalized( p )Gia_ObjId(p, pObj) == i+1Input %d of BoxA %d (1stCI = %d; 1stCO = %d) has TFI with CI %d, which corresponds to output %d of BoxB %d (1stCI = %d; 1stCO = %d). !Gia_ManBufNum(p)Gia_Man_t *Gia_ManDupUnnormalize(Gia_Man_t *)int Gia_ManLevelWithBoxes_rec(Gia_Man_t *, Gia_Obj_t *)int Gia_ManLevelWithBoxes(Gia_Man_t *)nBoxInputs == (int)pDelayTable[1]int Gia_ManLutLevelWithBoxes_rec(Gia_Man_t *, Gia_Obj_t *)int Gia_ManLutLevelWithBoxes(Gia_Man_t *)void *Gia_ManUpdateTimMan(Gia_Man_t *, Vec_Int_t *)Vec_IntSize(vBoxPres) == Tim_ManBoxNum(pManTime)void *Gia_ManUpdateTimMan2(Gia_Man_t *, Vec_Int_t *, int)Vec_IntSize(vBoxesLeft) <= Tim_ManBoxNum(pManTime)Gia_Man_t *Gia_ManUpdateExtraAig(void *, Gia_Man_t *, Vec_Int_t *)Gia_ManCoNum(p) == Tim_ManCiNum(pManTime) - Tim_ManPiNum(pManTime)curPo == Gia_ManCoNum(p)Gia_Man_t *Gia_ManUpdateExtraAig2(void *, Gia_Man_t *, Vec_Int_t *)Gia_ManCoNum(p) == Tim_ManCiNum(pManTime) - nRealPisGia_Man_t *Gia_ManDupMoveLast(Gia_Man_t *, int, int)void Gia_ManDupCollapse_rec(Gia_Man_t *, Gia_Obj_t *, Gia_Man_t *)!fSeq || p->vRegClassesGia_Man_t *Gia_ManDupCollapse(Gia_Man_t *, Gia_Man_t *, Vec_Int_t *, int)Gia_ManCiNum(p) == Tim_ManPiNum(pManTime) + Gia_ManCoNum(pBoxes)vBoxPres != NULL || Tim_ManPoNum(pManTime) == Gia_ManCoNum(pNew) - nBBoutsvBoxPres != NULL || Tim_ManPiNum(pManTime) == Gia_ManCiNum(pNew) - nBBinsVec_IntSize(p->vRegInits) == Gia_ManRegNum(pNew)%s_spec.aig%s_impl.aigDumped two parts of the miter into files "%s" and "%s". Verification failed for at least one output (%d). void Gia_ObjSetCoLevel(Gia_Man_t *, Gia_Obj_t *)Warning: Shuffled CI order to be correct sequential AIG.Warning: Unshuffled CI order to be correct AIG with boxes.The command has to terminate. Boxes are not in a topological order.The following information may help debugging (numbers are 0-based):In a correct topological order, BoxB should precede BoxA.Boxes are not in a topological order. Switching to level computation without boxes.Boxes of spec and design cannot be aligned. Cannot proceed.Spec has less boxes than the design. Cannot proceed.Spec has no box logic. Use standard flow.Design has no box logic. Use standard flow.Spec file is not given. Use standard flow.src/aig/gia/giaTis.cGia_Man_t *Gia_ManTisDupMuxes(Gia_Man_t *)void Gia_ManTisCollectMffc_rec(Gia_Man_t *, int, Vec_Int_t *, Vec_Int_t *)void Gia_ManTisCollectMffc(Gia_Man_t *, int, Vec_Int_t *, Vec_Int_t *)MFFC %d has %d nodes and %d leaves: Node %2d : Leaf %2d : src/aig/gia/giaTruth.cint Gia_Truth5ToGia(Gia_Man_t *, int *, int, unsigned int, int)int Gia_Truth6ToGia(Gia_Man_t *, int *, int, word, int)Error for output %d. Finished processing %d outputs. word Gia_LutComputeTruth6_rec(Gia_Man_t *, int, Vec_Wrd_t *)word Gia_LutComputeTruth6(Gia_Man_t *, int, Vec_Wrd_t *)void Gia_ObjComputeTruthTable6Lut_rec(Gia_Man_t *, int, Vec_Wrd_t *)Vec_WrdSize(vTemp) == Gia_ManObjNum(p)word Gia_ObjComputeTruthTable6Lut(Gia_Man_t *, int, Vec_Wrd_t *)i <= 6word Gia_ObjComputeTruth6(Gia_Man_t *, int, Vec_Int_t *, Vec_Wrd_t *)Vec_IntSize(vSupp) <= 6void Gia_ObjComputeTruth6CisSupport_rec(Gia_Man_t *, int, Vec_Int_t *)void Gia_ObjComputeTruthTable6_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Wrd_t *)word Gia_ObjComputeTruthTable6(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *, Vec_Wrd_t *)pLeaf->fMark0 || Gia_ObjIsRo(p, pLeaf)p->nTtVars == Gia_ManPiNum(p)word *Gia_ObjComputeTruthTable(Gia_Man_t *, Gia_Obj_t *)p->vTtMemory == NULLvoid Gia_ObjComputeTruthTableStart(Gia_Man_t *, int)void Gia_ObjCollectInternalCut_rec(Gia_Man_t *, int)!Gia_ObjHasNumId(p, iRoot)void Gia_ObjCollectInternalCut(Gia_Man_t *, int, Vec_Int_t *)Gia_ObjIsAnd(Gia_ManObj(p, iRoot))p->vTtMemory != NULLword *Gia_ObjComputeTruthTableCut(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)Vec_IntSize(vLeaves) <= p->nTtVarsi == Gia_ObjNumId(p, iObj)Gia_Man_t *Gia_ManIsoNpnReduce(Gia_Man_t *, Vec_Ptr_t **, int)Vec_IntEntry(vTt2Class[nVars], truthId) == -1Vec_IntEntry(vTt2Class[nVars], truthId) >= 0unsigned int Abc_Tt5Cofactor0(unsigned int, int)word Vec_WrdEntryLast(Vec_Wrd_t *)UUUUUUUU33333333""""""""DDDDDDDD 00000000EQGyU)] C k 1 g # ]  a  = WCg!i Y 7yEm!k)_=u#{7qQ!QAsE5c/Kg{!Gia_ManTerStateLookup( pState, nWords, pBins, nBins )src/aig/gia/giaTsim.cvoid Gia_ManTerStateInsert(unsigned int *, int, unsigned int **, int)iMaxTerValue >= 0int Gia_ManTerRetire2(Gia_ManTer_t *, unsigned int *)void Gia_ManTerStatePrint(unsigned int *, int, int) (0=%4d, 1=%4d, x=%4d) Found %d constant registers. Found %d non-ternary registers. Transforming %d const and %d equiv registers. Gia_ManTer_t *Gia_ManTerSimulate(Gia_Man_t *, int)Ternary simulation saturated after %d iterations. void Gia_ManTerSimulateRound(Gia_ManTer_t *)(Res0 & Res1) <= 3src/aig/gia/giaUnate.cint Gia_ManCheckUnate_rec(Gia_Man_t *, int)Inputs : Out%4d : %s void Gia_ManCheckUnateTest(Gia_Man_t *, int, int)src/aig/gia/giaUtil.cvoid Gia_ManCheckMark0(Gia_Man_t *)void Gia_ManCheckMark1(Gia_Man_t *)Gia_ManCiNum(p) == Vec_IntSize(vCiValues)void Gia_ManSetPhasePattern(Gia_Man_t *, Vec_Int_t *)p->vLevelsfloat Gia_ManLevelAve(Gia_Man_t *)Vec_IntSize(vCiLevels) == Gia_ManCiNum(p)int Gia_ManSetLevels(Gia_Man_t *, Vec_Int_t *)Vec_IntSize(vSlacks) == Gia_ManObjNum(p)Vec_Int_t *Gia_ManComputeSlacks(Gia_Man_t *)void Gia_ManCreateRefs(Gia_Man_t *)void Gia_ManDfsForCrossCut_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)int Gia_ManCrossCut(Gia_Man_t *, int)int Gia_ObjIsMuxType(Gia_Obj_t *)int Gia_ObjRecognizeExor(Gia_Obj_t *, Gia_Obj_t **, Gia_Obj_t **)Gia_Obj_t *Gia_ObjRecognizeMux(Gia_Obj_t *, Gia_Obj_t **, Gia_Obj_t **)Gia_ObjIsMuxType(pNode)pCtrl != NULLint Gia_ObjRecognizeMuxLits(Gia_Man_t *, Gia_Obj_t *, int *, int *)int Gia_NodeDeref_rec(Gia_Man_t *, Gia_Obj_t *)int Gia_NodeRef_rec(Gia_Man_t *, Gia_Obj_t *)int Gia_NodeMffcSize(Gia_Man_t *, Gia_Obj_t *)Gia_ObjIsCand(pNode)ConeSize1 >= 0void Gia_NodeCollect_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)int Gia_NodeMffcSizeSupp(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)void Gia_ObjPrint(Gia_Man_t *, Gia_Obj_t *)constant 0RO( %4d%s )RI( %4d%s )XOR( %4d%s, %4d%s )MUX( %4d%s, %4d%s, %4d%s ) mark0 mark1 Cut = { GIA manager has %d ANDs, %d XORs, %d MUXes. void Gia_ManPrintCo(Gia_Man_t *, Gia_Obj_t *)TFI cone of CO number %d: void Gia_ManPrintCollect_rec(Gia_Man_t *, Gia_Obj_t *, Vec_Int_t *)GIA logic cone for node %d: GIA logic cone for %d nodes: Var = %d. Words = %d. Truths = %d. Rounds = %d. Objects = %d. Total = %d. Objects %d are different. Representatives of objects %d are different. i >= 0 && i < Gia_ManPoNum(p)void Gia_ManSwapPos(Gia_Man_t *, int)%d nodes have reprs. %d nodes have nexts. Gia_ObjRepr(p, i) < iint Gia_ManHasChoices_very_old(Gia_Man_t *)Gia_ManHasChoices_very_old(): Error: %d internal nodes have no fanout and no repr. Gia_ManHasChoices_very_old(): Error: %d internal nodes have both fanout and repr. nGroupSize > 0Vec_Int_t *Gia_ManGroupProve(Gia_Man_t *, char *, int, int)pCommLine != NULLRUNNING MultiProve: Group size = %d. Command line = "%s". GROUP %4d : %4d <= PoId < %4d : vStatusCur != NULLVec_PtrSize(vCexes) == Gia_ManPoNum(p)Vec_IntSize(vOutMap) == Gia_ManPoNum(p)SUMMARY: Properties = %6d. UNSAT = %6d. UNDEC = %6d. Command timeTotal time Simulation converged after %d frames. Simulation terminated after %d frames. LutSizeMax <= 6void Gia_AigerWriteLut(Gia_Man_t *, char *)iLut == nLutsnSize1 == nSize2Successfully dumped %d bytes of binary data. Gia_ManRegNum(pNew) == 0Gia_Man_t *Gia_ManDupWithMuxPos(Gia_Man_t *)AIGs have different number of objects.Warning: AIG has repr data-strucure but not reprs.nOutputs == 0src/aig/ioa/ioaReadAig.cAig_Man_t *Ioa_ReadAigerFromMemory(char *, int, int)Reading AIGER files with liveness properties are currently not supported. Ioa_ReadAiger: The network check has failed.src/aig/ioa/ioaWriteAig.cVec_Str_t *Ioa_WriteAigerIntoMemoryStr(Aig_Man_t *)Ioa_WriteAiger(): Cannot open the output file "%s". This file was produced by the IOA package in ABC on %s void Ioa_WriteAiger(Aig_Man_t *, char *, int, int)n%s%cIoa_WriteAiger(): AIGER generation has failed because the allocated buffer is too small.Ioa_FileSize(): The file is unavailable (absent or open).src/aig/ivy/ivyBalance.cIvy_Obj_t *Ivy_NodeBalanceBuildSuper(Ivy_Man_t *, Vec_Ptr_t *, Ivy_Type_t, int)int Ivy_NodeBalanceCone_rec(Ivy_Obj_t *, Ivy_Obj_t *, Vec_Ptr_t *)!Ivy_IsComplement(pObj)Ivy_ObjIsNode(pObj)!Ivy_IsComplement(pObjOld)int Ivy_NodeBalance_rec(Ivy_Man_t *, Ivy_Obj_t *, Vec_Vec_t *, int, int)!Ivy_ObjIsBuf(pObjOld)Ivy_ObjIsNode(pObjOld)pObjOld->TravId == 0Vec_Ptr_t *Ivy_NodeBalanceCone(Ivy_Obj_t *, Vec_Vec_t *, int)Ivy_Regular(pObjLeft)->Level == Ivy_Regular(pObjRight)->Levelint Ivy_NodeBalanceFindLeft(Vec_Ptr_t *)void Ivy_NodeBalancePermute(Ivy_Man_t *, Vec_Ptr_t *, int, int)Type != IVY_AND || !Ivy_ObjIsConst1(Ivy_Regular(p0))src/aig/ivy/ivy.hIvy_Obj_t *Ivy_ObjCreateGhost(Ivy_Man_t *, Ivy_Obj_t *, Ivy_Obj_t *, Ivy_Type_t, Ivy_Init_t)p1 == NULL || !Ivy_ObjIsConst1(Ivy_Regular(p1))Type == IVY_PI || Ivy_Regular(p0) != Ivy_Regular(p1)Ivy_ManBalance(): The check has failed.Ivy_ObjIsNode(pGhost)src/aig/ivy/ivyCanon.cIvy_Obj_t *Ivy_CanonPair_rec(Ivy_Man_t *, Ivy_Obj_t *)Ivy_ObjIsAnd(pGhost) || (!Ivy_ObjFaninC0(pGhost) && !Ivy_ObjFaninC1(pGhost))Ivy_ObjFaninId0(pGhost) != 0 && Ivy_ObjFaninId1(pGhost) != 0Init != IVY_INIT_NONEIvy_Init_t Ivy_InitNotCond(Ivy_Init_t, int) ( ((AIvy_ManCheck: Node with ID %d is listed as number %d in the array of objects. Ivy_ManCheck: The AIG has non-standard constant or PI node with ID "%d". Ivy_ManCheck: The AIG has non-standard PO node with ID "%d". Ivy_ManCheck: The buffer with ID "%d" contains second fanin. Ivy_ManCheck: The latch with ID "%d" contains second fanin. Ivy_ManCheck: The latch with ID "%d" does not have initial state. Ivy_ManCheck: Latch with ID "%d" is not in the structural hashing table. Ivy_ManCheck: The AIG has internal node "%d" with a NULL fanin. Ivy_ManCheck: The AIG has node "%d" with a wrong ordering of fanins. Ivy_ManCheck: Node with ID "%d" has level %d but should have level %d. Ivy_ManCheck: Node with ID "%d" is not in the structural hashing table. Ivy_ManCheck: Node with ID "%d" has no fanouts. Ivy_ManCheck: Node with ID "%d" has mismatch between the number of fanouts and refs. Sequential AIG has %d dangling nodes. Node %d is a fanin of node %d but the fanout is not there. Node %d has prev %d without common fanin. Node %d is a fanout of node %d but the fanin is not there. !Ivy_IsComplement(pObj->pEquiv)src/aig/ivy/ivyCheck.cint Ivy_ManCheckChoices(Ivy_Man_t *)Node %d has member %d in its equiv class with %d fanouts. Ivy_ManCheck: The number of nodes in the structural hashing table is wrong.src/aig/ivy/ivyCut.cint Ivy_ManSeqFindCut_int(Ivy_Man_t *, Vec_Int_t *, Vec_Int_t *, int)LeafBest >= 0Ivy_ObjIsNode(pNode) || Ivy_ObjIsLatch(pNode) || Ivy_ObjIsBuf(pNode)Ivy_ObjIsNode(pNode)Vec_IntSize(vFront) <= nSizeLimit!Ivy_IsComplement(pRoot)void Ivy_ManSeqFindCut(Ivy_Man_t *, Ivy_Obj_t *, Vec_Int_t *, Vec_Int_t *, int)Ivy_ObjIsNode(pRoot)Ivy_ObjFaninId0(pRoot)Ivy_ObjFaninId1(pRoot)Vec_IntSize(vFront) <= nSizeint Ivy_ManFindBoolCut_rec(Ivy_Man_t *, Ivy_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *, Ivy_Obj_t *)pObj->fMarkA == 1int Ivy_ManFindBoolCutCost(Ivy_Obj_t *)int Ivy_ManFindBoolCut(Ivy_Man_t *, Ivy_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Ptr_t *)Ivy_ObjLevel(pRoot) == Ivy_ObjLevelNew(pRoot)(int)pObj->Level <= LevpObj->fMarkA ^ pObj->fMarkBpCutNew->uHashint Ivy_NodeCutFindOrAdd(Ivy_Store_t *, Ivy_Cut_t *)pCutStore->nCuts < pCutStore->nCutsMaxint Ivy_NodeCutFindOrAddFilter(Ivy_Store_t *, Ivy_Cut_t *)pCut->nSize > 0void Ivy_NodePrintCut(Ivy_Cut_t *)Node %d nLeaves <= IVY_CUT_INPUTIvy_Store_t *Ivy_NodeFindCutsAll(Ivy_Man_t *, Ivy_Obj_t *, int)pCutStore->nCuts == 1Total cuts = %6d. Trivial = %6d. Nodes = %6d. Satur = %6d. Leaf > 0int Ivy_NodeGetLeafCostOne(Ivy_Man_t *, int, Vec_Int_t *)int Ivy_NodeCutDeriveNew(Ivy_Cut_t *, Ivy_Cut_t *, int, int, int)IdNew0 < IdNew1pCutNew->nSize <= pCut->nSizeMaxsrc/aig/ivy/ivyCutTrav.cIvy_Store_t *Ivy_NodeFindCutsTravAll(Ivy_Man_t *, Ivy_Obj_t *, int, int, Vec_Ptr_t *, Vec_Ptr_t *, Vec_Int_t *, Vec_Vec_t *)Ivy_ObjTravId(pLeaf) < nNodesVec_PtrSize(vCuts0) > 0Vec_PtrSize(vCuts1) > 0pCut->nSize <= nLeavesvoid Ivy_NodeComputeVolume2(Ivy_Obj_t *, int, Vec_Ptr_t *, Vec_Ptr_t *)pFanin->Level <= pPivot->LevelIvy_ObjIsBuf(pObj) || Ivy_ObjIsAnd(pObj) || Ivy_ObjIsExor(pObj)src/aig/ivy/ivyDfs.cvoid Ivy_ManDfs_rec(Ivy_Man_t *, Ivy_Obj_t *, Vec_Int_t *)Ivy_ManLatchNum(p) == 0Vec_Int_t *Ivy_ManDfs(Ivy_Man_t *)Vec_IntSize(vNodes) == Ivy_ManNodeNum(p) + Ivy_ManBufNum(p)Vec_Int_t *Ivy_ManDfsSeq(Ivy_Man_t *, Vec_Int_t **)void Ivy_ManCollectCone_rec(Ivy_Obj_t *, Vec_Ptr_t *)void Ivy_ManCollectCone(Ivy_Obj_t *, Vec_Ptr_t *, Vec_Ptr_t *)!Ivy_ObjIsBuf(pObj)Vec_Vec_t *Ivy_ManLevelize(Ivy_Man_t *)p->vRequired == NULLVec_Int_t *Ivy_ManRequiredLevels(Ivy_Man_t *)Manager contains combinational loop! Node "%d" is encountered twice on the following path: int Ivy_ManIsAcyclic_rec(Ivy_Man_t *, Ivy_Obj_t *) -> (%dIvy_ObjIsNode(pObj) || Ivy_ObjIsBuf(pObj) (cone of %s "%d") int Ivy_ManSetLevels_rec(Ivy_Obj_t *, int)CI %d has a choice, which will not be visualized. {@@@@@@CEDDCfDDtD{DmDDvEEEE}EEBKtKI JHGGVIrIdIkI]IyIJJJJJJM9NMLL>MVMJMPMDM\MUUUU3333Node.fCompl == 0src/aig/ivy/ivyDsd.cint Ivy_TruthDsd(unsigned int, Vec_Int_t *)unsigned int Ivy_TruthDsdCompute_rec(int, Vec_Int_t *)Node.Type == IVY_DEC_MAJ || (VarC & 1) == 0Const1%sAND(EXOR(void Ivy_TruthDsdPrint_rec(FILE *, int, Vec_Int_t *)MUX(Node.Type == IVY_DEC_AND || (Var & 1) == 0Ivy_Obj_t *Ivy_ManDsdConstruct_rec(Ivy_Man_t *, Vec_Int_t *, int, Vec_Int_t *)Count0 == 0 || Count1 == 0int Ivy_TruthDecompose_rec(unsigned int, Vec_Int_t *)Count0 == 0 || Count2 == 0Count1 == 0 || Count2 == 0uTruthCof != 0 && ~uTruthCof != 0nSupp >= 3int Ivy_TruthRecognizeMuxMaj(unsigned int, int *, int, Vec_Int_t *)Num < 32Count[0] == 1 || Count[0] == 3Count[1] == 1 || Count[1] == 3Count[2] == 1 || Count[2] == 3iNum >= 0 && iNum <= 5void Ivy_DecSetVar(Ivy_Dec_t *, int, unsigned int)unsigned int Ivy_DecGetVar(Ivy_Dec_t *, int)Undecomposable!p->fFanoutsrc/aig/ivy/ivyFanout.cvoid Ivy_ManStartFanout(Ivy_Man_t *)void Ivy_ManStopFanout(Ivy_Man_t *)void Ivy_ObjAddFanout(Ivy_Man_t *, Ivy_Obj_t *, Ivy_Obj_t *)pFanin->pFanout != NULLvoid Ivy_ObjDeleteFanout(Ivy_Man_t *, Ivy_Obj_t *, Ivy_Obj_t *)ppPlaceN == NULL || *ppPlaceN == pFanoutvoid Ivy_ObjPatchFanout(Ivy_Man_t *, Ivy_Obj_t *, Ivy_Obj_t *, Ivy_Obj_t *)ppPlace == NULL || *ppPlace == pFanoutOldvoid Ivy_ObjCollectFanouts(Ivy_Man_t *, Ivy_Obj_t *, Vec_Ptr_t *)Ivy_Obj_t **Ivy_ObjNextFanoutPlace(Ivy_Obj_t *, Ivy_Obj_t *)!Ivy_IsComplement(pFanout)Ivy_ObjFanin1(pFanout) == pObjIvy_Obj_t **Ivy_ObjPrevFanoutPlace(Ivy_Obj_t *, Ivy_Obj_t *)Ivy_Obj_t **Ivy_ObjPrevNextFanoutPlace(Ivy_Obj_t *, Ivy_Obj_t *)Ivy_ObjFanin1(pTemp) == pObjIvy_Obj_t *Ivy_ObjPrevFanout(Ivy_Obj_t *, Ivy_Obj_t *)Ivy_Obj_t **Ivy_ObjNextPrevFanoutPlace(Ivy_Obj_t *, Ivy_Obj_t *)Ivy_Obj_t *Ivy_ObjNextFanout(Ivy_Obj_t *, Ivy_Obj_t *)Delay oriented mapping: Area recovery 2 : Area recovery 1 : nLimit <= 32src/aig/ivy/ivyFastMap.cvoid Ivy_FastMapNodeArea2(Ivy_Man_t *, Ivy_Obj_t *, int)pSupp->fMark == 0DelayOld <= pSupp->DelayRvoid Ivy_FastMapMark_rec(Ivy_Man_t *, Ivy_Obj_t *)int Ivy_FastMapNodeWillGrow(Ivy_Man_t *, Ivy_Obj_t *)int Ivy_FastMapNodeFaninCost(Ivy_Man_t *, Ivy_Obj_t *)void Ivy_FastMapNodeFaninUpdate(Ivy_Man_t *, Ivy_Obj_t *, Vec_Ptr_t *)int Ivy_FastMapNodeFaninCompact_int(Ivy_Man_t *, Ivy_Obj_t *, int, Vec_Ptr_t *)void Ivy_FastMapNodeRecover2(Ivy_Man_t *, Ivy_Obj_t *, int, Vec_Ptr_t *, Vec_Ptr_t *)pSupp->Delay <= pSupp->DelayRvoid Ivy_FastMapNodeRecover4(Ivy_Man_t *, Ivy_Obj_t *, int, Vec_Ptr_t *, Vec_Ptr_t *)%s : Delay = %3d. Area = %6d. void Ivy_FastMapNodeArea(Ivy_Man_t *, Ivy_Obj_t *, int)void Ivy_FastMapNode(Ivy_Man_t *, Ivy_Obj_t *, int)pSupp->nSize > 1pSupp->Delay > 0pSupp0->nSize >= pSupp1->nSizeint Ivy_FastMapMerge(Ivy_Supp_t *, Ivy_Supp_t *, Ivy_Supp_t *, int)pSupp->nRefs > 0void Ivy_FastMapRequired(Ivy_Man_t *, int, int)void Ivy_FastMapNodeRecover(Ivy_Man_t *, Ivy_Obj_t *, int, Vec_Ptr_t *, Vec_Ptr_t *)int Ivy_FastMapNodeDeref(Ivy_Man_t *, Ivy_Obj_t *)pSuppF->nRefs > 0int Ivy_FastMapNodeRef(Ivy_Man_t *, Ivy_Obj_t *)pSuppF->nRefs >= 0int Ivy_FastMapNodeAreaDerefed(Ivy_Man_t *, Ivy_Obj_t *)pSupp->nRefs == 0aResult == aResult2int Ivy_FastMapNodeAreaRefed(Ivy_Man_t *, Ivy_Obj_t *)߿AqEQGyU)] C k 1 g # ]  a  = WCg!i Y 7yEm!k)_=u#{7qQ!QAsE5c/Kg{Fraiging Ivy_ManLatchNum(pManAig) == 0src/aig/ivy/ivyFraig.cIvy_Man_t *Ivy_FraigPerform(Ivy_Man_t *, Ivy_FraigParams_t *)Ivy_Man_t *Ivy_FraigMiter(Ivy_Man_t *, Ivy_FraigParams_t *)void Ivy_NodeAssignRandom(Ivy_FraigMan_t *, Ivy_Obj_t *)void Ivy_NodeAssignConst(Ivy_FraigMan_t *, Ivy_Obj_t *, int)void Ivy_NodeSimulate(Ivy_FraigMan_t *, Ivy_Obj_t *)p->nSimWords <= 128unsigned int Ivy_NodeHash(Ivy_FraigMan_t *, Ivy_Obj_t *)p->lClasses.pHead == NULLvoid Ivy_FraigCreateClasses(Ivy_FraigMan_t *)Ivy_ObjClassNodeNext(pObj) == NULLi < p->nSimWordsvoid Ivy_FraigCheckOutputSimsSavePattern(Ivy_FraigMan_t *, Ivy_Obj_t *)Class { %d(%d)%cnChanges >= 1void Ivy_FraigResimulate(Ivy_FraigMan_t *)!Ivy_IsComplement( pNode )void Ivy_FraigAddClausesMux(Ivy_FraigMan_t *, Ivy_Obj_t *)Ivy_ObjIsMuxType( pNode )!Ivy_IsComplement(pNode)void Ivy_FraigAddClausesSuper(Ivy_FraigMan_t *, Ivy_Obj_t *, Vec_Ptr_t *)Ivy_ObjIsNode( pNode )Vec_Ptr_t *Ivy_FraigCollectSuper(Ivy_Obj_t *, int)!Ivy_ObjIsPi(pObj)void Ivy_FraigObjAddToFrontier(Ivy_FraigMan_t *, Ivy_Obj_t *, Vec_Ptr_t *)Ivy_ObjFaninVec(pObj) == NULLint Ivy_FraigSetActivityFactors_rec(Ivy_FraigMan_t *, Ivy_Obj_t *, int, int)Ivy_ObjSatNum(pObj)NewSize == dd->sizeDdNode *Ivy_FraigNodesAreEquivBdd_int(DdManager *, DdNode *, Vec_Ptr_t *, int)Ivy_ObjIsAnd(pNode)void Ivy_FraigExtractCone_rec(Ivy_Man_t *, Ivy_Obj_t *, Vec_Int_t *, Vec_Int_t *)pMiter->fPhase == pObjIvy->fPhaseAig_Man_t *Ivy_FraigExtractCone(Ivy_Man_t *, Ivy_Obj_t *, Ivy_Obj_t *, Vec_Int_t *)Ivy_Man_t *Ivy_FraigPerform_int(Ivy_Man_t *, Ivy_FraigParams_t *, ABC_INT64_T, ABC_INT64_T, ABC_INT64_T *, ABC_INT64_T *)Ivy_Obj_t *Ivy_ObjChild0Equiv(Ivy_Obj_t *)!pObj->pEquiv && !pObj->pFanoutIvy_FraigMan_t *Ivy_FraigStart(Ivy_Man_t *, Ivy_FraigParams_t *)k == Ivy_ManObjNum(pManAig)SimWords = %d. Rounds = %d. Mem = %0.2f MB. Classes: Beg = %d. End = %d. Final = %d. Miter = %d. Total = %d. Mux = %d. (Exor = %d.) SatVars = %d. int Ivy_FraigNodeIsConst(Ivy_FraigMan_t *, Ivy_Obj_t *)void Ivy_FraigNodeAddToSolver(Ivy_FraigMan_t *, Ivy_Obj_t *, Ivy_Obj_t *)Ivy_ObjSatNum(pNode)Ivy_ObjFaninVec(pNode) == NULLint Ivy_FraigSetActivityFactors(Ivy_FraigMan_t *, Ivy_Obj_t *, Ivy_Obj_t *)p->pParams->dActConeRatio > 0 && p->pParams->dActConeRatio < 1void Ivy_FraigSweep(Ivy_FraigMan_t *)Ivy_Regular(pObjNew) != Ivy_ManConst1(p->pManFraig)Ivy_Obj_t *Ivy_FraigAnd(Ivy_FraigMan_t *, Ivy_Obj_t *)int Ivy_FraigNodesAreEquiv(Ivy_FraigMan_t *, Ivy_Obj_t *, Ivy_Obj_t *)p->pHaig == NULLsrc/aig/ivy/ivyHaig.cvoid Ivy_ManHaigStart(Ivy_Man_t *, int)Starting : p->pHaig != NULLvoid Ivy_ManHaigTrasfer(Ivy_Man_t *, Ivy_Man_t *)void Ivy_ManHaigStop(Ivy_Man_t *)void Ivy_ManHaigCreateObj(Ivy_Man_t *, Ivy_Obj_t *)void Ivy_ManHaigCreateChoice(Ivy_Man_t *, Ivy_Obj_t *, Ivy_Obj_t *)Ivy_ObjRefs(pObjOldHaigR) > 0!Ivy_IsComplement(pObjOldHaigR->pEquiv)int Ivy_ManHaigCountChoices(Ivy_Man_t *, int *)void Ivy_ManHaigPostprocess(Ivy_Man_t *, int)Final : HAIG : Total choice nodes = %d. Total choices = %d. Skipped classes = %d. void Ivy_ManHaigSimulate(Ivy_Man_t *)Iter %d : Non-determinate = %d Ivy_Obj_t *Ivy_HaigObjRepr(Ivy_Obj_t *)Ivy_ObjRefs(pTemp) > 0int Ivy_HaigObjCountClass(Ivy_Obj_t *)Ivy_ObjRefs(pObj) > 0In0 != IVY_INIT_NONE && In1 != IVY_INIT_NONEIvy_Init_t Ivy_ManHaigSimulateChoice(Ivy_Init_t, Ivy_Init_t)HAIG is acyclicHAIG contains a cycleCompatibility fails.!Ivy_ObjFaninC0(pObj)src/aig/ivy/ivyMan.cIvy_Man_t *Ivy_ManDup(Ivy_Man_t *)Ivy_ManNodeNum(p) == Ivy_ManNodeNum(pNew)Ivy_ManLatchNum(p) == Ivy_ManLatchNum(pNew)Ivy_ManLatchNum(pMan) == 0Ivy_Man_t *Ivy_ManFrames(Ivy_Man_t *, int, int, int, Vec_Ptr_t **)Update lev Update levR Ivy_ObjIsNode(pObj) || Ivy_ObjIsLatch(pObj) || Ivy_ObjIsBuf(pObj)int Ivy_ManCleanupSeq(Ivy_Man_t *)Ivy_ObjRefs(pObj) == 0Structural hashing is not finished after %d forward latch moves. PI/PO = %d/%d A = %7d. L = %5d. MaxID = %7d. Lev = %3d. nLatches < Ivy_ManPiNum(p) && nLatches < Ivy_ManPoNum(p)void Ivy_ManMakeSeq(Ivy_Man_t *, int, int *)Ivy_ManPiNum(p) == Vec_PtrSize(p->vPis)Ivy_ManPoNum(p) == Vec_PtrSize(p->vPos)Vec_PtrSize( p->vBufs ) == 0The number of remaining buffers is %d. Ivy_ManFrames(): The check has failed.This circuit cannot be forward-retimed completely. Quitting.Ivy_ManMakeSeq(): The check has failed.src/aig/ivy/ivyMem.cvoid Ivy_ManAddMemory(Ivy_Man_t *)p->pListFree == NULLnLeaves > 2src/aig/ivy/ivyMulti.cint Ivy_MultiPlus(Ivy_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *, Ivy_Type_t, int, Vec_Ptr_t *)Vec_PtrSize( vSols ) > 0Type != IVY_LATCH || !Ivy_IsComplement(p0)BestK != -1int Ivy_MultiCover(Ivy_Man_t *, Ivy_Eva_t *, int, int, int, Vec_Ptr_t *)k < nLeaves@B@B@B@B!Ivy_IsComplement(pGhost)src/aig/ivy/ivyObj.cIvy_Obj_t *Ivy_ObjCreate(Ivy_Man_t *, Ivy_Obj_t *)Ivy_ObjIsGhost(pGhost)Ivy_TableLookup(p, pGhost) == NULLvoid Ivy_ObjConnect(Ivy_Man_t *, Ivy_Obj_t *, Ivy_Obj_t *, Ivy_Obj_t *)Ivy_ObjIsPi(pObj) || Ivy_ObjIsOneFanin(pObj) || pFan1 != NULLvoid Ivy_ObjDisconnect(Ivy_Man_t *, Ivy_Obj_t *)Ivy_ObjIsPi(pObj) || Ivy_ObjIsOneFanin(pObj) || Ivy_ObjFanin1(pObj) != NULLpObj->pNextFan0 == NULLpObj->pNextFan1 == NULLpObj->pPrevFan0 == NULLpObj->pPrevFan1 == NULLvoid Ivy_ObjPatchFanin0(Ivy_Man_t *, Ivy_Obj_t *, Ivy_Obj_t *)void Ivy_ObjDelete(Ivy_Man_t *, Ivy_Obj_t *, int)Ivy_ObjRefs(pObj) == 0 || !fFreeTopvoid Ivy_ObjDelete_rec(Ivy_Man_t *, Ivy_Obj_t *, int)!Ivy_ObjIsNone(pObj)void Ivy_ObjReplace(Ivy_Man_t *, Ivy_Obj_t *, Ivy_Obj_t *, int, int, int)Ivy_ObjIsNone(pObjOld) || !Ivy_ObjIsPi(pObjOld)!Ivy_ObjIsBuf(Ivy_Regular(pObjNew))pObjOld != Ivy_Regular(pObjNew)!Ivy_IsComplement(pObjNew)Ivy_ObjFanin0(pObjNew) == NULL || pObjOld != Ivy_ObjFanin0(pObjNew)Ivy_ObjFanin1(pObjNew) == NULL || pObjOld != Ivy_ObjFanin1(pObjNew)pObjOld->pFanout != NULLpObjNew->pFanout == NULLIvy_ObjRefs(pObjNew) == 0void Ivy_NodeFixBufferFanins(Ivy_Man_t *, Ivy_Obj_t *, int)void Ivy_ObjRefsDec(Ivy_Obj_t *)src/aig/ivy/ivyOper.cIvy_Obj_t *Ivy_Oper(Ivy_Man_t *, Ivy_Obj_t *, Ivy_Obj_t *, Ivy_Type_t)Type == IVY_AND || Type == IVY_EXORIvy_Obj_t *Ivy_Multi(Ivy_Man_t *, Ivy_Obj_t **, int, Ivy_Type_t)Ivy_Obj_t *Ivy_Miter(Ivy_Man_t *, Vec_Ptr_t *)BalanceRewriteOriginal:Cleanup after rewriting removed %d dangling nodes. src/aig/ivy/ivyRwr.cunsigned int Ivy_NodeGetTruth_rec(Ivy_Obj_t *, int *, int)nGain <= nNodesOld - nNodesNewvoid Ivy_GraphUpdateNetwork3(Ivy_Man_t *, Ivy_Obj_t *, Dec_Graph_t *, int, int)Ivy_ObjIsNode(pFanin) || Ivy_ObjIsCi(pFanin)int Ivy_NodeRewrite(Ivy_Man_t *, Rwt_Man_t *, Ivy_Obj_t *, int, int)nNums < 6unsigned int Ivy_NodeGetTruth(Ivy_Obj_t *, int *, int)Dec_Graph_t *Rwt_CutEvaluate(Ivy_Man_t *, Rwt_Man_t *, Ivy_Obj_t *, Vec_Ptr_t *, int, int, int *, unsigned int)(int)Ivy_Regular(pRootNew)->Level <= Requiredvoid Ivy_GraphUpdateNetwork(Ivy_Man_t *, Ivy_Obj_t *, Dec_Graph_t *, int, int)Ivy_ManRewritePre(): The check has failed.src/aig/ivy/ivySeq.cint Ivy_ManRewriteSeq(Ivy_Man_t *, int, int)!Ivy_ObjIsBuf(Ivy_ObjFanin0(pNode))!Ivy_ObjIsBuf(Ivy_ObjFanin1(pNode))unsigned int Ivy_CutGetTruth_rec(Ivy_Man_t *, int, int *, int)int Ivy_CutFindOrAddFilter(Ivy_Store_t *, Ivy_Cut_t *)void Ivy_CutPrintForNode(Ivy_Cut_t *)Cannot compute cuts for more than %d inputs. All = %6d. Minus = %6d. Triv = %6d. Node = %6d. Satur = %6d. Ivy_ObjIsNode(pFanin) || Ivy_ObjIsCi(pFanin) || Ivy_ObjIsConst1(pFanin)int Ivy_NodeRewriteSeq(Ivy_Man_t *, Rwt_Man_t *, Ivy_Obj_t *, int)unsigned int Ivy_CutGetTruth(Ivy_Man_t *, Ivy_Obj_t *, int *, int)Dec_Graph_t *Rwt_CutEvaluateSeq(Ivy_Man_t *, Rwt_Man_t *, Ivy_Obj_t *, Ivy_Cut_t *, char *, Vec_Ptr_t *, int, int *, unsigned int)!Ivy_ObjIsLatch(Ivy_Regular(pAnd0)) || !Ivy_ObjIsLatch(Ivy_Regular(pAnd1))int Ivy_GraphToNetworkSeqCountSeq(Ivy_Man_t *, Ivy_Obj_t *, Dec_Graph_t *, int)Dec_GraphLeaveNum(pGraph) == pCut->nSizevoid Ivy_GraphPrepare(Dec_Graph_t *, Ivy_Cut_t *, Vec_Ptr_t *, char *)Vec_PtrSize(vFanins) == pCut->nSizevoid Ivy_GraphUpdateNetworkSeq(Ivy_Man_t *, Ivy_Obj_t *, Dec_Graph_t *, int)i==0 || pDom->pArray[i-1] < pDom->pArray[i]int Ivy_CutCheckDominance(Ivy_Cut_t *, Ivy_Cut_t *)Ivy_Store_t *Ivy_CutComputeForNode(Ivy_Man_t *, Ivy_Obj_t *, int)Ivy_ObjIsNode(pLeaf)nLats + Ivy_LeafLat(iLeaf0) < IVY_LEAF_MASK && nLats + Ivy_LeafLat(iLeaf1) < IVY_LEAF_MASK!Ivy_IsComplement(pFanin)int Ivy_CutReadLeaf(Ivy_Obj_t *)nLats < IVY_LEAF_MASKint Ivy_CutDeriveNew(Ivy_Cut_t *, Ivy_Cut_t *, int, int, int)temp%02d.dot Node%d%s [label = "%d%s" Node%d%s [label = "%d%s(%d%s)" Node%d [label = "%d(%d%s)"title2 -> Node%d%s [style = invis]; Node%d%s [style = %s]src/aig/ivy/ivyTable.cIvy_Obj_t *Ivy_TableLookup(Ivy_Man_t *, Ivy_Obj_t *)Ivy_ObjIsLatch(pObj) || Ivy_ObjFaninId0(pObj) > 0Ivy_ObjFaninId1(pObj) == 0 || Ivy_ObjFaninId0(pObj) < Ivy_ObjFaninId1(pObj)void Ivy_TableInsert(Ivy_Man_t *, Ivy_Obj_t *)void Ivy_TableDelete(Ivy_Man_t *, Ivy_Obj_t *)*pPlace == pObj->Idvoid Ivy_TableUpdate(Ivy_Man_t *, Ivy_Obj_t *, int)Ivy_ObjIsHash(pObj)int *Ivy_TableFind(Ivy_Man_t *, Ivy_Obj_t *)void Ivy_TableResize(Ivy_Man_t *)Ivy_ObjIsAnd(pNode) || Ivy_ObjIsExor(pNode)src/aig/ivy/ivyUtil.cvoid Ivy_ManCollectCut_rec(Ivy_Man_t *, Ivy_Obj_t *, Vec_Int_t *)int Ivy_ManResetLevels_rec(Ivy_Obj_t *)Ivy_ObjIsNode(pNode) || Ivy_ObjIsBuf(pNode) || Ivy_ObjIsLatch(pNode)int Ivy_ObjRefDeref(Ivy_Man_t *, Ivy_Obj_t *, int, int)pNode0->nRefs > 0pNode1 == NULL || pNode1->nRefs > 0int Ivy_ObjMffcLabel(Ivy_Man_t *, Ivy_Obj_t *)void Ivy_ObjUpdateLevel_rec(Ivy_Man_t *, Ivy_Obj_t *)p->fFanout && p->vRequiredint Ivy_ObjLevelRNew(Ivy_Man_t *, Ivy_Obj_t *)void Ivy_ObjUpdateLevelR_rec(Ivy_Man_t *, Ivy_Obj_t *, int)int Ivy_ObjIsMuxType(Ivy_Obj_t *)Ivy_Obj_t *Ivy_ObjRecognizeMux(Ivy_Obj_t *, Ivy_Obj_t **, Ivy_Obj_t **)Ivy_ObjIsMuxType(pNode)void Ivy_ObjPrintVerbose(Ivy_Man_t *, Ivy_Obj_t *, int)latch (%d%s)buffer (%d%s)AND( %5d%s, %5d%s ) HAIG node not given HAIG node = %d%s { %5d %5d%sPOs: %d=%d%sTrying cut : { %6d(%d) } src/aig/hop/hopBalance.cint Hop_NodeBalanceCone_rec(Hop_Obj_t *, Hop_Obj_t *, Vec_Ptr_t *)Hop_ObjIsNode(pObj)Hop_Obj_t *Hop_NodeBalanceBuildSuper(Hop_Man_t *, Vec_Ptr_t *, Hop_Type_t, int)!Hop_IsComplement(pObjOld)Hop_Obj_t *Hop_NodeBalance_rec(Hop_Man_t *, Hop_Obj_t *, Vec_Vec_t *, int, int)Hop_ObjIsNode(pObjOld)Vec_Ptr_t *Hop_NodeBalanceCone(Hop_Obj_t *, Vec_Vec_t *, int)Hop_ObjLevel(Hop_Regular(pObjLeft)) == Hop_ObjLevel(Hop_Regular(pObjRight))int Hop_NodeBalanceFindLeft(Vec_Ptr_t *)void Hop_NodeBalancePermute(Hop_Man_t *, Vec_Ptr_t *, int, int)Type != AIG_AND || !Hop_ObjIsConst1(Hop_Regular(p0))src/aig/hop/hop.hHop_Obj_t *Hop_ObjCreateGhost(Hop_Man_t *, Hop_Obj_t *, Hop_Obj_t *, Hop_Type_t)p1 == NULL || !Hop_ObjIsConst1(Hop_Regular(p1))Type == AIG_PI || Hop_Regular(p0) != Hop_Regular(p1)Hop_ManBalance(): The check has failed.Hop_ManCheck: The PI node "%p" has fanins. Hop_ManCheck: The PO node "%p" has NULL fanin. Hop_ManCheck: The PO node "%p" has second fanin. Hop_ManCheck: The AIG has internal node "%p" with a NULL fanin. Hop_ManCheck: The AIG has node "%p" with a wrong ordering of fanins. Hop_ManCheck: Node "%p" is not in the structural hashing table. Hop_ManCheck: The number of nodes in the structural hashing table is wrong.Hop_ManCheck: The number of created nodes is wrong.src/aig/hop/hopDfs.cvoid Hop_ManDfs_rec(Hop_Obj_t *, Vec_Ptr_t *)!Hop_IsComplement(pNode)Vec_Ptr_t *Hop_ManDfsNode(Hop_Man_t *, Hop_Obj_t *)void Hop_ConeMark_rec(Hop_Obj_t *)void Hop_ConeCleanAndMark_rec(Hop_Obj_t *)int Hop_ConeCountAndMark_rec(Hop_Obj_t *)void Hop_ConeUnmark_rec(Hop_Obj_t *)int Hop_ObjFanoutCount_rec(Hop_Obj_t *, Hop_Obj_t *)!Hop_IsComplement(pPivot)int Hop_ObjFanoutCount(Hop_Obj_t *, Hop_Obj_t *)void Hop_Transfer_rec(Hop_Man_t *, Hop_Obj_t *)void Hop_Compose_rec(Hop_Man_t *, Hop_Obj_t *, Hop_Obj_t *, Hop_Obj_t *)Hop_Compose(): The PI variable %d is not defined. void Hop_Complement_rec(Hop_Man_t *, Hop_Obj_t *, Hop_Obj_t *)Hop_Complement(): The PI variable %d is not defined. void Hop_Remap_rec(Hop_Man_t *, Hop_Obj_t *)Hop_Remap(): The number of variables (%d) is more than the manager size (%d). k > 0 && k < nVarsHop_Obj_t *Hop_Remap(Hop_Man_t *, Hop_Obj_t *, unsigned int, int)pPermute[i] >= 0 && pPermute[i] < Hop_ManPiNum(p)Hop_Obj_t *Hop_Permute(Hop_Man_t *, Hop_Obj_t *, int, int *)src/aig/hop/hopMan.cvoid Hop_ManStop(Hop_Man_t *)p->fRefCountint Hop_ManCleanup(Hop_Man_t *)PI/PO = %d/%d. X = %5d. Cre = %7d. Del = %7d. Hop_Obj_t *Hop_ManFetchMemory(Hop_Man_t *)src/aig/hop/hopMem.cvoid Hop_ManAddMemory(Hop_Man_t *)!Hop_IsComplement(pGhost)src/aig/hop/hopObj.cHop_Obj_t *Hop_ObjCreate(Hop_Man_t *, Hop_Obj_t *)Hop_ObjIsNode(pGhost)pGhost == &p->Ghostvoid Hop_ObjConnect(Hop_Man_t *, Hop_Obj_t *, Hop_Obj_t *, Hop_Obj_t *)void Hop_ObjDisconnect(Hop_Man_t *, Hop_Obj_t *)void Hop_ObjDelete(Hop_Man_t *, Hop_Obj_t *)!Hop_ObjIsTerm(pObj)Hop_ObjRefs(pObj) == 0void Hop_ObjDelete_rec(Hop_Man_t *, Hop_Obj_t *)Hop_Obj_t *Hop_ObjRepr(Hop_Obj_t *)pOld != NULL && pNew != NULLvoid Hop_ObjCreateChoice(Hop_Obj_t *, Hop_Obj_t *)void Hop_ObjDeref(Hop_Obj_t *)i < Vec_PtrSize(p->vPis)src/aig/hop/hopOper.cHop_Obj_t *Hop_IthVar(Hop_Man_t *, int)Hop_Obj_t *Hop_Oper(Hop_Man_t *, Hop_Obj_t *, Hop_Obj_t *, Hop_Type_t)Type == AIG_AND || Type == AIG_EXORHop_Obj_t *Hop_Multi(Hop_Man_t *, Hop_Obj_t **, int, Hop_Type_t)Hop_Obj_t *Hop_Miter(Hop_Man_t *, Vec_Ptr_t *)src/aig/hop/hopTable.cHop_Obj_t *Hop_TableLookup(Hop_Man_t *, Hop_Obj_t *)Hop_ObjChild0(pGhost) && Hop_ObjChild1(pGhost)Hop_ObjFanin0(pGhost)->Id < Hop_ObjFanin1(pGhost)->Idvoid Hop_TableInsert(Hop_Man_t *, Hop_Obj_t *)Hop_TableLookup(p, pObj) == NULLvoid Hop_TableDelete(Hop_Man_t *, Hop_Obj_t *)Hop_ObjChild0(pObj) && Hop_ObjChild1(pObj)Hop_Obj_t **Hop_TableFind(Hop_Man_t *, Hop_Obj_t *)Hop_ObjFanin0(pObj)->Id < Hop_ObjFanin1(pObj)->Idvoid Hop_TableResize(Hop_Man_t *)Counter == nEntriessrc/aig/hop/hopTruth.cint Hop_ManConvertAigToTruth_rec1(Hop_Obj_t *)unsigned int *Hop_ManConvertAigToTruth_rec2(Hop_Obj_t *, Vec_Int_t *, int)nNodes == 0unsigned int *Hop_ManConvertAigToTruth(Hop_Man_t *, Hop_Obj_t *, int, Vec_Int_t *, int)nVars <= Hop_ManPiNum(p)word Hop_ManComputeTruth6_rec(Hop_Man_t *, Hop_Obj_t *)src/aig/hop/hopUtil.cvoid Hop_ObjCleanData_rec(Hop_Obj_t *)!Hop_ObjIsPo(pObj)void Hop_ObjCollectMulti(Hop_Obj_t *, Vec_Ptr_t *)int Hop_ObjIsMuxType(Hop_Obj_t *)int Hop_ObjRecognizeExor(Hop_Obj_t *, Hop_Obj_t **, Hop_Obj_t **)Hop_Obj_t *Hop_ObjRecognizeMux(Hop_Obj_t *, Hop_Obj_t **, Hop_Obj_t **)Hop_ObjIsMuxType(pNode)void Hop_ObjPrintVerbose(Hop_Obj_t *, int)Node %p : AND( %p%s, %p%s )# BLIF file written by procedure Hop_ManDumpBlif() in ABC # http://www.eecs.berkeley.edu/~alanmi/abc/ .names n%0*d n%0*d n%0*d .names n%0*d n%0*d Hop_ManDumpBlif(): AIG manager does not have POs.[[[[P\Y\b\k\\\\\]]]Z]]Z]]]]Z]Z]Z]]Z]]]]Z]]]h^^}}**** CUDD modifiable parameters **** Hard limit for cache size: %u Cache hit threshold for resizing: %u%% Garbage collection enabled: %s Limit for fast unique table growth: %u Maximum number of variables sifted per reordering: %d Maximum number of variable swaps per reordering: %d Maximum growth while sifting a variable: %g Dynamic reordering of BDDs enabled: %s Default BDD reordering method: %d Dynamic reordering of ZDDs enabled: %s Default ZDD reordering method: %d Realignment of ZDDs to BDDs enabled: %s Realignment of BDDs to ZDDs enabled: %s Dead nodes counted in triggering reordering: %s Group checking criterion: %d Recombination threshold: %d Symmetry violation threshold: %d Arc violation threshold: %d GA population size: %d Number of crossovers for GA: %d Next reordering threshold: %u **** CUDD non-modifiable parameters **** Memory in use: %lu Peak number of nodes: %ld Peak number of live nodes: %d Number of BDD variables: %d Number of ZDD variables: %d Number of cache entries: %u Number of cache look-ups: %.0f Number of cache hits: %.0f Number of cache insertions: %.0f Number of cache collisions: %.0f Number of cache deletions: %.0f Soft limit for cache size: %u Number of buckets in unique table: %u Used buckets in unique table: %.2f%% (expected %.2f%%) Number of BDD and ADD nodes: %u Number of ZDD nodes: %u Number of dead BDD and ADD nodes: %u Number of dead ZDD nodes: %u Total number of nodes allocated: %d Total number of nodes reclaimed: %.0f Garbage collections so far: %d Time for garbage collection: %.2f sec Reorderings so far: %d Time for reordering: %.2f sec %s reordering with converging randomsymmetric siftinglazy siftinggroup siftingannealinggeneticlinear sifting: from %ld to ... %ld nodes in %g sec Error: Can only abstract cubesError: Can only abstract cubesInvalid epsilon 333333?@ARQ?Unexpected condition in ddJumping AyPD#@%s%1de+%d.%u ??q,5Cannot subset, nil object Out-of-memory; Cannot subset Wrong prediction: %d versus actual %d savings == 0src/bdd/cudd/cuddApprox.cint UAmarkNodes(DdManager *, DdNode *, ApproxInfo *, int, int, double)Something is wrong, ought to be in info table int RAmarkNodes(DdManager *, DdNode *, ApproxInfo *, int, double)int BAmarkNodes(DdManager *, DdNode *, ApproxInfo *, int, double, double)Error: Can only abstract positive cubes ?((ptruint) unique->cache & (32 - 1)) == 0src/bdd/cudd/cuddCache.cint cuddInitCache(DdManager *, unsigned int, unsigned int)Cache used slots = %.2f%% (expected %.2f%%) ((ptruint) table->cache & (32 - 1)) == 0void cuddCacheResize(DdManager *)Permutation corrupted: invperm[%u] = %d perm[%d] = %d Error: node has illegal index Error: node has illegal children Error: node has illegal form Error: node has identical children Error: live node has dead children Error: node has illegal Then or Else pointers Error: wrong number of total nodes Error: wrong number of dead nodes Permutation corrupted: invpermZ[%u] = %d permZ[%d] = %d in ZDD Error: ZDD node has illegal index Error: ZDD node has complemented children Error: ZDD node has illegal children Error: ZDD node has zero then child Error: ZDD live node has dead children Error: ZDD node has illegal Then or Else pointers Error: wrong number of total nodes in ZDD Error: wrong number of dead nodes in ZDD node 0x%lx, id = %u, ref = %u, value = %g Error: wrong number of total nodes in constants Error: wrong number of dead nodes in constants ref count error at node 0x%lx, count = %d, id = %u, ref = %u, then = 0x%lx, else = 0x%lx Unique table %d is not the right power of 2 slots = %u shift = %d Wrong number of keys found in unique table %d (difference=%d) Wrong number of dead found in unique table no. %d (difference=%d) Wrong number of keys found in ZDD unique table no. %d (difference=%d) Wrong number of dead found in ZDD unique table no. %d (difference=%d) Wrong number of keys found in the constant table (difference=%d) Wrong number of dead found in the constant table (difference=%d) Wrong number of total keys found (difference=%d) Wrong number of total slots found (difference=%d) Wrong number of minimum dead found (%u vs. %u) Wrong number of total dead found (difference=%d) Average length of non-empty lists = %g *** DD heap profile for 0x%lx *** %5d: %5d nodes const: %5d nodes Summary: %d tables, %d non-empty, largest: %d (with %d nodes) node 0x%lx, id = %u, ref = %u, then = 0x%lx, else = 0x%lx root != NULLsrc/bdd/cudd/cuddCheck.cvoid cuddPrintVarGroups(DdManager *, MtrNode *, int, int)root->younger == NULL || root->younger->elder == rootroot->elder == NULL || root->elder->younger == rootnode->low >= root->low && (int) (node->low + node->size) <= (int) (root->low + root->size)node->parent == root(root->flags &~(MTR_TERMINAL | MTR_SOFT | MTR_FIXED | MTR_NEWNODE)) == 0parent is at 0x%lx, id = %u, ref = %u, then = 0x%lx, else = 0x%lx Cudd_Cofactor: Invalid restriction 1 Cudd_Cofactor: Invalid restriction 2 5u5I@\$*1d1st table insert failed Not in table, Something wrong Not in table: Something wrong pairValue != NONEsrc/bdd/cudd/cuddDecomp.cConjuncts *CheckTablesCacheAndReturn(DdNode *, DdNode *, DdNode *, st__table *, st__table *)%s%s | %s%s %s%d | %s%d !cuddIsConstant(F)src/bdd/cudd/cuddEssent.cDdTlcInfo *ddFindTwoLiteralClausesRecur(DdManager *, DdNode *, st__table *)cv == 0DdTlcInfo *computeClauses(DdTlcInfo *, DdTlcInfo *, DdHalfWord, int).model DD .inputs.model %s .inputs .outputs f%d.names %lx f%d .names %lx %s %s0 1 .def 0 %s1 1 digraph "DD" { size = "7.5,10" center = true; edge [dir = none]; { node [shape = plaintext]; "CONST NODES" [style = invis]; " %d " -> " %s " -> "CONST NODES"; } { rank = same; node [shape = box]; edge [style = invis]; "F%d"" %s "{ rank = same; " %d "; " %s "; { rank = same; "CONST NODES"; { node [shape = box]; } } -> "%lx" [style = solid]; "%lx" -> "%lx"; "%lx" -> "%lx" [style = dotted]; "%lx" -> "%lx" [style = dashed]; "%lx" [label = "%g"]; l("f%d",n("root",[a("OBJECT","f%d")],l("%s",n("root",[a("OBJECT","%s")],[e("edge",[a("EDGECOLOR","%s"),a("_DIR","none")],blue)]))%sv%df%d = .names %lx 1 .names %lx %s.names %s.names %u %lx %lx %lx .def 0 1 1 - 1 0 - 0 1 %lx %lx %lx .def 0 1 1 - 1 0 - 1 1 %lx %lx %lx 11- 1 0-0 1 %lx %lx %lx 11- 1 0-1 1 r("%p")l("%p",n("constant",[a("OBJECT","%g")],[]))l("%p",n("internal",[a("OBJECT","%s"),l("%p",n("internal",[a("OBJECT","%u"),a("_GO","ellipse")],[e("then",[a("EDGECOLOR","blue"),a("_DIR","none")],),e("else",[a("EDGECOLOR","%s"),a("_DIR","none")],green)]))n%p = %g n%p = %s * n%p + %s' * n%p%s n%p = v%u * n%p + v%u' * n%p%s !x%u%s%s((()$)w))(((((())o******Unknown group ckecking method %72c %8c%d %d %d %d %d%3s %d %d %d %d%*s %*s %*s %*s %s: type %s, %d rows, %d columns, %d entries %s: Illegal matrix type: %s %3c %d %d%s: Sparse right-hand side not yet supported %d right-hand side(s) %s: Unexpected colptr[0] (%d) %lf [@JO~[@JOUnable to set aside memory %ldtable->size == table->linearSizesrc/bdd/cudd/cuddLinear.cint Cudd_ReadLinear(DdManager *, int, int)Error: cuddLinearInPlace out of memory Change in size after identity transformation! From %d to %d AleftChild == index[0] || leftChild == index[1]src/bdd/cudd/cuddPriority.cDdNode *Cudd_Inequality(DdManager *, int, int, DdNode **, DdNode **)middleChild == index[0] || middleChild == index[1]rightChild == index[0] || rightChild == index[1]newIndex[0] == invalidIndex || newIndex[1] == invalidIndexDdNode *Cudd_Disequality(DdManager *, int, int, DdNode **, DdNode **)Error: The third argument of Cudd_CProjection should be a cube !Cudd_IsConstant(Y)DdNode *cuddCProjectionRecur(DdManager *, DdNode *, DdNode *, DdNode *)topf == topgDdNode *cuddBddClosestCube(DdManager *, DdNode *, DdNode *, double)!Cudd_IsConstant(cuddE(f)) || cuddE(f) == DD_ONE(dd)DdNode *separateCube(DdManager *, DdNode *, double *)!Cudd_IsConstant(t) || t == DD_ONE(dd)cuddI(dd,index) < cuddI(dd,cube->index)DdNode *createResult(DdManager *, unsigned int, unsigned int, DdNode *, double)%d %d %lfUnable to resize subtable %d for lack of memory Error: cuddSwapInPlace out of memory Offending nodes: f: address = %p value = %40.30f g: address = %p value = %40.30f We shouldn't be here!! We shouldn't be here! out-of-memory, couldn't measure DD cofactors. Cudd_SolveEqn: Out of memory for yIndex Cudd_SplitSet: out-of-memory. Something is wrong, ought to be node quality table Something wrong, st__table insert failed Something is wrong, ought to be in node quality table Something wrong, couldnt find nodes in node quality table This node should not be in the approximated table Cannot partition, nil object Something wrong, root node must be in table All computations are bogus, since root has path length greater than max path length within threshold %u, %u Something wrong, the entry exists but didnt show up in st__lookup Out of Memory and cant count path lengths Out of Memory, cannot allocate pages Something wrong, the entry doesn't exist Something wrong, node in table should have been created in top dist proc. Something wrong, both bot nodeStats should be there Path Length array seems to be all zeroes, check Something wrong, node must be in table Something wrong, node must be in table OUT of memory Out of memory Group: %dTotal Symmetric = %d Total Groups = %d [ypH[ypH_?@((ptruint) mem & (32 - 1)) == 0src/bdd/cudd/cuddTable.cDdNode *cuddAllocNode(DdManager *)cuddGarbageCollectUnable to resize constant subtable for lack of memory Slowing down table growth: GC fraction = %.2f minDead = %u i != CUDD_MAXINDEXvoid ddRehashZdd(DdManager *, int)Unable to resize ZDD subtable %d for lack of memory. %s: problem in constants %s: problem in table %d dead count != deleted This problem is often due to a missing call to Cudd_Ref or to an extra call to Cudd_RecursiveDeref. See the CUDD Programmer's Guide for additional details.9[_[O[9[: is the NULL DD : is the zero DD : %d nodes %d leaves %g minterms 2.4.2 unable to allocate %ld bytes retval == sizesrc/bdd/cudd/cuddUtil.cDdNodePtr *cuddNodeArray(DdNode *, int *)ID = %c0x%lx value = %-9g ID = %c0x%lx index = %u T = %-9g T = 0x%lx E = %c%-9g E = %c0x%lx % g ]bbdcccc hhgf'gflfgg'gflflfg'glflflflflflflflflflfpm&mlllKmnnnnncsr8tt#ss#ttQsss?sst tsnts.spsYtssCt2L#########}*** ERROR : illegal condition for ISOP (U < L).Error: cuddZddSwapInPlace out of memory subtable[%d]: ID = 0x%lx index = %u r = %u T = %d E = %d E = 0x%lx ZDD: is the empty ZDD : %d nodes %g minterms digraph "ZDD" { -> "%p" [style = solid]; "%p" -> "%p"; "%p" -> "%p" [style = dashed]; "%p" [label = "%g"]; ID = %d -0-?1?1?-0-iVarNonCan == -1src/bdd/extrab/extraBddAuto.cDdNode **Extra_bddSpaceExorGates(DdManager *, DdNode *, DdNode *)iVarNonCan != -1Cannot derive linear space, because DD manager does not have enough variables.nVars >= Abc_Base2Log(nFuncs)src/bdd/extrab/extraBddCas.cDdNode *Extra_bddEncodingBinary(DdManager *, DdNode **, int, DdNode **, int)nMulti < 32DdNode *Extra_bddEncodingNonStrict(DdManager *, DdNode **, int, DdNode *, DdNode **, int, int *)int Extra_bddNodePathsUnderCutArray(DdManager *, DdNode **, DdNode **, int, DdNode **, DdNode **, int)unsigned int Extra_CountCofactorMinterms(DdManager *, DdNode *, DdNode *, DdNode *)!( LevelTop == LevelF || LevelTop == LevelC ) || LevelTop == LevelAnCols == 1DdNode *CreateTheCodes_rec(DdManager *, DdNode *, int, DdNode **)void CountNodeVisits_rec(DdManager *, DdNode *, st__table *)p->nEdges > 0void CollectNodesAndComputePaths_rec(DdManager *, DdNode *, DdNode *, st__table *, st__table *)ļBpVars[v] == NULLsrc/bdd/extrab/extraBddImage.cExtra_ImageTree_t *Extra_bddImageStart(DdManager *, DdNode *, int, DdNode **, int, DdNode **, int)pNodes[v] == NULLOriginal care set support: pTree->bCareSuppCurrent care set support: bSupppVars[v]->nParts > 0Extra_ImageNode_t **Extra_CreateNodes(DdManager *, int, Extra_ImagePart_t **, int, Extra_ImageVar_t **)pNode->pPart == NULLvoid Extra_bddImageTreeDelete_rec(Extra_ImageNode_t *)nSupp == pVar->nPartsint Extra_BuildTreeNode(DdManager *, int, Extra_ImageNode_t **, int, Extra_ImageVar_t **)nSupp != 1Cudd_bddLeq( dd, pVar->bParts, dd->vars[iNode2] )n1 != -1Extra_ImageNode_t *Extra_MergeTopNodes(DdManager *, int, Extra_ImageNode_t **)Partitions = %d Variables: total = %d non-quantifiable = %d The latch dependency matrix:The care set depends on some vars that were not in the care set during scheduling.PrintKMap(): The on-set and the off-set overlap Function is constant %d. Truth table: 1-var functionPrintKMap(): The number of variables is less than zero or more than %d src/bdd/extrab/extraBddKmap.cvoid Extra_PrintKMap(FILE *, DdManager *, DdNode *, DdNode *, int, DdNode **, int, char **)PrintKMap(): The number of variables is more than %d \ PrintKMap(): Constant 1 PrintKMap(): Constant 0 void Extra_PrintKMapRelation(FILE *, DdManager *, DdNode *, DdNode *, int, int, DdNode **, DdNode **)4@nVars <= dd->sizesrc/bdd/extrab/extraBddMisc.cDdNode *Extra_bddMove(DdManager *, DdNode *, int) The number of referenced nodes = %d Constant 0Constant 1!Cudd_IsComplement(bSupp)int Extra_bddSuppSize(DdManager *, DdNode *)cuddE(bSupp) == b0!fHcontainsL || !fLcontainsHint Extra_bddSuppCheckContainment(DdManager *, DdNode *, DdNode *, DdNode **, DdNode **)bRes1 != b0DdNode *Extra_bddGetOneCube(DdManager *, DdNode *)iStart <= iStopDdNode *Extra_bddComputeRangeCube(DdManager *, int, int)iStart >= 0 && iStart <= dd->sizeiStop >= 0 && iStop <= dd->size(Cudd_IsComplement(bCube0) && Cudd_Regular(bCube0)->index == CUDD_CONST_INDEX) || (Cudd_IsComplement(bCube1) && Cudd_Regular(bCube1)->index == CUDD_CONST_INDEX)int Extra_bddVarIsInCube(DdNode *, int)VarNew < dd->sizeDdNode *extraBddMove(DdManager *, DdNode *, DdNode *)Runtime of Cudd_bddAnd Runtime of new procedureRecursive calls = %d |F| =%6d |G| =%6d |H| =%6d |F|*|G| =%9d # PLA file dumped by Extra_zddDumpPla() in ABC N = %5d K = %5d BddSize = %6d MemBdd = %8.3f MB MemBit = %8.3f MB Ratio = %8.3f %% DdNode *extraBddCountCubes(DdManager *, DdNode *, DdNode *, st__table *, int *, int)Lev < ddF->sizeDdNode *extraBddAndPermute(DdHashTable *, DdManager *, DdNode *, DdManager *, DdNode *, int *) Reordering in Extra_zddPrimes()Result is incorrect. Result verified. cuddT(zS) != z0src/bdd/extrab/extraBddSet.cint Extra_zddIsOneSubset(DdManager *, DdNode *)cuddT( cuddT(zCube) ) == z1src/bdd/extrab/extraBddSymm.cExtra_SymmInfo_t *Extra_SymmPairsCreateFromZdd(DdManager *, DdNode *, DdNode *)iVar1 != iVar2int Extra_bddCheckVarsSymmetric(DdManager *, DdNode *, int, int)iVar1 < dd->sizeiVar2 < dd->sizeint Extra_bddCheckVarsSymmetricNaive(DdManager *, DdNode *, int, int)bVars != b1DdNode *extraZddSymmPairsCompute(DdManager *, DdNode *, DdNode *)bFR->index == bVarsNew->indexDdNode *extraZddGetSymmetricVars(DdManager *, DdNode *, DdNode *, DdNode *)LevelFG < dd->sizeLevelFG == dd->perm[bVarsNew->index]LevelFG > dd->perm[bVars->index]DdNode *extraBddCheckVarsSymmetric(DdManager *, DdNode *, DdNode *)cuddT(bVarsR) == b1cuddT(cuddT(bVars)) == b1bRes0 != z0bRes != z0zS1 != z0DdNode *extraZddSelectOneSubset(DdManager *, DdNode *)555556""""""""DDDDDDDD 00000000UUUUUUUU33333333nVars == 3src/bdd/extrab/extraBddThresh.cint Extra_ThreshSelectWeights3(word *, int, int *)int Extra_ThreshSelectWeights4(word *, int, int *)int Extra_ThreshSelectWeights5(word *, int, int *)int Extra_ThreshSelectWeights6(word *, int, int *)int Extra_ThreshSelectWeights7(word *, int, int *)int Extra_ThreshSelectWeights8(word *, int, int *) Inequality [%d] = %ld > Heuristic method: is not TLF Heuristic method: Weights and threshold value: Abc_TtPosVar(t, nVars, i)void Abc_TtMakePosUnate(word *, int)No thresholdcuddT(zCube) == z1 && cuddE(zCube) == z0src/bdd/extrab/extraBddUnate.cExtra_UnateInfo_t *Extra_UnateInfoCreateFromZdd(DdManager *, DdNode *, DdNode *)iVar < dd->sizeint Extra_bddCheckUnateNaive(DdManager *, DdNode *, int)DdNode *extraZddUnateInfoCompute(DdManager *, DdNode *, DdNode *)bC1 != b0src/bdd/dsd/dsdCheck.cint Dsd_CheckRootFunctionIdentity_rec(DdManager *, DdNode *, DdNode *, DdNode *, DdNode *)bC2 != b0bC != b0src/bdd/dsd/dsdLocal.cDdNode *Extra_bddNodePointedByCube(DdManager *, DdNode *, DdNode *)!cuddIsConstant( bFR )bC0 == b0 || bC1 == b0nSuppMax <= dd->sizesrc/bdd/dsd/dsdMan.cDsd_Manager_t *Dsd_ManagerStart(DdManager *, int, int)#%02d: Ins=%2d. Gts=%3d. Pri=%3d. Max=%3d. Reuse=%2d. Csc=%2d. T= %.2f s. Bdd=%2d. pDsdMan->nRoots == nFuncssrc/bdd/dsd/dsdProc.cvoid Dsd_Decompose(Dsd_Manager_t *, DdNode **, int) Total outputs = %5d Decomposable outputs = %5d Completely decomposable outputs = %5d The sum of max gate sizes = %5d Shared BDD size = %5d Decomposition entries = %5d Pure decomposition time = %.2f sec Dsd_Node_t *dsdKernelDecompose_rec(Dsd_Manager_t *, DdNode *)pLR->Type == DSD_NODE_BUF || pLR->Type == DSD_NODE_OR || pLR->Type == DSD_NODE_EXOR || pLR->Type == DSD_NODE_PRIMEpHR->Type == DSD_NODE_BUF || pHR->Type == DSD_NODE_OR || pHR->Type == DSD_NODE_EXOR || pHR->Type == DSD_NODE_PRIMEfComp2 == 0!Dsd_IsComplement(pDENew)pLastDiffL == pLastDiffHnCommon == pLR->nDecs-1pLastDiffLTopLevel != CUDD_CONST_INDEXnNonOverlap > 0Dsd_Regular(pNonOverlap[0]) == pCurExtra_bddSuppContainVar( dd, pLR->S, bVarTop )Extra_bddSuppContainVar( dd, pHR->S, bVarTop )pCurHnEntries <= nEntriesMaxpThisR->G == NULLpThisR->S == NULLbSuppNewnListSize+1 == p->nDecsvoid dsdKernelCopyListPlusOne(Dsd_Node_t *, Dsd_Node_t *, Dsd_Node_t **, int)nListSize == p->nDecsvoid dsdKernelCopyListPlusOneMinusOne(Dsd_Node_t *, Dsd_Node_t *, Dsd_Node_t **, int, int)nCommon > 0void dsdKernelComputeSumOfComponents(Dsd_Manager_t *, Dsd_Node_t **, int, DdNode **, DdNode **, int)Dsd_Node_t *dsdKernelFindContainingComponent(Dsd_Manager_t *, Dsd_Node_t *, DdNode *, int *)The cumulative decomposability statistics: Decomposability statistics for individual outputs:R˼rir,Tsrc/bdd/dsd/dsdTree.cint Dsd_TreeGetAigCost_rec(Dsd_Node_t *)!Dsd_IsComplement( pNode )pNode->nVisits >= 0nNodesAlloc == nNodesDsd_Node_t **Dsd_TreeCollectNodesDfs(Dsd_Manager_t *, int *)Dsd_Node_t **Dsd_TreeCollectNodesDfsOne(Dsd_Manager_t *, Dsd_Node_t *, int *)Output >= 0 && Output < pDsdMan->nRootsvoid Dsd_TreePrint(FILE *, Dsd_Manager_t *, char **, char **, int, int)Level >= 0 && Level < 6word Dsd_TreeFunc2Truth_rec(DdManager *, DdNode *)Const%dpNode->Type == DSD_NODE_BUF || pNode->Type == DSD_NODE_PRIME || pNode->Type == DSD_NODE_OR || pNode->Type == DSD_NODE_EXORvoid Dsd_TreePrint2_rec(FILE *, DdManager *, Dsd_Node_t *, int, char **)|%d|%8s = void Dsd_TreePrint2(FILE *, Dsd_Manager_t *, char **, char **, int)DdNode *Dsd_TreeGetPrimeFunctionOld(DdManager *, Dsd_Node_t *, int)pNode->Type == DSD_NODE_PRIMEvoid Dsd_TreeUnmark_rec(Dsd_Node_t *)pNode->nVisits > 0void Dsd_TreeGetInfo_rec(Dsd_Node_t *, int)int Dsd_TreeCountNonTerminalNodes_rec(Dsd_Node_t *)int Dsd_TreeCountPrimeNodes_rec(Dsd_Node_t *)int Dsd_TreeCollectDecomposableVars_rec(DdManager *, Dsd_Node_t *, int *, int *)void Dsd_TreeCollectNodesDfs_rec(Dsd_Node_t *, Dsd_Node_t **, int *)!Dsd_IsComplement(pNode)pNode->Type == DSD_NODE_BUF || pNode->Type == DSD_NODE_CONST1 || pNode->Type == DSD_NODE_PRIME || pNode->Type == DSD_NODE_OR || pNode->Type == DSD_NODE_EXORvoid Dsd_TreePrint_rec(FILE *, Dsd_Node_t *, int, char **, char *, int, int *, int)NOT(%s) = Constant 1. PRIME(void Dsd_NodePrint_rec(FILE *, Dsd_Node_t *, int, char *, int, int *)fCompNew == 0 <%d>-Infepd->type.bits.exponent == EPD_MAX_BIN || epd->type.bits.exponent == 0src/bdd/epd/epd.cvoid EpdGetString(EpDouble *, char *)%e+0%d-0%depd1->type.bits.exponent == EPD_MAX_BINvoid EpdMultiply(EpDouble *, double)void EpdMultiply2(EpDouble *, EpDouble *)epd2->type.bits.exponent == EPD_MAX_BINvoid EpdMultiply3(EpDouble *, EpDouble *, EpDouble *)void EpdDivide(EpDouble *, double)void EpdDivide2(EpDouble *, EpDouble *)void EpdDivide3(EpDouble *, EpDouble *, EpDouble *)void EpdAdd(EpDouble *, double)void EpdAdd2(EpDouble *, EpDouble *)void EpdAdd3(EpDouble *, EpDouble *, EpDouble *)void EpdSubtract(EpDouble *, double)void EpdSubtract2(EpDouble *, EpDouble *)void EpdSubtract3(EpDouble *, EpDouble *, EpDouble *)%EE%dN=0x%-8lx C=0x%-8lx Y=0x%-8lx E=0x%-8lx P=0x%-8lx F=%x L=%u S=%u P27<Asrc/bdd/mtr/mtrGroup.cvoid Mtr_PrintGroups(MtrNode *, int)(%u%d %d %ssrc/bdd/reo/reoApi.cvoid Extra_ReorderSetMinimizationType(reo_man *, reo_min_type)p->nNodesBeg == p->nNodesCursrc/bdd/reo/reoCore.cvoid reoReorderArray(reo_man *, DdManager *, DdNode **, DdNode **, int, int *)ITER #%d: p->nWidthEnd <= p->nWidthBegp->nAplEnd <= p->nAplBegp->nNodesEnd <= p->nNodesBegint reoCheckZeroRefs(reo_plane *)p->pPlanes[i].statsNodesint reoCheckLevels(reo_man *)pUnit->lev == iINITIAL:REO: Internal verification is okay!REO: Internal verification has failed!An important message from the REO reordering engine:The BDD given to the engine for reordering contains complemented edges.Currently, such BDDs cannot be reordered for the minimum width.Therefore, minimization for the number of BDD nodes is performed.Total == p->nNodesCursrc/bdd/reo/reoProfile.cvoid reoProfileNodesStart(reo_man *)Level %2d: Width = %5d. NODES: Total = %6d. Average = %6.2f. APL: Total = %8.2f. Average =%6.2f. Level = %2d. Width = %3d. p->nWidthCur == TotalWidthvoid reoProfileWidthPrint(reo_man *)WIDTH: Maximum = %5d. Total = %7d. pUnit->TopRef <= Levelvoid reoProfileWidthVerifyLevel(reo_plane *, int)pUnit->pE->TopRef <= Level + 1pUnit->pT->TopRef <= Level + 1p->pOrderInt[i] == pPerm[i]src/bdd/reo/reoShuffle.cDdNode *reoShuffle(reo_man *, DdManager *, DdNode *, int *, int *)dd->size < 1000void Extra_ShuffleTest(reo_man *, DdManager *, DdNode *)reoShuffle() Error: BDD size is too large.reoShuffle() Error: Cannot find a variable.ffffff?cAHz>p->nSupp > 0src/bdd/reo/reoSift.cvoid reoReorderSift(reo_man *)VarCurrent != -1CostCurrent == p->pPlanes[VarCurrent].statsCostAbove + p->pPlanes[VarCurrent].statsCost + p->pPlanes[VarCurrent].statsCostBelowq >= BestQq <= BestQfabs( CostBest - CostCurrent ) < REO_COST_EPSILONreoReorderSift(): Error! On the return move, the costs are different.reoReorderSift(): Error! On the return move, the costs are different.reoReorderSift(): Error! On the backward move, the costs are different.lev0 >= 0 && lev1 < p->nSuppsrc/bdd/reo/reoSwap.cdouble reoReorderSwapAdjacentVars(reo_man *, int, int)p->pPlanes[lev0].statsNodes && p->pPlanes[lev1].statsNodespListOld0 && pListOld1pUnitER->TopRef == lev1pUnitT->TopRef == lev1p->HTable[HKey].Sign != p->SignaturepNewPlane20->lev == lev1pNew1ER->TopRefNew == lev1 || pNew1ER->TopRefNew == lev2pNew1T->TopRefNew == lev1 || pNew1T->TopRefNew == lev2!Cudd_IsComplement(pNew2T)pNewPlane21->lev == lev1pNew2ER->TopRefNew == lev1 || pNew2ER->TopRefNew == lev2pNew2T->TopRefNew == lev1 || pNew2T->TopRefNew == lev2!Cudd_IsComplement(pNewPlane21)pUnit->lev == lev0!p->fMinApl || pUnit->Weight > 0.0!p->fMinApl || pUnit->Weight == 0.0pUnitsrc/bdd/reo/reoTransfer.creo_unit *reoTransferNodesToUnits_rec(reo_man *, DdNode *)bResDdNode *reoTransferUnitsToNodes_rec(reo_man *, reo_unit *)E != T!Cudd_IsComplement(T)reoUnitsAddToFreeUnitList(): Memory manager ran out of memory!_ENC.blif_LUT.blifpi%03dOutEnc_%02dMTBDD reordered = %6d nodes Variable reordering time = %.2f sec cec %s %sSingle BDD size = %6d nodes MTBDD = %6d nodes .outputs F.names %s%lx %s .names %s%lx InputNames[Node->index]src/bdd/cas/casCore.cvoid WriteDDintoBLIFfile(FILE *, DdNode *, char *, char *, char **).names %s %s%lx %s%lx %s%lx .names %s %s%lx_i %s%lx %s%lx .names %s%lx %s%lx_i Nodes before = %d. Nodes after = %d. void WriteDDintoBLIFfileReorder(DdManager *, FILE *, DdNode *, char *, char *, char **)RetValue == p->nColssrc/bdd/cas/casDec.cint CreateDecomposedNetwork(DdManager *, DdNode *, char **, int, char *, int, int, int)p->nMulti == 1p->nCols == 2Cudd_IsConstant( p->paNodes[0] )Cudd_IsConstant( p->paNodes[1] )Stage %3d: In = %3d InP = %3d Cols = %5d Multi = %2d Simple = %2d Level = %3d LUTs: Total = %5d. Final = %5d. Simple = %5d. (%6.2f %%) Memory = %6.2f MB Pure decomposition time = %.2f sec Encoding time = %.2f sec Output file writing time = %.2f sec void WriteLUTSintoBLIFfile(FILE *, DdManager *, LUT **, int, DdNode **, char **, int, char *)#----------------- LUT #%d ---------------------- LUT%02d_%02dL%02d_L%02d_%02d_The LUT size is too smallBDDs blew up during qualitification scheduling. src/bdd/bbr/bbrCex.cAbc_Cex_t *Aig_ManVerifyUsingBddsCountExample(Aig_Man_t *, DdManager *, DdNode **, Vec_Ptr_t *, DdNode *, int, int, int)BDDs blew up during image computation. pValues[Saig_ManPiNum(p)+i] == 0Counter-example generation timeAig_ManVerifyUsingBdds(): Counter-example verification has FAILED.src/bdd/bbr/bbrImage.cBbr_ImageTree_t *Bbr_bddImageStart(DdManager *, DdNode *, int, DdNode **, int, DdNode **, int, int)Bbr_ImageNode_t **Bbr_CreateNodes(DdManager *, int, Bbr_ImagePart_t **, int, Bbr_ImageVar_t **)void Bbr_bddImageTreeDelete_rec(Bbr_ImageNode_t *)int Bbr_BuildTreeNode(DdManager *, int, Bbr_ImageNode_t **, int, Bbr_ImageVar_t **, int *, int)pVars[v]->nParts > 1int Bbr_FindBestVariable(DdManager *, int, Bbr_ImageNode_t **, int, Bbr_ImageVar_t **)Bbr_ImageNode_t *Bbr_MergeTopNodes(DdManager *, int, Bbr_ImageNode_t **)src/bdd/bbr/bbrNtbdd.cDdNode *Bbr_NodeGlobalBdds_rec(DdManager *, Aig_Obj_t *, int, int, ProgressBar *, int *, int)Aig_ObjGlobalBdd(pNode) == NULLPsrc/bdd/bbr/bbrReach.cDdNode *Bbr_bddComputeRangeCube(DdManager *, int, int)dd->size == Saig_ManCiNum(p)DdNode **Aig_ManCreatePartitions(DdManager *, Aig_Man_t *, int, int)Reached timeout after image computation (%d seconds). p->pSeqModel == NULLint Aig_ManComputeReachable(DdManager *, Aig_Man_t *, DdNode **, DdNode *, DdNode **, Saig_ParBbr_t *, int)Frame = %3d. BDD = %5d. Reachability analysis is stopped after %d frames. Reachability analysis completed after %d frames. The miter is proved unreachable after %d iterations. nIters >= pPars->nIterMax || nBddSize >= pPars->nBddMaxVerified only for states reachable in %d frames. int Aig_ManVerifyUsingBdds_int(Aig_Man_t *, Saig_ParBbr_t *)Reached timeout after constructing global BDDs (%d seconds). Aig_ManCiNum(p) < Aig_ManCiNum(pInit)int Aig_ManVerifyUsingBdds(Aig_Man_t *, Saig_ParBbr_t *)Aig_ManRegNum(p) == Aig_ManRegNum(pInit)pCexOld != NULLiBitOld < iBitNewiBitOld == pCexOld->nBitsiBitNew == pCexNew->nBitsPiGrp1 >= 1 && iGrp1 < p->nCols - 1src/bdd/llb/llb1Cluster.cvoid Llb_MtrCombineSelectedColumns(Llb_Mtr_t *, int, int)iGrp2 >= 1 && iGrp2 < p->nCols - 1p->pColGrps[iGrp1] != NULLp->pColGrps[iGrp2] != NULLp->pColSums[i] == 0void Llb_ManClusterCompress(Llb_Mtr_t *)p->pMatrix[i] != NULL *** Using %d hint%s: src/bdd/llb/llb1Constr.cDdNode *Llb_ManComputeIndCase_rec(Aig_Man_t *, Aig_Obj_t *, DdManager *, Vec_Ptr_t *)The AIG has %d property outputs. There is no hints.dpi =%3d po =%3d ff =%3d int =%5d var =%5d part =%5d and =%5d lev =%4d vHints == NULLsrc/bdd/llb/llb1Core.cint Llb_ManModelCheckAig(Aig_Man_t *, Gia_ParLlb_t *, Vec_Int_t *, DdManager **)Original matrix: Matrix after clustering: Matrix after scheduling: src/bdd/llb/llb1Group.cvoid Llb_ManGroupCollect_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)void Llb_ManGroupCreate_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)Llb_Grp_t *Llb_ManGroupCreate(Llb_Man_t *, Aig_Obj_t *)p->vNodes == NULLLlb_Grp_t *Llb_ManGroupsCombine(Llb_Grp_t *, Llb_Grp_t *)void Llb_ManGroupMarkNodes_rec(Aig_Man_t *, Aig_Obj_t *)Llb_Grp_t *Llb_ManGroupCreateFromCuts(Llb_Man_t *, Vec_Int_t *, Vec_Int_t *)pMan->vGroups == NULLvoid Llb_ManPrepareGroups(Llb_Man_t *)iInput >= 0src/bdd/llb/llb1Hint.cint Llb_ManMaxFanoutCi(Aig_Man_t *)%d %3d Vec_IntSize(vResult) >= nCandMaxVec_Int_t *Llb_ManCollectHighFanoutObjects(Aig_Man_t *, int, int)pPars->nHintDepth > 0int Llb_ManModelCheckAigWithHints(Aig_Man_t *, Gia_ParLlb_t *)p->vNs2Glo == NULLsrc/bdd/llb/llb1Man.cvoid Llb_ManPrepareVarMap(Llb_Man_t *)p->vCs2Glo == NULLp->vGlo2Cs == NULLp->vGlo2Ns == NULLiVarLi >= 0 && iVarLi < Vec_IntSize(p->vVar2Obj)iVarLo >= 0 && iVarLo < Vec_IntSize(p->vVar2Obj)p->vVarBegs == NULLvoid Llb_ManPrepareVarLimits(Llb_Man_t *)p->vVarEnds == NULLCounter == p->pColSums[iCol]src/bdd/llb/llb1Matrix.cvoid Llb_MtrVerifyRowsAll(Llb_Mtr_t *)Counter == p->pRowSums[iRow]void Llb_MtrVerifyColumnsAll(Llb_Mtr_t *)%3s iGrp1 <= iGrp2void Llb_MtrPrintMatrixStats(Llb_Mtr_t *)[%4d x %4d] Life-span =%6.2f Max-cut =%5d Cut size is not zero (%d). iCol >= 0 && iCol < p->nColsvoid Llb_MtrAddColumn(Llb_Mtr_t *, Llb_Grp_t *)iRow >= 0 && iRow < p->nRowsAig_ObjIsCand(pObj)src/bdd/llb/llb1Pivot.cint Llb_ManTracePaths_rec(Aig_Man_t *, Aig_Obj_t *, Aig_Obj_t *)Obj =%5d. Lev =%3d. Fanout =%5d. Count = %3d. void Llb_ManLabelLiCones_rec(Aig_Man_t *, Aig_Obj_t *)src/bdd/llb/llb1Reach.cDdNode *Llb_ManConstructOutBdd(Aig_Man_t *, Aig_Obj_t *, DdManager *)iGroupFirst <= iGroupLastDdNode *Llb_ManConstructQuantCubeIntern(Llb_Man_t *, Llb_Grp_t *, int, int)iGroupLast >= iGrpPlaceDdNode *Llb_ManConstructQuantCubeFwd(Llb_Man_t *, Llb_Grp_t *, int)iGroupFirst <= iGrpPlaceDdNode *Llb_ManConstructQuantCubeBwd(Llb_Man_t *, Llb_Grp_t *, int)Aig_ManCiNum(p->pAig) == Aig_ManCiNum(p->pAigGlo)DdNode *Llb_ManCreateConstraints(Llb_Man_t *, Vec_Int_t *, int)Vec_PtrSize(p->vRings) > 0Abc_Cex_t *Llb_ManReachDeriveCex(Llb_Man_t *)bImage != NULLpValues[i] == 0nPiOffset == Saig_ManRegNum(p->pAig)RetValue >= 0 && RetValue < Saig_ManPoNum(p->pAigGlo)p->dd == NULLint Llb_ManReachability(Llb_Man_t *, Vec_Int_t *, DdManager **)p->ddG == NULLp->ddR == NULLReached timeout (%d seconds) during constructing the bad states. Reached timeout during image computation (%d seconds). Reached timeout (%d seconds) during ring transfer. p->pAigGlo->pSeqModel == NULLOutput ??? of miter "%s" was asserted in frame %d (counter-example is not produced). Reached timeout (%d seconds) during image computation. Reached timeout (%d seconds) during image computation in transfer 1. Reached timeout (%d seconds) during image computation in transfer 2. F =%5d : Im =%6d (%4d %3d) Rea =%6d (%4d%4d) p->ddG->bFunc == NULL*pddGlo == NULLiCol1 >= 0 && iCol1 < p->nColssrc/bdd/llb/llb1Sched.cvoid Llb_MtrSwapColumns(Llb_Mtr_t *, int, int)iCol2 >= 0 && iCol2 < p->nColsCounter == 1int Llb_MtrFindBestColumn(Llb_Mtr_t *, int)iCol >= 1 && iCol < p->nCols - 1void Llb_MtrUseSelectedColumn(Llb_Mtr_t *, int)p->pProdNums[iVar] >= 0Counter == p->pProdNums[iVar]void Llb_MtrVerifyColumns(Llb_Mtr_t *, int)Cudd_ReadSize(dd) == Aig_ManCiNum(pInit)src/bdd/llb/llb2Bad.cDdNode *Llb_BddComputeBad(Aig_Man_t *, DdManager *, abctime)DdNode *Llb_BddQuantifyPis(Aig_Man_t *, DdManager *, DdNode *)src/bdd/llb/llb2Core.cAbc_Cex_t *Llb_CoreDeriveCex(Llb_Img_t *)RetValue >= 0 && RetValue < Saig_ManPoNum(p->pInit)Reached timeout (%d seconds) before image computation. Reached timeout (%d seconds) while computing bad states. Reached timeout (%d seconds) during transfer 0. p->pInit->pSeqModel == NULLint Llb_CoreReachability_int(Llb_Img_t *, Vec_Ptr_t *, Vec_Ptr_t *)Output ??? was asserted in frame %d (counter-example is not produced). Reachable states = %.0f. (Ratio = %.4f %%) F =%3d : Image =%6d (%4d%4d) Reach =%6d reached.blifReached states with %d BDD nodes are dumpted into file "reached.blif". p->vVarsCs != NULLvoid Llb_CoreSetVarMaps(Llb_Img_t *)p->vVarsNs != NULLiVarCs >= 0 && iVarCs < Aig_ManObjNumMax(p->pAig)iVarNs >= 0 && iVarNs < Aig_ManObjNumMax(p->pAig)Reached timeout (%d seconds) while deriving the partitions. Reached timeout (%d seconds) after partitioning. Total runtime of the min-cut-based reachability engineVec_IntEntry( vDriRefs, Aig_ObjFaninId0(pObj) ) >= 1src/bdd/llb/llb2Driver.cDdNode *Llb_DriverPhaseCube(Aig_Man_t *, Vec_Int_t *, DdManager *)@BVec_PtrSize(vSupps) == Vec_PtrSize(vResult)src/bdd/llb/llb2Flow.cVec_Ptr_t *Llb_ManCutSupps(Aig_Man_t *, Vec_Ptr_t *)Vec_PtrSize(vMaps) == Vec_PtrSize(vResult)+1Vec_Ptr_t *Llb_ManCutMap(Aig_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *)lo int Llb_ManCutLiNum(Aig_Man_t *, Vec_Ptr_t *)int Llb_ManCutVolume_rec(Aig_Man_t *, Aig_Obj_t *)void Llb_ManCutNodes_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)Vec_Ptr_t *Llb_ManCutSupp(Aig_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *)Leaf: %3d=%3d+%3d+%3d Root: %3d=%3d+%3d+%3d Supp: %3d=%3d+%3d+%3d Range: %3d=%3d+%3d+%3d S =%3d. V =%3d. Aig_ObjIsNode(pObj) || Aig_ObjIsCi(pObj) || Aig_ObjIsConst1(pObj)int Llb_ManFlowBwdPath2_rec(Aig_Man_t *, Aig_Obj_t *)void Llb_ManFlowLabelTfi_rec(Aig_Man_t *, Aig_Obj_t *)int Llb_ManFlowVerifyCut_rec(Aig_Man_t *, Aig_Obj_t *)!pObj->fMarkA && pObj->fMarkBVec_Ptr_t *Llb_ManFlow(Aig_Man_t *, Vec_Ptr_t *, int *)Vec_PtrSize(vMinCut) == FlowVec_Ptr_t *Llb_ManFlowCompute(Aig_Man_t *)void Llb_ManFlowCleanMarkB_rec(Aig_Obj_t *)void Llb_ManFlowSetMarkA_rec(Aig_Obj_t *)void Llb_ManFlowPrepareCut(Aig_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *)void Llb_ManFlowUnmarkCone(Aig_Man_t *, Vec_Ptr_t *)pObj->fMarkB == 1void Llb_ManFlowCollectAndMarkCone_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)void Llb_ManFlowCollectAndMarkCone(Aig_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *)Saig_ManPoNum(p) == 0Vec_Ptr_t *Llb_ManComputeCutLi(Aig_Man_t *)Vol > nVolMinVec_Ptr_t *Llb_ManFlowFindBestCut(Aig_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *, int)Finished computing %d partitions. Aig_Obj_t *Llb_ObjGetFanoutPath(Aig_Man_t *, Aig_Obj_t *)Llb_ManFlow() error! The computed min-cut is not a cut!Could not break the cut.nSize == Aig_ManObjNumMax(p)src/bdd/llb/llb2Image.cVec_Ptr_t *Llb_ImgSupports(Aig_Man_t *, Vec_Ptr_t *, Vec_Int_t *, Vec_Int_t *, int, int)li %2d : Quant0 = %2d : Quant1 = DdManager *Llb_ImgPartition(Aig_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *, abctime)dd->bFunc2 == NULLvoid Llb_ImgQuantifyFirst(Aig_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *, int)Part %2d : Init =%5d. Quant =%5d. Reo = %5d. Reo = %5d. Supp = %3d. dd->bFunc2 != NULLvoid Llb_ImgQuantifyReset(Vec_Ptr_t *) %2d : Pt0 =%6d. Pt1 =%6d. Im0 =%6d. Im1 =%6d. Supp =%3d. Reordering... Before =%5d. After =%5d. p->pVars[pVar->iVar] == pVarsrc/bdd/llb/llb3Image.cvoid Llb_NonlinRemoveVar(Llb_Mgr_t *, Llb_Var_t *)p->pParts[pPart->iPart] == pPartvoid Llb_NonlinRemovePart(Llb_Mgr_t *, Llb_Prt_t *)Vec_IntSize(pVar->vParts) > 0DdNode *Llb_NonlinCreateCube1(Llb_Mgr_t *, Llb_Prt_t *)Vec_IntEntry(pVar->vParts, 0) == pPart->iPartDdNode *Llb_NonlinCreateCube2(Llb_Mgr_t *, Llb_Prt_t *, Llb_Prt_t *)Var %3d : Part %3d : Subsetting %3d : (Supp =%3d Node =%5d) -> (Supp =%3d Node =%5d) Vec_IntSize(pVar->vParts) > 1int Llb_NonlinQuantify1(Llb_Mgr_t *, Llb_Prt_t *, int)int Llb_NonlinQuantify2(Llb_Mgr_t *, Llb_Prt_t *, Llb_Prt_t *)void Llb_NonlinCutNodes_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)Vec_Ptr_t *Llb_NonlinBuildBdds(Aig_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *, DdManager *)!Cudd_IsConstant(bFunc)void Llb_NonlinAddPartition(Llb_Mgr_t *, int, DdNode *)void Llb_NonlinCheckVars(Llb_Mgr_t *)pPart->nSize == Cudd_DagSize(pPart->bFunc)void Llb_NonlinVerifyScores(Llb_Mgr_t *)nScore == pVar->nScoreDdManager *Llb_NonlinImageStart(Aig_Man_t *, Vec_Ptr_t *, Vec_Ptr_t *, int *, int *, int, abctime)BestVar = %4d/%4d. Value =%6d. Orig =%6d. Size0 =%6d. Original = %6d. SuppSize = %3d. Result = %6d. SuppSize = %3d. iVarLi >= 0 && iVarLi < Aig_ManObjNumMax(p->pAig)src/bdd/llb/llb3Nonlin.cvoid Llb_NonlinPrepareVarMap(Llb_Mnn_t *)iVarLo >= 0 && iVarLo < Aig_ManObjNumMax(p->pAig)Abc_Cex_t *Llb_NonlinDeriveCex(Llb_Mnn_t *)Order: int Llb_NonlinReachability(Llb_Mnn_t *)p->dd->bFunc == NULLReached timeout (%d seconds) during image computation in quantification. I =%3d : Fr =%7d Im =%7d (%4d %4d) S =%4d cL =%5d cG =%5d Image build and-ex other Transfer1Transfer2Global reo reoG Llb4_Nonlin4TransformCex(): There is no transition between state %d and %d. src/bdd/llb/llb4Cex.cAbc_Cex_t *Llb4_Nonlin4TransformCex(Aig_Man_t *, Vec_Ptr_t *, int, int)Vec_Ptr_t *Llb4_Nonlin4VerifyCex(Aig_Man_t *, Abc_Cex_t *)Llb4_Nonlin4NormalizeCex(): The given CEX does not fail outputs of pAigRpm. Llb4_Nonlin4TransformCex(): Counter-example verification has FAILED.Llb4_Nonlin4TransformCex(): There is no last transition that makes the property fail.Llb4_Nonlin4TransformCex(): The SAT solver is unsat after adding last clause.Llb4_Nonlin4TransformCex(): SAT solver is invalid.Llb4_Nonlin4TransformCex(): Counter-example generation has failed.Llb4_Nonlin4NormalizeCex(): The number of PIs in the reparametrized AIG and in the CEX do not agree.Llb4_Nonlin4NormalizeCex(): The number of flops in the original and reparametrized AIGs do not agree.src/bdd/llb/llb4Image.cvoid Llb_Nonlin4RemoveVar(Llb_Mgr_t *, Llb_Var_t *)void Llb_Nonlin4RemovePart(Llb_Mgr_t *, Llb_Prt_t *)DdNode *Llb_Nonlin4CreateCube1(Llb_Mgr_t *, Llb_Prt_t *)DdNode *Llb_Nonlin4CreateCube2(Llb_Mgr_t *, Llb_Prt_t *, Llb_Prt_t *)int Llb_Nonlin4Quantify1(Llb_Mgr_t *, Llb_Prt_t *)int Llb_Nonlin4Quantify2(Llb_Mgr_t *, Llb_Prt_t *, Llb_Prt_t *)void Llb_Nonlin4CutNodes_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Ptr_t *)void Llb_Nonlin4AddPartition(Llb_Mgr_t *, int, DdNode *)void Llb_Nonlin4CheckVars(Llb_Mgr_t *)void Llb_Nonlin4VerifyScores(Llb_Mgr_t *)!Cudd_IsComplement(pPart->bFunc)Vec_Ptr_t *Llb_Nonlin4Group(DdManager *, Vec_Ptr_t *, Vec_Int_t *, int)?Llb_ObjBddVar(vOrder, pObj) < 0src/bdd/llb/llb4Nonlin.cvoid Llb_Nonlin4CreateOrder_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Int_t *, int *)Counter <= Aig_ManCiNum(pAig) + Aig_ManRegNum(pAig) + (vNodes?Vec_IntSize(vNodes):0)Vec_Int_t *Llb_Nonlin4CreateOrder(Aig_Man_t *)Llb_ObjBddVar(vOrder, pObjLo) >= 0void Llb_Nonlin4SetupVarMap(DdManager *, Aig_Man_t *, Vec_Int_t *)Llb_ObjBddVar(vOrder, pObjLi) >= 0Vec_Ptr_t *Llb_Nonlin4DeriveCex(Llb_Mnx_t *, int, int)fBackward || pValues[Llb_ObjBddVar(p->vOrder, pObj)] == 0int Llb_Nonlin4Reachability(Llb_Mnx_t *)Reached timeout (%d seconds) during remapping bad states. p->pAig->pSeqModel == NULLReached timeout (%d seconds) during remapping next states. I =%5d : Fr =%7d ImNs =%7d ImCs =%7d Rea =%7d Remap Total = %d. Direct LO = %d. Compl LO = %d. Aig_Man_t *Llb_ReachableStates(Aig_Man_t *)Cudd_ReadSize(dd) == Saig_ManRegNum(pAig)reachedThe number of objects is more than 2^15. Clustering cannot be used.src/bdd/llb/llb4Sweep.cvoid Llb_Nonlin4SweepOrder_rec(Aig_Man_t *, Aig_Obj_t *, Vec_Int_t *, int *, int)Added %d cut points. Used %d high fanout points. Groups: Groups =%3d Variables: all =%4d pi =%4d po =%4d lo =%4d li =%4d and =%4dCounter == Aig_ManNodeNum(pAig)void Llb4_Nonlin4Sweep(Aig_Man_t *, int, int, DdManager **, Vec_Int_t **, Vec_Ptr_t **, int)Counter == nCutPoints;Pi<4====l===$=8=L=$==$=D=0T=D=t=======T=0d=D=\=p=$=D=T=d=====$$=pT=$==L====h4=D>>,T>hd > >>d>>T>H>\#>t'>)><*>->2><2>h3>|45>5>46>7>9>:>4:>;> <> $=>`J>dQ>Q>Q>Q>0$Z>|^>4_>h>xi>n>o>p>r>$t>u>>>,D>x>>(>>t>T>T>8D>4>>>$>>,$>L4>8$>L>DD>`D>T>hd>|>t>>>$4>DD>X$>>>>>,>@>TT>>>>0t>P>pt>>t>>><4>\>|>>,>x>>>T>D>d>$>>>HD>>>>PT??4t?$? ? ??? ?t?T?Ht ?!?"?d&?$'?D,?\d-? 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