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OpenOCD has different commands for NOR and NAND flash; the “flash” command works with NOR flash, while the “nand” command works with NAND flash. This partially reflects different hardware technologies: NOR flash usually supports direct CPU instruction and data bus access, while data from a NAND flash must be copied to memory before it can be used. (SPI flash must also be copied to memory before use.) However, the documentation also uses “flash” as a generic term; for example, “Put flash configuration in board-specific files”.
Flash Steps:
flash bank
flash subcommand
Many CPUs have the ablity to “boot” from the first flash bank. This means that misprogramming that bank can “brick” a system, so that it can’t boot. JTAG tools, like OpenOCD, are often then used to “de-brick” the board by (re)installing working boot firmware.
Configures a flash bank which provides persistent storage for addresses from base to base + size - 1. These banks will often be visible to GDB through the target’s memory map. In some cases, configuring a flash bank will activate extra commands; see the driver-specific documentation.
cfi for external flash, or else
the name of a microcontroller with embedded flash memory.
See Flash Driver List.
Note: This command is not available after OpenOCD initialization has completed. Use it in board specific configuration files, not interactively.
Prints a one-line summary of each device that was
declared using flash bank, numbered from zero.
Note that this is the plural form;
the singular form is a very different command.
Retrieves a list of associative arrays for each device that was
declared using flash bank, numbered from zero.
This returned list can be manipulated easily from within scripts.
Identify the flash, or validate the parameters of the configured flash. Operation
depends on the flash type.
The num parameter is a value shown by flash banks.
Most flash commands will implicitly autoprobe the bank;
flash drivers can distinguish between probing and autoprobing,
but most don’t bother.
One feature distinguishing NOR flash from NAND or serial flash technologies
is that for read access, it acts exactly like any other addressible memory.
This means you can use normal memory read commands like mdw or
dump_image with it, with no special flash subcommands.
See Memory access, and Image access.
Write access works differently. Flash memory normally needs to be erased before it’s written. Erasing a sector turns all of its bits to ones, and writing can turn ones into zeroes. This is why there are special commands for interactive erasing and writing, and why GDB needs to know which parts of the address space hold NOR flash memory.
Note: Most of these erase and write commands leverage the fact that NOR flash chips consume target address space. They implicitly refer to the current JTAG target, and map from an address in that target’s address space back to a flash bank. A few commands use abstract addressing based on bank and sector numbers, and don’t depend on searching the current target and its address space. Avoid confusing the two command models.
Some flash chips implement software protection against accidental writes, since such buggy writes could in some cases “brick” a system. For such systems, erasing and writing may require sector protection to be disabled first. Examples include CFI flash such as “Intel Advanced Bootblock flash”, and AT91SAM7 on-chip flash. See flash protect.
Erase sectors in bank num, starting at sector first
up to and including last.
Sector numbering starts at 0.
Providing a last sector of last
specifies "to the end of the flash bank".
The num parameter is a value shown by flash banks.
Erase sectors starting at address for length bytes. Unless pad is specified, address must begin a flash sector, and address + length - 1 must end a sector. Specifying pad erases extra data at the beginning and/or end of the specified region, as needed to erase only full sectors. The flash bank to use is inferred from the address, and the specified length must stay within that bank. As a special case, when length is zero and address is the start of the bank, the whole flash is erased. If unlock is specified, then the flash is unprotected before erase starts.
Fills flash memory with the specified word (32 bits), halfword (16 bits), or byte (8-bit) pattern, starting at address and continuing for length units (word/halfword/byte). No erasure is done before writing; when needed, that must be done before issuing this command. Writes are done in blocks of up to 1024 bytes, and each write is verified by reading back the data and comparing it to what was written. The flash bank to use is inferred from the address of each block, and the specified length must stay within that bank.
Write the binary filename to flash bank num,
starting at offset bytes from the beginning of the bank.
The num parameter is a value shown by flash banks.
Read length bytes from the flash bank num starting at offset
and write the contents to the binary filename.
The num parameter is a value shown by flash banks.
Compare the contents of the binary file filename with the contents of the
flash num starting at offset. Fails if the contents do not match.
The num parameter is a value shown by flash banks.
Write the image filename to the current target’s flash bank(s). Only loadable sections from the image are written. A relocation offset may be specified, in which case it is added to the base address for each section in the image. The file [type] can be specified explicitly as bin (binary), ihex (Intel hex), elf (ELF file), s19 (Motorola s19). mem, or builder. The relevant flash sectors will be erased prior to programming if the erase parameter is given. If unlock is provided, then the flash banks are unlocked before erase and program. The flash bank to use is inferred from the address of each image section.
Warning: Be careful using the erase flag when the flash is holding data you want to preserve. Portions of the flash outside those described in the image’s sections might be erased with no notice.
- When a section of the image being written does not fill out all the sectors it uses, the unwritten parts of those sectors are necessarily also erased, because sectors can’t be partially erased.
- Data stored in sector "holes" between image sections are also affected. For example, "
flash write_image erase ..." of an image with one byte at the beginning of a flash bank and one byte at the end erases the entire bank – not just the two sectors being written.Also, when flash protection is important, you must re-apply it after it has been removed by the unlock flag.
Check erase state of sectors in flash bank num,
and display that status.
The num parameter is a value shown by flash banks.
Print info about flash bank num, a list of protection blocks and their status. Use sectors to show a list of sectors instead.
The num parameter is a value shown by flash banks.
This command will first query the hardware, it does not print cached
and possibly stale information.
Enable (on) or disable (off) protection of flash blocks
in flash bank num, starting at protection block first
and continuing up to and including last.
Providing a last block of last
specifies "to the end of the flash bank".
The num parameter is a value shown by flash banks.
The protection block is usually identical to a flash sector.
Some devices may utilize a protection block distinct from flash sector.
See flash info for a list of protection blocks.
Sets the default value used for padding any image sections, This should normally match the flash bank erased value. If not specified by this comamnd or the flash driver then it defaults to 0xff.
This is a helper script that simplifies using OpenOCD as a standalone programmer. The only required parameter is filename, the others are optional. See Flash Programming.
As noted above, the flash bank command requires a driver name,
and allows driver-specific options and behaviors.
Some drivers also activate driver-specific commands.
This is a special driver that maps a previously defined bank to another address. All bank settings will be copied from the master physical bank.
The virtual driver defines one mandatory parameters,
So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to the flash bank defined at address 0x1fc00000. Any cmds executed on the virtual banks are actually performed on the physical banks.
flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
flash bank vbank0 virtual 0xbfc00000 0 0 0 \
$_TARGETNAME $_FLASHNAME
flash bank vbank1 virtual 0x9fc00000 0 0 0 \
$_TARGETNAME $_FLASHNAME
The “Common Flash Interface” (CFI) is the main standard for
external NOR flash chips, each of which connects to a
specific external chip select on the CPU.
Frequently the first such chip is used to boot the system.
Your board’s reset-init handler might need to
configure additional chip selects using other commands (like: mww to
configure a bus and its timings), or
perhaps configure a GPIO pin that controls the “write protect” pin
on the flash chip.
The CFI driver can use a target-specific working area to significantly
speed up operation.
The CFI driver can accept the following optional parameters, in any order:
To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes) wide on a sixteen bit bus:
flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
To configure one bank of 32 MBytes built from two sixteen bit (two byte) wide parts wired in parallel to create a thirty-two bit (four byte) bus with doubled throughput:
flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a SPI flash connected to them. To access this flash from the host, the device is first programmed with a special proxy bitstream that exposes the SPI flash on the device’s JTAG interface. The flash can then be accessed through JTAG.
Since signaling between JTAG and SPI is compatible, all that is required for a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate the flash chip select when the JTAG state machine is in SHIFT-DR. Such a bitstream for several Xilinx FPGAs can be found in contrib/loaders/flash/fpga/xilinx_bscan_spi.py. It requires migen and a Xilinx toolchain to build.
This flash bank driver requires a target on a JTAG tap and will access that
tap directly. Since no support from the target is needed, the target can be a
"testee" dummy. Since the target does not expose the flash memory
mapping, target commands that would otherwise be expected to access the flash
will not work. These include all *_image and
$target_name m* commands as well as program. Equivalent
functionality is available through the flash write_bank,
flash read_bank, and flash verify_bank commands.
target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
set _XILINX_USER1 0x02
set _DR_LENGTH 1
flash bank $_FLASHNAME spi 0x0 0 0 0 \
$_TARGETNAME $_XILINX_USER1 $_DR_LENGTH
NXP’s LPC43xx and LPC18xx families include a proprietary SPI Flash Interface (SPIFI) peripheral that can drive and provide memory mapped access to external SPI flash devices.
The lpcspifi driver initializes this interface and provides program and erase functionality for these serial flash devices. Use of this driver requires a working area of at least 1kB to be configured on the target device; more than this will significantly reduce flash programming times.
The setup command only requires the base parameter. All other parameters are ignored, and the flash size and layout are configured by the driver.
flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
Some devices form STMicroelectronics (e.g. STR75x MCU family, SPEAr MPU family) include a proprietary “Serial Memory Interface” (SMI) controller able to drive external SPI flash devices. Depending on specific device and board configuration, up to 4 external flash devices can be connected.
SMI makes the flash content directly accessible in the CPU address
space; each external device is mapped in a memory bank.
CPU can directly read data, execute code and boot from SMI banks.
Normal OpenOCD commands like mdw can be used to display
the flash content.
The setup command only requires the base parameter in order to identify the memory bank. All other parameters are ignored. Additional information, like flash size, are detected automatically.
flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
This driver supports QSPI flash controller of Marvell’s Wireless Microcontroller platform.
The flash size is autodetected based on the table of known JEDEC IDs hardcoded in the OpenOCD sources.
flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
The ADUC702x analog microcontrollers from Analog Devices include internal flash and use ARM7TDMI cores. The aduc702x flash driver works with models ADUC7019 through ADUC7028. The setup command only requires the target argument since all devices in this family have the same memory layout.
flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
All members of the Apollo microcontroller family from Ambiq Micro include internal flash and use ARM’s Cortex-M4 core. The host connects over USB to an FTDI interface that communicates with the target using SWD.
The ambiqmicro driver reads the Chip Information Register detect the device class of the MCU. The Flash and Sram sizes directly follow device class, and are used to set up the flash banks. If this fails, the driver will use default values set to the minimum sizes of an Apollo chip.
All Apollo chips have two flash banks of the same size. In all cases the first flash bank starts at location 0, and the second bank starts after the first.
# Flash bank 0
flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
# Flash bank 1 - same size as bank0, starts after bank 0.
flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
$_TARGETNAME
Flash is programmed using custom entry points into the bootloader. This is the only way to program the flash as no flash control registers are available to the user.
The ambiqmicro driver adds some additional commands:
Erase entire bank.
Erase device pages.
Program OTP is a one time operation to create write protected flash. The user writes sectors to sram starting at 0x10000010. Program OTP will write these sectors from sram to flash, and write protect the flash.
All members of the ATSAMD, ATSAMR, ATSAML and ATSAMC microcontroller families from Atmel include internal flash and use ARM’s Cortex-M0+ core. This driver uses the same cmd names/syntax as See at91sam3.
Issues a complete Flash erase via the Device Service Unit (DSU). This can be used to erase a chip back to its factory state and does not require the processor to be halted.
Secures the Flash via the Set Security Bit (SSB) command. This prevents access to the Flash and can only be undone by using the chip-erase command which erases the Flash contents and turns off the security bit. Warning: at this time, openocd will not be able to communicate with a secured chip and it is therefore not possible to chip-erase it without using another tool.
at91samd set-security enable
Shows or sets the EEPROM emulation size configuration, stored in the User Row of the Flash. When setting, the EEPROM size must be specified in bytes and it must be one of the permitted sizes according to the datasheet. Settings are written immediately but only take effect on MCU reset. EEPROM emulation requires additional firmware support and the minumum EEPROM size may not be the same as the minimum that the hardware supports. Set the EEPROM size to 0 in order to disable this feature.
at91samd eeprom at91samd eeprom 1024
Shows or sets the bootloader size configuration, stored in the User Row of the Flash. This is called the BOOTPROT region. When setting, the bootloader size must be specified in bytes and it must be one of the permitted sizes according to the datasheet. Settings are written immediately but only take effect on MCU reset. Setting the bootloader size to 0 disables bootloader protection.
at91samd bootloader at91samd bootloader 16384
This command releases internal reset held by DSU and prepares reset vector catch in case of reset halt. Command is used internally in event event reset-deassert-post.
All members of the AT91SAM3 microcontroller family from Atmel include internal flash and use ARM’s Cortex-M3 core. The driver currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note that the driver was orginaly developed and tested using the AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in the family was cribbed from the data sheet. Note to future readers/updaters: Please remove this worrysome comment after other chips are confirmed.
The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips have one flash bank. In all cases the flash banks are at the following fixed locations:
# Flash bank 0 - all chips flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME # Flash bank 1 - only 256K chips flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
Internally, the AT91SAM3 flash memory is organized as follows.
Unlike the AT91SAM7 chips, these are not used as parameters
to the flash bank command:
The AT91SAM3 driver adds some additional commands:
With no parameters, show or show all,
shows the status of all GPNVM bits.
With show number, displays that bit.
With set number or clear number,
modifies that GPNVM bit.
This command attempts to display information about the AT91SAM3
chip. First it read the CHIPID_CIDR [address 0x400e0740, see
Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
document id: doc6430A] and decodes the values. Second it reads the
various clock configuration registers and attempts to display how it
believes the chip is configured. By default, the SLOWCLK is assumed to
be 32768 Hz, see the command at91sam3 slowclk.
This command shows/sets the slow clock frequency used in the
at91sam3 info command calculations above.
All members of the AT91SAM4 microcontroller family from Atmel include internal flash and use ARM’s Cortex-M4 core. This driver uses the same cmd names/syntax as See at91sam3.
All members of the AT91SAM4L microcontroller family from Atmel include internal flash and use ARM’s Cortex-M4 core. This driver uses the same cmd names/syntax as See at91sam3.
The AT91SAM4L driver adds some additional commands:
This command releases internal reset held by SMAP and prepares reset vector catch in case of reset halt. Command is used internally in event event reset-deassert-post.
All members of the ATSAMV, ATSAMS, and ATSAME families from Atmel include internal flash and use ARM’s Cortex-M7 core. This driver uses the same cmd names/syntax as See at91sam3.
All members of the AT91SAM7 microcontroller family from Atmel include internal flash and use ARM7TDMI cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
For chips which are not recognized by the controller driver, you must provide additional parameters in the following order:
flash info
It is recommended that you provide zeroes for all of those values except the clock frequency, so that everything except that frequency will be autoconfigured. Knowing the frequency helps ensure correct timings for flash access.
The flash controller handles erases automatically on a page (128/256 byte)
basis, so explicit erase commands are not necessary for flash programming.
However, there is an “EraseAll“ command that can erase an entire flash
plane (of up to 256KB), and it will be used automatically when you issue
flash erase_sector or flash erase_address commands.
Set or clear a “General Purpose Non-Volatile Memory” (GPNVM) bit for the processor. Each processor has a number of such bits, used for controlling features such as brownout detection (so they are not truly general purpose).
Note: This assumes that the first flash bank (number 0) is associated with the appropriate at91sam7 target.
The AVR 8-bit microcontrollers from Atmel integrate flash memory. The current implementation is incomplete.
All members of the EFM32 microcontroller family from Energy Micro include internal flash and use ARM Cortex-M3 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
A special feature of efm32 controllers is that it is possible to completely disable the debug interface by writing the correct values to the ’Debug Lock Word’. OpenOCD supports this via the following command:
efm32 debuglock num
The num parameter is a value shown by flash banks.
Note that in order for this command to take effect, the target needs to be reset.
The current implementation is incomplete. Unprotecting flash pages is not
supported.
All members of the FM3 microcontroller family from Fujitsu
include internal flash and use ARM Cortex-M3 cores.
The fm3 driver uses the target parameter to select the
correct bank config, it can currently be one of the following:
mb9bfxx1.cpu, mb9bfxx2.cpu, mb9bfxx3.cpu,
mb9bfxx4.cpu, mb9bfxx5.cpu or mb9bfxx6.cpu.
flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
include internal flash and use ARM Cortex-M4 cores.
The fm4 driver uses a family parameter to select the
correct bank config, it can currently be one of the following:
MB9BFx64, MB9BFx65, MB9BFx66, MB9BFx67, MB9BFx68,
S6E2Cx8, S6E2Cx9, S6E2CxA or S6E2Dx,
with x treated as wildcard and otherwise case (and any trailing
characters) ignored.
flash bank ${_FLASHNAME}0 fm4 0x00000000 0 0 0 \
$_TARGETNAME S6E2CCAJ0A
flash bank ${_FLASHNAME}1 fm4 0x00100000 0 0 0 \
$_TARGETNAME S6E2CCAJ0A
The current implementation is incomplete. Protection is not supported, nor is Chip Erase (only Sector Erase is implemented).
Kx and KLx members of the Kinetis microcontroller family from Freescale include internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically recognizes flash size and a number of flash banks (1-4) using the chip identification register, and autoconfigures itself.
flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
Select what source is used when writing to a Flash Configuration Field. protection mode builds FCF content from protection bits previously set by ’flash protect’ command. This mode is default. MCU is protected from unwanted locking by immediate writing FCF after erase of relevant sector. write mode enables direct write to FCF. Protection cannot be set by ’flash protect’ command. FCF is written along with the rest of a flash image. BEWARE: Incorrect flash configuration may permanently lock the device!
Set value to write to FOPT byte of Flash Configuration Field. Used in kinetis ’fcf_source protection’ mode only.
Checks status of device security lock. Used internally in examine-end event.
Issues a halt via the MDM-AP. This command can be used to break a watchdog reset loop when connecting to an unsecured target.
Issues a complete flash erase via the MDM-AP. This can be used to erase a chip back to its factory state, removing security. It does not require the processor to be halted, however the target will remain in a halted state after this command completes.
For FlexNVM devices only (KxxDX and KxxFX). Command shows or sets data flash or EEPROM backup size in kilobytes, sets two EEPROM blocks sizes in bytes and enables/disables loading of EEPROM contents to FlexRAM during reset.
For details see device reference manual, Flash Memory Module, Program Partition command.
Setting is possible only once after mass_erase. Reset the device after partition setting.
Show partition size:
kinetis nvm_partition info
Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
kinetis nvm_partition dataflash 32 512 1536 on
Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks of 1024 bytes and its contents is not loaded to FlexRAM during reset:
kinetis nvm_partition eebkp 16 1024 1024 off
Issues a reset via the MDM-AP. This causes the MCU to output a low pulse on the RESET pin, which can be used to reset other hardware on board.
For Kx devices only (KLx has different COP watchdog, it is not supported). Command disables watchdog timer.
KE members of the Kinetis microcontroller family from Freescale include internal flash and use ARM Cortex-M0+. The driver automatically recognizes the KE family and sub-family using the chip identification register, and autoconfigures itself.
flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
Checks status of device security lock. Used internally in examine-end event.
Issues a complete Flash erase via the MDM-AP. This can be used to erase a chip back to its factory state. Command removes security lock from a device (use of SRST highly recommended). It does not require the processor to be halted.
Command disables watchdog timer.
This is the driver to support internal flash of all members of the LPC11(x)00 and LPC1300 microcontroller families and most members of the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000 and LPC54100 microcontroller families from NXP.
Note: There are LPC2000 devices which are not supported by the lpc2000 driver: The LPC2888 is supported by the lpc288x driver. The LPC29xx family is supported by the lpc2900 driver.
The lpc2000 driver defines two mandatory and one optional parameters, which must appear in the following order:
Note: If you don’t provide calc_checksum when you’re writing the vector table, the boot ROM will almost certainly ignore your flash image. However, if you do provide it, with most tool chains
verify_imagewill fail.
LPC flashes don’t require the chip and bus width to be specified.
flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
lpc2000_v2 14765 calc_checksum
Displays the four byte part identifier associated with the specified flash bank.
The LPC2888 microcontroller from NXP needs slightly different flash support from its lpc2000 siblings. The lpc288x driver defines one mandatory parameter, the programming clock rate in Hz. LPC flashes don’t require the chip and bus width to be specified.
flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
This driver supports the LPC29xx ARM968E based microcontroller family from NXP.
The predefined parameters base, size, chip_width and
bus_width of the flash bank command are ignored. Flash size and
sector layout are auto-configured by the driver.
The driver has one additional mandatory parameter: The CPU clock rate
(in kHz) at the time the flash operations will take place. Most of the time this
will not be the crystal frequency, but a higher PLL frequency. The
reset-init event handler in the board script is usually the place where
you start the PLL.
The driver rejects flashless devices (currently the LPC2930).
The EEPROM in LPC2900 devices is not mapped directly into the address space.
It must be handled much more like NAND flash memory, and will therefore be
handled by a separate lpc2900_eeprom driver (not yet available).
Sector protection in terms of the LPC2900 is handled transparently. Every time a
sector needs to be erased or programmed, it is automatically unprotected.
What is shown as protection status in the flash info command, is
actually the LPC2900 sector security. This is a mechanism to prevent a
sector from ever being erased or programmed again. As this is an irreversible
mechanism, it is handled by a special command (lpc2900 secure_sector),
and not by the standard flash protect command.
Example for a 125 MHz clock frequency:
flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
Some lpc2900-specific commands are defined. In the following command list,
the bank parameter is the bank number as obtained by the
flash banks command.
Calculates a 128-bit hash value, the signature, from the whole flash content. This is a hardware feature of the flash block, hence the calculation is very fast. You may use this to verify the content of a programmed device against a known signature. Example:
lpc2900 signature 0 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
Reads the 912 bytes of customer information from the flash index sector, and saves it to a file in binary format. Example:
lpc2900 read_custom 0 /path_to/customer_info.bin
The index sector of the flash is a write-only sector. It cannot be
erased! In order to guard against unintentional write access, all following
commands need to be preceeded by a successful call to the password
command:
You need to use this command right before each of the following commands:
lpc2900 write_custom, lpc2900 secure_sector,
lpc2900 secure_jtag.
The password string is fixed to "I_know_what_I_am_doing". Example:
lpc2900 password 0 I_know_what_I_am_doing Potentially dangerous operation allowed in next command!
Writes the content of the file into the customer info space of the flash index sector. The filetype can be specified with the type field. Possible values for type are: bin (binary), ihex (Intel hex format), elf (ELF binary) or s19 (Motorola S-records). The file must contain a single section, and the contained data length must be exactly 912 bytes.
Attention: This cannot be reverted! Be careful!
Example:
lpc2900 write_custom 0 /path_to/customer_info.bin bin
Secures the sector range from first to last (including) against further program and erase operations. The sector security will be effective after the next power cycle.
Attention: This cannot be reverted! Be careful!
Secured sectors appear as protected in the flash info command.
Example:
lpc2900 secure_sector 0 1 1
flash info 0
#0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
# 0: 0x00000000 (0x2000 8kB) not protected
# 1: 0x00002000 (0x2000 8kB) protected
# 2: 0x00004000 (0x2000 8kB) not protected
Irreversibly disable the JTAG port. The new JTAG security setting will be effective after the next power cycle.
Attention: This cannot be reverted! Be careful!
Examples:
lpc2900 secure_jtag 0
This drivers handles the integrated NOR flash on Milandr Cortex-M based controllers. A known limitation is that the Info memory can’t be read or verified as it’s not memory mapped.
flash bank <name> mdr <base> <size> \
0 0 <target#> type page_count sec_count
Example usage:
if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
flash bank ${_CHIPNAME}_info.flash mdr 0x00000000 0x01000 \
0 0 $_TARGETNAME 1 1 4
} else {
flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
0 0 $_TARGETNAME 0 32 4
}
This drivers handles the integrated NOR flash on NIIET Cortex-M4 based controllers. Flash size and sector layout are auto-configured by the driver. Main flash memory is called "Bootflash" and has main region and info region. Info region is NOT memory mapped by default, but it can replace first part of main region if needed. Full erase, single and block writes are supported for both main and info regions. There is additional not memory mapped flash called "Userflash", which also have division into regions: main and info. Purpose of userflash - to store system and user settings. Driver has special commands to perform operations with this memmory.
flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
Some niietcm4-specific commands are defined:
Read byte from main or info userflash region.
Write byte to main or info userflash region.
Erase all userflash including info region.
Erase sectors of main or info userflash region, starting at sector first up to and including last.
Check sectors protect.
Protect sectors of main or info userflash region, starting at sector first up to and including last.
Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
Configure external memory interface for boot.
Perform emergency erase of all flash (bootflash and userflash).
Show information about flash driver.
All members of the nRF51 microcontroller families from Nordic Semiconductor include internal flash and use ARM Cortex-M0 core.
flash bank $_FLASHNAME nrf51 0 0x00000000 0 0 $_TARGETNAME
Some nrf51-specific commands are defined:
Erases the contents of the code memory and user information configuration registers as well. It must be noted that this command works only for chips that do not have factory pre-programmed region 0 code.
This driver is an implementation of the “on chip flash loader” protocol proposed by Pavel Chromy.
It is a minimalistic command-response protocol intended to be used over a DCC when communicating with an internal or external flash loader running from RAM. An example implementation for AT91SAM7x is available in contrib/loaders/flash/at91sam7x/.
flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
The PIC32MX microcontrollers are based on the MIPS 4K cores, and integrate flash memory.
flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
Some pic32mx-specific commands are defined:
Programs the specified 32-bit value at the given address in the specified chip bank.
Unlock and erase specified chip bank. This will remove any Code Protection.
All members of the PSoC 41xx/42xx microcontroller family from Cypress include internal flash and use ARM Cortex-M0 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
Note: Erased internal flash reads as 00. System ROM of PSoC 4 does not implement erase of a flash sector.
flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
psoc4-specific commands
Enables or disables autoerase mode for a flash bank.
If flash_autoerase is off, use mass_erase before flash programming. Flash erase command fails if region to erase is not whole flash memory.
If flash_autoerase is on, a sector is both erased and programmed in one system ROM call. Flash erase command is ignored. This mode is suitable for gdb load.
The num parameter is a value shown by flash banks.
Erases the contents of the flash memory, protection and security lock.
The num parameter is a value shown by flash banks.
All members of the SiM3 microcontroller family from Silicon Laboratories include internal flash and use ARM Cortex-M3 cores. It supports both JTAG and SWD interface. The sim3x driver tries to probe the device to auto detect the MCU. If this failes, it will use the size parameter as the size of flash bank.
flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
There are 2 commands defined in the sim3x driver:
Erases the complete flash. This is used to unlock the flash. And this command is only possible when using the SWD interface.
Lock the flash. To unlock use the sim3x mass_erase command.
All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller families from Texas Instruments include internal flash. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself. 6
flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
Performs the Recovering a "Locked" Device procedure to restore the flash and its associated nonvolatile registers to their factory default values (erased). This is the only way to remove flash protection or re-enable debugging if that capability has been disabled.
Note that the final "power cycle the chip" step in this procedure must be performed by hand, since OpenOCD can’t do it.
Warning: if more than one Stellaris chip is connected, the procedure is applied to all of them.
All members of the STM32F0, STM32F1 and STM32F3 microcontroller families from ST Microelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
Note that some devices have been found that have a flash size register that contains an invalid value, to workaround this issue you can override the probed value used by the flash driver.
flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
If you have a target with dual flash banks then define the second bank as per the following example.
flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
Some stm32f1x-specific commands 7 are defined:
Locks the entire stm32 device.
The num parameter is a value shown by flash banks.
Unlocks the entire stm32 device.
The num parameter is a value shown by flash banks.
Read and display the stm32 option bytes written by
the stm32f1x options_write command.
The num parameter is a value shown by flash banks.
Writes the stm32 option byte with the specified values.
The num parameter is a value shown by flash banks.
All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from ST Microelectronics include internal flash and use ARM Cortex-M3/M4/M7 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
Note that some devices have been found that have a flash size register that contains an invalid value, to workaround this issue you can override the probed value used by the flash driver.
flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
Some stm32f2x-specific commands are defined:
Locks the entire stm32 device.
The num parameter is a value shown by flash banks.
Unlocks the entire stm32 device.
The num parameter is a value shown by flash banks.
Reads and displays user options and (where implemented) boot_addr0 and boot_addr1.
The num parameter is a value shown by flash banks.
Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
Warning: The meaning of the various bits depends on the device, always check datasheet!
The num parameter is a value shown by flash banks, user_options a
12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, boot_addr0 and boot_addr1
two halfwords (of FLASH_OPTCR1).
All members of the STM32L microcontroller families from ST Microelectronics include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
Note that some devices have been found that have a flash size register that contains an invalid value, to workaround this issue you can override the probed value used by the flash driver. If you use 0 as the bank base address, it tells the driver to autodetect the bank location assuming you’re configuring the second bank.
flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
Some stm32lx-specific commands are defined:
Mass erases the entire stm32lx device (all flash banks and EEPROM
data). This is the only way to unlock a protected flash (unless RDP
Level is 2 which can’t be unlocked at all).
The num parameter is a value shown by flash banks.
All members of the STR7 microcontroller family from ST Microelectronics
include internal flash and use ARM7TDMI cores.
The str7x driver defines one mandatory parameter, variant,
which is either STR71x, STR73x or STR75x.
flash bank $_FLASHNAME str7x \
0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
Activate the Debug/Readout protection mechanism for the specified flash bank.
Most members of the STR9 microcontroller family from ST Microelectronics
include internal flash and use ARM966E cores.
The str9 needs the flash controller to be configured using
the str9x flash_config command prior to Flash programming.
flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME str9x flash_config 0 4 2 0 0x80000
Configures the str9 flash controller.
The num parameter is a value shown by flash banks.
Only use this driver for locking/unlocking the device or configuring the option bytes.
Use the standard str9 driver for programming.
Before using the flash commands the turbo mode must be enabled using the
str9xpec enable_turbo command.
Here is some background info to help you better understand how this driver works. OpenOCD has two flash drivers for the str9:
Before we run any commands using the str9xpec driver we must first disable the str9 core. This example assumes the str9xpec driver has been configured for flash bank 0.
# assert srst, we do not want core running # while accessing str9xpec flash driver jtag_reset 0 1 # turn off target polling poll off # disable str9 core str9xpec enable_turbo 0 # read option bytes str9xpec options_read 0 # re-enable str9 core str9xpec disable_turbo 0 poll on reset halt
The above example will read the str9 option bytes. When performing a unlock remember that you will not be able to halt the str9 - it has been locked. Halting the core is not required for the str9xpec driver as mentioned above, just issue the commands above manually or from a telnet prompt.
Several str9xpec-specific commands are defined:
Restore the str9 into JTAG chain.
Enable turbo mode, will simply remove the str9 from the chain and talk directly to the embedded flash controller.
Lock str9 device. The str9 will only respond to an unlock command that will erase the device.
Prints the part identifier for bank num.
Configure str9 boot bank.
Configure str9 lvd source.
Configure str9 lvd threshold.
Configure str9 lvd reset warning source.
Read str9 option bytes.
Write str9 option bytes.
unlock str9 device.
Most members of the TMS470 microcontroller family from Texas Instruments include internal flash and use ARM7TDMI cores. This driver doesn’t require the chip and bus width to be specified.
Some tms470-specific commands are defined:
Saves programming keys in a register, to enable flash erase and write commands.
Reports the clock speed, which is used to calculate timings.
Disables (1) or enables (0) use of the PLL to speed up the flash clock.
All members of the XMC1xxx microcontroller family from Infineon. This driver does not require the chip and bus width to be specified.
All members of the XMC4xxx microcontroller family from Infineon. This driver does not require the chip and bus width to be specified.
Some xmc4xxx-specific commands are defined:
Saves flash protection passwords which are used to lock the user flash
Removes Flash write protection from the selected user bank
Compared to NOR or SPI flash, NAND devices are inexpensive and high density. Today’s NAND chips, and multi-chip modules, commonly hold multiple GigaBytes of data.
NAND chips consist of a number of “erase blocks” of a given size (such as 128 KBytes), each of which is divided into a number of pages (of perhaps 512 or 2048 bytes each). Each page of a NAND flash has an “out of band” (OOB) area to hold Error Correcting Code (ECC) and other metadata, usually 16 bytes of OOB for every 512 bytes of page data.
One key characteristic of NAND flash is that its error rate is higher than that of NOR flash. In normal operation, that ECC is used to correct and detect errors. However, NAND blocks can also wear out and become unusable; those blocks are then marked "bad". NAND chips are even shipped from the manufacturer with a few bad blocks. The highest density chips use a technology (MLC) that wears out more quickly, so ECC support is increasingly important as a way to detect blocks that have begun to fail, and help to preserve data integrity with techniques such as wear leveling.
Software is used to manage the ECC. Some controllers don’t support ECC directly; in those cases, software ECC is used. Other controllers speed up the ECC calculations with hardware. Single-bit error correction hardware is routine. Controllers geared for newer MLC chips may correct 4 or more errors for every 512 bytes of data.
You will need to make sure that any data you write using
OpenOCD includes the apppropriate kind of ECC. For example,
that may mean passing the oob_softecc flag when
writing NAND data, or ensuring that the correct hardware
ECC mode is used.
The basic steps for using NAND devices include:
nand device
nand probe.
nand subcommand
NOTE: At the time this text was written, the largest NAND flash fully supported by OpenOCD is 2 GiBytes (16 GiBits). This is because the variables used to hold offsets and lengths are only 32 bits wide. (Larger chips may work in some cases, unless an offset or length is larger than 0xffffffff, the largest 32-bit unsigned integer.) Some larger devices will work, since they are actually multi-chip modules with two smaller chips and individual chipselect lines.
NAND chips must be declared in configuration scripts, plus some additional configuration that’s done after OpenOCD has initialized.
Declares a NAND device, which can be read and written to
after it has been configured through nand probe.
In OpenOCD, devices are single chips; this is unlike some
operating systems, which may manage multiple chips as if
they were a single (larger) device.
In some cases, configuring a device will activate extra
commands; see the controller-specific documentation.
NOTE: This command is not available after OpenOCD initialization has completed. Use it in board specific configuration files, not interactively.
Prints a summary of each device declared
using nand device, numbered from zero.
Note that un-probed devices show no details.
> nand list
#0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
blocksize: 131072, blocks: 8192
#1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
blocksize: 131072, blocks: 8192
>
Probes the specified device to determine key characteristics
like its page and block sizes, and how many blocks it has.
The num parameter is the value shown by nand list.
You must (successfully) probe a device before you can use
it with most other NAND commands.
Reads binary data from the NAND device and writes it to the file,
starting at the specified offset.
The num parameter is the value shown by nand list.
Use a complete path name for filename, so you don’t depend on the directory used to start the OpenOCD server.
The offset and length must be exact multiples of the device’s page size. They describe a data region; the OOB data associated with each such page may also be accessed.
NOTE: At the time this text was written, no error correction
was done on the data that’s read, unless raw access was disabled
and the underlying NAND controller driver had a read_page
method which handled that error correction.
By default, only page data is saved to the specified file. Use an oob_option parameter to save OOB data:
oob_raw
nand raw_access, which just
controls whether a hardware-aware access method is used.
oob_only
Erases blocks on the specified NAND device, starting at the
specified offset and continuing for length bytes.
Both of those values must be exact multiples of the device’s
block size, and the region they specify must fit entirely in the chip.
If those parameters are not specified,
the whole NAND chip will be erased.
The num parameter is the value shown by nand list.
NOTE: This command will try to erase bad blocks, when told
to do so, which will probably invalidate the manufacturer’s bad
block marker.
For the remainder of the current server session, nand info
will still report that the block “is” bad.
Writes binary data from the file into the specified NAND device,
starting at the specified offset. Those pages should already
have been erased; you can’t change zero bits to one bits.
The num parameter is the value shown by nand list.
Use a complete path name for filename, so you don’t depend on the directory used to start the OpenOCD server.
The offset must be an exact multiple of the device’s page size. All data in the file will be written, assuming it doesn’t run past the end of the device. Only full pages are written, and any extra space in the last page will be filled with 0xff bytes. (That includes OOB data, if that’s being written.)
NOTE: At the time this text was written, bad blocks are ignored. That is, this routine will not skip bad blocks, but will instead try to write them. This can cause problems.
Provide at most one option parameter. With some
NAND drivers, the meanings of these parameters may change
if nand raw_access was used to disable hardware ECC.
write_page routine, that routine may write the OOB
with hardware-computed ECC data.
oob_only
oob_raw
write_page routine, that routine may modify the OOB
before it’s written, to include hardware-computed ECC data.
oob_softecc
oob_softecc_kw
Verify the binary data in the file has been programmed to the
specified NAND device, starting at the specified offset.
The num parameter is the value shown by nand list.
Use a complete path name for filename, so you don’t depend on the directory used to start the OpenOCD server.
The offset must be an exact multiple of the device’s page size.
All data in the file will be read and compared to the contents of the
flash, assuming it doesn’t run past the end of the device.
As with nand write, only full pages are verified, so any extra
space in the last page will be filled with 0xff bytes.
The same options accepted by nand write,
and the file will be processed similarly to produce the buffers that
can be compared against the contents produced from nand dump.
NOTE: This will not work when the underlying NAND controller
driver’s write_page routine must update the OOB with a
hardward-computed ECC before the data is written. This limitation may
be removed in a future release.
Checks for manufacturer bad block markers on the specified NAND
device. If no parameters are provided, checks the whole
device; otherwise, starts at the specified offset and
continues for length bytes.
Both of those values must be exact multiples of the device’s
block size, and the region they specify must fit entirely in the chip.
The num parameter is the value shown by nand list.
NOTE: Before using this command you should force raw access
with nand raw_access enable to ensure that the underlying
driver will not try to apply hardware ECC.
The num parameter is the value shown by nand list.
This prints the one-line summary from "nand list", plus for
devices which have been probed this also prints any known
status for each block.
Sets or clears an flag affecting how page I/O is done.
The num parameter is the value shown by nand list.
This flag is cleared (disabled) by default, but changing that
value won’t affect all NAND devices. The key factor is whether
the underlying driver provides read_page or write_page
methods. If it doesn’t provide those methods, the setting of
this flag is irrelevant; all access is effectively “raw”.
When those methods exist, they are normally used when reading
data (nand dump or reading bad block markers) or
writing it (nand write). However, enabling
raw access (setting the flag) prevents use of those methods,
bypassing hardware ECC logic.
This can be a dangerous option, since writing blocks
with the wrong ECC data can cause them to be marked as bad.
As noted above, the nand device command allows
driver-specific options and behaviors.
Some controllers also activate controller-specific commands.
This driver handles the NAND controllers found on AT91SAM9 family chips from Atmel. It takes two extra parameters: address of the NAND chip; address of the ECC controller.
nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
AT91SAM9 chips support single-bit ECC hardware. The write_page and
read_page methods are used to utilize the ECC hardware unless they are
disabled by using the nand raw_access command. There are four
additional commands that are needed to fully configure the AT91SAM9 NAND
controller. Two are optional; most boards use the same wiring for ALE/CLE:
Configure the address line used for latching commands. The num
parameter is the value shown by nand list.
Configure the address line used for latching addresses. The num
parameter is the value shown by nand list.
For the next two commands, it is assumed that the pins have already been properly configured for input or output.
Configure the RDY/nBUSY input from the NAND device. The num
parameter is the value shown by nand list. pio_base_addr
is the base address of the PIO controller and pin is the pin number.
Configure the chip enable input to the NAND device. The num
parameter is the value shown by nand list. pio_base_addr
is the base address of the PIO controller and pin is the pin number.
This driver handles the NAND controllers found on DaVinci family chips from Texas Instruments. It takes three extra parameters: address of the NAND chip; hardware ECC mode to use (hwecc1, hwecc4, hwecc4_infix); address of the AEMIF controller on this processor.
nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
All DaVinci processors support the single-bit ECC hardware,
and newer ones also support the four-bit ECC hardware.
The write_page and read_page methods are used
to implement those ECC modes, unless they are disabled using
the nand raw_access command.
These controllers require an extra nand device
parameter: the clock rate used by the controller.
Configures use of the MLC or SLC controller mode.
MLC implies use of hardware ECC.
The num parameter is the value shown by nand list.
At this writing, this driver includes write_page
and read_page methods. Using nand raw_access
to disable those methods will prevent use of hardware ECC
in the MLC controller mode, but won’t change SLC behavior.
This driver handles the NAND controller in i.MX31. The mxc driver should work for this chip aswell.
This driver handles the NAND controller found in Freescale i.MX chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35). The driver takes 3 extra arguments, chip (mx27, mx31, mx35), ecc (noecc, hwecc) and optionally if bad block information should be swapped between main area and spare area (biswap), defaults to off.
nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
Turns on/off bad block information swaping from main area, without parameter query status.
These controllers require an extra nand device
parameter: the address of the controller.
nand device orion 0xd8000000
These controllers don’t define any specialized commands.
At this writing, their drivers don’t include write_page
or read_page methods, so nand raw_access won’t
change any behavior.
These S3C family controllers don’t have any special
nand device options, and don’t define any
specialized commands.
At this writing, their drivers don’t include write_page
or read_page methods, so nand raw_access won’t
change any behavior.
Configures a mflash for soc host bank at address base. The pin number format depends on the host GPIO naming convention. Currently, the mflash driver supports s3c2440 and pxa270.
Example for s3c2440 mflash where RST pin is GPIO B1:
mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0
Example for pxa270 mflash where RST pin is GPIO 43:
mflash bank $_FLASHNAME pxa270 0x08000000 43 0
Configure mflash PLL. The frequency is the mflash input frequency, in Hz. Issuing this command will erase mflash’s whole internal nand and write new pll. After this command, mflash needs power-on-reset for normal operation. If pll was newly configured, storage and boot(optional) info also need to be update.
Configure bootable option. If bootable option is set, mflash offer the first 8 sectors (4kB) for boot.
Configure storage information. For the normal storage operation, this information must be written.
Dump size bytes, starting at offset bytes from the beginning of the bank num, to the file named filename.
Probe mflash.
Write the binary file filename to mflash bank num, starting at offset bytes from the beginning of the bank.
Currently there is a stellaris mass_erase command.
That seems pointless since the same effect can be had using the
standard flash erase_address command.
Currently there is a stm32f1x mass_erase command.
That seems pointless since the same effect can be had using the
standard flash erase_address command.
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